Multi-die memory device with reduced peak current

Abstract

The present disclosure relates to multi-die memory devices with reduced peak current. A memory device includes a substrate including a substrate contact pad. The memory device includes a first memory die including a first power contact pad electrically coupled to the substrate contact pad and a first power circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power contact pad electrically coupled to the substrate contact pad and a second power circuit on the second memory die, and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to managing peak current levels and current consumption in multi-die semiconductor devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure is directed to a memory device comprising: a substrate including substrate contacts; a first memory die coupled to the substrate, the first memory die including: a first power contact pad electrically coupled to the substrate contacts and a first power circuit on the first memory die; and a first electrostatic discharge (ESD) power clamping contact pad electrically coupled to the substrate contact pad and a first ESD power clamping circuit on the first memory die; and a second memory die including: a second power contact pad electrically coupled to the substrate contacts and a second power circuit on the second memory die; and a second ESD power clamping contact pad electrically coupled to a second ESD power clamping circuit on the second memory die, wherein the second ESD power clamping contact pad is electrically disconnected from the substrate contacts.

[0004] In another aspect, this disclosure relates to a semiconductor device comprising: a substrate; a first semiconductor die coupled to the substrate, the first semiconductor die comprising: a first contact pad electrically coupled to a first circuit on the first semiconductor die, wherein the first circuit includes at least one active circuit element; and a second contact pad electrically coupled to a second circuit on the first semiconductor die, wherein the second circuit includes at least one passive circuit element; wherein the substrate comprises substrate contacts electrically coupled to the first and second contact pads; and a second semiconductor die comprising: a third contact pad electrically coupled to a third circuit on the second semiconductor die, wherein the third circuit includes at least one active circuit element; and a fourth contact pad electrically coupled to a fourth circuit on the second semiconductor die, wherein the fourth circuit includes only passive circuit elements; wherein the substrate contacts are electrically coupled to the third contact pad; and wherein the fourth contact pad is electrically disconnected from the substrate contacts.

[0005] In another aspect, this disclosure relates to a system comprising: a controller; and a memory device coupled to the controller, the memory device comprising: a substrate including substrate contacts; a first memory die coupled to the substrate, the first memory die comprising: a first power contact pad electrically coupled to the substrate contacts and a first power circuit on the first memory die; and a first electrostatic discharge (ESD) power clamping contact pad electrically coupled to the substrate contact pad and a first ESD power clamping circuit on the first memory die; and a second memory die comprising: a second power contact pad electrically coupled to the substrate contacts and a second power circuit on the second memory die; and a second ESD power clamping contact pad electrically coupled to a second ESD power clamping circuit on the second memory die, wherein the second ESD power clamping contact pad is electrically disconnected from the substrate contacts. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to one or more embodiments of the present disclosure.

[0009] Figures 3 to 6 This is a schematic diagram of a multi-die memory device assembly according to an embodiment of the present disclosure.

[0010] Figures 7 to 9 This is a simplified partial cross-sectional view of a memory device assembly according to an embodiment of the present disclosure.

[0011] Figure 10 This is a schematic diagram illustrating a system including a memory device according to an embodiment of the present disclosure.

[0012] Figure 11 A flowchart illustrating an example method for manufacturing a memory device assembly according to an embodiment of the present disclosure.

[0013] Figure 12 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0014] This disclosure relates to a semiconductor device comprising a plurality of semiconductor dies (e.g., memory dies) in a stacked assembly configured to reduce peak current levels and total current consumption levels (e.g., reserve current) during powered-on operating modes of the semiconductor device. For example, the semiconductor device may include a memory device comprising a plurality of memory dies having a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more memory dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0016] Packaged memory dies, including memory chips, microprocessor chips, and imager chips, typically comprise one or more memory dies mounted on a substrate and encapsulated in a hermetically sealed enclosure (e.g., a plastic protective cover) or covered by a thermally conductive cap. A memory die may include active circuitry (e.g., providing functional features such as power supplies, memory cells, processor circuitry, and / or imager devices) and passive circuitry (e.g., electrostatic discharge (ESD) circuitry including one or more passive components such as capacitors and resistors), as well as one or more bonding pads electrically connected to the circuitry. The bonding pads may be electrically connected to terminals outside the protective cover to allow the memory die to be connected to higher-level circuitry systems.

[0017] For example, a semiconductor device, such as a memory device assembly, may include multiple memory dies stacked on a substrate in a shingled manner and covered by an encapsulation. Each memory die includes one or more contact pads to a corresponding integrated circuit. The contact pads may be wire-bonded (e.g., in a daisy-chain configuration) to substrate contacts to provide connectivity to the integrated circuit via solder balls.

[0018] Using semiconductor dies, various bonding pads can be connected to multiple circuits within a memory die. For example, in a NAND memory die, a single bonding pad can be connected to active driver circuitry (e.g., a power supply) and passive ESD protection circuitry (e.g., including one or more capacitors). The ESD protection circuitry can be designed to provide the required amount of capacitance to protect a single active driver circuit (e.g., protecting one or more transistors coupled to an interface pin of an integrated circuit from electrostatic discharge).

[0019] In certain memory device assemblies comprising multiple memory dies with active driver circuitry connected in parallel (e.g., where corresponding bonding pads from each memory die are connected to the same external terminal or interface), input / output (I / O) speed requirements have increased. This presents design challenges in balancing fast I / O operation speeds with the robustness of ESD circuitry used to manage the effects of electrostatic discharge on integrated circuits. One approach is to reduce I / O pin capacitance by decreasing the number of ESD circuitry elements and reducing the gate contact distance of pull-up or pull-down devices. However, this lowers the level of ESD management for the device.

[0020] To adequately protect the internal circuitry of a memory device from ESD damage, ESD power clamping circuitry can be employed on the positive power supply (e.g., also referred to as "Vccq") and the "0" volt or ground voltage (e.g., also referred to as "Vssq"). However, during the power-on mode of the memory device, ESD power clamping circuitry causes significant spikes or increases in the peak current level of the memory device (e.g., also referred to as "Iccq"), which may degrade device performance.

[0021] The aspects of this disclosure address the above and other drawbacks by implementing a semiconductor device configuration that includes an arrangement of active circuitry (e.g., power supply circuitry or driver circuitry) and passive circuitry (e.g., ESD power clamping circuitry) that manages ESD levels in the semiconductor device while reducing peak current levels during powered-on operation of the semiconductor device. In embodiments, the semiconductor device includes a memory device having multiple memory dies. When memory dies having ESD protection circuitry (e.g., ESD power clamping circuitry) connected to the same bonding pad as the active circuitry (e.g., power supply circuitry or driver circuitry) are connected together at different package densities (e.g., a package including two memory dies, a package including four memory dies, a package including four memory dies and a data bus, etc.), it is impossible to optimize the peak current level consumed by the ESD protection circuitry for each package density. Therefore, semiconductor devices, such as memory devices, according to embodiments of this disclosure provide package-level configurability of peak current levels to overcome this challenge.

[0022] This disclosure relates to a semiconductor device assembly including a substrate and a plurality of semiconductor dies coupled to the substrate. In an embodiment, the semiconductor device is a memory device including a first memory die of a plurality of die assemblies. The first memory die includes a first contact pad electrically coupled to a first circuit on the first memory die including at least one active circuit element (e.g., a power supply, such as Vccq), and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements (e.g., an ESD power clamping circuit). In an embodiment, the substrate includes substrate contacts electrically coupled to the first and second contact pads of the first memory die. The memory device assembly further includes a second memory die, the second memory die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element (e.g., a power supply or driver circuit), and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements (e.g., an ESD power clamping circuit). In an embodiment, in order to manage the peak current level associated with the power-on operation of the memory device, the substrate contact (e.g., an interface pin) may be electrically coupled to a third contact pad and electrically disconnected from a fourth contact pad.

[0023] According to an embodiment, one or more contact pads associated with the ESD clamping circuitry of one or more memory dies in a multi-die memory device assembly can be electrically disconnected from the substrate interface. Advantageously, by maintaining the ESD power clamping circuitry of the second memory die of the memory device electrically disconnected from the substrate interface arrangement, the ESD power clamping circuitry does not consume spare or leakage current, thereby reducing the total peak current level consumed by the memory device. Furthermore, the electrical isolation of the one or more contact pads associated with the ESD clamping circuitry of the multi-die memory device assembly results in those ESD clamping circuitry not contributing to the peak current level during powered-on operation. Additionally, due to fewer connected ESD clamping circuitry, a reduced current level is consumed during operation of the semiconductor device. Advantageously, considering the reduced number of electrically connected ESD power clamping circuitry, the reduced current consumption leads to power savings and extended battery life associated with the memory device.

[0024] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to one or more embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or such computing device including memory and processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., storage device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, crosspoint non-volatile memory allows for in-place write operations compared to multiple flash-based memories, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical block addresses (e.g., logical block addresses (LBAs), namespaces) and physical block addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device that includes a raw memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] In one embodiment, the memory subsystem 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling interactions between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may send memory access commands corresponding to requests received from the host system 120 to the memory device 130, such as programming commands, read commands, or other commands. Additionally, the memory interface component 113 may receive data from the memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0041] According to an embodiment, the memory device 130 includes a multi-die package 135 comprising a plurality of memory dies assembled on a substrate. Each of the plurality of memory dies includes one or more contact pads provided to enable contact with an integrated circuit having active components (hereinafter referred to as and schematically illustrated as...). Figures 3 to 6Electrical connections to the power supply circuitry (in the memory). In an embodiment, each of the plurality of memory dies includes one or more individual or dedicated contact pads associated with an integrated circuit having passive components (referred to herein and schematically illustrated as an electrostatic discharge (ESD) power clamping circuit). In an embodiment, one or more power circuit pads are arranged adjacent to or immediately adjacent to the corresponding ESD power clamping circuit pads associated with one or more ESD power clamping circuits 138.

[0042] In one embodiment, the memory device 130 includes an assembly stack of multiple memory dies in a multi-die package 137. Therefore, the multi-die package includes a set of ESD power clamping pads associated with ESD power clamping circuitry 138 of the multiple memory dies in the package. In one embodiment, fewer than the entire set of ESD power clamping pads are bonded to contact pads on the substrate (e.g., contact pads associated with I / O interface pins) or corresponding power contact pads. Advantageously, the use of dedicated contact pads allows each of the memory dies to be manufactured in the same manner, providing flexibility in the configuration of wired assemblies in the multi-die package, wherein one or more of the dedicated ESD power clamping contact pads may be electrically isolated (e.g., not electrically connected) relative to the substrate contact pads. In one embodiment, by electrically disconnecting one or more of the ESD power clamping contact pads from the substrate contacts, the total peak current level is reduced because the disconnected ESD power clamp will not consume current during power-on of the memory device 130. Additionally, the amount of current consumed (e.g., backup or leakage current) is reduced due to the presence of one or more electrically disconnected ESD power clamps. These disconnected or unengaged ESD clamps do not draw current during operation of the memory device, thereby saving power and battery life.

[0043] In one embodiment, the ESD power clamping contact pad may be arranged or positioned on the ground side of the memory die (e.g., adjacent to the 0-volt or ground power contact pad). In another embodiment, the ESD power clamping contact pad may be arranged or positioned on the power side of the memory die (e.g., adjacent to the positive power supply). In yet another embodiment, the ESD power clamping contact pad may be arranged or positioned on both the power side and the ground side of the memory die.

[0044] Figure 2 A first device in the form of a presentable memory device 130 according to an embodiment and a presentable memory subsystem (e.g., Figure 1A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0045] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column.

[0046] In one embodiment, the memory device 100 includes a multi-die package 137 comprising a plurality of memory dies disposed on a substrate. In another embodiment, the multi-die package 137 includes one or more ESD power clamping circuits 138, which include associated ESD power clamping contact pads as described herein. In yet another embodiment, the multi-die package 137 includes at least a portion of the memory cells of the memory cell array 204. Figure 2 (Not shown in the text), it can be programmed to one of at least two target data states.

[0047] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Memory device 130 also includes input / output (I / O) control circuitry 212 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 212 and control logic 28 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses.

[0049] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 22 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 for output to memory subsystem controller 115; then, new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2 (Not shown) The data status of the memory cells in the memory cell array 204 can be sensed, for example, by sensing the status of the data lines connected to the memory cells. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0050] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, and write protection WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. Memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0051] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 218. Data can then be written to data register 220 for programming memory cell array 204.

[0052] In this embodiment, cache register 218 may be omitted, and data may be written directly to data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0053] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component.

[0054] In addition, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0055] According to an embodiment, the memory device 130 includes a plurality of memory dies arranged in a stacked manner on a substrate. Each of the memory dies in the multi-die package 137 of the memory device 130 includes power and ESD power clamping circuitry 138 for providing ESD protection to the memory device 130. The memory die also includes a first set of one or more dedicated contact pads associated with the power supply and a second set of one or more dedicated contact pads associated with the ESD power clamping circuitry.

[0056] In this embodiment, each ESD power clamping circuit is associated with a dedicated contact pad. In this embodiment, the dedicated contact pad using the ESD power clamping circuit enables the use of multiple memory dies with the same structure and layout to achieve different package densities while providing the required amount of ESD protection, and reducing or managing the peak current level consumed during the power-on operation of the memory device 130. Additionally, because one or more ESD power clamping circuits are disconnected (e.g., not engaged), a reduction or lower level of backup current is consumed.

[0057] Figure 3 This is a simplified schematic illustration of an example semiconductor device assembly comprising multiple semiconductor dies. Figure 3 In the examples shown, according to embodiments of this disclosure, the semiconductor device assembly is a memory device assembly 300 comprising multiple memory dies (e.g., a dual-die package or DDP). As shown, the memory device assembly 300 includes a substrate 301 and two memory dies 302 and 303 (e.g., memory dies having a consistent or identical structure). In embodiments, each memory die 302 and 303 includes multiple contact pads, such as first contact pads 305 to fourth contact pads 308 and fifth contact pads 311 to eighth contact pads 314 of memory die 302, each providing connectivity to circuitry with active components (e.g., power supply circuitry) or circuitry with passive components (e.g., ESD power clamping circuitry). For example, as... Figure 3 As shown, contact pad 311 provides connectivity to the first power circuit 340, contact pad 312 provides connectivity to the first ESD power clamping circuit 341, contact pad 313 provides connectivity to the second power circuit 342, and contact pad 314 provides connectivity to the second ESD power clamping circuit 343.

[0058] In one embodiment, the first contact pad 305 and the third contact pad 307 correspond to the power supply side of the first memory die 302. In this embodiment, the first contact pad 305 is electrically coupled to the positive power supply (e.g., VCCQ) of the first memory die 302. In another embodiment, the first contact pad 305 and the third contact pad 307 correspond to the ground side (e.g., 0 volts or VSSQ) of the first memory die 302. In yet another embodiment, the first contact pad 305 corresponds to the power supply side of the first memory die 302, and the third contact pad 307 corresponds to the ground side of the first memory die 303.

[0059] Because each ESD power clamping circuit is provided with dedicated contact pads (e.g., contact pads 306, 308, 312, and 314), the assembly 300 can be configured to have the required amount of ESD protection for each power circuit, while managing the contribution to peak current consumption levels during memory device power-on and the contribution to total current consumption levels (e.g., standby or leakage current levels) during memory device operation.

[0060] For reference Figure 3 As can be seen, substrate 301 includes two substrate contacts 321 and 322. The first substrate contact 321 (e.g., interface pin 1) (e.g., via wire bonding 330) is connected to the first contact pad 305 of memory die 302 and the fifth contact pad 311 of memory die 303 (corresponding to power supply circuit 340). In an embodiment, substrate contact 321 (e.g., via wire bonding 331) is connected to the second contact pad 306 of memory die 302 (corresponding to ESD power clamping circuit 312). Additionally, as... Figure 3 As shown, the second substrate contact 322 (e.g., interface pin 2) (e.g., via wire bonding 332) is connected to the third contact pad 307 of the memory die 302 and the seventh contact pad 313 of the memory die 303 (corresponding to power supply circuit 342). In an embodiment, for the memory die 302, the substrate contact 322 (e.g., via wire bonding 333) is connected to the fourth contact pad 308 of the memory die 302 (corresponding to ESD power clamping circuit 312).

[0061] As shown, the fifth contact pad 312 and the eighth contact pad 314 of the memory die 303 are not connected to the substrate contacts 321 and 322 (e.g., electrically isolated). Therefore, the corresponding ESD power clamping circuits (e.g., 341 and 343) are disconnected, and no current is consumed during the power-on period of the memory device 300 or during operation of the memory device 300. By electrically disconnecting the second contact pad 312 and the fourth contact pad 314 (corresponding to the ESD protection circuitry) on the upper memory die 303 from the substrate contacts 321 and 322, the total peak current level consumed during the power-on period of the memory device is less than the total peak current level consumed when the ESD power clamping circuits from each memory die in the assembly 300 are connected. Furthermore, the total reserve current consumed is also reduced compared to an assembly in which all ESD power clamping circuits for each memory die are connected and consume current.

[0062] although Figure 3 While described and illustrated as including multiple identical memory dies, in other embodiments, memory device assemblies having different types of memory dies may possess similar features. For example, in one embodiment, a memory device assembly may include logic dies and memory dies, one or both of which may include discrete contact pads for passive circuitry to be connected as needed during packaging. Furthermore, although... Figure 3 The memory die described and illustrated includes two power supply circuits; however, it will be readily apparent to those skilled in the art that this embodiment is merely one example, and memory dies with different numbers of power supply circuits may also be provided. Furthermore, Figure 3 The contact pads for the ESD power clamping circuit, which have been described and illustrated as providing contact pads separate from the contact pads of the power supply circuit, may, in other embodiments, provide circuits with other active elements besides the power supply circuit, and may also provide other circuits that include only passive components (e.g., resistors, capacitors, inductors, etc.).

[0063] although Figure 3 It has been described and illustrated that multiple wire connections are present at each substrate contact 321 and 322 to provide connectivity with multiple contact pads in one of the semiconductor dies 302 in the assembly 300; however, in other embodiments, other wire connection arrangements may be used. In one embodiment, the first substrate contact 321 may utilize a wire connection between a first contact pad 311 and a second contact pad 312 of the memory die 302. Figure 3 (Not shown) The second contact pad 312 (corresponding to the ESD power clamping circuit) is connected to only one memory die 302 in the assembly 300.

[0064] Figure 4This is a simplified schematic illustration of an example semiconductor device (e.g., a memory device assembly 400 including multiple memory dies (e.g., a quad die package or QDP)) according to embodiments of the present disclosure. As shown, the memory device assembly 400 includes a substrate 401 and four memory dies 402, 403, 404, and 405 (e.g., memory dies having a consistent or identical structure). In an embodiment, each memory die 402 to 405 includes multiple contact pads, such as first contact pads 406 to fourth contact pads 409, fifth contact pads 411 to eighth contact pads 414 for memory die 402, ninth contact pads 415 to twelfth contact pads 418 for memory die 404, and thirteenth contact pads 419 to sixteenth contact pads 422 for memory die 405, each providing connectivity to circuitry with active components (e.g., power supply circuitry, such as 440 and 442) or circuitry with passive components (e.g., ESD power clamping circuitry, such as 441 and 443). For example, such as Figure 4 As shown, contact pad 419 provides connectivity to the first power circuit 440, contact pad 420 provides connectivity to the first ESD power clamping circuit 441, contact pad 413 provides connectivity to the second power circuit 442, and contact pad 414 provides connectivity to the second ESD power clamping circuit 443.

[0065] like Figure 4 As shown, the memory device assembly includes a set of dedicated contact pads (e.g., contact pads 407, 409, 412, 414, 416, 418, 420, and 422) that provide connectivity to corresponding ESD power clamping circuitry (also referred to as "a set of ESD contact pads"). In embodiments, as... Figure 4 As shown, only contact pads 407 and 409 of the set of ESD contact pads (of the memory die 402) are electrically connected to the substrate contact pads (e.g., 421 and 422). Therefore, the remaining ESD contact pads of the set of ESD contact pads (e.g., contact pads 412, 414, 416, 418, 420, and 422) are configured to be electrically disconnected from the substrate contacts. Thus, while the ESD power clamping corresponding to the electrically connected ESD contact pads (e.g., contact pads 407 and 409) provides ESD protection to the memory device 400, the disconnected ESD contact pads do not contribute to the peak current level or the total current consumption level (e.g., spare or leakage current) of the memory device 400 during power-on.

[0066] Figure 5This is a simplified schematic illustration of an example semiconductor device assembly (e.g., a memory device package 500 including multiple memory dies and one or more data bus circuits) according to embodiments of the present disclosure. As shown, the memory device assembly 500 includes a substrate 501 and four memory dies 502, 503, 504, and 505 (e.g., memory dies having a consistent or identical structure). In an embodiment, each memory die 502 to 505 includes multiple contact pads, such as first contact pads 506 to third contact pads 508, fourth contact pads 509 to sixth contact pads 511 for memory die 502, seventh contact pads 512 to ninth contact pads 514 for memory die 504, and thirteenth contact pads 515 to sixteenth contact pads 517 for memory die 505, each providing connectivity to circuitry with active components (e.g., power supply circuitry, such as 540), circuitry with passive components (e.g., ESD power clamping circuitry, such as 541), or a data bus (e.g., data bus 550). For example, such as Figure 5 As shown, contact pad 515 provides connectivity to the first power supply circuit 540, contact pad 516 provides connectivity to the first ESD power clamping circuit 541, and contact pad 517 provides connectivity to the data bus 550.

[0067] like Figure 5 As shown, a portion of the set of dedicated contact pads (e.g., contact pads 510 and 516) associated with the ESD power clamping circuitry is disconnected from the substrate contacts (e.g., contacts 521, 522, and 523). In an embodiment, each of the set of contact pads associated with the data bus 550 (e.g., contact pads 508, 511, 514, and 517) is electrically connected to the substrate contacts (e.g., I / O pins 522, 523).

[0068] Although in the foregoing embodiments, the dedicated contact pads for each connected ESD power clamping circuit are described and illustrated as having corresponding dedicated wire connections, in other embodiments, the contact pads may be connected in other ways. For example, Figure 6 A simplified schematic diagram illustrating a semiconductor device assembly (e.g., a memory device assembly 600) according to an embodiment of the present disclosure is provided. Assembly 600 includes a substrate 601 and two memory dies 602 and 603 (e.g., memory dies having the same physical structure and layout). Each memory die 602 and 603 includes a plurality of contact pads, such as first contact pads 606 to fourth contact pads 609 of memory die 602 and fifth contact pads 611 to eighth contact pads 614 of memory die 603, each providing connectivity to circuitry having active components (e.g., power supply circuitry 640, 642) or circuitry having passive components (e.g., ESD power clamping circuitry 641, 643). Figure 6As shown, ESD power clamping contact pads 607, 609, 612 and 614 are positioned adjacent to the corresponding power contact pads 606, 608, 611 and 613, respectively, so that a single wire connection 630 can be used to connect two pads.

[0069] For reference Figure 6 As can be seen, substrate 601 includes two substrate contacts 621 and 622. The first substrate contact 621 is connected via a single wire bond 630 to the first contact pad 606 (corresponding to a power supply circuit) and the second contact pad 607 (corresponding to an ESD power clamping circuit) of the first semiconductor die 602 (e.g., using solder bond 641). The first substrate contact 621 is further connected via a wire bond connecting the solder bond 641 of the first contact pads 606 and 607 of the first memory die 602 to the fifth contact pad 611 (corresponding to a power supply circuit) of the second memory die 603. Similarly, the second substrate contact 622 is connected via a single wire bond to the third contact pad 608 and the seventh contact pad 613 (corresponding to a power supply circuit) and the fourth contact pad 609 (corresponding to an ESD protection circuit) of the first memory die 602 (e.g., using solder bond). The second substrate contact 622 is further connected by a wire connection between the solder joint of the third contact pad 608 and the fourth contact pad 609 of the first memory die 602 and the seventh contact pad 613 (corresponding to the power supply circuit) of the second memory die 603.

[0070] According to embodiments of this disclosure, a memory die with closely spaced bonding pads can be configured for optionally connecting any number of different circuits having any desired functionality other than or replacing ESD power clamping circuits and power circuits. Furthermore, closely spaced bonding pads can be provided in any of several ways, such as those described above. Figures 3 to 6 The example illustrates the bonding pad. For instance, Figure 7 A simplified partial cross-sectional view illustrating a semiconductor device (e.g., memory device 700) according to an embodiment of the present technology. Figure 7 In the memory device 701 described herein, closely spaced bonding pads 702 and 703 are provided under a layer of passivation or polyamide material 705 and are thus separated by a small area 706 of passivation or polyamide material. A solder ball 704 of sufficient volume can be provided to bridge this area 706 of passivation or polyamide material and thus connect the closely spaced bonding pads 702 and 703.

[0071] Using another example, Figure 8 A simplified partial cross-sectional view illustrating another semiconductor device (e.g., memory device 800) according to an embodiment of the present technology is shown. Figure 8In the memory device 801 described herein, closely spaced bonding pads 802 and 803 are provided under a layer of passivation or polyamide material 805, but additional processing steps have been performed to remove the passivation or polyamide material 805 between the closely spaced bonding pads 802 and 803 (e.g., by including an etch-stopping material 806 under the area between the closely spaced bonding pads 802 and 803 to allow the passivation or polyamide material 805 to be etched away between them). This arrangement facilitates the easy attachment of solder balls 804 to the closely spaced bonding pads 802 and 803 (due to the absence of non-wettable material between them).

[0072] In yet another embodiment, Figure 9 A simplified partial cross-sectional view illustrating another semiconductor device (e.g., memory device 900) according to an embodiment of the present technology is shown. Figure 9 In the memory device 901 described herein, closely spaced bonding pads 902 and 903 are provided over a layer of passivation or polyamide material 905 (e.g., in a redistribution layer). This arrangement also facilitates the easy attachment of solder balls 904 to the closely spaced bonding pads 902 and 903 (due to the absence of non-wettable material between them).

[0073] Although memory device packaging has been illustrated in the foregoing examples, where circuitry with passive components (e.g., ESD protection circuitry) has been explained and described using dedicated contact pads for providing connectivity via wire bonding, those skilled in the art will readily appreciate that other methods of die-to-die or die-to-substrate connectivity can also be used to provide package-level connectivity configurability. For example, circuitry with passive components can be arranged in a non-shingled stack with semiconductor dies having dedicated TSVs, where optional connectivity is provided by including or omitting solder joints between adjacent TSVs in the stack. Other interconnect technologies can also be provided.

[0074] Furthermore, although in the foregoing examples the semiconductor device assembly (e.g., memory device assembly) has been described as comprising a single stack of semiconductor dies, in other embodiments of the present technology, the memory device assembly may comprise multiple stacks of semiconductor dies, wherein passive circuitry may optionally be connected via dedicated contact pads. For example, in one embodiment of the present technology, the memory device assembly may comprise multiple laterally separated stacks of semiconductor dies (e.g., two stacks each with four dies, two stacks each with eight dies, four stacks each with four dies, etc.), wherein less than all available ESD circuitry in each stack is electrically coupled to active circuitry. In another embodiment, the memory device assembly may include a single stack of semiconductor dies, wherein a subset of the dies in the stack are separately connected to a substrate (e.g., a shingled stack, wherein eight dies grouped as a first subset are electrically coupled to the substrate, fewer than all available dies in the first subset have electrically coupled ESD circuitry, and another eight dies grouped as a second subset above the first eight dies are separately electrically coupled to the substrate from the first subset, the shingled offset direction is opposite to that of the first subset, fewer than all available dies in the second subset have electrically coupled ESD circuitry, etc.).

[0075] The above references Figures 3 to 9 Any of the described memory device assemblies can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 10 The system 1000 is schematically shown in the diagram. System 1000 may include a memory device assembly 1002, a power supply 1004, a driver 1006, a processor 1008, and / or other subsystems or components 1010. The memory device assembly 1002 may include components generally similar to those described in the reference above. Figures 3 to 9 The described memory device features characteristics. The resulting system 1000 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 1000 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 1000 may be housed in a single unit or distributed above multiple interconnected units (e.g., via a communication network). Components of system 1000 may also include remote devices and any of a wide variety of computer-readable media.

[0076] Figure 11 This is a flowchart illustrating an example method of manufacturing or configuring a memory device assembly according to an embodiment of the present disclosure. At operation 1110, a substrate is provided. For example, a substrate including at least one substrate contact of the memory device assembly is provided. The at least one substrate contact may be a pin or contact associated with an I / O interface of a memory subsystem.

[0077] At operation 1120, coupling is performed. For example, multiple memory dies are coupled to a substrate. In an example, the multiple memory dies include a first memory die and a second memory die assembled on and coupled to the substrate in a stacked arrangement.

[0078] At operation 1130, electrical coupling is performed. For example, a first contact pad of the first memory die is electrically coupled to a substrate contact. In an embodiment, the first contact pad is associated with a first power source (e.g., the power source of the first memory die).

[0079] At operation 1140, electrical coupling is performed. For example, the second contact pad of the second memory die is electrically coupled to the substrate contact. In an embodiment, the first contact pad is associated with a second power source (e.g., the power source of the second memory die).

[0080] At operation 1150, electrical coupling is performed. For example, a third contact pad of the first memory die is electrically coupled to a substrate contact. In an embodiment, the first contact pad is associated with an ESD power clamping circuit (e.g., an ESD power clamping circuit for the first memory die). In an embodiment, a fourth contact pad of the second memory die associated with an ESD power clamping circuit (e.g., an ESD power clamping circuit for the second memory die) is not electrically coupled to a substrate contact.

[0081] In one embodiment, the first and second memory dies have the same arrangement (e.g., each having a power-related contact pad and a dedicated contact pad associated with ESD power clamping circuitry). In another embodiment, by not connecting the ESD power clamping circuitry contact pad (e.g., a fourth contact pad) to the substrate contacts, the ESD power clamping circuitry of the second memory die does not consume current during power-on operation of the memory device. Advantageously, this reduces the peak current level during power-on operation while providing ESD protection (via the electrically coupled ESD power clamping circuitry of the first memory die).

[0082] Figure 12 This describes an instance machine of computer system 1200, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 1200 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110 may be used to perform operations of a controller according to embodiments of the present disclosure (e.g., to execute an operating system to perform operations corresponding to memory device 130). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0083] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by said machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform one or more of the methods discussed herein.

[0084] The example computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1218, which communicate with each other via a bus 1230.

[0085] Processing device 1202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein. Computer system 1200 may further include a network interface device 1208 for communication via network 1220.

[0086] Data storage system 1218 may include machine-readable storage medium 1224 (also referred to as computer-readable medium) on which one or more instruction sets 1226 or software embodying any one or more of the methods or functions described herein are stored. Instructions 1226 may also reside wholly or at least partially within main memory 1204 and / or processing device 1202 during execution by computer system 1200, which also constitute machine-readable storage medium. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 may correspond to... Figure 1 The memory subsystem 110.

[0087] In one embodiment, instruction 1226 includes instructions for implementing the functionality of the memory subsystem and memory device. Although machine-readable storage medium 1224 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0088] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithms are described and represented in a manner that those skilled in the art of data processing use to most effectively communicate the essence of their work to others skilled in the art. Algorithms herein are generally considered to be self-consistent sequences of operations that produce desired results. These operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, primarily for general reasons, to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0089] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0090] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk or media suitable for storing electronic instructions, each coupled to a computer system bus, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0092] This disclosure may be provided as a computer program product or software, which may include machine-readable media having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0093] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: a substrate comprising a first substrate contact, a second substrate contact, and a third substrate contact; a first memory die coupled to the substrate, the first memory die comprising: a first power contact pad electrically coupled to the first substrate contact and a first power circuit on the first memory die; a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die; a second memory die comprising: a second power contact pad electrically coupled to the first substrate contact and a second power circuit on the second memory die; a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the first substrate contact and the second substrate contact; and a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

2. The memory device of claim 1, wherein the first memory die and the second memory die comprise a same physical arrangement.

3. The memory device of claim 1, wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

4. The memory device of claim 1, wherein the first ESD power clamp circuit comprises one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die.

5. The memory device of claim 1, wherein the second ESD power clamp circuit does not contribute to a peak current level of the memory device during a power-on operation of the memory device.

6. The memory device of claim 1, wherein the first substrate contact is electrically coupled to the first power contact pad and the first ESD power clamp contact pad through a single wire bond and a single solder ball.

7. The memory device of claim 1, wherein the first substrate contact is electrically coupled to the second power contact pad through a wire bond between the first power contact pad and the second power contact pad.

8. The memory device of claim 1, wherein the second ESD power clamp circuit does not contribute to a total current consumption level of the memory device.

9. The memory device of claim 1, wherein the first power contact pad corresponds to a positive voltage supply of the first memory die. ​ ​ ​ 10. The memory device of claim 1, wherein the first power contact pad corresponds to a ground voltage supply of the first memory die.

11. The memory device of claim 1, wherein the first memory die includes a third power contact pad.

12. The memory device of claim 11, wherein the first power contact pad corresponds to a positive voltage supply of the first memory die, and the third power contact pad corresponds to a ground voltage supply of the first memory die.

13. A memory system, comprising: a controller; and a memory device coupled to the controller, the memory device comprising: a substrate comprising a first substrate contact, a second substrate contact, and a third substrate contact; a first memory die coupled to the substrate, the first memory die comprising: a first power contact pad electrically coupled to the first substrate contact and a first power circuit on the first memory die; a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die; a second memory die comprising: a second power contact pad electrically coupled to the first substrate contact and a second power circuit on the second memory die; a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

14. The memory system of claim 13, wherein the first memory die and the second memory die include a same physical arrangement.

15. The memory system of claim 13, wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

16. The memory system of claim 13, wherein the first ESD power clamp circuit includes one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die; and wherein the second ESD power clamp circuit does not contribute to a peak current level of the memory device during a power-on operation of the memory device.

17. The memory system of claim 13, wherein the first power contact pad corresponds to a positive voltage supply of the first memory die.

18. The memory system of claim 13, wherein the first power contact pad corresponds to a ground voltage supply of the first memory die.

19. The memory system of claim 13, wherein the first memory die includes a third power contact pad; and wherein the first power contact pad corresponds to a positive voltage supply for the first memory die, and the third power contact pad corresponds to a ground voltage supply for the first memory die.

20. A semiconductor device, comprising: a substrate including a first substrate contact, a second substrate contact, and a third substrate contact; a first memory die coupled to the substrate, the first memory die including: a first power contact pad electrically coupled to the first substrate contact and a first power circuit on the first memory die; a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die; a second memory die including: a second power contact pad electrically coupled to the first substrate contact and a second power circuit on the second memory die; a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and a third memory die including a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

Images