A Design Method of In-Memory Computing Logic Based on Unipolar Spin-Orbit Torque Magnetic Memory
By optimizing the order of read and write operations and using read delay logic, the magnetic polarization recovery time in US-SOT-MRAM is minimized, improving the speed and reliability of in-memory computing.
Patent Information
- Application Number
- CN202210322727.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-30
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2042-03-30
AI Technical Summary
The existing unipolar flip spin orbit torque magnetic memory has the problem of long recovery time of the free layer magnetization direction in the in-memory operation, resulting in an increased operation logic design time and the risk of data errors.
By optimizing the read and write logic design in the memory array, including TRS logic and RD logic, four operation logic steps are designed: two inputs and two inputs or three inputs, multiple selections and 1-bit full addition logic, put the write logic and TRS logic as much as possible, and appropriately increase the write voltage, reduce the flip operation on the same memory cell, and extend the step interval to reduce the impact of recovery time.
It effectively reduces the recovery time of the free layer magnetization direction flip, reduces power consumption, and improves the speed and reliability of the computing logic, achieving faster in-memory computing.
Smart Images
Figure CN114708893B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of non-volatile memory design, and particularly relates to a method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory. Background Art
[0002] In recent years, more and more storage technologies have been applied to in-memory operations. Among them, non-volatile memories have the following advantages compared to volatile memories: 1. Non-volatility, data will not be lost after power-off; 2. Fast read and write speed; 3. Low static power consumption, etc. Therefore, non-volatile memories are widely used in the field of in-memory computing.
[0003] Magnetic random access memory (MRAM) in non-volatile storage technology is widely used in in-memory operations. It is mainly divided into two types: spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM). The latest unipolar switching spin-orbit torque magnetic random access memory (US-SOT-MRAM) has the following advantages compared to traditional SOT-MRAM and STT-MRAM:
[0004] 1. Fast read and write speed, the read and write current is in the microampere level; 2. The conversion current of writing 1 and writing 0 is symmetric; 3. Only read operation has current flowing through the oxide layer, and oxide layer penetration will not occur; 4. By adjusting the ratio of field torque and damping torque, unassisted flipping without external magnetic field can be achieved, reducing power consumption.
[0005] After the write current reaching the threshold size in any direction on the heavy metal strip of US-SOT-MRAM, the magnetization direction of its free layer will not flip instantaneously and completely, but it takes nearly several nanoseconds of recovery time to completely flip the magnetization direction. This period of recovery time occurs between two steps of the operation logic design, greatly increasing the time required for the entire operation logic and generating data errors under specific operations. This will result in a large gap in speed and reliability between the in-memory operations implemented by it and other non-volatile storage technologies. Therefore, how to optimize for the recovery time of the free layer magnetization flipping is a very crucial issue. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory, which optimizes four operation logic steps in the memory array to minimize the impact of the recovery time of the free layer magnetization switching in the write operation, and improves the speed and reduces the power consumption by avoiding data write-back operations.
[0007] To achieve the above technical objectives, the technical solution adopted by the present invention is as follows:
[0008] A method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory, comprising:
[0009] Step 1: Design the TRS logic and the RD logic through the basic read logic and write logic in the array;
[0010] Step 2: Based on the unipolar switching characteristics of the spin-orbit torque magnetic memory, design the in-memory operation logic based on the read logic, write logic, TRS logic, and RD logic, including: two-input AND, two-input OR, three-input majority selection, and 1-bit full adder logic.
[0011] To optimize the above technical solution, the specific measures also include:
[0012] The above-mentioned TRS refers to: for two memory cells A and B in the same column of the memory array, different magnitudes of current are generated by controlling the resistance value difference of the storage in cell A to perform a write logic operation on the cell B to be written.
[0013] The above-mentioned RD logic refers to: using the result latch principle in the read circuit to delay the read result, so that the next step can perform a selection logic based on the read circuit result.
[0014] The above Step 2 designs the in-memory operation logic according to the following design criteria:
[0015] 1) Place the write logic and the TRS logic as much as possible at the last step of the entire operation logic steps;
[0016] 2) Increase the write voltage;
[0017] 3) When the operation logic involves multiple steps, perform the flipping logic on different memory cells. After a memory cell is flipped, reduce the write logic and the TRS logic for that memory cell in the subsequent steps;
[0018] 4) If the previous step flips a memory cell and the subsequent step performs the write logic and the TRS logic on the same memory cell, lengthen the interval between the two steps.
[0019] The above-mentioned two-input AND logic is specifically:
[0020] Step 1: Perform a write logic operation on memory cell B3. Turn on transistors WWL1, SLS3, and BLS3 within the cycle, and apply a write current to the heavy metal band of B3.
[0021] Step 2: Perform a read logic operation on memory cell A3. Turn on transistors RWL0 and BLS3 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through memory cell A3, and the read circuit outputs the read result.
[0022] Step 3: When the read result of A3 = 1, perform a TRS logic operation with B3 as the control unit and A3 as the unit to be written.
[0023] When the read result of A3 = 0, no operation is performed.
[0024] The read delay circuit delays the output of the read result, controls the TRS voltage input transistor using the read result, turns on transistors RWL1, WWL0, and SLS3 within the cycle, generates different magnitudes of TRS current according to the resistance value of memory cell B3, and uses this TRS current to change the state of memory cell A3.
[0025] The above two-input OR logic is specifically as follows:
[0026] Step 1: Perform a read logic operation on A2. Turn on transistors RWL0 and BLS2 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through memory cell A2, and the read circuit outputs the read result.
[0027] Step 2: When the read result of A2 = 1, no operation is performed.
[0028] When the read result of A2 = 0, perform a TRS logic with B2 as the control unit and A2 as the unit to be written.
[0029] The read delay circuit delays the output of the read result, controls the TRS voltage input transistor using the read result, and turns on transistors RWL1, WWL0, and SLS2 within the cycle.
[0030] The above three-input majority logic is specifically as follows:
[0031] Step 1: Perform a TRS logic operation with B1 as the control unit and C1 as the unit to be written. Turn on transistors RWL1, WWL2, and SLS1 within the cycle, generate different magnitudes of TRS current according to the resistance value of memory cell B1, and use this TRS current to change the state of memory cell A1.
[0032] Step 2: Perform TRS logic operation with A1 as the control unit and B1 as the unit to be written. Turn on transistors RWL0, WWL1, and SLS1 within the cycle. Generate TRS currents of different magnitudes according to the resistance value of the B1 storage unit, and use this TRS current to change the state of the A1 storage unit.
[0033] Step 3: Perform read logic operation on C1. Turn on transistors RWL2 and BLS1 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through the storage unit A1, and the read circuit outputs the read result.
[0034] Step 4: When the C1 read result = 1, no operation is performed; when the C1 read result = 0, perform TRS logic operation with B1 as the control unit and A1 as the unit to be written.
[0035] The read delay circuit delays the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL1, WWL0, and SLS1 within the cycle.
[0036] The above 1-bit full adder logic is specifically as follows:
[0037] Step 1: Perform TRS logic operation with B0 as the control unit and Cin0 as the unit to be written. Turn on transistors RWL2, CL1, and CRWL12 within the cycle. Generate TRS currents of different magnitudes according to the resistance value of the B0 storage unit, and use this TRS current to change the state of the Cin0 storage unit.
[0038] Step 2: Perform read logic on Cin0. Turn on transistors CRWL11 and CRWL12 within the cycle. The carry module of the full adder has an independent read drive circuit, and a read current will flow through the storage unit Cin0, and the read circuit outputs the read result.
[0039] Step 3: When the Cin0 read result = 1, perform TRS logic operation with A0 as the control unit and Cout0 as the unit to be written; when the Cin0 read result = 0, no operation is performed. The read delay circuit delays the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL1, CL2, and CRWL22 within the cycle.
[0040] Step 4: When the Cin0 read result = 1, no operation is performed; when the Cin0 read result = 0, perform TRS logic with B0 as the control unit and Cout0 as the unit to be written. The read delay circuit continues to delay the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL2, CL2, and CRWL22 within the cycle.
[0041] Step 5: When the Cin0 read result = 1, perform write logic on A0; when the Cin0 read result = 0, no operation is performed.
[0042] The read delay circuit continues to delay the output of the read result, and uses the read result to control the write voltage input transistor, turning on transistors SLS0, WWL1, and BLS0 within the cycle.
[0043] The present invention has the following beneficial effects:
[0044] In view of the unipolar switching characteristic of the novel SOT-MRAM, the present invention realizes four operation logics of two-input AND, two-input OR, three-input majority selection, and 1-bit full adder operation through basic read and write operations within the array.
[0045] The present invention can avoid the recovery time problem of the magnetization direction reversal of the free layer of SOT-MRAM to the greatest extent, can eliminate the data write-back operation, reduce power consumption and delay, and improve performance and the speed of operation logic.
[0046] The maximum number of steps required for the four operation logic designs of the present invention is 5 steps, the time for each step can be controlled at about 0.3 nanoseconds, and the power consumption is in the order of dozens of femtojoules. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 is the TRS logic structure diagram;
[0048] Figure 2 is the storage array structure diagram;
[0049] Figure 3 is the 1-bit full adder structure diagram;
[0050] Figure 4 is the method flow chart of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0051] The following further describes the embodiments of the present invention in detail with reference to the accompanying drawings.
[0052] As Figure 4 shown, a method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory includes:
[0053] Step 1: Design the TRS logic and the RD logic through basic read logic and write logic within the array;
[0054] Two basic logics are proposed for the basic read and write logics:
[0055] Tunnel Resistance Switching Logic (TRS) and Read Delay Logic (RD).
[0056] The TRS logic is as Figure 1As shown, for two storage cells A and B in the same column within a storage array, different magnitudes of current are generated through the difference in the resistance values stored in cell A (the control cell) to perform a write logic operation on cell B (the cell to be written).
[0057] The RD logic utilizes the result latch principle in the read circuit to delay the read result, enabling the selection logic in the next step to be based on the read circuit result.
[0058] Step 2: For the unipolar switching characteristic of the spin-orbit torque magnetic memory, based on the read logic, write logic, TRS logic, and RD logic, design the in-memory operation logic, including: two-input AND, two-input OR, three-input majority selection, and 1-bit full adder logic.
[0059] The four operation logics of single-bit two-input AND, two-input OR, three-input majority selection, and 1-bit full adder logic are all implemented by the four basic logics of read logic, write logic, TRS logic, and RD logic. Among them, the write logic and TRS logic will flip the resistance value of the storage cell, and there is a problem of the recovery time of the free layer magnetization direction flip, while the read logic and RD logic do not have this problem. After verification and analysis, the recovery time problem occurs in: the previous step flips the cell of the write logic or the cell to be written in the TRS logic, and the subsequent step performs the write logic on this cell or uses this cell as the cell to be written in the TRS logic.
[0060] To minimize the impact of the recovery time, design the in-memory operation logic following the following design criteria:
[0061] 1. Place the write logic and TRS logic as close as possible to the last step of the entire operation logic.
[0062] 2. Appropriately increase the write voltage.
[0063] 3. When the operation logic involves multiple steps, perform the flip logic on different storage cells as much as possible. After a storage cell is flipped, minimize the write logic and TRS logic on this cell in the subsequent steps.
[0064] 4. If there is a situation where the previous step flips a storage cell and the subsequent step performs the write logic and TRS logic on the same cell, try to lengthen the interval between the two steps as much as possible.
[0065] Such as Figure 2 As shown, the specific two-input AND logic is as follows:
[0066] Step 1: Perform a write logic operation on storage cell B3. Open transistors WWL1, SLS3, and BLS3 within the cycle, and apply a write current to the heavy metal strip of B3.
[0067] Step 2: Perform a read logic operation on storage unit A3. Transistors RWL0 and BLS3 are turned on within the cycle. Since SL0 is connected to the read circuit, a read current will flow through storage unit A3, and the read circuit outputs a read result.
[0068] Step 3: When the read result of A3 = 1, perform a TRS logic operation with B3 as the control unit and A3 as the unit to be written.
[0069] When the read result of A3 = 0, no operation is performed.
[0070] The read delay circuit delays the output of the read result. The read result is used to control the TRS voltage input transistor. Transistors RWL1, WWL0, and SLS3 are turned on within the cycle. Different magnitudes of TRS currents are generated according to the resistance value of the B3 storage unit, and the state of storage unit A3 is changed using this TRS current.
[0071] As Figure 2 shown, the specific two-input OR logic is as follows:
[0072] Step 1: Perform a read logic operation on A2. Transistors RWL0 and BLS2 are turned on within the cycle. Since SL0 is connected to the read circuit, a read current will flow through storage unit A2, and the read circuit outputs a read result.
[0073] Step 2: When the read result of A2 = 1, no operation is performed.
[0074] When the read result of A2 = 0, perform a TRS logic with B2 as the control unit and A2 as the unit to be written.
[0075] The read delay circuit delays the output of the read result. The read result is used to control the TRS voltage input transistor. Transistors RWL1, WWL0, and SLS2 are turned on within the cycle.
[0076] As Figure 2 shown, the specific three-input majority logic is as follows:
[0077] Step 1: Perform a TRS logic operation with B1 as the control unit and C1 as the unit to be written. Transistors RWL1, WWL2, and SLS1 are turned on within the cycle. Different magnitudes of TRS currents are generated according to the resistance value of the B1 storage unit, and the state of the A1 storage unit is changed using this TRS current.
[0078] Step 2: Perform a TRS logic operation with A1 as the control unit and B1 as the unit to be written. Transistors RWL0, WWL1, and SLS1 are turned on within the cycle. Different magnitudes of TRS currents are generated according to the resistance value of the B1 storage unit, and the state of the A1 storage unit is changed using this TRS current.
[0079] Step 3: Perform a read logic operation on C1. Turn on transistors RWL2 and BLS1 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through memory cell A1, and the read circuit will output a read result.
[0080] Step 4: When the C1 read result = 1, do nothing; when the C1 read result = 0, perform a TRS logic operation with B1 as the control unit and A1 as the unit to be written.
[0081] The read delay circuit delays the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL1, WWL0, and SLS1 within the cycle.
[0082] As Figure 3 shown, the 1-bit full adder logic is specifically as follows:
[0083] Step 1: Perform a TRS logic operation with B0 as the control unit and Cin0 as the unit to be written. Turn on transistors RWL2, CL1, and CRWL12 within the cycle. Generate different magnitudes of TRS current according to the resistance value of the B0 memory cell, and use this TRS current to change the state of the Cin0 memory cell.
[0084] Step 2: Perform a read logic on Cin0. Turn on transistors CRWL11 and CRWL12 within the cycle. The carry module of the full adder has an independent read drive circuit, a read current will flow through memory cell Cin0, and the read circuit will output a read result.
[0085] Step 3: When the Cin0 read result = 1, perform a TRS logic operation with A0 as the control unit and Cout0 as the unit to be written; when the Cin0 read result = 0, do nothing. The read delay circuit delays the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL1, CL2, and CRWL22 within the cycle.
[0086] Step 4: When the Cin0 read result = 1, do nothing; when the Cin0 read result = 0, perform a TRS logic with B0 as the control unit and Cout0 as the unit to be written. The read delay circuit continues to delay the output of the read result, uses the read result to control the TRS voltage input transistor, and turns on transistors RWL2, CL2, and CRWL22 within the cycle.
[0087] Step 5: When the Cin0 read result = 1, perform a write logic on A0; when the Cin0 read result = 0, do nothing;
[0088] The read delay circuit continues to delay the output of the read result, uses the read result to control the write voltage input transistor, and turns on transistors SLS0, WWL1, and BLS0 within the cycle.
[0089] The realized logic is summarized as follows: Two-input AND logic: A3 = AND(A3, B3); two-input OR logic: A2 = OR(A2, B2); three-input majority logic: A1 = MAJ(A1, B1, C1); 1-bit full adder logic: A0 = A0 + B0 + Cin0, Cout0 = carry;
[0090] All output results directly overwrite the input results, thus removing the data write-back logic.
[0091] In the two-input AND logic design, although the storage unit B3 is flipped in step one, in step three, B3 is used as the control unit of the TRS logic, and there is an intermediate step, so the recovery time has little impact on this logic. The written unit A3 in step three will be flipped. Since it is in the last step of this operation logic, its recovery time can be placed between the two operation logics. This time involves the reading and transmission of operation logic data and can be recovered in parallel.
[0092] In the two-input OR logic design, the TRS logic that will have a state flip is placed in the last step, and its recovery time is considered in the operation logic.
[0093] In the three-input majority logic design, the storage unit C1 is flipped in step one, and the read logic of C1 is performed in step three, so its recovery time does not need to be considered; the storage unit B1 is flipped in step two, and B1 is used as the control unit of the TRS logic in step four, so its recovery time also does not need to be considered.
[0094] In the 1-bit full adder logic design:
[0095] The storage unit Cin0 is flipped in step one;
[0096] The read logic of Cin0 is performed in step two, so its recovery time does not need to be considered;
[0097] Both step three and step four will flip the storage unit Cout0, but these two steps will not occur simultaneously, so the recovery time can be considered outside the logic;
[0098] The storage unit A0 is flipped in step five. Since it is in the last step, its recovery time is considered in the operation logic.
[0099] The above is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.
Claims
1. A method for designing in-memory operation logic based on a unipolarity switching spin-orbit torque magnetic memory, characterized in that, Including: Step 1: Design the TRS logic and RD logic through the basic read logic and write logic within the array; Step 2: For the unipolar switching characteristic of the spin-orbit torque magnetic memory, design the in-memory operation logic based on the read logic, write logic, TRS logic, and RD logic, including: two-input AND, two-input OR, three-input majority, and 1-bit full adder logic; The TRS logic refers to: for two memory cells A and B in the same column of the memory array, different magnitudes of current are generated by controlling the resistance value difference stored in cell A to perform a write logic operation on the cell B to be written; The RD logic refers to: using the result latch principle in the read circuit, delaying the read result so that the next step can perform a selection logic based on the read circuit result.
2. The method for designing in-memory operation logic based on a unipolarity switching spin-orbit torque magnetic memory according to claim 1, wherein The in-memory operation logic in Step 2 is designed following the following design criteria: 1) Place the write logic and TRS logic in the last step of the entire operation logic process; 2) Increase the write voltage; 3) When the operation logic involves multiple steps, perform a flip logic on different memory cells. After a memory cell is flipped, reduce the write logic and TRS logic for that memory cell in subsequent steps; 4) If there is a situation where the memory cell is flipped in the previous step and the write logic and TRS logic are performed on the same memory cell in the subsequent step, lengthen the interval between the two steps.
3. A method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory according to claim 1 or 2, characterized in that Assume that the two-input AND logic circuit includes two SOT-MTJ devices in the same column of the array and the corresponding read / write control circuits. In the array, it has a basic arrangement structure of 2-transistor 1-MTJ, 2T1MTJ. MTJA3 and MTJB3 store two input values respectively, and the AND logic result is stored covering MTJA3. Then the two-input AND logic is specifically as follows: Step 1: Perform a write logic operation on memory cell B3. In the cycle, turn on transistors WWL1, SLS3, and BLS3, and apply a write current to the heavy metal band of B3; Step 2: Perform a read logic operation on memory cell A3. In the cycle, turn on transistors RWL0 and BLS3. Since SL0 is connected to the read circuit, a read current will flow through memory cell A3, and the read circuit outputs the read result; Step 3: When the read result of A3 = 1, perform a TRS logic operation with B3 as the control unit and A3 as the cell to be written; When the read result of A3 = 0, no operation is performed; The read delay circuit delays the output of the read result, uses the read result to control the TRS voltage input transistor, turns on transistors RWL1, WWL0, and SLS3 in the cycle, generates different magnitudes of TRS current according to the resistance value of memory cell B3, and uses this TRS current to change the state of memory cell A3.
4. A method for designing in-memory computing logic based on a unipolarity-rotated spin-orbit torque magnetic memory according to claim 1 or 2, characterized in that, Assume that the two-input OR logic circuit includes two SOT-MTJ devices in the same column of the array and the corresponding read / write control circuits. In the array, it has a basic arrangement structure of 2T1MTJ. MTJA2 and MTJB2 store two input values respectively, and the OR logic result is stored covering MTJA2. Then the two-input OR logic is specifically as follows: Step 1: Perform a read logic operation on A2. Turn on transistors RWL0 and BLS2 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through the memory cell A2, and the read circuit will output a read result. Step 2: When the read result of A2 = 1, no operation is performed. When the read result of A2 = 0, perform the TRS logic with B2 as the control unit and A2 as the unit to be written. The read delay circuit delays the output of the read result. Use the read result to control the TRS voltage input transistor, and turn on transistors RWL1, WWL0, and SLS2 within the cycle.
5. A method for designing in-memory operation logic based on a unipolar switching spin-orbit torque magnetic memory according to claim 1 or 2, characterized in that, Assume that the three-input majority logic circuit includes three SOT-MTJ devices in the same column of the array and the corresponding read / write control circuits. In the array, it has a basic 2T1MTJ layout structure. MTJA1, MTJB1, and MTJC1 store three input values respectively, and the majority logic result overwrites the value stored in MTJA1. Then the three-input majority logic is specifically as follows: Step 1: Perform the TRS logic operation with B1 as the control unit and C1 as the unit to be written. Turn on transistors RWL1, WWL2, and SLS1 within the cycle. Generate different magnitudes of TRS currents according to the resistance value of the B1 memory cell, and use this TRS current to change the state of the A1 memory cell. Step 2: Perform the TRS logic operation with A1 as the control unit and B1 as the unit to be written. Turn on transistors RWL0, WWL1, and SLS1 within the cycle. Generate different magnitudes of TRS currents according to the resistance value of the B1 memory cell, and use this TRS current to change the state of the A1 memory cell. Step 3: Perform a read logic operation on C1. Turn on transistors RWL2 and BLS1 within the cycle. Since SL0 is connected to the read circuit, a read current will flow through the memory cell A1, and the read circuit will output a read result. Step 4: When the read result of C1 = 1, no operation is performed; when the read result of C1 = 0, perform the TRS logic operation with B1 as the control unit and A1 as the unit to be written. The read delay circuit delays the output of the read result. Use the read result to control the TRS voltage input transistor, and turn on transistors RWL1, WWL0, and SLS1 within the cycle.
6. A method for designing in-memory operation logic based on a unipolarity-rotated spin-orbit torque magnetic memory according to claim 1 or 2, characterized in that Assume that the 1-bit full adder logic circuit includes two SOT-MTJ devices in the same column of the array and two carry storage SOT-MTJ devices outside the array, as well as the corresponding read / write control circuits. In the array, it has a basic 2T1MTJ layout structure. MTJA0 and MTJB0 store 1-bit addend and augend respectively, MTJCin0 and MTJCout0 store the generated carry information, and the final full adder result overwrites the value stored in MTJA1, and the carry information is stored in MTJCout0. Then the 1-bit full adder logic is specifically as follows: Step 1: Perform the TRS logic operation with B0 as the control unit and Cin0 as the unit to be written. Turn on transistors RWL2, CL1, and CRWL12 within the cycle. Generate different magnitudes of TRS currents according to the resistance value of the B0 memory cell, and use this TRS current to change the state of the Cin0 memory cell. Step 2: Perform read logic on Cin0. Turn on transistors CRWL11 and CRWL12 within the cycle. The carry module of the full adder has an independent read drive circuit. A read current will flow through the storage cell Cin0, and the read circuit outputs the read result. Step 3: When the Cin0 read result = 1, perform a TRS logic operation with A0 as the control unit and Cout0 as the unit to be written; when the Cin0 read result = 0, do not operate. The read delay circuit delays the output of the read result and uses the read result to control the TRS voltage input transistor. Turn on transistors RWL1, CL2, and CRWL22 within the cycle. Step 4: When the Cin0 read result = 1, do not operate; when the Cin0 read result = 0, perform TRS logic with B0 as the control unit and Cout0 as the unit to be written. The read delay circuit continues to delay the output of the read result and uses the read result to control the TRS voltage input transistor. Turn on transistors RWL2, CL2, and CRWL22 within the cycle. Step 5: When the Cin0 read result = 1, perform write logic on A0; when the Cin0 read result = 0, do not operate. The read delay circuit continues to delay the output of the read result and uses the read result to control the write voltage input transistor. Turn on transistors SLS0, WWL1, and BLS0 within the cycle.