Memory circuit and operating method thereof

Abstract

The present disclosure relates to a memory circuit and an operating method thereof. A memory circuit includes: a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter, and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal and generate a first signal. The first N-type transistor is coupled to the NAND logic gate and is configured to receive a first precharge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage source and is configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate and is configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate and is configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

Description

Technical Field

[0001] The present disclosure relates to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured for data storage. As ICs become smaller and more complex, the resistance of the wires within these digital devices has also changed, affecting their operating voltage and overall IC performance. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a memory circuit is provided, comprising: a NAND logic gate configured to receive a first bit line signal and a second bit line signal and generate a first signal; a first N-type transistor coupled to the NAND logic gate and configured to receive a first precharge signal; a second N-type transistor coupled to the first N-type transistor and a reference voltage source and configured to receive a first clock signal; a first inverter coupled to the NAND logic gate and configured to output a data signal inverted from the first signal; and a first latch coupled to the NAND logic gate and configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

[0004] According to a second aspect of the present disclosure, a memory circuit is provided, comprising: a NAND logic gate configured to receive a first bit line signal and a second bit line signal and to generate a first signal in response to the first bit line signal and the second bit line signal; a first N-type transistor having: a first drain coupled to a first voltage source node of the NAND logic gate; a first gate configured to receive a first precharge signal; and a first source coupled to the first node; a second N-type transistor having: a second drain coupled to the first drain and the first voltage source node of the NAND logic gate; a second gate configured to receive a second precharge signal different from the first precharge signal; and a second source coupled to the first source and the first node; a first latch coupled to the NAND logic gate via a second node and configured to latch the first signal in response to at least the first precharge signal or the second precharge signal; and a first inverter coupled to the NAND logic gate and configured to output a data signal inverted from the first signal.

[0005] According to a third aspect of the present disclosure, a method for operating a memory circuit is provided, the method comprising: receiving a first bit line signal and a second bit line signal through a NAND logic gate circuit; generating a first signal through the NAND logic gate circuit in response to the first bit line signal and the second bit line signal, wherein generating the first signal comprises: enabling the NAND logic gate circuit in response to at least a first precharge signal; and latching a state of the first signal through a latch in response to at least the first precharge signal or a first clock signal, the latch comprising a first inverter and a second inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a circuit diagram of a memory circuit according to some embodiments.

[0008] Figure 2 is a circuit diagram of a circuit according to some embodiments.

[0009] Figure 3 is a circuit diagram of a NAND logic gate circuit according to some embodiments.

[0010] Figure 4A is a circuit diagram of a pull-up circuit according to some embodiments.

[0011] Figure 4B is a circuit diagram of a pull-up circuit according to some embodiments.

[0012] Figure 4C is a circuit diagram of a circuit according to some embodiments.

[0013] Figure 4D is a circuit diagram of a circuit according to some embodiments.

[0014] Figure 4E is a circuit diagram of a circuit according to some embodiments.

[0015] Figure 5 is a timing diagram of waveforms of a memory circuit according to some embodiments.

[0016] Figure 6 is a circuit diagram of a circuit according to some embodiments.

[0017] Figure 7 is a circuit diagram of a circuit according to some embodiments.

[0018] Figure 8is a circuit diagram of a circuit according to some embodiments.

[0019] Figure 9A is a circuit diagram of a circuit according to some embodiments.

[0020] Figure 9B is a timing diagram of waveforms of a memory circuit according to some embodiments.

[0021] Figure 10 is a circuit diagram of a circuit according to some embodiments.

[0022] Figure 11 is a flow chart of a method of operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, materials, values, steps, and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, by itself, indicate the relationship between the various embodiments and / or configurations being discussed.

[0024] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0025] According to some embodiments, a memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter, and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal and to generate a first signal.

[0026] The first N-type transistor is coupled to the NAND logic gate and configured to receive a first precharge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage source and configured to receive a first clock signal.

[0027] In some embodiments, the first inverter is coupled to the NAND logic gate and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate and configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

[0028] In some embodiments, a first N-type transistor is coupled between a second N-type transistor and a first voltage source node of a NAND logic gate. In some embodiments, by including the first N-type transistor between the second N-type transistor and the first voltage source node of the NAND logic gate, the first N-type transistor can be disabled, thereby disabling the NAND logic gate circuit in response to a first pre-charge signal. In some embodiments, by disabling the NAND logic gate circuit in response to the first pre-charge signal, the memory circuit reduces the number of toggling transistors, thereby reducing power consumption, compared to other approaches.

[0029] Memory circuit

[0030] Figure 1 is a circuit diagram of a memory circuit 100 according to some embodiments. Figure 1 In the embodiment of FIG. 1 , integrated circuit 100 is a memory macro.

[0031] Memory circuit 100 includes a memory cell array 102, a local input / output (LIO) circuit 104, and a global input / output (GIO) circuit 106. Memory cell array 102 is coupled to LIO circuit 104 via bit lines BL. LIO circuit 104 is coupled to GIO circuit 106 via global bit lines GBL.

[0032] Memory cell array 102 includes an array of memory cells having N rows and M columns, where M and N are positive integers. For simplicity and ease of illustration, memory cell array 102 is shown with a single memory cell 102 a. In some embodiments, each memory cell in memory cell array 102 is configured to store a corresponding bit of data.

[0033] The rows of cells in the memory cell array 102 are arranged in a first direction X (not shown). The columns of cells in the memory cell array 102 are arranged in a second direction Y (not shown). The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X.

[0034] Memory cell array 102 also includes N word lines (not shown for ease of illustration) coupled to respective rows of memory cells in memory cell array 102. Each row in memory cell array 102 is associated with a respective word line. Each word line WL extends in a first direction X (not shown).

[0035] The memory cell array 102 also includes M bit lines coupled to respective columns of memory cells in the memory cell array 102. Each column in the memory cell array 102 is associated with a respective bit line. Each bit line BL extends in a second direction Y (not shown).

[0036] Each memory cell in the memory cell array 102 is coupled to a corresponding bit line BL. In some embodiments, the memory cell array 102 is a single-ended memory, and thus each memory cell in the memory cell array 102 is coupled to a corresponding bit line BL.

[0037] In some embodiments, the memory cell array 102 is a two-terminal memory, and thus each memory cell in the memory cell array 102 is coupled to a corresponding pair of bit lines BL. The bit lines are configured to carry bit line signals (not shown).

[0038] In some embodiments, the memory cell array 102 is a non-volatile random access memory (NVRAM) array. In some embodiments, each memory cell in the memory cell array 102 corresponds to a static random access memory (SRAM) cell. Different types of memory cells in the memory cell array 102 are within the contemplated scope of the present disclosure. For example, in some embodiments, each memory cell in the memory cell array 102 is a magnetoresistive random access memory (MRAM). In some embodiments, each memory cell in the memory cell array 102 corresponds to a resistive random access memory (RRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a dynamic random access memory (DRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a one-time programmable (OTP) memory cell. In some embodiments, the memory cell array 102 corresponds to flash memory. Other configurations of the memory cell array 102 are within the scope of the present disclosure.

[0039] LIO circuit 104 is configured to receive bit line signals (not shown) on corresponding bit lines from memory cell array 102. In some embodiments, LIO circuit 104 includes a sense amplifier (not shown), wherein the bit line signals from memory cell array 102 are amplified and then output by LIO circuit 104 to GIO circuit 106 as global bit line signals GBL_UP and GBL_DN. In some embodiments, at least global bit line signal GBL_UP or GBL_DN corresponds to read data stored in memory cell array 102. In some embodiments, memory cell array 102 is divided into an upper portion and a lower portion, and global bit line signal GBL_UP corresponds to read data stored in the upper portion of memory cell array 102, and global bit line signal GBL_DN corresponds to read data stored in the lower portion of memory cell array 102. Other configurations of LIO circuit 104 are within the scope of the present disclosure.

[0040] GIO circuit 106 receives global bit line signals GBL_UP and GBL_DN on global bit line GBL from LIO circuit 104. GIO circuit 106 is configured to output data signal DOUT in response to at least global bit line signals GBL_UP and GBL_DN. Data signal DOUT corresponds to data stored in memory cell array 102. In some embodiments, data signal DOUT corresponds to at least global bit line signal GBL_UP or GBL_DN.

[0041] In some embodiments, LIO circuit 104 and GIO circuit 106 are combined into a single IO circuit. In some embodiments, at least LIO circuit 104 or GIO circuit 106 includes a latch circuit (not shown) configured to latch data stored in memory cell array 102. Other configurations of GIO circuit 106 are within the scope of the present disclosure.

[0042] Other configurations of memory circuit 100 are within the scope of this disclosure.

[0043] Figure 2 is a circuit diagram of circuit 200 according to some embodiments.

[0044] Circuit 200 is Figure 1 In some embodiments, the circuit 200 is a readout circuit configured to read data stored in the memory cell array 102.

[0045] Circuit 200 includes a NAND logic gate 220, N-type metal oxide semiconductor (NMOS) transistors N1, N2, N3, N4, N5, N6, and N7, P-type metal oxide semiconductor (PMOS) transistors P1, P2, P3, P4, and P5, and inverters I1 and I2.

[0046] The first input terminal Nd1 of the NAND logic gate 220 is configured to receive the global bit line signal GBL_UP. In some embodiments, the first input terminal Nd1 of the NAND logic gate 220 is directly coupled to Figure 4A The second input terminal Nd2 of the NAND logic gate 220 is configured to receive the global bit line signal GBL_DN. In some embodiments, the second input terminal Nd2 of the NAND logic gate 220 is directly coupled to Figure 4B Pull-up device 400B.

[0047] The output of the NAND logic gate 220 is configured to output a signal QB. The NAND logic gate 220 is configured to generate the signal QB based on the global bit line signal GBL_UP and the global bit line signal GBL_DN. The output of the NAND logic gate 220 is coupled to at least the node Nd5.

[0048] NAND logic gate 220 has a first voltage source node Nd3 and a second voltage source node Nd4. In some embodiments, first voltage source node Nd3 of NAND logic gate 220 is configured to receive power supply voltage VDD. In some embodiments, second voltage source node Nd4 of NAND logic gate 220 is configured to receive reference power supply voltage VSS. In some embodiments, reference power supply voltage VSS is different from power supply voltage VDD.

[0049] The gate terminal of PMOS transistor P1 is configured to receive clock signal RCKB. In some embodiments, at least clock signal RCKB or RCK (described below) is a read clock signal configured to cause circuit 200 to read data stored in memory cell array 102. The source terminal of PMOS transistor P1 is coupled to voltage source node VDDN. Voltage source node VDDN has power supply voltage VDD. The drain terminal of PMOS transistor P1 is coupled to first voltage source node Nd3 of NAND logic gate 220.

[0050] In some embodiments, if the PMOS transistor P1 is turned off in response to the clock signal RCKB, the first voltage source node Nd3 of the NAND logic gate 220 is electrically floating. In some embodiments, if the PMOS transistor P1 is turned on in response to the clock signal RCKB, the first voltage source node Nd3 of the NAND logic gate 220 is coupled to the power supply voltage node VDDN and receives the power supply voltage VDD.

[0051] The gate terminal of the NMOS transistor N1 is configured to receive a clock signal RCK. In some embodiments, the clock signal RCK is in phase with the clock signal RCKB, and vice versa. The source terminal of the NMOS transistor N1 is coupled to a reference voltage source node VSSN. The reference voltage source node VSSN has a reference power supply voltage VSS.

[0052] A drain terminal of the NMOS transistor N1 , a source terminal of the NMOS transistor N2 , and a source terminal of the NMOS transistor N3 are each coupled together.

[0053] The gate terminal of the NMOS transistor N2 is configured to receive the precharge signal PCHB_UP. The gate terminal of the NMOS transistor N3 is configured to receive the precharge signal PCHB_DN. The drain terminal of the NMOS transistor N2 and the drain terminal of the NMOS transistor N3 are each coupled together and further coupled to the second voltage source node Nd4 of the NAND logic gate 220.

[0054] In some embodiments, if the NMOS transistor N1 is turned off in response to the clock signal RCKB, the second voltage source node Nd4 of the NAND logic gate 220 is electrically floating. In some embodiments, if the NMOS transistors N2 and N3 are turned off in response to the respective precharge signals PCHB_UP and PCHB_DN, the second voltage source node Nd4 of the NAND logic gate 220 is electrically floating.

[0055] In some embodiments, if the NMOS transistor N1 is turned on in response to the clock signal RCK and at least one of the NMOS transistors N2 or N3 is turned on in response to the corresponding precharge signal PCHB_UP or PCHB_DN, the second voltage source node Nd4 of the NAND logic gate 220 is coupled to the reference power supply voltage VSSN and receives the reference power supply voltage VSS.

[0056] The input of inverter I1, node Nd5, the output of NAND logic gate 220, the input of inverter I2, the drain of NMOS transistor N5, and the drain of PMOS transistor P5 are coupled together. The input of inverter I1 is configured to receive signal QB from at least node Nd5. In some embodiments, the input of inverter I1 is configured to receive signal QB from NAND logic gate 220. In some embodiments, the input of inverter I1 is configured to receive signal QB from the drain of NMOS transistor N5 and the drain of PMOS transistor P5.

[0057] The output terminal of the inverter I1 is configured to output an output data signal DOUT. In some embodiments, the output data signal DOUT corresponds to the output data signal from Figure 1The output signal of the memory cell array 102. In some embodiments, the output data signal DOUT is inverted to the signal QB, and vice versa.

[0058] The input of inverter I2 is configured to receive signal QB from at least node Nd5. In some embodiments, the input of inverter I2 is configured to receive signal QB from NAND logic gate 220. In some embodiments, the input of inverter I2 is configured to receive signal QB from the drain of NMOS transistor N5 and the drain of PMOS transistor P5.

[0059] The output of inverter I2 is configured to output signal QBB. In some embodiments, signal QBB is in phase inversion of signal QB, and vice versa. The output of inverter I2 is coupled to the gate of NMOS transistor N5 and the gate of PMOS transistor P5.

[0060] The gate terminal of the PMOS transistor P2 is configured to receive the clock signal RCK. The source terminal of the PMOS transistor P2 is coupled to a voltage source node VDDN.

[0061] A drain terminal of the PMOS transistor P2 , a drain terminal of the PMOS transistor P4 , and a source terminal of the PMOS transistor P5 are each coupled together.

[0062] The gate terminal of the PMOS transistor P3 is configured to receive the precharge signal PCHB_UP. The source terminal of the PMOS transistor P3 is coupled to the voltage source node VDDN. In some embodiments, the source terminal of the PMOS transistor P3 and the source terminal of the PMOS transistor P2 are coupled together.

[0063] The drain terminal of the PMOS transistor P3 and the source terminal of the PMOS transistor P4 are coupled together. The gate terminal of the PMOS transistor P4 is configured to receive the precharge signal PCHB_DN.

[0064] The gate terminal of the PMOS transistor P5, the gate terminal of the NMOS transistor N5, and the output terminal of the inverter I2 are each coupled together. The gate terminal of the PMOS transistor P5 is configured to receive the signal QBB. The gate terminal of the NMOS transistor N5 is configured to receive the signal QBB. The drain terminal of the PMOS transistor P5 and the drain terminal of the NMOS transistor N5 are coupled together.

[0065] The drain terminal of the PMOS transistor P5 or the drain terminal of the NMOS transistor N5 is configured to output a signal QBB1. In some embodiments, the signal QBB1 is a latched version of the signal QB. In some embodiments, the signal QBB1 is inversely proportional to the signal QBB, and vice versa. In some embodiments, the signal QBB1 corresponds to a feedback signal fed back to the node Nd5.

[0066] The gate terminal of the NMOS transistor N4 is configured to receive the clock signal RCKB, and the source terminal of the NMOS transistor N4 is coupled to the reference voltage source node VSSN.

[0067] A drain terminal of the NMOS transistor N4 , a drain terminal of the NMOS transistor N6 , and a source terminal of the NMOS transistor N5 are each coupled together.

[0068] The gate terminal of the NMOS transistor N6 is configured to receive the precharge signal PCHB_UP. The source terminal of the NMOS transistor N6 and the drain terminal of the NMOS transistor N7 are coupled together.

[0069] The gate terminal of the NMOS transistor N7 is configured to receive the precharge signal PCHB_DN. The source terminal of the NMOS transistor N7 is coupled to the reference voltage source node VSSN. In some embodiments, the source terminal of the NMOS transistor N7 and the source terminal of the NMOS transistor N4 are coupled together.

[0070] In some embodiments, the PMOS transistor P5 and the NMOS transistor N5 form an inverter 13. In some embodiments, the inverter 13, the PMOS transistor P2, and the NMOS transistor N4 form a tri-state inverter (not labeled).

[0071] In some embodiments, when inverter I3 is coupled to voltage source node VDDN and reference supply voltage node VSSN, inverter I3 is enabled. In some embodiments, when inverter I3 is decoupled from voltage source node VDDN and reference supply voltage node VSSN, inverter I3 is disabled. The source terminal of PMOS transistor P5 has voltage source node Nd6, and the source terminal of NMOS transistor N5 has voltage source node Nd7. For example, in some embodiments, voltage source node Nd6 of PMOS transistor P5 is coupled to supply voltage node VDDN and configured to receive supply voltage VDD, and voltage source node Nd7 of NMOS transistor N5 is coupled to reference supply voltage node VSSN and configured to receive reference supply voltage VSS, thereby enabling inverter I3. For example, in some embodiments, voltage source node Nd6 of PMOS transistor P5 is not coupled to supply voltage node VDDN, and voltage source node Nd7 of NMOS transistor N5 is not coupled to reference supply voltage node VSSN, thereby disabling inverter I3.

[0072] In some embodiments, when inverter I3 is enabled or disabled, latch 230 is enabled or disabled, respectively. In some embodiments, when inverter I3 is enabled, inverters I2 and I3 are serially coupled inverters and thus function as latch 230 configured to latch the state of signal QB.

[0073] Latch 230 is configured to maintain the states of node Nd5 and signal QB and data signal DOUT when latch 230 is enabled. In some embodiments, latch 230 is enabled when NAND logic gate 220 is electrically floating or disabled, and vice versa.

[0074] In some embodiments, inverter I2, PMOS transistors P2 and P5, and NMOS transistors N4 and N5 form a latch 230 configured to latch the state of signal QB. For example, in some embodiments, when signal RCK is logic high, PMOS transistor P2 and NMOS transistor N4 are turned on, and thus PMOS transistor P5 and NMOS transistor N5 function as inverter I3. In other words, inverter I3 is enabled. In these embodiments, signal RCK is logic high, turning on PMOS transistor P2, and signal RCKB is logic low, turning on NMOS transistor N4. In response to PMOS transistor P2 and NMOS transistor N4 turning on, respective voltage source nodes Nd6 and Nd7 are electrically coupled to respective power supply voltage nodes VDDN and reference power supply voltage nodes VSSN. Therefore, in these embodiments, inverter I2, PMOS transistors P2 and P5, and NMOS transistors N4 and N5 latch the state of signal QB.

[0075] In some embodiments, inverter I2, PMOS transistors P3, P4, and P5, and NMOS transistors N5, N6, and N7 form a latch 230 configured to latch the state of signal QB. For example, in some embodiments, when both pre-charge signal PCHB_UP and pre-charge signal PCHB_DN are logic low, corresponding PMOS transistors P3 and P4, as well as corresponding NMOS transistors N6 and N7, are turned on, and thus PMOS transistor P5 and NMOS transistor N5 function as inverter I3. In other words, inverter I3 is enabled. In these embodiments, pre-charge signal PCHB_UP being logic low turns on PMOS transistor P3 and also causes pre-charge signal PCH_UP to be logic high, thereby turning on NMOS transistor N6. Pre-charge signal PCHB_DN being logic low turns on PMOS transistor P4 and also causes pre-charge signal PCH_DN to be logic high, thereby turning on NMOS transistor N7. In response to PMOS transistors P3 and P4 and NMOS transistors N6 and N7 being turned on, respective voltage source nodes Nd6 and Nd7 are electrically coupled to respective power supply voltage node VDDN and reference power supply voltage node VSSN. Thus, in these embodiments, inverter I2, PMOS transistors P3, P4, and P5, and NMOS transistors N5, N6, and N7 latch the state of signal QB.

[0076] Other configurations of transistors, numbers of transistors, or types of transistors in circuit 200 are within the scope of the present disclosure.

[0077] NAND logic gate circuit

[0078] Figure 3 is a circuit diagram of a NAND logic gate circuit 300 according to some embodiments.

[0079] NAND logic gate circuit 300 can be used as Figure 2 and Figures 6-10 NAND logic gate 220.

[0080] NAND logic gate circuit 300 is Figure 2 The embodiments of the NAND logic gate 220 are described below, and thus similar detailed description is omitted.

[0081] The NAND logic gate circuit 300 includes PMOS transistors P8 and P9 and NMOS transistors N8 and N9.

[0082] The gate terminal of the PMOS transistor P8 is configured to receive the global bit line signal GBL_UP. The source terminal of the PMOS transistor P8 is coupled to Figure 2 The first voltage source node Nd3 of the NAND logic gate 220 is connected to the NAND logic gate 220.

[0083] The gate terminal of the PMOS transistor P9 is configured to receive the global bit line signal GBL_DN. The source terminal of the PMOS transistor P9 is coupled to Figure 2 The first voltage source node Nd3 of the NAND logic gate 220. In some embodiments, the source terminal of the PMOS transistor P8 and the source terminal of the PMOS transistor P9 are coupled together.

[0084] The drain terminal of the PMOS transistor P8 , the drain terminal of the PMOS transistor P9 , and the drain terminal of the NMOS transistor N8 are coupled together.

[0085] The gate terminal of the NMOS transistor N8 is configured to receive the global bit line signal GBL_UP. The source terminal of the NMOS transistor N8 and the drain terminal of the NMOS transistor N9 are coupled together.

[0086] A gate terminal of the NMOS transistor N9 is configured to receive the global bit line signal GBL_DN. A source terminal of the NMOS transistor N9 is coupled to the second voltage source node Nd4.

[0087] Other configurations of transistors, numbers of transistors, or types of transistors in NAND logic gate circuit 300 are within the scope of the present disclosure.

[0088] Pull-up circuit

[0089] Figure 4A is a circuit diagram of a pull-up circuit 400A according to some embodiments.

[0090] The pull-up circuit 400A can be used with Figure 2 Integrated circuit 200 or Figure 3 The NAND logic gate circuit 300 is used together with the NAND logic gate circuit 300, and thus similar detailed description is omitted.

[0091] For example, in some embodiments, the pull-up circuit 400A may be connected to Figure 2 The circuit 200 or corresponding Figures 6-10 The circuits 600 - 1000 are used together and are coupled to a first input terminal (eg, node Nd1 ) of the NAND logic gate 220 .

[0092] For example, in some embodiments, the pull-up circuit 400A may be connected to Figure 3 The NAND logic gate circuit 300 is used together with the NAND logic gate circuit 300 and is coupled to the first input terminal (eg, node Nd1 ) of the NAND logic gate 220 .

[0093] Pull-up circuit 400A is coupled to node Nd1. Pull-up circuit 400A is configured to receive a precharge signal PCHB_UP. Pull-up circuit 400A is configured to precharge node Nd1 to a predetermined voltage level in response to precharge signal PCHB_UP. In some embodiments, the predetermined voltage level corresponds to a logical value, such as a logic high or a logic low. In some embodiments, the predetermined voltage level corresponds to a value of power supply voltage VDD or reference power supply voltage VSS. Other configurations of pull-up circuit 400A are within the scope of this disclosure.

[0094] Pull-up circuit 400A includes a PMOS transistor P10. The gate terminal of PMOS transistor P10 is configured to receive a precharge signal PCHB_UP. The source terminal of PMOS transistor P10 is coupled to a voltage source node VDDN. The drain terminal of PMOS transistor P10 is coupled to node Nd1. The voltage at node Nd1 corresponds to global bit line signal GBL_UP. In some embodiments, PMOS transistor P4 is configured to precharge global bit line signal GBL_UP at node Nd1 to a predetermined voltage level in response to precharge signal PCHB_UP.

[0095] Other configurations of transistors, number of transistors, or transistor types for PMOS transistor P10 are within the scope of the present disclosure.

[0096] Figure 4B is a circuit diagram of a pull-up circuit 400B according to some embodiments.

[0097] Pull-up circuit 400B can be used with Figure 2 Integrated circuit 200 or Figure 3 The NAND logic gate circuit 300 is used together with the NAND logic gate circuit 300, and thus similar detailed description is omitted.

[0098] For example, in some embodiments, the pull-up circuit 400B can be connected to Figure 2 The circuit 200 or corresponding Figures 6-10 The circuits 600 - 1000 are used together and are coupled to the second input terminal (eg, node Nd2 ) of the NAND logic gate 220 .

[0099] For example, in some embodiments, the pull-up circuit 400B can be connected to Figure 3 The NAND logic gate circuit 300 is used together with the NAND logic gate circuit 300 and is coupled to the second input terminal (eg, node Nd2 ) of the NAND logic gate 220 .

[0100] Pull-up circuit 400B is coupled to node Nd2. Pull-up circuit 400B is configured to receive a precharge signal PCHB_DN. Pull-up circuit 400B is configured to precharge node Nd2 to a predetermined voltage level in response to precharge signal PCHB_DN. In some embodiments, the predetermined voltage level corresponds to a logic high value or a logic low value. Other configurations of pull-up circuit 400B are within the scope of this disclosure.

[0101] Pull-up circuit 400B includes a PMOS transistor P11. The gate terminal of PMOS transistor P11 is configured to receive precharge signal PCHB_DN. The source terminal of PMOS transistor P11 is coupled to voltage source node VDDN. The drain terminal of PMOS transistor P11 is coupled to node Nd2. The voltage at node Nd2 corresponds to global bit line signal GBL_DN. In some embodiments, PMOS transistor P4 is configured to precharge global bit line signal GBL_DN at node Nd2 to a predetermined voltage level in response to precharge signal PCHB_DN.

[0102] Other configurations of transistors, number of transistors, or transistor types for the PMOS transistor P11 are within the scope of the present disclosure.

[0103] Figure 4C is a circuit diagram of circuit 400C according to some embodiments.

[0104] The circuit 400C is configured to generate a precharge signal PCH_UP and a precharge signal PCHB_UP.

[0105] Circuit 400C can be used with Figure 2 Integrated circuit 200 or Figure 4A The pull-up circuit 400A is used together with the pull-up circuit 400A, and thus similar detailed description is omitted.

[0106] For example, in some embodiments, circuit 400C may be used with Figure 2 The circuit 200 or corresponding Figures 6-10 The transistor 100 is used together with the circuits 600-1000 and is coupled to at least the gate of the NMOS transistor N2, the gate of the PMOS transistor P3, or the gate of the NMOS transistor N6.

[0107] For example, in some embodiments, circuit 400C may be used with Figure 4A The pull-up circuit 400A is used together with the pull-up circuit 400A and is coupled to the gate of the PMOS transistor P10.

[0108] Circuit 400C includes inverter 14 and inverter 15. In some embodiments, circuit 400C is configured to generate precharge signal PCH_UP and precharge signal PCHB_UP.

[0109] Inverter I4 is configured to generate a pre-charge signal PCH_UP in response to the pre-charge signal RPCHB_UP. The input of inverter I4 is configured to receive the pre-charge signal RPCHB_UP. In some embodiments, the pre-charge signal RPCHB_UP is received from an external circuit (not shown). In some embodiments, the input of inverter I4 is coupled to the external circuit (not shown). The output of inverter I4 is configured to output the pre-charge signal PCH_UP to at least the input of inverter I5 or node Nd8. In some embodiments, the pre-charge signal PCH_UP is inverted with the pre-charge signal RPCHB_UP, and vice versa. The output of inverter I4 is coupled to at least the input of inverter I5 or node Nd8.

[0110] In some embodiments, the output of the inverter I4, the node Nd8, and the gate of the NMOS transistor N6 are coupled together. In some embodiments, the gate of the NMOS transistor N6 is configured to receive the precharge signal PCH_UP from the output of the inverter I4.

[0111] Inverter I5 is configured to generate precharge signal PCHB_UP in response to precharge signal PCH_UP. An input of inverter I5 is configured to receive precharge signal PCH_UP. An input of inverter I5 is coupled to at least an output of inverter I4 or node Nd8.

[0112] The output of inverter I5 is configured to output precharge signal PCHB_UP to at least node Nd9. In some embodiments, precharge signal PCHB_UP is inverted to precharge signal PCH_UP, and vice versa. The output of inverter I5 is coupled to at least node Nd9.

[0113] In some embodiments, the output terminal of the inverter I5, the node Nd9, and the gate of the PMOS transistor P3 are coupled together. In some embodiments, the gate of the PMOS transistor P3 is configured to receive the precharge signal PCHB_UP from the output terminal of the inverter I5.

[0114] In some embodiments, the output of the inverter I5, the node Nd9, and the gate of the NMOS transistor N2 are coupled together. In some embodiments, the gate of the NMOS transistor N2 is configured to receive the precharge signal PCHB_UP from the output of the inverter I5.

[0115] In some embodiments, the output terminal of the inverter I5, the node Nd9, and the gate of the PMOS transistor P10 are coupled together. In some embodiments, the gate of the PMOS transistor P10 is configured to receive the precharge signal PCHB_UP from the output terminal of the inverter I5.

[0116] In some embodiments, the output terminal of the inverter I5, the node Nd9, and at least the gate of the NMOS transistor N2, the gate of the PMOS transistor P3, or the gate of the PMOS transistor P10 are each coupled together.

[0117] Other configurations of circuit 400C are within the scope of the present disclosure. Other configurations of the inverters, number of inverters, or type of inverters of at least inverters 14 or 15 are within the scope of the present disclosure.

[0118] Figure 4D is a circuit diagram of a circuit 400D according to some embodiments.

[0119] The circuit 400D is configured to generate a precharge signal PCH_DN and a precharge signal PCHB_DN.

[0120] Circuit 400D can be used with Figure 2 Integrated circuit 200 or Figure 4B The pull-up circuit 400B is used together with the pull-up circuit 400B, and thus similar detailed description is omitted.

[0121] For example, in some embodiments, circuit 400D may be used with Figure 2 The circuit 200 or corresponding Figures 6-10 The transistor 600 is used together with the circuits 600-1000 and is coupled to at least the gate of the NMOS transistor N3, the gate of the PMOS transistor P4, or the gate of the NMOS transistor N7.

[0122] For example, in some embodiments, circuit 400D may be used with Figure 4B The pull-up circuit 400B is used together with the pull-up circuit 400B and is coupled to the gate of the PMOS transistor P11.

[0123] Circuit 400D includes inverter I6 and inverter 17. In some embodiments, circuit 400D is configured to generate precharge signal PCH_DN and precharge signal PCHB_DN.

[0124] Inverter I6 is configured to generate a precharge signal PCH_DN in response to precharge signal RPCHB_DN. The input of inverter I6 is configured to receive precharge signal RPCHB_DN. In some embodiments, precharge signal RPCHB_DN is received from an external circuit (not shown). In some embodiments, the input of inverter I6 is coupled to an external circuit (not shown). The output of inverter I6 is configured to output precharge signal PCH_DN to at least the input of inverter I7 or node Nd10. In some embodiments, precharge signal PCH_DN is inverted with precharge signal RPCHB_DN, and vice versa. The output of inverter I6 is coupled to at least the input of inverter I7 or node Nd10.

[0125] In some embodiments, the output of inverter I6, node Nd10, and the gate of NMOS transistor N7 are coupled together. In some embodiments, the gate of NMOS transistor N7 is configured to receive precharge signal PCH_DN from the output of inverter I6.

[0126] Inverter I7 is configured to generate precharge signal PCHB_DN in response to precharge signal PCH_DN. An input of inverter I7 is configured to receive precharge signal PCH_DN. An input of inverter I7 is coupled to at least an output of inverter I6 or node Nd10.

[0127] The output of inverter I7 is configured to output precharge signal PCHB_DN to at least node Nd11. In some embodiments, precharge signal PCHB_DN is inverted to precharge signal PCH_DN, and vice versa. The output of inverter I7 is coupled to at least node Nd11.

[0128] In some embodiments, the output terminal of the inverter I7, the node Nd11, and the gate of the PMOS transistor P4 are coupled together. In some embodiments, the gate of the PMOS transistor P4 is configured to receive the precharge signal PCHB_DN from the output terminal of the inverter I7.

[0129] In some embodiments, the output terminal of the inverter I7, the node Nd11, and the gate of the NMOS transistor N3 are coupled together. In some embodiments, the gate of the NMOS transistor N3 is configured to receive the precharge signal PCHB_DN from the output terminal of the inverter I7.

[0130] In some embodiments, the output terminal of the inverter I7, the node Nd11, and the gate of the PMOS transistor P11 are coupled together. In some embodiments, the gate of the PMOS transistor P11 is configured to receive the precharge signal PCHB_DN from the output terminal of the inverter I7.

[0131] In some embodiments, the output terminal of the inverter I7, the node Nd11, and at least the gate of the NMOS transistor N3, the gate of the PMOS transistor P4, or the gate of the PMOS transistor P11 are each coupled together.

[0132] Other configurations of circuit 400D are within the scope of the present disclosure. Other configurations of the inverters, number of inverters, or type of inverters of at least inverters 16 or 17 are within the scope of the present disclosure.

[0133] Figure 4E is a circuit diagram of circuit 400E according to some embodiments.

[0134] The circuit 400E is configured to generate a clock signal RCKB and a clock signal RCK.

[0135] Circuit 400E can be used with Figure 2 The integrated circuit 200 is used together with the integrated circuit 200 of FIG. 1 , and thus similar detailed description is omitted.

[0136] For example, in some embodiments, circuit 400E may be used with Figure 2 The circuit 200 or corresponding Figures 6-10 The circuits 600 - 1000 are used together and are coupled to at least the gate of the NMOS transistor N1 , the gate of the PMOS transistor P2 , or the gate of the NMOS transistor N4 .

[0137] Circuit 400E includes inverter 18 and inverter 19. In some embodiments, circuit 400E is configured to generate clock signal RCKB and clock signal RCK.

[0138] Inverter I8 is configured to generate a clock signal RCKB in response to clock signal RCLK. The input of inverter I8 is configured to receive clock signal RCLK. In some embodiments, clock signal RCLK is received from an external circuit (not shown). In some embodiments, at least clock signal RCLK, RCKB, or RCK is a read clock signal configured to cause circuit 200 to read data stored in memory cell array 102. In some embodiments, the input of inverter I8 is coupled to an external circuit (not shown). The output of inverter I8 is configured to output clock signal RCKB to at least the input of inverter I9 or node Nd12. In some embodiments, clock signal RCKB is in phase with clock signal RCLK, and vice versa. The output of inverter I8 is coupled to at least the input of inverter I9 or node Nd12.

[0139] In some embodiments, the output of the inverter I8, the node Nd12, and the gate of the NMOS transistor N4 are coupled together. In some embodiments, the gate of the NMOS transistor N4 is configured to receive the clock signal RCKB from the output of the inverter I8.

[0140] In some embodiments, the output of the inverter I8, the node Nd12, and the gate of the PMOS transistor P1 are coupled together. In some embodiments, the gate of the PMOS transistor P1 is configured to receive the clock signal RCKB from the output of the inverter I8.

[0141] In some embodiments, at least the output terminal of the inverter I8 , the node Nd12 , the gate of the NMOS transistor N4 , or the gate of the PMOS transistor P1 are coupled together.

[0142] The inverter I9 is configured to generate a clock signal RCK in response to the clock signal RCKB. The input of the inverter I9 is configured to receive the clock signal RCKB. The input of the inverter I9 is coupled to at least the output of the inverter I8 or the node Nd12.

[0143] The output of the inverter I9 is configured to output the clock signal RCK to at least the node Nd13. In some embodiments, the clock signal RCK is in phase opposition to the clock signal RCKB, and vice versa. The output of the inverter I9 is coupled to at least the node Nd13.

[0144] In some embodiments, the output of the inverter I9, the node Nd13, and the gate of the PMOS transistor P2 are coupled together. In some embodiments, the gate of the PMOS transistor P2 is configured to receive the clock signal RCK from the output of the inverter I9.

[0145] In some embodiments, the output of the inverter I9, the node Nd13, and the gate of the NMOS transistor N1 are coupled together. In some embodiments, the gate of the NMOS transistor N1 is configured to receive the clock signal RCK from the output of the inverter I9.

[0146] In some embodiments, at least the output terminal of the inverter I9, the node Nd13, the gate of the NMOS transistor N1, or the gate of the PMOS transistor P2 are coupled together.

[0147] Other configurations of circuit 400E are within the scope of the present disclosure. Other configurations of the inverters, number of inverters, or type of inverters of at least inverter 18 or 19 are within the scope of the present disclosure.

[0148] Waveform

[0149] Figure 5 According to some embodiments, Figure 2 A timing diagram 500 is shown of waveforms for a memory circuit such as circuit 200 in FIG.

[0150] In some embodiments, Figure 5 According to some embodiments at least Figure 3-4E Circuit 300-400E or Figures 6-10 A timing diagram 500 of waveforms of circuits 600-1000.

[0151] At time T0, precharge signal PCHB_DN transitions from logic high to logic low, thereby turning on PMOS transistor P11 of precharge circuit 400B. In response to PMOS transistor P11 of precharge circuit 400B turning on, node Nd2 is pulled toward voltage source VDD, thereby causing global bit line signal GBL_DN to transition from logic low to logic high. At time T0, because clock signal RCK is logic low, NMOS transistor N1 is turned off, and because clock signal RCKB is logic high, PMOS transistor P1 is turned off, and thus NAND logic gate 220 is electrically floating.

[0152] At time T1, the precharge signal PCHB_DN is logic low and the global bit line signal GBL_DN is logic high. At time T1, the clock signal RCLK transitions from logic low to logic high, causing the clock signal RCKB to transition from logic high to logic low and the clock signal RCK to transition from logic low to logic high.

[0153] In response to a transition of clock signal RCKB from logic high to logic low, PMOS transistor P1 turns on, thereby coupling first voltage source node Nd3 of NAND logic gate 220 to power supply voltage node VDDN. In response to a transition of clock signal RCK from logic low to logic high, NMOS transistor N1 turns on. However, because precharge signals PCHB_DN and PCHB_UP are both logic low, corresponding NMOS transistors N3 and N2 are turned off, and second voltage source node Nd4 of NAND logic gate 220 is not coupled to reference power supply voltage node VSSN. Therefore, second voltage source node Nd4 of NAND logic gate 220 is electrically floating.

[0154] At time T2, clock signal RCLK is logic high, clock signal RCKB is logic low, signal QB is logic high, and data signal DOUT is logic low. In some embodiments, because the data stored in memory cell 102a is logic low or "0", time T2-T8 is referred to as reading "0".

[0155] At time T3, pre-charge signal PCHB_UP transitions from logic low to logic high, causing PMOS transistor P10 of pre-charge circuit 400A to begin turning off. In response to PMOS transistor P10 of pre-charge circuit 400A turning off, node Nd1 is decoupled from voltage source node VDDN, and global bit line signal GBL_UP is no longer pre-charged to logic high via PMOS transistor P10. In some embodiments, because global bit line signal GBL_UP is no longer pre-charged to logic high via PMOS transistor P10, data stored in memory cell 102a is reflected on global bit line signal GBL_UP.

[0156] At time T4, precharge signal PCHB_UP is still transitioning from logic low to logic high. However, precharge signal PCHB_UP is almost logic high, thereby turning on NMOS transistor N2. In response to NMOS transistor N2 turning on, second voltage source node Nd4 of NAND logic gate 220 is coupled to reference supply voltage node VSSN. Therefore, NAND logic gate 220 is not electrically floating. Because global bit line signals GBL_UP and GBL_DN are both logic high and NAND logic gate 220 is not electrically floating, the output of NAND logic gate 220 is logic low, causing signal QB to transition from logic high to logic low at time T4. In response to signal QB transitioning from logic high to logic low, data signal DOUT transitions from logic low to logic high at time T4.

[0157] At time T5, signal QB is logic low and data signal DOUT is logic high. When data signal DOUT is logic high, circuit 200 reads the data stored in memory cell 102a as "1" even if the data stored in memory cell 102a is "0," and is referred to as a read "1" glitch. In some embodiments, a glitch is an unnecessary or undesirable signal transition.

[0158] At time T5, the global bit line signal GBL_UP transitions from logic high to logic low, causing the output of the NAND logic gate 220 to begin transitioning from logic low to logic high, thereby causing the signal QB to transition from logic low to logic high. At time T5, in response to the signal QB transitioning from logic low to logic high, the data signal DOUT transitions from logic high to logic low.

[0159] At time T6, the global bit line signal GBL_UP is logic low, causing the output of the NAND logic gate 220 to be logic high, causing the signal QB to be logic high. In response to the signal QB being logic high, the data signal DOUT is logic low at time T6. When the data signal DOUT is logic low, the circuit 200 correctly reads the data stored in the memory cell 102a as "0", and the circuit 200 resolves the read "1" glitch.

[0160] Time T4-T6 is referred to as a read "1" glitch, and the read "1" glitch between time T2-T4 has a duration G1. In some embodiments, by including NMOS transistor N2 in circuit 200 and delaying the transition of precharge signal PCHB_UP from logic low to logic high (e.g., time T3), the duration G1 of the read "1" glitch is reduced compared to other approaches.

[0161] At time T7 , the clock signal RCLK transitions from logic high to logic low, thereby causing the clock signal RCKB to transition from logic low to logic high, and the clock signal RCK to transition from logic high to logic low.

[0162] At time T8 , the clock signal RCLK is logic low, causing the clock signal RCKB to be logic high, and the clock signal RCK is still transitioning from logic high to logic low.

[0163] In response to the clock signal RCKB being logic high, the PMOS transistor P1 is turned off, thereby disconnecting the first voltage source node Nd3 of the NAND logic gate 220 from the power supply voltage node VDDN.

[0164] In response to the clock signal RCK transitioning from logic high to logic low, NMOS transistor N1 is turned off, thereby decoupling the second voltage source node Nd4 of NAND logic gate 220 from reference supply voltage node VSSN. Consequently, second voltage source node Nd4 of NAND logic gate 220 is electrically floating. In some embodiments, because NAND logic gate 220 is electrically floating, changes at the input of NAND logic gate 220 are not reflected at the output. In some embodiments, during this time, latch 230 is configured to maintain the states of node Nd5, signal QB, and data signal DOUT.

[0165] At time T9, the precharge signal PCHB_UP transitions from logic high to logic low, thereby turning on the PMOS transistor P10 of the precharge circuit 400A. In response to the PMOS transistor P10 of the precharge circuit 400A turning on, the node Nd1 is coupled to the voltage source node VDDN, and the global bit line signal GBL_UP is precharged to logic high through the PMOS transistor P10 between times T10 and T11.

[0166] Between time T9 and T10 , the pre-charge signal PCHB_UP completes its transition to logic high.

[0167] Between time T10 and T11 , the global bit line signal GBL_UP transitions from logic low to logic high.

[0168] At time T11 , the global bit line signal GBL_UP is logic high.

[0169] like Figure 5 As shown, the falling edge 512a of the precharge signal PCHB_UP can be advanced in time by a duration C1. Similarly, the rising edge 514a of the global bit line signal GBL_UP can be advanced in time by a duration C2. In some embodiments, the duration C2 is equal to the duration C1. In some embodiments, the duration C2 is different from the duration C1.

[0170] Therefore, as the falling edge of the precharge signal PCHB_UP is advanced in time, the rising edge of the global bit signal GBL_UP is also advanced in time, and vice versa.

[0171] In some embodiments, the falling edge of the pre-charge signal PCHB_UP is delayed from the falling edge of the clock signal RCK, but the delay between the falling edge of the pre-charge signal PCHB_UP and the falling edge of the clock signal RCK is less than the delay of other methods. In some embodiments, the falling edge of the pre-charge signal PCHB_UP occurs simultaneously with the falling edge of the clock signal RCK. In some embodiments, by advancing the falling edge of the pre-charge signal PCHB_UP and reducing the delay between the falling edge of the pre-charge signal PCHB_UP and the falling edge of the clock signal RCK, the circuit 200 can be pre-charged faster than other methods, thereby resulting in an improvement in read cycle time.

[0172] From T12-T16, the circuit 200 is arranged to have a similar configuration as the circuit 200 from time T0-T11. Therefore, for the sake of brevity, a detailed description of the circuit 200 from time T12-T16 is omitted.

[0173] In some embodiments, when NAND logic gate 220 is electrically floating, latch 230 is configured to maintain the states of node Nd5 and signal QB and data signal DOUT.

[0174] For example, when clock signal RCK is logic low, PMOS transistor P2 is turned on, and when clock signal RCKB is logic high, NMOS transistor N4 is turned on, thereby enabling inverter I3. In some embodiments, inverter I3 is enabled when it is coupled to voltage source node VDDN and reference voltage source node VSSN. Therefore, in some embodiments, inverter I3 is enabled via PMOS transistor P2 and NMOS transistor N4 at least during times T0-T1, T8-12, and T15-T16, and latch 230 maintains the states of node Nd5, signal QB, and data signal DOUT.

[0175] For example, when the precharge signal PCHB_UP is logic low, the PMOS transistor P3 is turned on, and the precharge signal PCH_UP is logic high, which turns on the NMOS transistor N6, and when the precharge signal PCHB_DN is logic low, the PMOS transistor P4 is turned on, and the precharge signal PCH_DN is logic high, which turns on the NMOS transistor N7, thereby enabling the inverter I3.

[0176] Thus, in some embodiments, at least between times T9-T13 or T8-T12 (e.g., for curve 512a, where pre-charge signal PCHB_UP is advanced by duration C1), inverter I3 is enabled via PMOS transistors P3 and P4 and NMOS transistors N6 and N7, and latch 230 maintains the states of node Nd5, signal QB, and data signal DOUT. In some embodiments, the waveform of pre-charge signal PCHB_UP and the waveform of pre-charge signal PCHB_DN are alternated. In some embodiments, the waveform of global bit line signal GBL_UP and the waveform of global bit line signal GBL_DN are alternated. Other timing diagrams of waveforms for circuits 200, 400A-400E, 600-900A, and 1000 are within the scope of the present disclosure.

[0177] Figure 6 is a circuit diagram of circuit 600 according to some embodiments.

[0178] Circuit 600 is Figure 2 200, and thus similar detailed descriptions are omitted. Figure 2 Compared to circuit 200, circuit 600 does not include NMOS transistors N1 and N4 and PMOS transistors P1 and P2. Compared to other approaches, by not including NMOS transistors N1 and N4 and PMOS transistors P1 and P2, circuit 600 includes fewer switching transistors, thereby reducing power consumption.

[0179] In some embodiments, by not including NMOS transistors N1 and N4 and PMOS transistors P1 and P2 , circuit 600 does not switch in response to clock signals RCK and RCKB.

[0180] Circuit 600 is Figure 1 The embodiments of the GIO circuit 106 are described below, and thus similar detailed description is omitted.

[0181] Circuit 600 includes NAND logic gate 220 , NMOS transistors N2 , N3 , N5 , N6 , and N7 , PMOS transistors P3 , P4 , and P5 , and inverters I1 and I2 .

[0182] and Figure 2 Compared to the circuit 200 , the circuit 600 does not include the NMOS transistors N1 and N4 and the PMOS transistors P1 and P2 .

[0183] By not including the PMOS transistor P1, the first voltage source node Nd3 of the NAND logic gate 220 of the circuit 600 is directly coupled to the power supply voltage node VDDN and receives the power supply voltage VDD. Similarly, Figure 3Source terminals of the PMOS transistors P8 and P9 of the NAND logic gate circuit 300 are directly coupled to the power supply voltage node VDDN and receive the power supply voltage VDD.

[0184] By excluding the NMOS transistor N1 , source terminals of the NMOS transistors N2 and N3 are directly coupled to the reference power supply voltage node VSSN and receive the reference power supply voltage VSS.

[0185] In some embodiments, by not including the NMOS transistor N1 and the PMOS transistor P1 , the circuit 600 does not include stacked PMOS transistors, thereby increasing the speed of the NAND logic gate 220 compared to other approaches.

[0186] In some embodiments, by excluding PMOS transistor P2 and NMOS transistor N4, PMOS transistor P5 is coupled to power supply voltage node VDDN through a single path (e.g., through PMOS transistors P3 and P4), and NMOS transistor N5 is coupled to reference power supply voltage node VSSN through a single path (e.g., through NMOS transistors N6 and N7). In other words, PMOS transistor P5 is not coupled to power supply voltage node VDDN through PMOS transistor P2, and NMOS transistor N5 is not coupled to reference power supply voltage node VSSN through NMOS transistor N4.

[0187] In some embodiments, by not including NMOS transistors N1 and N4 and PMOS transistors P1 and P2 , circuit 600 does not switch or change states in response to clock signals RCK and RCKB, thereby reducing power consumption compared to other approaches.

[0188] In some embodiments, the timing diagram of the operation of circuit 600 is similar to Figure 5 500 , but the timing diagram of the operation of the circuit 600 does not include the clock signals RCLK, RCK, and RCKB, and similar detailed description is omitted.

[0189] Other configurations of transistors, numbers of transistors, or types of transistors for circuit 600 are within the scope of the present disclosure.

[0190] Figure 7 is a circuit diagram of circuit 700 according to some embodiments.

[0191] Circuit 700 is Figure 2 200, and thus similar detailed descriptions are omitted. Figure 2Compared to circuit 200, circuit 700 does not include NMOS transistors N6 and N7. Compared to other approaches, by not including NMOS transistors N6 and N7, circuit 700 includes fewer switching transistors, thereby reducing power consumption.

[0192] In some embodiments, by not including NMOS transistors N6 and N7 , circuit 700 does not include transistors that switch in response to precharge signals PCH_UP and PCH_DN.

[0193] Circuit 700 is Figure 1 The embodiments of the GIO circuit 106 are described below, and thus similar detailed description is omitted.

[0194] Circuit 700 includes NAND logic gate 220 , NMOS transistors N1 , N2 , N3 , N4 , and N5 , PMOS transistors P1 , P2 , P3 , P4 , and P5 , and inverters I1 and I2 .

[0195] and Figure 2 Compared to circuit 200 , circuit 700 does not include NMOS transistors N6 and N7 .

[0196] In some embodiments, by excluding NMOS transistors N6 and N7, NMOS transistor N5 is coupled to reference supply voltage node VSSN via a single path (e.g., via NMOS transistor N4). In other words, NMOS transistor N5 is not coupled to reference supply voltage node VSSN via NMOS transistors N6 and N7. In some embodiments, by excluding NMOS transistors N6 and N7, circuit 700 includes fewer transistors, thereby reducing power consumption, compared to other approaches.

[0197] In some embodiments, the timing diagram of the operation of circuit 700 is similar to Figure 5 500 , and similar detailed description is omitted.

[0198] Other configurations of transistors, numbers of transistors, or types of transistors for circuit 700 are within the scope of the present disclosure.

[0199] Figure 8 is a circuit diagram of circuit 800 according to some embodiments.

[0200] Circuit 800 is Figure 2 200, and thus similar detailed descriptions are omitted. Figure 2Compared to the circuit 200, the circuit 800 does not include the NMOS transistor N3, and the NMOS transistor N2 is controlled by the precharge signal PCHB_UP or PCHB_DN. Compared to other methods, by not including the NMOS transistor N3, the circuit 800 includes fewer switching transistors, thereby reducing power consumption.

[0201] Circuit 800 is Figure 1 The embodiments of the GIO circuit 106 are described below, and thus similar detailed description is omitted.

[0202] Circuit 800 includes NAND logic gate 220 , NMOS transistors N1 , N2 , N4 , N5 , N6 , and N7 , PMOS transistors P1 , P2 , P3 , P4 , and P5 , and inverters I1 and I2 .

[0203] and Figure 2 Compared to circuit 200, circuit 800 does not include NMOS transistor N3. In some embodiments, NMOS transistor N2 is controlled by precharge signal PCHB_UP or PCHB_DN. In some embodiments, by not including NMOS transistor N3, second voltage source node Nd4 of NAND logic gate 220 is coupled to reference supply voltage node VSSN via a single path (e.g., through NMOS transistors N1 and N2). In other words, second voltage source node Nd4 of NAND logic gate 220 is not coupled to reference supply voltage node VSSN via NMOS transistor N3.

[0204] In some embodiments, by not including the NMOS transistor N3 , the circuit 800 includes fewer transistors, thereby reducing power consumption, compared to other approaches.

[0205] In some embodiments, the timing diagram of the operation of circuit 800 is similar to Figure 5 500 , and similar detailed description is omitted.

[0206] Other configurations of transistors, numbers of transistors, or types of transistors for circuit 800 are within the scope of the present disclosure.

[0207] Figure 9A is a circuit diagram of circuit 900A according to some embodiments.

[0208] Circuit 900A is Figure 8 800, and therefore similar detailed descriptions are omitted. Figure 8Compared to circuit 800, NMOS transistor N2 is controlled by control signal S1. In some embodiments, control signal S1 has the same logic level and timing characteristics as at least precharge signal PCHB_UP or PCHB_DN, and thus similar detailed description is omitted. In some embodiments, signal S1 is an inverted version of at least global bit line signal GBL_UP or GBL_DN.

[0209] In some embodiments, the control signal S1 is received from an external circuit (not shown). In some embodiments, the gate terminal of the NMOS transistor N2 is coupled to the external circuit (not shown) and is configured to receive the control signal S1. In some embodiments, the control signal S1 does not have the same waveform curve as the precharge signal PCHB_UP or PCHB_DN by being generated by the external circuit (not shown) and may have a waveform curve as shown in FIG. Figure 9B Other waveforms shown.

[0210] and Figure 8 Compared to circuit 800, NMOS transistor N2 of circuit 900A is not controlled by precharge signal PCHB_UP or PCHB_DN. In some embodiments, by controlling NMOS transistor N2 of circuit 900A via signal S1 (instead of precharge signal PCHB_UP or PCHB_DN), signal S1 can track the behavior of precharge signal PCHB_UP or PCHB_DN, or be the same as precharge signal PCHB_UP or PCHB_DN, thereby preventing a read "1" glitch (in the following example). Figure 9B ).

[0211] Circuit 900A is Figure 1 The embodiments of the GIO circuit 106 are described below, and thus similar detailed description is omitted.

[0212] Circuit 900A includes a NAND logic gate 220 , NMOS transistors N1 , N2 , N4 , N5 , N6 , and N7 , PMOS transistors P1 , P2 , P3 , P4 , and P5 , and inverters I1 and I2 .

[0213] In some embodiments, by not including the NMOS transistor N3 , the circuit 900A includes fewer switching transistors, thereby reducing power consumption, compared to other approaches.

[0214] Other configurations of transistors, numbers of transistors, or transistor types for circuit 900A are within the scope of the present disclosure.

[0215] Figure 9B According to some embodiments, Figure 9A 900B is a timing diagram of waveforms for a memory circuit such as circuit 900A in FIG. Figure 9B According to some embodiments at least Figure 9A and Figure 10 A timing diagram 900B of waveforms of circuits 900A or 1000 is shown.

[0216] In some embodiments, the timing diagram 900B is Figure 5 5. However, the timing diagram 500 of FIG. 5 also includes the signal S1, and thus similar detailed description is omitted.

[0217] exist Figure 9B In the timing diagram 900B, signal S1 is described, but the timing diagram 900B also includes Figure 5 In some embodiments, signal S1 is an inverted version of the global bit line signal GBL_UP, thereby completely removing the read “1” glitch from signal QB and data signal DOUT. Figure 9B In some embodiments, signal S1 is an inverted version of the global bit line signal GBL_DN.

[0218] Waveform 900B is described from time T3-T6 and for the sake of brevity, Figure 9B Other details of the transition of signal S1 in and the effect on memory circuit 900B are not described, but they are similar to Figure 5 The timing of the global bit line signal GBL_UP described in Figure 5 The voltage level of the precharge signal PCHB_UP is described in , and thus similar detailed description is omitted.

[0219] From time T3 to T4, the precharge signal PCHB_UP changes from logic low to logic high. However, Figure 9A In the embodiment, since the NMOS transistor N2 is controlled by the signal S1, the NMOS transistor N2 is not turned on. Since the NMOS transistor N2 is not turned on in response to the transition of the precharge signal PCHB_UP, the signal QB is Figure 9B There is no transition from logic high to logic low at time T4 in Figure 5 ), and the data signal DOUT is Figure 9B There is no transition from logic low to logic high at time T4 in .

[0220] exist Figure 9BAt time T5, global bit line signal GBL_UP transitions from logic high to logic low, and signal S1 transitions from logic low to logic high. However, because the transition of global bit line signal GBL_UP from logic high to logic low occurs simultaneously with the transition of signal S1 from logic low to logic high, the read "1" glitch is effectively removed from signal QB and data signal DOUT. For example, in response to the transition of signal S1 from logic low to logic high, NMOS transistor N2 is turned on, thereby coupling second voltage source node Nd4 of NAND logic gate 220 to reference supply voltage node VSSN. Therefore, NAND logic gate 220 is not electrically floating. Furthermore, in response to the transition of global bit line signal GBL_UP from logic high to logic low and the fact that NAND logic gate 220 is not electrically floating, the output of NAND logic gate 220 remains logic high because at least one of global bit line signals GBL_UP or GBL_DN is logic low. Therefore, the output of the NAND logic gate 220 and the signal QB are logic high, and the data signal DOUT is logic low.

[0221] At time T6 , the global bit line signal GBL_UP is logic low, the signal S1 is logic high, the signal QB is logic high, and the data signal DOUT is logic low.

[0222] Details of the operation of the circuit 900A from time T12 - T15 of the timing diagram 900B are the same as details of the operation of the circuit 900A from time T3 - T6 , and thus the same detailed description is omitted.

[0223] Figure 10 is a circuit diagram of circuit 1000 according to some embodiments.

[0224] Circuit 1000 is a variation of memory circuit 900 of FIG. 9 , and thus similar detailed descriptions are omitted. Compared to memory circuit 900 of FIG. 9 , circuit 1000 does not include NMOS transistors N6 and N7 and PMOS transistors P3 and P4. By not including NMOS transistors N6 and N7 and PMOS transistors P3 and P4, circuit 1000 includes fewer switching transistors, thereby reducing power consumption, compared to other approaches.

[0225] In some embodiments, by not including NMOS transistors N6 and N7 and PMOS transistors P3 and P4 , circuit 1000 does not switch in response to precharge signals PCHB_UP, PCHB_DN, PCH_UP, and PCH_DN.

[0226] Circuit 1000 is Figure 1 The embodiments of the GIO circuit 106 are described below, and thus similar detailed description is omitted.

[0227] Circuit 1000 includes a NAND logic gate 220 , NMOS transistors N1 , N2 , N4 , and N5 , PMOS transistors P1 , P2 , and P5 , and inverters I1 and I2 .

[0228] Compared to the memory circuit 900 of FIG. 9 , the circuit 1000 does not include the NMOS transistors N6 and N7 and the PMOS transistors P3 and P4 .

[0229] In some embodiments, by excluding PMOS transistors P3 and P4 and NMOS transistors N6 and N7, PMOS transistor P5 is coupled to power supply voltage node VDDN through a single path (e.g., through PMOS transistor P2), and NMOS transistor N5 is coupled to reference power supply voltage node VSSN through a single path (e.g., through NMOS transistor N4). In other words, PMOS transistor P5 is not coupled to power supply voltage node VDDN through PMOS transistors P3 and P4, and NMOS transistor N5 is not coupled to reference power supply voltage node VSSN through NMOS transistors N6 and N7.

[0230] In some embodiments, by not including NMOS transistors N6 and N7 and PMOS transistors P3 and P4 , circuit 1000 does not switch or change states in response to precharge signals PCHB_UP, PCHB_DN, PCH_UP, and PCH_DN, thereby reducing power consumption compared to other approaches.

[0231] In some embodiments, by not including NMOS transistors N6 and N7 and PMOS transistors P3 and P4 , circuit 1000 includes fewer switching transistors, thereby reducing power consumption, compared to other approaches.

[0232] In some embodiments, the timing diagram of the operation of circuit 1000 is similar to Figure 9B 900B, and similar detailed description is omitted.

[0233] Other configurations of transistors, numbers of transistors, or types of transistors for circuit 1000 are within the scope of the present disclosure.

[0234] method

[0235] Figure 11 is a flow chart of a method of operating a circuit according to some embodiments.

[0236] In some embodiments, Figure 11 Yes Operation Figure 1 memory circuits, or Figure 2-Figure 3 、 Figures 4A-4E or Figures 6-10 It should be understood that the circuit can be Figure 11 Additional operations may be performed before, during, and / or after the method 1100 depicted in FIG. 1 , and some other operations may be described only briefly herein. It should be understood that the method 1100 utilizes circuits 100, 200, 300, 400A-400E, 600, 700, 800, 900A, or 1000, or Figure 5 Characteristics of one or more of waveforms 500.

[0237] In operation 1102 of method 1100, NAND logic gate circuit 220 receives a first bit line signal and a second bit line signal. In some embodiments, the first bit line signal of method 1100 includes a global bit line signal GBL_UP. In some embodiments, the second bit line signal of method 1100 includes a global bit line signal GBL_DN.

[0238] In operation 1104 of method 1100, the NAND logic gate circuit generates a first signal in response to the first bit line signal and the second bit line signal. In some embodiments, the first signal of method 1100 includes a signal QB.

[0239] In some embodiments, operation 1104 includes at least operation 1106 or 1108 .

[0240] In operation 1106 of method 1100, a NAND logic gate circuit is enabled in response to at least a first precharge signal. In some embodiments, the first precharge signal of method 1100 includes at least precharge signal PCHB_UP or PCHB_DN. In some embodiments, operation 1106 includes at least operations 1106a, 1106b, or 1106c.

[0241] In some embodiments, operation 1106a includes turning on at least a first N-type transistor in response to a first precharge signal. In some embodiments, the first N-type transistor is coupled between a NAND logic gate and a reference supply voltage node VSSN. In some embodiments, the first N-type transistor of method 1100 includes at least an NMOS transistor N2 or N3. In some embodiments, operation 1106b includes turning off at least a first P-type transistor in response to the first precharge signal. In some embodiments, the first P-type transistor is coupled to an input of the NAND logic gate. In some embodiments, the first P-type transistor of method 1100 includes at least a PMOS transistor P10 or P11. In some embodiments, operation 1106c includes causing the first signal to transition from a first logic value (0) to a second logic value (1) in response to a transition of the first bit line signal from a second logic value (1) to a first logic value (0).

[0242] In operation 1108 of method 1100, the latch is disabled in response to at least the first precharge signal or the first clock signal. In some embodiments, the latch of method 1100 includes at least latch 230. In some embodiments, the first clock signal of method 1100 includes at least clock signal RCLK, RCKB, or RCK.

[0243] At operation 1110 of method 1100, a state of a first signal is latched by a latch in response to at least a first precharge signal or a first clock signal. In some embodiments, the latch of method 1100 includes a first inverter and a second inverter. In some embodiments, the first inverter of method 1100 includes inverters I2 or I3. In some embodiments, the first inverter of method 1100 includes inverters I3 or I2.

[0244] In some embodiments, operation 1110 includes at least operation 1112 or 1114 .

[0245] In operation 1112 of method 1100, the NAND logic gate circuit is disabled in response to at least the first pre-charge signal. In some embodiments, operation 1112 includes disabling the NAND logic gate circuit in response to the first pre-charge signal transitioning to a low logic value after time T8.

[0246] At operation 1114 of method 1100, the second inverter is enabled in response to at least the first pre-charge signal or the first clock signal. In some embodiments, operation 1114 includes enabling the second inverter in response to the first pre-charge signal transitioning to a low logic value (e.g., after time T8). In some embodiments, operation 1114 includes enabling the second inverter in response to the first clock signal transitioning to a low logic value (e.g., after time T8).

[0247] By operating the method 1100, the memory circuit operates to achieve the benefits discussed above with respect to the memory circuits 100-1000. Figure 2-Figure 5 Method 1100 is described, but it should be understood that method 1100 utilizes Figures 6-10 Characteristics of one or more of the following.

[0248] In some embodiments, one or more operations of method 1100 are not performed. Figure 2-Figure 10 The various PMOS or NMOS transistors shown in FIG. 1 have specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of the present disclosure are not limited to specific transistor types, and Figure 2-Figure 10One or more of the PMOS or NMOS transistors shown in the figure may be replaced with corresponding transistors of different transistor / doping types. Similarly, the low or high logic values of the various signals used in the above description are also used for illustration. The embodiments of the present disclosure are not limited to specific logic values when the signals are activated and / or deactivated. It is within the scope of the various embodiments to select different logic values. Figure 2-Figure 10 It is within the scope of various embodiments to select a different number of inverters. Figure 2-Figure 10 It is within the scope of various embodiments to select a different number of transistors in . Figure 2-Figure 10 It is within the scope of various embodiments to select a different number of NAND logic gates.

[0249] It will be readily apparent to one skilled in the art that one or more of the disclosed embodiments achieve one or more of the advantages set forth above. After reading the foregoing description, one skilled in the art will be able to effect various variations, substitutions of equivalents, and various other embodiments broadly disclosed herein. It is therefore intended that the protection granted herein be limited only by the definitions contained in the appended claims and their equivalents.

[0250] One aspect of the present specification relates to a memory circuit. The memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter, and a first latch. In some embodiments, the NAND logic gate is configured to receive a first bitline signal and a second bitline signal and generate a first signal. In some embodiments, the first N-type transistor is coupled to the NAND logic gate and is configured to receive a first precharge signal. In some embodiments, the second N-type transistor is coupled to the first N-type transistor and a reference voltage source and is configured to receive a first clock signal. In some embodiments, the first inverter is coupled to the NAND logic gate and is configured to output a data signal inverted from the first signal. In some embodiments, the first latch is coupled to the NAND logic gate and is configured to latch the first signal in response to at least the first clock signal or the first precharge signal. In some embodiments, a NAND logic gate includes: a first input terminal of the NAND logic gate configured to receive a first bitline signal; a second input terminal of the NAND logic gate configured to receive a second bitline signal; an output terminal of the NAND logic gate configured to output a first signal in response to the first bitline signal and the second bitline signal; a first voltage source node; and a second voltage source node coupled to a first N-type transistor. In some embodiments, the first N-type transistor includes: a first gate configured to receive a first precharge signal; a first drain coupled to the second voltage source node of the NAND logic gate; and a first source coupled to a second N-type transistor. In some embodiments, the second N-type transistor includes: a second gate configured to receive a first clock signal; a second drain coupled to the first source; and a second source coupled to a reference voltage source. In some embodiments, the memory circuit further includes a third N-type transistor having: a third gate configured to receive a second precharge signal different from the first precharge signal; a third source coupled to the second drain and the first source; and a third drain coupled to the first drain and the first voltage source node of the NAND logic gate. In some embodiments, the memory circuit further comprises a first P-type transistor, a first source of the first P-type transistor being coupled to a first voltage source different from a reference voltage source, a first gate of the first P-type transistor being configured to receive a second clock signal inverted from the first clock signal, and a first drain of the first P-type transistor being coupled to a first voltage source node of the NAND logic gate. In some embodiments, the first latch comprises a second inverter having an input and an output, the input of the second inverter being configured to receive the first signal and coupled to the first node and the output of the NAND logic gate, and the output of the second inverter being configured to output the second signal inverted from the first signal.In some embodiments, the first latch further includes a first P-type transistor, the gate of which is configured to receive the second signal; the source of the first P-type transistor is coupled to the first voltage source node, and the drain of the first P-type transistor is coupled to at least the first node. In some embodiments, the first latch further includes a first N-type transistor, the gate of which is configured to receive the second signal and is coupled to the gate of the first P-type transistor and the output of the second inverter; the source of the first N-type transistor is coupled to the second voltage source node, and the drain of the first N-type transistor is coupled to the first node and the drain of the first P-type transistor. In some embodiments, the first latch further includes a second P-type transistor, the gate of which is configured to receive the first clock signal, the source of the second P-type transistor is coupled to a first voltage source different from the reference voltage source, and the drain of the second P-type transistor is coupled to the first voltage source node and the source of the first P-type transistor. In some embodiments, the first latch further comprises a second N-type transistor, the gate of the second N-type transistor being configured to receive a second clock signal inverted from the first clock signal, the source of the second N-type transistor being coupled to the reference voltage source, and the drain of the second N-type transistor being coupled to a second voltage source node and the source of the first N-type transistor. In some embodiments, the first latch further comprises a second P-type transistor, the gate of the second P-type transistor being configured to receive the first pre-charge signal, and the source of the second P-type transistor being coupled to a first voltage source different from the reference voltage source. In some embodiments, the first latch further comprises a third P-type transistor, the gate of the third P-type transistor being configured to receive a second pre-charge signal different from the first pre-charge signal, the source of the third P-type transistor being coupled to the drain of the second P-type transistor, and the drain of the third P-type transistor being coupled to the first voltage source node and the source of the first P-type transistor. In some embodiments, the first latch further comprises a second N-type transistor, the gate of the second N-type transistor being configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal, and the source of the second N-type transistor being coupled to the reference voltage source. In some embodiments, the first latch further includes a third N-type transistor, a gate of the third N-type transistor being configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal, a source of the third N-type transistor being coupled to the drain of the second N-type transistor, and a drain of the third N-type transistor being coupled to the second voltage source node and the source of the first N-type transistor.

[0251] Another aspect of the present disclosure relates to a memory circuit. The memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first latch, and a first inverter. In some embodiments, the NAND logic gate is configured to receive a first bitline signal and a second bitline signal and generate a first signal in response to the first bitline signal and the second bitline signal. In some embodiments, the first N-type transistor has a first drain coupled to a first voltage source node of the NAND logic gate; a first gate configured to receive a first precharge signal; and a first source coupled to the first node. In some embodiments, the second N-type transistor has a second drain coupled to the first drain and the first voltage source node of the NAND logic gate; a second gate configured to receive a second precharge signal different from the first precharge signal; and a second source coupled to the first source and the first node. In some embodiments, the first latch is coupled to the NAND logic gate via a second node and is configured to latch the first signal in response to at least the first precharge signal or the second precharge signal. In some embodiments, the first inverter is coupled to the NAND logic gate and configured to output a data signal inverted from the first signal. In some embodiments, the NAND logic gate has a second voltage source node coupled to the first voltage source, and the first source, the second source, and the first node are coupled to a reference voltage source. In some embodiments, the first latch includes a second inverter having an input and an output. In some embodiments, the input of the second inverter is configured to receive the first signal and is coupled to the output of the NAND logic gate and the second node, and the output of the second inverter is configured to output a second signal that is an inverted version of the first signal. In some embodiments, the first latch also includes a first P-type transistor having a third gate configured to receive the second signal, a third source coupled to the third voltage source node, and a third drain coupled to at least the second node. In some embodiments, the first latch also includes a third N-type transistor having a fourth gate configured to receive the second signal and coupled to the third gate and the output of the second inverter, a fourth source coupled to the fourth voltage source node, and a fourth drain coupled to the third drain and the second node. In some embodiments, the first latch also includes a second P-type transistor having a fifth gate configured to receive the first precharge signal and a fifth source coupled to the first voltage source. In some embodiments, the first latch also includes a third P-type transistor having: a sixth gate configured to receive a second pre-charge signal different from the first pre-charge signal; a sixth source coupled to the fifth drain of the second P-type transistor; and a sixth drain coupled to the third voltage source node and the third source.In some embodiments, the first latch further includes a second N-type transistor having a seventh gate configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal, and a seventh source coupled to a reference voltage source. In some embodiments, the first latch further includes a third N-type transistor having an eighth gate configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal; an eighth source coupled to the seventh drain of the second N-type transistor; and an eighth drain coupled to a fourth voltage source node and a fourth source. In some embodiments, the memory circuit further includes a third N-type transistor having a third gate configured to receive a first clock signal; a third drain coupled to the first source, the second source, and the first node; and a third source coupled to the reference voltage source. In some embodiments, the memory circuit further includes a first P-type transistor having a fourth source coupled to the first voltage source; a fourth gate configured to receive a second clock signal inverted from the first clock signal; and a fourth drain coupled to the second voltage source node of the NAND logic gate.

[0252] Another aspect of the present disclosure relates to a method for operating a memory circuit. The method includes receiving a first bitline signal and a second bitline signal via a NAND logic gate circuit, and generating a first signal via the NAND logic gate circuit in response to the first bitline signal and the second bitline signal. In some embodiments, generating the first signal includes enabling the NAND logic gate circuit in response to at least a first precharge signal. In some embodiments, the method further includes latching a state of the first signal via a latch in response to at least the first precharge signal or a first clock signal, the latch including a first inverter and a second inverter. In some embodiments, enabling the NAND logic gate circuit in response to at least the first precharge signal includes turning on at least a first N-type transistor coupled between the NAND logic gate circuit and a reference power supply voltage node in response to the first precharge signal. In some embodiments, latching the state of the first signal in response to at least the first precharge signal or the first clock signal includes disabling the NAND logic gate circuit in response to at least the first precharge signal; and enabling the second inverter in response to at least the first precharge signal or the first clock signal.

[0253] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0254] Example 1. A memory circuit comprising: a NAND logic gate configured to receive a first bit line signal and a second bit line signal and generate a first signal; a first N-type transistor coupled to the NAND logic gate and configured to receive a first precharge signal; a second N-type transistor coupled to the first N-type transistor and a reference voltage source and configured to receive a first clock signal; a first inverter coupled to the NAND logic gate and configured to output a data signal inverted from the first signal; and a first latch coupled to the NAND logic gate and configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

[0255] Example 2. The memory circuit of Example 1, wherein the NAND logic gate comprises: a first input of the NAND logic gate configured to receive the first bit line signal; a second input of the NAND logic gate configured to receive the second bit line signal; an output of the NAND logic gate configured to output the first signal in response to the first bit line signal and the second bit line signal; a first voltage source node; and a second voltage source node coupled to the first N-type transistor.

[0256] Example 3. The memory circuit of Example 2, wherein the first N-type transistor comprises: a first gate configured to receive the first precharge signal; a first drain coupled to the second voltage source node of the NAND logic gate; and a first source coupled to the second N-type transistor.

[0257] Example 4. The memory circuit of Example 3, wherein the second N-type transistor includes: a second gate configured to receive the first clock signal; a second drain coupled to the first source; and a second source coupled to the reference voltage source.

[0258] Example 5. The memory circuit of Example 4 further includes: a third N-type transistor having: a third gate configured to receive a second precharge signal different from the first precharge signal, a third source coupled to the second drain and the first source, and a third drain coupled to the first drain and a second voltage source node of the NAND logic gate.

[0259] Example 6. The memory circuit according to Example 2 further includes: a first P-type transistor, a first source of the first P-type transistor is coupled to a first voltage source different from the reference voltage source, a first gate of the first P-type transistor is configured to receive a second clock signal inverted from the first clock signal, and a first drain of the first P-type transistor is coupled to the first voltage source node of the NAND logic gate.

[0260] Example 7. A memory circuit according to Example 1, wherein the first latch includes: a second inverter having an input and an output, the input of the second inverter being configured to receive the first signal and coupled to the first node and the output of the NAND logic gate; and the output of the second inverter being configured to output a second signal inverted from the first signal.

[0261] Example 8. A memory circuit according to Example 7, wherein the first latch further includes: a first P-type transistor, the gate of the first P-type transistor being configured to receive the second signal, the source of the first P-type transistor being coupled to a first voltage source node, and the drain of the first P-type transistor being coupled to at least the first node; and a first N-type transistor, the gate of the first N-type transistor being configured to receive the second signal and coupled to the gate of the first P-type transistor and the output of the second inverter, the source of the first N-type transistor being coupled to a second voltage source node, and the drain of the first N-type transistor being coupled to the first node and the drain of the first P-type transistor.

[0262] Example 9. A memory circuit according to Example 8, wherein the first latch further includes: a second P-type transistor, the gate of the second P-type transistor being configured to receive the first clock signal, the source of the second P-type transistor being coupled to a first voltage source different from the reference voltage source, and the drain of the second P-type transistor being coupled to the first voltage source node and the source of the first P-type transistor; and a second N-type transistor, the gate of the second N-type transistor being configured to receive a second clock signal inverted from the first clock signal, the source of the second N-type transistor being coupled to the reference voltage source, and the drain of the second N-type transistor being coupled to the second voltage source node and the source of the first N-type transistor.

[0263] Example 10. A memory circuit according to Example 8, wherein the first latch further includes: a second P-type transistor, the gate of the second P-type transistor being configured to receive the first pre-charge signal, and the source of the second P-type transistor being coupled to a first voltage source different from the reference voltage source; and a third P-type transistor, the gate of the third P-type transistor being configured to receive a second pre-charge signal different from the first pre-charge signal, the source of the third P-type transistor being coupled to the drain of the second P-type transistor, and the drain of the third P-type transistor being coupled to the first voltage source node and the source of the first P-type transistor.

[0264] 11. The memory circuit of Example 8, wherein the first latch further comprises: a second N-type transistor, the gate of the second N-type transistor being configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal, and the source of the second N-type transistor being coupled to the reference voltage source; and a third N-type transistor, the gate of the third N-type transistor being configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal, the source of the third N-type transistor being coupled to the drain of the second N-type transistor, and the drain of the third N-type transistor being coupled to the second voltage source node and the source of the first N-type transistor.

[0265] Example 12. A memory circuit comprising: a NAND logic gate configured to receive a first bit line signal and a second bit line signal and generate a first signal in response to the first bit line signal and the second bit line signal; a first N-type transistor having: a first drain coupled to a first voltage source node of the NAND logic gate; a first gate configured to receive a first precharge signal; and a first source coupled to a first node; a second N-type transistor having: a second drain coupled to the first drain and the first voltage source node of the NAND logic gate; a second gate configured to receive a second precharge signal different from the first precharge signal; and a second source coupled to the first source and the first node; a first latch coupled to the NAND logic gate via a second node and configured to latch the first signal in response to at least the first precharge signal or the second precharge signal; and a first inverter coupled to the NAND logic gate and configured to output a data signal inverted from the first signal.

[0266] Example 13. The memory circuit of Example 12, wherein the NAND logic gate has a second voltage supply node coupled to a first voltage source, and the first source, the second source, and the first node are coupled to a reference voltage source.

[0267] Example 14. A memory circuit according to Example 13, wherein the first latch includes: a second inverter having an input and an output, the input of the second inverter being configured to receive the first signal and coupled to the output of the NAND logic gate and the second node; and the output of the second inverter being configured to output a second signal inverted from the first signal.

[0268] Example 15. A memory circuit according to Example 14, wherein the first latch further includes: a first P-type transistor having: a third gate configured to receive the second signal; a third source coupled to a third voltage source node; and a third drain coupled to at least the second node; and a third N-type transistor having: a fourth gate configured to receive the second signal and coupled to the third gate and the output of the second inverter; a fourth source coupled to a fourth voltage source node; and a fourth drain coupled to the third drain and the second node.

[0269] Example 16. A memory circuit according to Example 15, wherein the first latch further includes: a second P-type transistor having: a fifth gate configured to receive the first pre-charge signal; and a fifth source coupled to the first voltage source; and a third P-type transistor having: a sixth gate configured to receive a second pre-charge signal different from the first pre-charge signal; a sixth source coupled to the fifth drain of the second P-type transistor; and a sixth drain coupled to the third voltage source node and the third source.

[0270] Example 17. A memory circuit according to Example 16, wherein the first latch further includes: a second N-type transistor, the seventh gate of the second N-type transistor being configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal, and the seventh source of the second N-type transistor being coupled to the reference voltage source; and a third N-type transistor having: an eighth gate configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal; an eighth source coupled to the seventh drain of the second N-type transistor; and an eighth drain coupled to the fourth voltage source node and the fourth source.

[0271] Example 18. The memory circuit of Example 12 further includes: a third N-type transistor having: a third gate configured to receive a first clock signal; a third drain coupled to the first source, the second source, and the first node; and a third source coupled to a reference voltage source; and a first P-type transistor having: a fourth source coupled to the first voltage source; a fourth gate configured to receive a second clock signal inverted from the first clock signal; and a fourth drain coupled to the second voltage source node of the NAND logic gate.

[0272] Example 19. A method of operating a memory circuit, the method comprising: receiving a first bit line signal and a second bit line signal through a NAND logic gate circuit; generating a first signal through the NAND logic gate circuit in response to the first bit line signal and the second bit line signal, wherein generating the first signal comprises: enabling the NAND logic gate circuit in response to at least a first precharge signal; and latching a state of the first signal through a latch in response to at least the first precharge signal or a first clock signal, the latch comprising a first inverter and a second inverter.

[0273] Example 20. A method according to Example 19, wherein enabling the NAND logic gate circuit in response to at least the first precharge signal includes: turning on at least a first N-type transistor in response to the first precharge signal, the first N-type transistor coupled between the NAND logic gate circuit and a reference power supply voltage node; and latching the state of the first signal in response to at least the first precharge signal or the first clock signal includes: disabling the NAND logic gate circuit in response to at least the first precharge signal; and enabling the second inverter in response to at least the first precharge signal or the first clock signal.

Claims

1. A memory circuit comprising: A NAND logic gate configured to receive a first bit line signal and a second bit line signal and generate a first signal; a first N-type transistor coupled to the NAND logic gate and configured to receive a first precharge signal; a second N-type transistor coupled to the first N-type transistor and a reference voltage source, and configured to receive a first clock signal; a first inverter coupled to the NAND logic gate and configured to output a data signal inverted from the first signal; as well as A first latch is coupled to the NAND logic gate and configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

2. The memory circuit according to claim 1, wherein The NAND logic gate includes: The first input terminal of the NAND logic gate is configured to receive the first bit line signal; The second input terminal of the NAND logic gate is configured to receive the second bit line signal; The output terminal of the NAND logic gate is configured to output the first signal in response to the first bit line signal and the second bit line signal; a first voltage supply node; and A second voltage source node is coupled to the first N-type transistor.

3. The memory circuit according to claim 2, wherein: The first N-type transistor includes: a first gate configured to receive the first precharge signal; a first drain coupled to a second voltage source node of the NAND logic gate; and The first source is coupled to the second N-type transistor.

4. The memory circuit according to claim 3, wherein: The second N-type transistor includes: a second gate configured to receive the first clock signal; a second drain coupled to the first source; and The second source is coupled to the reference voltage source.

5. The memory circuit according to claim 4 , further comprising: A third N-type transistor having: a third gate configured to receive a second precharge signal different from the first precharge signal; a third source coupled to the second drain and the first source, and The third drain is coupled to the first drain and the second voltage source node of the NAND logic gate.

6. The memory circuit according to claim 2, further comprising: a first P-type transistor, wherein a first source of the first P-type transistor is coupled to a first voltage source different from the reference voltage source, a first gate of the first P-type transistor is configured to receive a second clock signal inverted from the first clock signal, and a first drain of the first P-type transistor is coupled to a first voltage source node of the NAND logic gate.

7. The memory circuit according to claim 1, wherein The first latch comprises: A second inverter having an input terminal and an output terminal, An input terminal of the second inverter is configured to receive the first signal and is coupled to the first node and the output of the NAND logic gate; and An output terminal of the second inverter is configured to output a second signal inverted from the first signal.

8. The memory circuit according to claim 7, wherein: The first latch further includes: a first P-type transistor, a gate of the first P-type transistor being configured to receive the second signal, a source of the first P-type transistor being coupled to a first voltage source node, and a drain of the first P-type transistor being coupled to at least the first node; and a first N-type transistor, a gate of the first N-type transistor being configured to receive the second signal and coupled to the gate of the first P-type transistor and the output of the second inverter, a source of the first N-type transistor being coupled to a second voltage source node, and a drain of the first N-type transistor being coupled to the first node and the drain of the first P-type transistor.

9. The memory circuit according to claim 8, wherein The first latch further includes: a second P-type transistor, a gate of the second P-type transistor being configured to receive the first clock signal, a source of the second P-type transistor being coupled to a first voltage source different from the reference voltage source, and a drain of the second P-type transistor being coupled to the first voltage source node and the source of the first P-type transistor; and a second N-type transistor, wherein a gate of the second N-type transistor is configured to receive a second clock signal inverted from the first clock signal, a source of the second N-type transistor is coupled to the reference voltage source, and a drain of the second N-type transistor is coupled to the second voltage source node and the source of the first N-type transistor.

10. The memory circuit according to claim 8, wherein The first latch further includes: a second P-type transistor, a gate of the second P-type transistor being configured to receive the first precharge signal and a source of the second P-type transistor being coupled to a first voltage source different from the reference voltage source; and a third P-type transistor, wherein the gate of the third P-type transistor is configured to receive a second pre-charge signal different from the first pre-charge signal, the source of the third P-type transistor is coupled to the drain of the second P-type transistor, and the drain of the third P-type transistor is coupled to the first voltage source node and the source of the first P-type transistor.

11. The memory circuit according to claim 8, wherein The first latch further includes: a second N-type transistor having a gate configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal and a source coupled to the reference voltage source; and a third N-type transistor, a gate of the third N-type transistor being configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal, a source of the third N-type transistor being coupled to the drain of the second N-type transistor, and a drain of the third N-type transistor being coupled to the second voltage supply node and the source of the first N-type transistor.

12. A memory circuit comprising: a NAND logic gate configured to receive a first bit line signal and a second bit line signal and generate a first signal in response to the first bit line signal and the second bit line signal; A first N-type transistor having: a first drain coupled to the first voltage source node of the NAND logic gate; and a first gate configured to receive a first precharge signal; and a first source coupled to the first node; A second N-type transistor having: a second drain coupled to the first drain and the first voltage source node of the NAND logic gate; a second gate a first electrode configured to receive a second pre-charge signal different from the first pre-charge signal; and a second source coupled to the first source and the first node; a first latch coupled to the NAND logic gate via a second node and configured to latch the first signal in response to at least the first precharge signal or the second precharge signal; as well as A first inverter is coupled to the NAND logic gate and configured to output a data signal inverted from the first signal.

13. The memory circuit according to claim 12, wherein: The NAND logic gate has a second voltage supply node coupled to a first voltage supply, and The first source, the second source, and the first node are coupled to a reference voltage source.

14. The memory circuit according to claim 13, wherein: The first latch comprises: A second inverter having an input terminal and an output terminal, An input terminal of the second inverter is configured to receive the first signal and is coupled to the output of the NAND logic gate and the second node; and An output terminal of the second inverter is configured to output a second signal inverted from the first signal.

15. The memory circuit according to claim 14, wherein The first latch further includes: a first P-type transistor having: a third gate configured to receive the second signal; a third source coupled to a third voltage source node; and a third drain coupled to at least the second node; and A third N-type transistor has: a fourth gate configured to receive the second signal and coupled to the third gate and the output of the second inverter; a fourth source coupled to a fourth voltage source node; and a fourth drain coupled to the third drain and the second node.

16. The memory circuit according to claim 15, wherein The first latch further includes: a second P-type transistor having: a fifth gate configured to receive the first precharge signal; and a fifth source coupled to the first voltage source; and A third P-type transistor has: a sixth gate configured to receive a second pre-charge signal different from the first pre-charge signal; a sixth source coupled to the fifth drain of the second P-type transistor; and a sixth drain coupled to the third voltage source node and the third source.

17. The memory circuit according to claim 16, wherein: The first latch further includes: a second N-type transistor, a seventh gate of the second N-type transistor being configured to receive an inverted second pre-charge signal inverted from the second pre-charge signal, and a seventh source of the second N-type transistor being coupled to the reference voltage source; and A third N-type transistor has: an eighth gate configured to receive an inverted first pre-charge signal inverted from the first pre-charge signal; an eighth source coupled to the seventh drain of the second N-type transistor; and an eighth drain coupled to the fourth voltage source node and the fourth source.

18. The memory circuit of claim 12, further comprising: A third N-type transistor having: a third gate configured to receive the first clock signal; a third drain coupled to the first source, the second source and the first node; and a third source coupled to a reference voltage source; as well as A first P-type transistor having: a fourth source coupled to a first voltage source; a fourth gate configured to receive a second clock signal inverted from the first clock signal; and a fourth drain coupled to the second voltage source node of the NAND logic gate.

19. A method of operating a memory circuit, the method comprising: receiving a first bit line signal and a second bit line signal through a NAND logic gate circuit; Generating a first signal in response to the first bit line signal and the second bit line signal by the NAND logic gate circuit, wherein generating the first signal comprises: The NAND logic gate circuit is enabled in response to at least a first precharge signal; and a state of the first signal is latched by a latch in response to at least the first precharge signal or a first clock signal, the latch including a first inverter and a second inverter.

20. The method according to claim 19, wherein Enabling the NAND logic gate circuit in response to at least the first precharge signal includes: turning on at least a first N-type transistor in response to the first precharge signal, the first N-type transistor being coupled between the NAND logic gate circuit and a reference power supply voltage node; and Latching a state of the first signal in response to at least the first precharge signal or the first clock signal includes: disabling a NAND logic gate circuit in response to at least the first precharge signal; and The second inverter is enabled in response to at least the first precharge signal or the first clock signal.

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