A method of manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method, and relates to the technical field of semiconductors, which prevents the first gate electrode on a second region from being damaged when the first gate electrode on a first region is removed. The semiconductor device manufacturing method comprises the following steps: forming at least one layer of first nanowires or sheets on a first region of a substrate, and forming at least one layer of second nanowires or sheets on a second region of the substrate. A first mask layer and a second mask layer are formed. The first mask layer is filled in at least one gap. The second mask layer covers the second region. An etching selectivity ratio of the first mask layer and the second mask layer is greater than a preset threshold. Under the mask effect of the second mask layer, a part of the first mask layer corresponding to the first region is removed, and the first gate electrode on the first region is removed. A second gate electrode is formed on at least a first gate dielectric layer located at the periphery of the at least one layer of first nanowires or sheets, and the second gate electrode and the first gate electrode are different in material and / or thickness.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a manufacturing method of semiconductor device. BACKGROUND

[0002] In actual manufacturing process of semiconductor device, a first ring gate transistor is formed on a first region of the semiconductor device. A second ring gate transistor is formed on a second region of the semiconductor device. In order to make the two ring gate transistors have different threshold voltages, a commonly used method is to set the gate of the two ring gate transistors as different materials and / or different thicknesses.

[0003] However, in the semiconductor device obtained by using the existing manufacturing method, the gate of the first ring gate transistor or the second ring gate transistor cannot meet the requirement of the corresponding threshold voltage, thereby resulting in a low yield of the semiconductor device. SUMMARY

[0004] The present application aims to provide a manufacturing method of semiconductor device, which is used to make the first gate on the second region remain intact when the first gate on the first region is removed, and thereby make the threshold voltages of the first ring gate transistor and the second ring gate transistor both meet the working requirement, and improve the yield of the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of semiconductor device, which comprises:

[0006] A substrate is provided, which has a first region and a second region.

[0007] At least one layer of first nanowire or sheet is formed on the first region to form a first ring gate transistor, and at least one layer of second nanowire or sheet is formed on the second region to form a second ring gate transistor. A first gate dielectric layer and a first gate are sequentially formed around the outer periphery of the at least one layer of first nanowire or sheet and the at least one layer of second nanowire or sheet, and on the substrate. There is a gap between at least part of two adjacent layers of first gate along the thickness direction of the substrate.

[0008] A first mask layer and a second mask layer are formed. The first mask layer at least fills in the gap. The second mask layer covers the second region. The etching selectivity ratio of the first mask layer and the second mask layer is greater than a preset threshold value.

[0009] Under the masking effect of the second mask layer, the part of the first mask layer corresponding to the first region is removed; and the first gate on the first region is removed.

[0010] A second gate is formed on at least the first gate dielectric layer located at the outer periphery of the at least one layer of first nanowire or sheet, and the material and / or thickness of the second gate and the first gate are different.

[0011] Compared with the prior art, the manufacturing method of the semiconductor device provided by the application first covers a second mask layer on the second region before removing the part of the first mask layer corresponding to the first region. The etching selectivity ratio of the first mask layer to the second mask layer is greater than a preset threshold. Based on this, in the actual application process, even if it takes a long etching time to completely remove the part of the first mask layer corresponding to the first region, the etchant for etching the first mask layer will not etch the second mask layer, or the etching amount of the etchant on the second mask layer is small, so as not to expose the first gate located in the second region. Thus, when the first gate located in the first region is removed, the first gate located in the second region can be completely retained under the masking effect of the second mask layer. At the same time, because the materials and / or thicknesses contained in the first gate and the second gate are different. Therefore, the first ring gate transistor and the second ring gate transistor formed by the manufacturing method provided by the application can also prevent the boundary between the first ring gate transistor and the second ring gate transistor from moving under the premise of having different threshold voltages, and improve the yield of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0013] Figure 1 is a structure sectional view of the prior art after forming a mask material covering the first region and the second region of the semiconductor device and filling the gap;

[0014] Figure 2 is a structure sectional view after removing the part of the mask material covering the first region on the basis of Figure 1 ;

[0015] Figure 3 is a structure sectional view after removing the part of the mask material located in the gap in the first region on the basis of Figure 2 ;

[0016] Figure 4 is a structure sectional view after forming a first gate dielectric layer and a first gate in the embodiment of the application;

[0017] Figure 5 is a structure sectional view after covering the first mask layer on the first region and the second region and filling the gap with the first mask layer in the embodiment of the application on the basis of Figure 4 ;

[0018] Figure 6 is a structure sectional view after forming a first gate dielectric layer and a first gate in the embodiment of the application; Figure 5a structure sectional view after removing a part of the first mask material layer covering the second region on the basis of the structure sectional view shown in FIG. 6;

[0019] Figure 7 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 6 a structure sectional view after covering a second mask material layer on the basis of the structure sectional view shown in FIG. 6;

[0020] Figure 8 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 7 a structure sectional view after performing etching back processing on the second mask material layer on the basis of the structure sectional view shown in FIG. 6, until the top of the second mask material layer is flush with the top of the part of the first mask layer covering the first region;

[0021] Figure 9 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 8 a structure sectional view after removing the part of the first mask layer corresponding to the first region on the basis of the structure sectional view shown in FIG. 6;

[0022] Figure 10 for the embodiment of the present application after removing the first gate electrode located in the first region;

[0023] Figure 11 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 10 a structure sectional view after forming a second gate electrode on the basis of the structure sectional view shown in FIG. 6;

[0024] Figure 12 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 11 a structure sectional view after removing the remaining part of the first mask layer and the second mask layer on the basis of the structure sectional view shown in FIG. 6;

[0025] Figure 13 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 10 a structure sectional view after removing the remaining part of the first mask layer and the second mask layer on the basis of the structure sectional view shown in FIG. 6;

[0026] Figure 14 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 13 a structure sectional view after forming a second gate electrode on the basis of the structure sectional view shown in FIG. 6;

[0027] Figure 15 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 5 a structure sectional view after removing the part of the first mask material layer covering the first region and the second region on the basis of the structure sectional view shown in FIG. 6;

[0028] Figure 16 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 15 a structure sectional view after covering a second mask material layer on the first region and the second region on the basis of the structure sectional view shown in FIG. 6;

[0029] Figure 17 for the embodiment of the present application on the basis of the structure sectional view shown in FIG. 5; Figure 16a structure sectional view after removing a part of the second mask material layer covering the first region on the basis of the structure sectional view of Fig. 1;

[0030] Figure 18 A process flow chart of a semiconductor device manufacturing method is provided for the embodiments of the present application.

[0031] Reference signs: 1 is a first region; 2 is a second region; 3 is a first nanowire or sheet; 4 is a second nanowire or sheet; 5 is a first gate dielectric layer; 6 is a first gate electrode; 7 is a void; 8 is a first mask layer; 9 is a second mask layer; 10 is a first mask material layer; 11 is a second mask material layer; 12 is a second gate electrode. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, the description of well-known structures and techniques is omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0033] In the drawings, various structural schematic diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details may be omitted. The shapes of various regions, layers, and the relative size and positional relationship therebetween shown in the drawings are merely exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0034] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0035] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0036] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0037] Referring to Figures 1 to 3 , the prior art is described, the semiconductor device includes a first region 1 and a second region 2. The first region 1 is provided with a first ring gate transistor. The second region 2 is provided with a second ring gate transistor. The first ring gate transistor and the second ring gate transistor can be N-type ring gate transistors and P-type ring gate transistors, respectively. Alternatively, the first ring gate transistor and the second ring gate transistor are both N-type ring gate transistors. Alternatively, the first ring gate transistor and the second ring gate transistor are both P-type ring gate transistors. In the process of obtaining the first ring gate transistor and the second ring gate transistor with different threshold voltages by the existing manufacturing method, the first gate on the first region 1 is usually removed first, and the first gate on the second region 2 is retained, and then a second gate with different materials and / or thickness from the first gate is formed on the first region 1. In actual application, referring to Figure 1 , when the mask layer is formed, the mask material will cover the first region 1 and the second region 2 at the same time, and fill the gap 7 between the first gate 6 of the adjacent layer. Then, referring to Figure 2 , the mask material on the first region 1 is selectively removed. At this time, it is relatively easy to remove the part of the mask material covering the first region 1, but because the size of the gap 7 of the first region 1 is small, it takes a long etching time to completely remove the part of the mask material in the gap 7 of the first region 1. Referring to Figure 3Because the portion of the mask material in the second region 2 contains the same material as the portion in the first region 1, the etchant also removes the portion of the mask material in the second region 2 during this period, resulting in partial or complete exposure of the first gate 6 in the second region 2. Consequently, when the first gate 6 in the first region 1 is subsequently removed, because the first gate 6 in the second region 2 contains the same material as the first gate 6 in the first region 1, the exposed portion of the first gate 6 in the second region 2 is also damaged and cannot be completely preserved. This causes the boundary between the first gate-ring transistor and the second gate-ring transistor to shift, resulting in the threshold voltage of the second gate-ring transistor not meeting requirements. This, in turn, leads to a decrease in the yield of the semiconductor device and affects the performance of the manufactured semiconductor device.

[0038] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a semiconductor device. This method involves covering a second mask layer on a second region before removing a portion of the first mask layer corresponding to a first region. The etching selectivity ratio between the second mask layer and the first mask layer is greater than a preset threshold, and the portion of the first mask layer corresponding to the first region is removed under the masking effect of the second mask layer. Thus, even if completely removing the first mask layer located within the gaps in the first region requires a long etching time, the etchant used to etch the first mask layer will not etch the second mask layer, or the etchant's etching amount on the second mask layer will be minimal, thereby preventing the first gate located in the second region from being exposed. When removing the first gate located in the first region, the first gate in the second region is not damaged under the masking effect of the second mask layer and is thus completely preserved.

[0039] Reference Figure 18 This invention provides a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 4 to 17 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes:

[0040] First, a substrate is provided; the substrate has a first region and a second region.

[0041] Specifically, the substrate can be any semiconductor substrate, such as a silicon substrate, a silicon-on-insulator substrate, a germanium-silicon substrate, or a germanium substrate. (See reference...) Figures 11 to 14 The substrate has a first region 1, which is the region corresponding to the formation of the first gate ring transistor. Therefore, the position of the first region 1 on the substrate and the type of impurities doped in the first region 1 can be set with reference to the formation position of the first gate ring transistor on the substrate and the conductivity type of the first gate ring transistor. The position of the second region 2 on the substrate and the type of impurities doped in the second region 2 can be set with reference to the formation position of the second gate ring transistor on the substrate and the conductivity type of the second gate ring transistor.

[0042] For example, in the case that the first and second ring gate transistors are both N-type transistors, the first and second regions are doped with P-type impurities. In the case that the first and second ring gate transistors are both P-type transistors, the first and second regions are doped with N-type impurities. In the case that the first and second ring gate transistors are N-type and P-type transistors respectively, the first and second regions are doped with P-type and N-type impurities respectively.

[0043] In some cases, a shallow trench isolation for defining the active region is further formed on the substrate. The material contained in the shallow trench isolation can be an insulating material such as SiN, Si3N4, SiO2, SiCO, etc.

[0044] Reference is made to Figure 4 The formation of the first ring gate transistor on the first region 1 includes at least one layer of first nanowires or sheets 3, and the formation of the second ring gate transistor on the second region 2 includes at least one layer of second nanowires or sheets 4. A first gate dielectric layer 5 and a first gate electrode 6 are sequentially formed around the outer periphery of the at least one layer of first nanowires or sheets 3 and the at least one layer of second nanowires or sheets 4, and on the substrate. Along the thickness direction of the substrate, there is a gap 7 between at least some adjacent two layers of first gate electrodes 6.

[0045] Specifically, as mentioned above, the conductive types of the first and second ring gate transistors can be the same or different. For example, both can be N-type transistors or P-type transistors. One can be an N-type transistor and the other can be a P-type transistor.

[0046] As to the material and the number of layers contained in the first and second nanowires or sheets, they can be set according to actual needs. For example, the material contained in the first nanowires or sheets can be Si 1-x Ge x , where 0≤x≤1. For example, the material contained in the first nanowires or sheets can be Si, Si 0.5 Ge 0.5 , Ge, etc. And the material contained in the second nanowires or sheets can be Si 1-y Ge y , where 0≤y≤1. For example, the material contained in the second nanowires or sheets can be Si, Si 0.75 Ge 0.25 , Ge, etc. Specifically, the materials contained in the first and second nanowires or sheets can be the same or different.

[0047] In addition, when the first ring gate transistor includes at least two layers of the first nanowire or sheet, the spacing between the first nanowire or sheet in the bottom layer and the substrate, and the spacing between adjacent first nanowires or sheets can be the same or different. When the second ring gate transistor includes at least two layers of the second nanowire or sheet, the spacing between the second nanowire or sheet in the bottom layer and the substrate, and the spacing between adjacent second nanowires or sheets can be the same or different.

[0048] As for the specific location of the above-mentioned gap, it can be divided into the following cases according to the number of layers of the first nanowire or sheet formed on the first region, and the number of layers of the second nanowire or sheet formed on the second region:

[0049] If the first region only has one layer of the first nanowire or sheet, then the first gate surrounding the outer periphery of the first nanowire or sheet in the bottom layer has a gap with the first gate on the substrate. Similarly, if there is only one layer of the second nanowire or sheet on the second region, then the first gate surrounding the outer periphery of the second nanowire or sheet in the bottom layer has a gap with the first gate on the substrate.

[0050] Referring to Figure 4 In the case where the first ring gate transistor has at least two layers of the first nanowire or sheet 3, the gap 7 is between the first gate 6 on the substrate and the first gate 6 surrounding the outer periphery of the first nanowire or sheet 3 in the bottom layer, and / or between the first gates 6 surrounding the outer periphery of the first nanowire or sheet 3 in adjacent two layers. Specifically, there can be a gap between the first gate surrounding only the outer periphery of the first nanowire or sheet in the bottom layer and the first gate on the substrate. Alternatively, at least one pair of first gates surrounding the outer periphery of two adjacent first nanowires or sheets has a gap. Alternatively, referring to Figure 4 , the first gate 6 surrounding the outer periphery of the first nanowire or sheet 3 in the bottom layer has a gap 7 with the first gate 6 on the substrate, and at least one pair of first gates 6 surrounding the outer periphery of two adjacent first nanowires or sheets 3 also has a gap 7.

[0051] Referring to Figure 4 In the case where the second ring gate transistor has at least two layers of the second nanowire or sheet 4, the gap 7 is between the first gate 6 on the substrate and the first gate 6 surrounding the outer periphery of the second nanowire or sheet 4 in the bottom layer, and / or between the first gates 6 surrounding the outer periphery of the second nanowire or sheet 4 in adjacent two layers. Specifically, the second region 2 has a gap 7 with the first region 1, which will not be described here.

[0052] The material and thickness of the first gate dielectric layer and the first gate can be set according to actual requirements. For example, the material of the first gate dielectric layer can be HfO2, ZrO2, TiO2, or Al2O3, or other material with high dielectric constant. The material of the first gate can be TiN, TaN, or TiSiN, or other conductive material.

[0053] In some cases, the first region further has a source region, a drain region, a side wall, and a dielectric layer included in the first ring gate transistor formed thereon. The first nanowire or sheet is located between and in contact with the source region and the drain region. The dielectric layer covers at least the source region and the drain region. The side wall is located between the dielectric layer and the first gate dielectric layer and the first gate. Correspondingly, the second region further has a source region, a drain region, a side wall, and a dielectric layer included in the second ring gate transistor formed thereon. Specifically, the positional relationship between the structures included in the second ring gate transistor can refer to the positional relationship between the structures in the first ring gate transistor, which will not be described herein. The material of the source region and the drain region can be Si, Ge, or other semiconductor material. The material of the side wall and the dielectric layer can be silicon oxide, silicon nitride, silicon carbon oxide, or other insulating material.

[0054] In actual application, the at least one layer of first nanowire or sheet on the first region to form the first ring gate transistor and the at least one layer of second nanowire or sheet on the second region to form the second ring gate transistor can include the following steps: first, along the thickness direction of the substrate, at least one layer of stack can be formed on the substrate by epitaxial growth or other processes. Each layer of stack includes a sacrificial layer and a channel layer on the sacrificial layer. The thickness of the sacrificial layer and the channel layer can be set according to actual needs. Etching the at least one layer of stack and the substrate from top to bottom to form a first fin structure on the first region and a second fin structure on the second region. Form a shallow trench isolation on the part of the substrate exposed outside the first fin structure and the second fin structure. The part of the first fin structure and the second fin structure exposed outside the shallow trench isolation is the first fin part and the second fin part respectively. The first fin part and the second fin part each have a source region forming area, a drain region forming area, and a transition area between the source region forming area and the drain region forming area. Form a sacrificial gate and a sidewall covering the outer periphery of the transition area of the first fin part and the second fin part. The length extension direction of the sacrificial gate is different from the length extension direction of the first fin part and the second fin part. The sidewall is at least located on both sides of the sacrificial gate in the width direction. Then, remove the part of the first fin part and the second fin part in the source region forming area and the drain region forming area. And at least in the source region forming area and the drain region forming area on the first region to form the source region and the drain region of the first ring gate transistor, at least in the source region forming area and the drain region forming area on the second region to form the source region and the drain region of the second ring gate transistor. Then, form a dielectric material covering the formed structure, and perform a back etching process on the dielectric material until the top of the sacrificial gate is exposed, and the remaining part of the dielectric material forms a dielectric layer. Then, remove the sacrificial gate, and remove the part of the sacrificial layer in the transition area included in the first fin part and the second fin part, so that the part of the channel layer in the transition area on the first region forms a corresponding first nanowire or sheet, and the part of the channel layer in the transition area on the second region forms a corresponding second nanowire or sheet. Refer to Figure 4 The first gate dielectric layer 5 and the first gate 6 can be formed in sequence on the outer periphery of the first nanowire or sheet 3 and the outer periphery of the second nanowire or sheet 4 by atomic layer deposition or other processes. As known from the above, the thickness of each layer of sacrificial layer determines the existence form of the above-mentioned void 7, so the thickness of each layer of sacrificial layer can be set by referring to the position of the void 7 described in the foregoing. For example, taking the first region as an example, in the case of forming at least two layers of first nanowire or sheet on the first region, if the void is only located between the substrate and the bottommost layer of first nanowire or sheet, the thickness of the bottommost layer of sacrificial layer is greater than that of the remaining sacrificial layers.

[0055] It should be noted that the above structure can be formed in various ways. How to form the above structure is not the main feature of the embodiments of the present application, and therefore, in the present specification, only a brief introduction is made so that the person skilled in the art can easily implement the present application. The person skilled in the art can fully conceive other ways to make the above structure.

[0056] With reference to Figures 4 to 8 , and Figure 16 and Figure 17 , the first mask layer 8 and the second mask layer 9 are formed. The first mask layer 8 at least fills in the gap 7. The second mask layer 9 covers the second region 2. The etching selectivity ratio of the first mask layer 8 and the second mask layer 9 is greater than a preset threshold.

[0057] It should be noted that the etching selectivity ratio of the first mask layer and the second mask layer refers to the quotient obtained by dividing the etching rate of the first mask layer by the etching rate of the second mask layer under a certain etching process. Due to the difference in the materials contained in the first mask layer and the second mask layer, as well as the actual application scenarios and other factors, the size of the above-mentioned preset threshold can also be different, and therefore, the size of the preset threshold is not specifically limited. It is only necessary to satisfy that when the part of the first mask layer located in the gap in the first region is completely removed, the second mask layer is still retained and can cover the first gate on the second region so that it is not exposed. For example: the above-mentioned preset threshold can be greater than or equal to 5:1.

[0058] Specifically, the materials contained in the first mask layer and the second mask layer, as well as the forming process of the two, can be set according to the actual situation. For example: the first mask layer or the second mask layer can be a bottom anti-reflective layer or a spin-on carbon layer. In addition, a spin coating process or the like can be used to form the first mask layer and the second mask layer to obtain uniform first mask layer and second mask layer. At this time, the first mask layer and the second mask layer are both spin-on mask layers. Of course, the first mask layer and the second mask layer can also be formed by other processes.

[0059] In addition, with reference to Figure 8 , the above-mentioned first mask layer 8 at least filling in the gap can be that the first mask layer 8 covers the first region 1 and fills in the gap. Alternatively, with reference to Figure 17 , the first mask layer 8 can only fill in the gap. It can be understood that due to the different formation ranges of the first mask layer 8, the process of manufacturing the first mask layer 8 and the second mask layer 9 can also be different. Specifically, the above-mentioned formation of the first mask layer 8 and the second mask layer 9 can be divided into the following two cases:

[0060] The first case: with reference to Figure 8 , the first mask layer 8 covers the first region 1 and fills in the gap., the first mask layer 8 covers the first region 1 and fills the gap. In this case, the forming of the first mask layer 8 and the second mask layer 9 includes the following steps:

[0061] Referring to Figure 4 and Figure 5 , the first mask material layer 10 is formed to cover the first region 1 and the second region 2 and fill the gap 7.

[0062] It should be noted that the first mask material layer covering the first region means that the first mask material layer covers the top and sidewall of the whole structure composed of at least one layer of first nanowires or sheets. Similarly, the first mask material layer covering the second region means that the first mask material layer covers the top and sidewall of the whole structure composed of at least one layer of second nanowires or sheets.

[0063] In actual application, the first mask material layer is the film layer for forming the first mask layer, so its forming process can be selected according to the information such as the material contained in the first mask layer. For example, when the first mask layer is a spin-on carbon layer, a spin coating process can be used to form the first mask material layer. When the first mask layer is a bottom anti-reflective layer, a physical vapor deposition or chemical vapor deposition process can be used to form the first mask material layer.

[0064] Referring to Figure 6 , the part of the first mask material layer covering the second region 2 is selectively removed, so that the remaining part of the first mask material layer forms the first mask layer 8.

[0065] In actual application, photolithography and etching processes can be used to selectively remove the part of the first mask material layer covering the second region, and the part of the first mask material layer covering the first region and filling the gap is retained to obtain the first mask layer. Specifically, the process and etchant for etching the part of the first mask material layer covering the second region can be determined according to the material contained in the first mask material layer. For example, in the case where the material contained in the first mask material layer is a bottom anti-reflective layer, a dry etching process can be used, such as etching by F-based gas such as CF4 or using a mixed gas of F-based and O-based.

[0066] Referring to Figure 7 , the second mask material layer 11 is formed to cover the first mask layer 8 and the second region 2. Specifically, the forming process and information such as the material contained in the second mask material layer 11 can be referred to the foregoing, which will not be described here.

[0067] Referring to Figure 8The second mask material layer is etched back until the top of the second mask material layer is flush with the top of the portion of the first mask layer 8 located on the first region 1, so that the remaining second mask material layer forms a second mask layer 9.

[0068] In actual application, the process and etchant used in the etching back process can be determined according to the material contained in the second mask material layer. For example, when the second mask material layer is a bottom anti-reflective layer, dry etching can be performed using F-based gas or using a mixture of F-based and O-based gas to obtain the second mask layer.

[0069] The second case: refer to Figure 17 The first mask layer 8 is filled in the gap. In this case, the formation of the first mask layer 8 and the second mask layer 9 includes the following steps:

[0070] Refer to Figure 4 and Figure 5 , a first mask material layer 10 is formed covering the first region 1 and the second region 2, and filling in the gap 7. Specifically, the formation process of the first mask material layer 10 and other information can be referred to the foregoing, which will not be repeated here.

[0071] Refer to Figure 15 , the portion of the first mask material layer covering the first region 1 and the second region 2 is removed, so that the portion of the first mask material layer remaining in the gap forms the first mask layer 8. Specifically, the first mask material layer can be etched directly according to the etching process and etchant described above. The portion of the first mask material layer located in the gap is preserved by the first gate.

[0072] Refer to Figure 16 , a second mask material layer 11 is formed covering the first region 1 and the second region 2. Specifically, the formation process of the second mask material layer 11 and other information can be referred to the foregoing, which will not be repeated here.

[0073] Refer to Figure 17 , the portion of the second mask material layer covering the first region 1 is selectively removed, so that the remaining second mask material layer forms the second mask layer 9. Specifically, the portion of the second mask material layer covering the first region 1 can be selectively removed using processes such as photolithography and etching. The specific etching process and etchant used can be referred to the foregoing, which will not be repeated here.

[0074] Refer to Figure 8 , Figure 9 and Figure 17 , under the mask action of the second mask layer 9, the portion of the first mask layer 8 corresponding to the first region 1 is removed; and the first gate 6 corresponding to the first region 1 is removed.

[0075] Specifically, removing the part of the first mask layer corresponding to the first region means that Figure 8 if the first mask layer 8 not only fills in the gap but also covers the first region 1, the part of the first mask layer 8 covering the first region 1 and filling in the gap on the first region 1 needs to be removed. Referring to Figure 17 if the first mask layer 8 only fills in the gap on the first region 1 and the second region 2, only the part of the first mask layer 8 filling in the gap on the first region 1 needs to be removed. The etching process and etchant used to remove the part of the first mask layer 8 corresponding to the first region 1 can be set according to the material contained in the first mask layer 8 and the actual application scenario.

[0076] For example, in the case of a bottom anti-reflective layer as the first mask layer, dry etching can be performed using F-based gas or a mixture of F-based and O-based gas to remove the part of the first mask layer corresponding to the first region. Of course, a suitable etching liquid can also be selected for wet etching.

[0077] For another example, in the case of a spin-on carbon layer as the first mask layer, dry etching can be performed using a mixture of O2 and N2 or a mixture of O2, CH4 and Ar to remove the part of the first mask layer corresponding to the first region. Of course, a suitable etching liquid can also be selected for wet etching.

[0078] In addition, referring to Figure 9 and Figure 10 after removing the part of the first mask layer corresponding to the first region 1, the entire first gate 6 on the first region 1 is exposed. Then, the first gate 6 on the first region 1 can be removed by dry etching or wet etching process. Specifically, the etchant used can be determined according to the material contained in the first gate 6. For example, when the material contained in the first gate 6 is TiN, a mixed solution of NH4OH, H2O2 and H2O or a mixed solution of HCI, H2O2 and H2O can be used to etch and remove the first gate 6.

[0079] Referring to Figures 10 to 14 at least a second gate 12 is formed on at least one first gate dielectric layer 5 located on the periphery of at least one first nanowire or sheet 3. The second gate 12 and the first gate 6 contain different materials and / or have different thicknesses.

[0080] Specifically, referring to Figure 10After the first gate electrode in the first region 1 is removed, the second mask layer 9 still covers the second region 2 and the gap in the second region 2 is filled with the remaining part of the first mask layer 8. Based on this, the forming position of the second gate electrode 12 is different according to the removal sequence of the second mask layer 9 and the remaining part of the first mask layer 8. Specifically, it can be divided into the following two cases:

[0081] The first case: referring to Figures 10 to 12 , after the second gate electrode 12 is formed on at least the first gate dielectric layer 5 located at the outer periphery of at least one layer of the first nanowire or sheet 3, the manufacturing method of the semiconductor device further comprises the step of removing the second mask layer 9 and the remaining part of the first mask layer 8.

[0082] In actual application, in this case, referring to Figure 11 , the second gate electrode 12 can be formed by atomic layer deposition and other processes first. Referring to Figure 12 , the second mask layer and the remaining part of the first mask layer in the gap in the second region are removed by etching process. At this time, the gate electrode on the second region 2 is still the original first gate electrode 6. It should be noted that when the second gate electrode is formed on the outer periphery of the first gate dielectric layer in the first region, the upper surface of the second mask layer will also deposit the second gate electrode. At this time, the second gate electrode on the second mask layer can be removed by planarization or selective removal, so as to expose the upper surface of the second mask layer, and then remove the remaining part of the second mask layer and the first mask layer.

[0083] In addition, the material and thickness of the second gate electrode can be set according to the actual application scenario, which is not limited here. Specifically, the material and thickness of the second gate electrode can be set according to the actual application scenario, as long as at least one of the material and thickness of the second gate electrode is different from the material and thickness of the first gate electrode, respectively.

[0084] The second case: referring to Figure 10 , Figure 13 and Figure 14 , after the first gate electrode 6 on the first region 1 is removed, and before the second gate electrode 12 is formed on at least the first gate dielectric layer 5 located at the outer periphery of at least one layer of the first nanowire or sheet 3, the manufacturing method of the semiconductor device further comprises the step of removing the second mask layer 9 and the remaining part of the first mask layer 8.

[0085] In actual application, in this case, referring to Figure 13 , the second mask layer and the remaining part of the first mask layer are removed by etching process first. At this time, the first gate dielectric layer 5 located on the first region 1 and the first gate electrode 6 located on the second region 2 are exposed. Referring to Figure 14Then, a second gate 12 is formed on the first gate dielectric layer 5 in the first region 1 by atomic layer deposition or other processes. In this process, the second gate 12 is also formed on the first gate 6 in the second region 2. Accordingly, the gate of the second ring gate transistor is composed of the first gate 6 and the second gate 12. The gate of the first ring gate transistor is composed of the second gate 12. Based on this, the threshold voltage of the first ring gate transistor and the second ring gate transistor is different due to the difference in the material and / or thickness of the second gate 12 and the second gate 12.

[0086] It should be noted that, when removing the remaining part of the second mask layer and the first mask layer, an etchant with a similar etching rate for the second mask layer and the first mask layer can be selected to remove the two layers at one time. Alternatively, different etchants can be selected to remove the second mask layer first and then remove the remaining part of the first mask layer.

[0087] As can be seen from the above, with reference to Figures 4 to 17 , the second mask layer 9 is covered on the second region 2 before the first mask layer 8 in the first region 1 is removed. The etching selectivity ratio of the second mask layer 9 to the first mask layer 8 is greater than a preset threshold value. The first mask layer 8 in the first region 1 is removed under the masking effect of the second mask layer 9. In this way, when the part of the first mask layer 8 in the first region 1 is completely removed, the second mask layer 9 is still retained and can cover the first gate 6 in the second region 2, so that the first gate 6 is not exposed. In this way, when the first gate 6 in the first region 1 is removed, the first gate 6 in the second region 2 can be completely retained under the masking effect of the second mask layer 8. The semiconductor device manufactured by the method has better performance.

[0088] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0089] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a substrate; The substrate has a first region and a second region; The first ring gate transistor is formed in the first region, comprising at least one layer of first nanowire or sheet, and the second ring gate transistor is formed in the second region, comprising at least one layer of second nanowire or sheet; a first gate dielectric layer and a first gate are sequentially formed around the outer periphery of the at least one layer of first nanowire or sheet and the at least one layer of second nanowire or sheet, and on the substrate; along the thickness direction of the substrate, there is a gap between at least some adjacent first gate layers; A first mask material layer is formed covering the first region and the second region, and filling the gaps therein; Selectively remove the portion of the first mask material layer covering the second region, such that the remaining portion of the first mask material layer forms the first mask layer; A second mask material layer is formed covering the first mask layer and the second region; The second mask material layer is etched back until the top of the second mask material layer is flush with the top of the portion of the first mask layer covering the first region, so that the remaining second mask material layer forms the second mask layer. The etching selectivity ratio of the first mask layer and the second mask layer is greater than a preset threshold; Under the masking effect of the second mask layer, the portion of the first mask layer corresponding to the first region is removed; And remove the first gate on the corresponding first region; A second gate is formed on at least one gate dielectric layer located on the outer periphery of the at least one first nanowire or sheet, and the second gate and the first gate contain different materials and / or have different thicknesses.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When the first ring-gate transistor has at least two layers of the first nanowires or sheets, the gap is located between the first gate located on the substrate and the outer periphery of the bottommost first nanowire or sheet, and / or between the first gates on the outer periphery of two adjacent layers of the first nanowires or sheets; and / or, In the case where the second ring gate transistor has at least two layers of the second nanowires or sheets, the gap is located between the first gate located on the substrate and the outer periphery of the bottommost second nanowire or sheet, and / or between the first gates on the outer periphery of two adjacent layers of the second nanowires or sheets.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material contained in the first nanowire or sheet is Si. 1-x Ge x ; Where 0 ≤ x ≤ 1; and / or, The material contained in the second nanowire or sheet is Si. 1-y Ge y Where 0≤y≤1.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first mask layer fills the voids; The formation of the first mask layer and the second mask layer includes: A first mask material layer is formed covering the first region and the second region, and filling the gaps therein; Remove the portion of the first mask material layer covering the first region and the second region, such that the remaining portion of the first mask material layer within the gap forms the first mask layer; A second mask material layer is formed covering the first region and the second region; The portion of the second mask material layer covering the first region is selectively removed, such that the remaining second mask material layer forms the second mask layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Both the first mask layer and the second mask layer are spin-coated mask layers.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first mask layer or the second mask layer is a bottom anti-reflective layer or a spin-coated carbon layer.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When the first mask layer is a bottom anti-reflective layer, F-based gas or a mixture of F-based and O-based gas is used to remove the portion of the first mask layer corresponding to the first region.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When the first mask layer is a spin-coated carbon layer, a mixture of O2 and N2 or a mixture of O2, CH4 and Ar is used to remove the portion of the first mask layer corresponding to the first region.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that: After forming the second gate on the first gate dielectric layer located at least on the outer periphery of the at least one first nanowire or wafer, the method of manufacturing the semiconductor device further includes: removing the second mask layer and the remaining portion of the first mask layer; or, After removing the first gate corresponding to the first region, and before forming the second gate on the first gate dielectric layer located at least on the outer periphery of the at least one first nanowire or wafer, the method of manufacturing the semiconductor device further includes: removing the second mask layer and the remaining portion of the first mask layer.

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