A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor, and is used for inhibiting the leakage of a parasitic channel in a ring gate transistor and improving the working performance of a semiconductor device comprising the ring gate transistor. The semiconductor device comprises a substrate, a ring gate transistor and an isolation layer. The ring gate transistor is formed on the substrate. The isolation layer is filled at least between the substrate and a gate stack structure possessed by the ring gate transistor, and the isolation layer is located at least below a channel possessed by the ring gate transistor. The area of the isolation layer covering the substrate is less than or equal to the area of the gate stack structure covering the substrate. The manufacturing method of the semiconductor device provided by the application is used for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Compared with a fin field effect transistor, the gate stack structure of the ring gate transistor is formed not only on the top and sidewall of the channel, but also on the bottom of the channel, so as to inhibit the short channel effect and enhance the gate control ability of the ring gate transistor.

[0003] However, in the case that the channel of the ring gate transistor comprises at least one nanosheet, it is difficult to inhibit the leakage of the parasitic channel in the ring gate transistor by using the existing punchthrough prevention implantation process, thereby reducing the working performance of the ring gate transistor. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method thereof, for inhibiting the leakage of the parasitic channel in the ring gate transistor and improving the working performance of the semiconductor device comprising the ring gate transistor.

[0005] In order to achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising: a substrate, a ring gate transistor and an isolation layer.

[0006] The ring gate transistor is formed on the substrate. The isolation layer is filled at least between the substrate and the gate stack structure of the ring gate transistor, and the isolation layer is located at least below the channel of the ring gate transistor. The area of the substrate covered by the isolation layer is less than or equal to the area of the substrate covered by the gate stack structure.

[0007] Compared with the prior art, in the semiconductor device provided by the present application, the isolation layer is filled at least between the substrate and the gate stack structure of the ring gate transistor, and the isolation layer is located at least below the channel of the ring gate transistor. That is, the isolation layer isolates the part of the gate stack structure below the channel of the ring gate transistor from the substrate. In this case, since the isolation layer has an isolation property, even if the semiconductor device provided by the present application loads a voltage of a corresponding size on the gate stack structure during operation, the semiconductor structure below the channel will not be turned on, so as to inhibit the leakage of the parasitic channel and improve the working performance of the semiconductor device.

[0008] The present application also provides a manufacturing method of a semiconductor device, comprising:

[0009] A substrate is provided.

[0010] A ring gate transistor and an isolation layer are formed on the substrate. The isolation layer at least fills between the substrate and a gate stack structure of the ring gate transistor, and the isolation layer is at least located below a channel of the ring gate transistor. An area of the substrate covered by the isolation layer is less than or equal to an area of the substrate covered by the gate stack structure.

[0011] Compared with the prior art, the semiconductor device manufacturing method provided by the present application has the same beneficial effects as the semiconductor device provided by the present application, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0013] Figure 1 A structure schematic diagram of the structure after forming the first fin structure and the barrier layer on the substrate;

[0014] Figure 2 A structure sectional view of the structure after forming the fin field effect transistor on the substrate;

[0015] Figure 3 A structure sectional view of the structure after processing the second fin structure by using the punch-through prevention implantation process;

[0016] Figure 4 A structure sectional view of the structure after forming the ring gate transistor based on the second fin structure;

[0017] Figure 5 A structure schematic diagram of the structure after forming the pre-formed layer and at least one laminated material layer on the substrate in the embodiment of the present application;

[0018] Figure 6 A structure schematic diagram of the structure after forming the fin structure on the substrate in the embodiment of the present application;

[0019] Figure 7 A structure schematic diagram of the structure after forming the shallow trench isolation on the substrate in the embodiment of the present application;

[0020] Figure 8 A first structure sectional view of the structure shown in FIG. 1 along the A-A' direction; Figure 7

[0021] A second structure sectional view of the structure shown in FIG. 1 along the A-A' direction; Figure 9 Figure 7 A third structure sectional view of the structure shown in FIG. 1 along the A-A' direction;

[0022] Figure 10 Figure 7 A fourth structure sectional view of the structure shown in FIG. 1 along the A-A' direction; ​​

[0023] Figure 11 Structure schematic diagram after forming the sacrificial gate and the side wall in the embodiment of the present application;

[0024] Figure 12 First structure schematic diagram after forming the source region and the drain region in the embodiment of the present application;

[0025] Figure 13 First structure sectional view along A-A' direction after forming the source region and the drain region in the embodiment of the present application;

[0026] Figure 14 Second structure sectional view along A-A' direction after forming the source region and the drain region in the embodiment of the present application;

[0027] Figure 15 Third structure sectional view along A-A' direction after forming the source region and the drain region in the embodiment of the present application;

[0028] Figure 16 Fourth structure schematic diagram after forming the source region and the drain region in the embodiment of the present application;

[0029] Figure 17 Fourth structure sectional view along A-A' direction after forming the source region and the drain region in the embodiment of the present application;

[0030] Figure 18 Structure schematic diagram after forming the dielectric layer and removing the sacrificial gate in the embodiment of the present application;

[0031] Figure 19 Structure sectional view along A-A' direction after forming the dielectric layer and removing the sacrificial gate in the embodiment of the present application;

[0032] Figure 20 Structure sectional view along B-B' direction after forming the dielectric layer and removing the sacrificial gate in the embodiment of the present application;

[0033] Figure 21 Structure sectional view along A-A' direction after removing the part of the pre-formed structure under at least one layer of the stack in the embodiment of the present application;

[0034] Figure 22 Structure sectional view along A-A' direction after removing the part of the pre-formed structure under at least one layer of the stack and the sacrificial layer in the embodiment of the present application;

[0035] Figure 23 First structure sectional view along A-A' direction after forming the isolation material layer in the embodiment of the present application;

[0036] Figure 24 First structure sectional view along B-B' direction after forming the isolation material layer in the embodiment of the present application;

[0037] Figure 25 A cross-sectional view of the second structure along the A-A' direction after forming the isolation material layer in the embodiment of the present application;

[0038] Figure 26 A cross-sectional view of the second structure along the B-B' direction after forming the isolation layer in the embodiment of the present application;

[0039] Figure 27 A schematic view of the first structure after forming the isolation layer in the embodiment of the present application;

[0040] Figure 28 A cross-sectional view of the first structure along the A-A' direction after forming the isolation layer in the embodiment of the present application;

[0041] Figure 29 A cross-sectional view of the first structure along the B-B' direction after forming the isolation layer in the embodiment of the present application;

[0042] Figure 30 A cross-sectional view of the second structure along the B-B' direction after forming the isolation layer in the embodiment of the present application;

[0043] Figure 31 A schematic view of the third structure after forming the isolation layer in the embodiment of the present application;

[0044] Figure 32 A cross-sectional view of the third structure along the B-B' direction after forming the isolation layer in the embodiment of the present application;

[0045] Figure 33 A cross-sectional view of the first structure along the A-A' direction after forming the ring gate transistor in the embodiment of the present application;

[0046] Figure 34 A cross-sectional view of the first structure along the B-B' direction after forming the ring gate transistor in the embodiment of the present application;

[0047] Figure 35 A cross-sectional view of the second structure along the B-B' direction after forming the ring gate transistor in the embodiment of the present application;

[0048] Figure 36 A cross-sectional view of the third structure along the B-B' direction after forming the ring gate transistor in the embodiment of the present application;

[0049] Figure 37 A flow chart of the manufacturing method of the semiconductor device provided in the embodiment of the present application.

[0050] Reference signs: 11 is a substrate, 12 is a pre-formed layer, 121 is a pre-formed structure, 13 is a stack material layer, 131 is a sacrificial material layer, 1311 is a sacrificial layer, 132 is a channel material layer, 1321 is a channel layer, 133 is a stack, 14 is a fin structure, 141 is a fin, 1411 is a source region forming area, 1412 is a drain region forming area, 1413 is a transition region, 15 is a shallow trench isolation, 16 is a sacrificial gate, 17 is a sidewall, 18 is a source region, 19 is a drain region, 20 is a dielectric layer, 21 is a gate forming area, 22 is an isolation material layer, 221 is an isolation layer, 2211 is a middle region, 2212 is an outer region, 23 is a channel, 231 is a nanosheet, 24 is a gate stack structure, 241 is a gate dielectric layer, 242 is a gate, 25 is a gate-all-around transistor, 26 is a first fin structure, 27 is a barrier layer, 28 is a second fin structure, 29 is a center region. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0052] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0053] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intervening layer / element between them. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present disclosure, the technical solutions and beneficial effects more clear and apparent, the present disclosure will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present disclosure and not to limit the present disclosure.

[0054] In addition, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0055] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0056] The fin field effect transistor has a first fin structure and a shallow trench isolation formed on a substrate. The part of the first fin structure exposed outside the shallow trench isolation is a fin portion. The part of the fin portion surrounded by the gate stack structure corresponds to the channel of the fin field effect transistor. In this case, when the fin field effect transistor is in working state, the channel is controlled by the gate stack structure, so that the conduction between the source region and the drain region can be realized. While the part of the first fin structure surrounded by the shallow trench isolation is separated from the gate stack structure by the shallow trench isolation, so that this part is away from the control of the gate stack structure, and the channel punch-through effect is easy to occur, resulting in a parasitic channel.

[0057] As shown in Figure 1 and Figure 2 To solve the problem of parasitic channel leakage in the fin field effect transistor, during the process of manufacturing the fin field effect transistor, after the first fin structure 26 and the shallow trench isolation 15 are formed on the substrate 11, the anti-punching implantation process is used to implant impurity ions opposite to the conductive type of the impurities doped in the source region and the drain region into at least the first fin structure 26, to form a blocking layer 27 in the middle and lower part of the first fin structure 26, so as to use the highly doped blocking layer 27 to suppress the parasitic channel.

[0058] With the development of semiconductor technology, gate-around transistors (GOTMTs) have emerged. Compared to fin field-effect transistors (FETs), GOTMTs have a gate stacking structure formed not only on the top and sidewalls of the channel but also at the bottom, thereby enhancing the gate control capability, suppressing short-channel effects, and resulting in higher performance. However, when the channel width of a GOTMT is wide, it is difficult to solve the problem of parasitic channel leakage using the aforementioned anti-punch-through injection process. Specifically, for example... Figure 3 and Figure 4 As shown, during the fabrication of the gate-around transistor, because the channel 23 of the gate-around transistor has a relatively wide width, the second fin structure 28 formed on the substrate 11 also has a relatively wide width. Based on this, when ionic impurities are implanted into the second fin structure 28 using a punch-through implantation process, the ionic impurities have difficulty entering the central region 29 along the width direction of the second fin structure 28; that is, the central region 29 along the width direction of the second fin structure 28 does not completely form a barrier layer 27. In this case, after applying an appropriate voltage to the gate stack structure 24 of the gate-around transistor, the source and drain regions can not only conduct through the channel, but the aforementioned central region 29 also suffers from parasitic channel leakage, thereby reducing the operating performance of the gate-around transistor.

[0059] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiments of the present invention, at least an isolation layer is filled between the substrate and the gate stack structure of the gate-around transistor. This isolation layer is located between the source and drain regions of the gate-around transistor, thereby isolating the portion of the gate stack structure located below the channel of the gate-around transistor from the substrate. This prevents the semiconductor structure below the channel from conducting, thereby suppressing parasitic channel leakage current and improving the operating performance of the semiconductor device.

[0060] like Figures 33 to 36 As shown, an embodiment of the present invention provides a semiconductor device comprising: a substrate 11, a gate-around transistor 25, and an isolation layer 221. The gate-around transistor 25 is formed on the substrate 11. The isolation layer 221 at least fills the space between the substrate 11 and the gate stack structure 24 of the gate-around transistor 25, and the isolation layer 221 is at least located below the channel of the gate-around transistor 25. The area of ​​the isolation layer 221 covering the substrate 11 is less than or equal to the area of ​​the gate stack structure 24 covering the substrate 11.

[0061] The substrate described above can be any semiconductor substrate, such as a silicon substrate, a silicon-on-insulator substrate, or a germanium-silicon substrate. In some cases, shallow trench isolation is formed on the substrate to define the active region. The material contained in the shallow trench isolation can be an insulating material such as SiN, Si3N4, SiO2, or SiCO.

[0062] like Figures 33 to 36 As shown, the aforementioned gate-ring transistor 25 may include a source region 18, a drain region 19, a channel 23, and a gate stack structure 24. Figures 8 to 15 As shown, the specific formation locations of the source region 18 and the drain region 19 differ depending on the extent to which they are formed during the manufacturing process. For example, Figure 13 As shown, when the formation range of source region 18 and drain region 19 is large, source region 18 and drain region 19 can be formed alternately on substrate 11. Alternatively, as... Figure 14 and Figure 15 As shown, when the formation range of the source region 18 and the drain region 19 is small, the source region 18 and the drain region 19 can be formed alternately on the surface of the pre-formed structure 121 (the pre-formed structure 121 is a structure pre-formed to form the isolation layer 221, which will be explained in detail in the manufacturing method below, and will not be repeated here), or formed alternately above the pre-formed structure 121. Figures 12 to 15 As shown, the source region 18 and drain region 19 can be structures formed on the substrate 11 by etching and epitaxial growth after the formation of the sacrificial gate 16 and sidewall 17. Alternatively, as... Figure 16 and Figure 17 As shown, the source region 18 and drain region 19 can be structures formed by directly implanting ions into the source and drain regions. The channel 23 is located between the source region 18 and drain region 19, and is in contact with both. The channel 23 has at least one layer of nanosheets 231 spaced along the thickness direction of the substrate 11. The lowermost nanosheet 231 is spaced from the substrate 11. The number of nanosheet layers 231, the spacing between adjacent nanosheets 231, and the quantity of nanosheets 231 can be set according to actual needs and are not specifically limited here. The spacing between the lowermost nanosheet 231 and the substrate 11 can be set according to the specifications of the gate stack structure 24 and the thickness of the isolation layer 221. The gate stack structure 24 surrounds the outer periphery of the channel 23. Specifically, the gate stack structure 24 includes a gate dielectric layer 241 surrounding the outer periphery of the channel 23 and a gate 242 formed on the gate dielectric layer 241. The thickness of the gate dielectric layer 241 and the specifications of the gate 242 can be set according to actual conditions.

[0063] The source region, drain region, and at least one nanosheet contain semiconductor materials. Specifically, the materials contained in the source and drain regions can be chosen according to actual conditions, and are not specifically limited here. The materials contained in the source and drain regions can be the same or different. The material contained in at least one nanosheet can be Si. 1-x Ge x Where 0 ≤ x ≤ 1. For example: at least one nanosheet may contain materials such as Si, Si0.5 Ge 0.5 Or Ge, etc.

[0064] The gate dielectric layer can contain materials with high dielectric constants, such as HfO2, ZrO2, TiO2, or Al2O3. The gate can contain conductive materials such as TiN, TaN, or TiSiN.

[0065] In some cases, such as Figures 33 to 36 As shown, the aforementioned gate-ring transistor 25 may further include sidewalls 17 and a dielectric layer 20. The dielectric layer 20 at least covers the surface of the source region 18 facing away from the substrate 11, and at least covers the surface of the drain region 19 facing away from the substrate 11. The top of the dielectric layer 20 may be flush with the top of the gate stack structure 24. It should be understood that during the manufacturing process of the semiconductor device provided in the embodiments of the present invention, as... Figures 18 to 32 As shown, the presence of dielectric layer 20 protects the source region 18 and drain region 19 from etching, cleaning, and other operations during the etching of the sacrificial gate and sacrificial layer 1311. Specifically, the material contained in the dielectric layer 20 can be an insulating material such as SiO2 or SiN.

[0066] For the aforementioned sidewalls, the sidewalls can be formed between the dielectric layer and the gate stack structure to facilitate the formation of a gate stack structure surrounding the outer periphery of the channel and to isolate the gate stack structure from the subsequently formed conductive structure, thereby improving the yield of the semiconductor device. The sidewalls contain insulating materials. Specifically, the materials contained in the sidewalls and the thickness of the sidewalls can be designed according to the actual application scenario, and are not specifically limited here.

[0067] like Figure 36 As shown, along the length of the isolation layer 221, the isolation layer 221 can only fill the space between the substrate 11 and the gate stack structure 24, that is, the isolation layer 221 is only located below the channel. In this case, the area of ​​the isolation layer 221 covering the substrate 11 is smaller than the area of ​​the gate stack structure 24 covering the substrate 11. Or, as... Figures 33 to 35 As shown, along the length of the isolation layer 221, the isolation layer 221 can fill the space between the gate stack structure 24 and the substrate 11, and between the gate stack structure 24 and the shallow trench isolation 15. In this case, the area of ​​the isolation layer 221 covering the substrate 11 is equal to the area of ​​the gate stack structure 24 covering the substrate 11. The bottom surface height of the isolation layer 221 can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided in this embodiment of the invention. For example, the bottom surface of the isolation layer 221 can be flush with the bottom surfaces of the source region 18 and the drain region 19 of the gate ring transistor 25.

[0068] For example, such as Figures 33 to 35As shown, when the area of ​​the isolation layer 221 covering the substrate 11 is equal to the area of ​​the gate stack structure covering the substrate 11, the isolation layer 221 has a central region 2211 and an outer region 2212 along its length. The central region 2211 is the region of the isolation layer 221 located below the channel 23. The outer regions 2212 are located on both sides of the central region 2211. The top height of the central region 2211 is greater than or equal to the top height of the outer region 2212.

[0069] In practical applications, such as Figures 21 to 32 As shown, the aforementioned isolation layer 221 is obtained by etching back the isolation material layer 22 formed in at least a portion of the gate formation region and in the cutout region located between at least one stacked layer 133 and the substrate 11. During the etching back process, under the masking effect of the topmost channel layer 1321, the portion of the isolation material layer 22 located below the at least one stacked layer 133 is retained, thereby forming the portion of the isolation layer 221 located in the middle region 2211. Along the length extension direction of the gate formation region, the portions of the isolation material layer 22 located on both sides of the middle region 2211 are not protected by the topmost channel layer 1321. Therefore, after etching back the isolation material layer 22 to obtain the isolation layer 221, the top height of the isolation layer 221 located in the outer region 2212 is less than or equal to the top height of the isolation layer 221 located in the middle region 2211. Specifically, when the top heights of the two regions are different, the height difference can be determined according to the actual situation. Therefore, the thickness of the portion of the isolation layer 221 located within the outer region 2212 can have various possible values, as long as the top height of the middle region 2211 is greater than or equal to the top height of the outer region 2212. Thus, during the back-etching process of the isolation material layer 22, it is not necessary to strictly control the etching conditions in order to obtain the isolation layer 221 formed only in the hollow area or to obtain the isolation layer 221 where the middle region 2211 is equal to the top height of the outer region 2212, thereby reducing the etching difficulty of the back-etching process.

[0070] Furthermore, as mentioned earlier, the specific locations of the source and drain regions vary depending on the extent to which they are formed during the manufacturing process. Correspondingly, the relative positions of the source and drain regions with the isolation layer also differ. Specifically, at least a portion of the isolation layer is located between the source and drain regions of the gate-around transistor. Alternatively, the isolation layer is located below the region between the source and drain regions of the gate-around transistor.

[0071] In some cases, when the source and drain regions are relatively large, they are located on the substrate. An isolation layer is located between the source and drain regions and contacts both regions. When a portion of the source and drain regions are located within the etched portion of the pre-formed layer, they are located on the surface of the pre-formed structure. A portion of the isolation layer is located between the source and drain regions and contacts both regions. In other cases, when the source and drain regions are relatively small, they are located above the pre-formed structure. The isolation layer is located below the region between the source and drain regions.

[0072] The materials contained in the aforementioned isolation layer can be configured according to actual needs. For example, the isolation layer may contain a dielectric material, including silicon oxide, silicon nitride, and silicon carbide. The thickness of the isolation layer can be 3 nm to 50 nm. Of course, the thickness of the isolation layer can also be set to other suitable values. Preferably, the thickness of the isolation layer is 10 nm to 15 nm.

[0073] As can be seen from the above, such as Figures 33 to 36 As shown, in the semiconductor device provided by this embodiment of the invention, the isolation layer 221 can isolate the portion of the gate stack structure 24 located below the channel 23 of the ring gate transistor 25 from the substrate 11. In this case, because the isolation layer 221 has isolation characteristics, even if a voltage of a corresponding magnitude is applied to the gate stack structure 24 during the operation of the semiconductor device provided by this embodiment of the invention, the semiconductor structure such as the substrate 11 located below the channel 23 will not conduct, thereby suppressing parasitic channel leakage current and improving the operating performance of the semiconductor device.

[0074] like Figure 37 As shown, embodiments of the present invention also provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 5 to 36 The illustrated perspective view and cross-sectional view describe the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes:

[0075] First, a substrate is provided. The specific details of the substrate can be found in the previous text and will not be repeated here.

[0076] like Figures 5 to 36 As shown, a gate-around transistor 25 and an isolation layer 221 are formed on a substrate 11. The isolation layer 221 at least fills the space between the substrate 11 and the gate stack structure 24 of the gate-around transistor 25, and the isolation layer 221 is located at least below the channel of the gate-around transistor 25. The area of ​​the isolation layer 221 covering the substrate 11 is less than or equal to the area of ​​the gate stack structure 24 covering the substrate 11.

[0077] Specifically, information regarding the structure of the aforementioned gate-around transistor, the materials contained in the isolation layer, and the specifications of the isolation layer can be found in the preceding text and will not be repeated here.

[0078] In one example, such as Figures 5 to 32 As shown, forming an isolation layer 221 on the substrate 11 may include the following steps:

[0079] like Figures 5 to 17 As shown, a pre-formed structure 121 and a stacked structure (not shown) are formed on a substrate 11. The stacked structure includes at least one stacked layer 133 and a source region 18 and a drain region 19 of a gate-around transistor. At least one stacked layer 133 is located on the pre-formed structure 121. At least one stacked layer 133 is located between the source region 18 and the drain region 19, and at least one stacked layer 133 is in contact with the source region 18 and the drain region 19. Each stacked layer 133 includes a sacrificial layer 1311 and a channel layer 1321 located on the sacrificial layer 1311.

[0080] Specifically, the structures of the source and drain regions, as well as the materials they contain, can be found in the preceding text and will not be repeated here. Figures 12 to 17 As shown, the relative positional relationship between the source region 18 and the drain region 19 and the pre-formed structure 121 is related to the formation range of the source region 18 and the drain region 19. Specifically, the positional relationship between the source region 18 and the drain region 19 and the pre-formed structure 121 can be divided into the following three types:

[0081] The first type: such as Figure 12 and Figure 13 ,as well as Figure 16 and Figure 17 As shown, the source region 18 and the drain region 19 can both be located on the substrate 11. The preformed structure 121 is located between the source region 18 and the drain region 19, and the preformed structure 121 is in contact with the source region 18 and the drain region 19.

[0082] The second type: such as Figure 14 As shown, the source region 18 and the drain region 19 can both be located on the preformed structure 121, and the bottom surface of the stacked structure is in contact with the top surface of the preformed structure 121.

[0083] The third type: such as Figure 15 As shown, the source region 18 and the drain region 19 can both be located above the preformed structure 121.

[0084] As can be seen from the above, the formation range of the source region and the drain region can be implemented in a variety of ways. Therefore, the semiconductor device manufacturing method provided by the embodiments of the present invention has the characteristics of diverse formation methods, thereby reducing the manufacturing difficulty.

[0085] The aforementioned channel layer is a film layer forming at least one nanosheet. Therefore, the number of layers in the stack on the pre-formed structure can be set according to the number of nanosheet layers in the channel. For example, when the channel has two nanosheet layers, two stacked layers need to be formed on the pre-formed structure. Furthermore, the material contained in the channel layer can also be set according to the material contained in the nanosheets. For example, the material contained in the channel layer can be Si. 1-x Ge x Where 0 ≤ x ≤ 1. The material contained in the sacrificial layer can be Si. 1-y Ge y Where 0≤y≤1 and |xy|≥0.2. Based on this, there is a certain etching selectivity between the materials contained in the sacrificial layer and the channel layer. Therefore, when the sacrificial layer is removed to form corresponding nanosheets for each channel layer, the channel layer can be unaffected by etching and other operations, thereby improving the yield of semiconductor devices.

[0086] For the aforementioned preformed structure, the region beneath at least one layer of the preformed structure (i.e., the hollowed-out region hereinafter) is the region containing at least a portion of the isolation layer. This region will be released subsequently by removing the portion of the preformed structure beneath at least one layer of the stack; therefore, the thickness of the portion of the preformed structure beneath at least one layer of the stack is equal to the thickness of the isolation layer. For example, the thickness of the portion of the preformed structure beneath at least one layer of the stack can be 3 nm to 50 nm. Furthermore, the material contained in the aforementioned preformed structure can be Si. 1-z Ge z Where 0 ≤ z ≤ 1, and |xz| ≥ 0.25, so as to facilitate the formation of at least one stacked layer on the pre-formed structure by epitaxial growth. Simultaneously, there is a certain etching selectivity between the materials contained in the pre-formed structure and the channel layer, which allows the channel layer to be unaffected by etching operations when removing the portion of the pre-formed structure located below at least one stacked layer, thereby improving the yield of the semiconductor device. Furthermore, the materials contained in the pre-formed structure also need to have a certain etching selectivity with the materials contained in the substrate. Based on this, as... Figure 21 and Figure 22 As shown, during the process of removing the portion of the preformed structure located below at least one stack 133 to obtain the cutout area, the etchant used to etch the preformed structure does not affect the substrate, thereby improving the yield of semiconductor devices.

[0087] Specifically, the material contained in the sacrificial layer can be the same as or different from the material contained in the pre-formed structure. Furthermore, when the channel layer, sacrificial layer, and pre-formed structure all contain germanium, the difference in germanium content among them can be set according to actual conditions, as long as it can be applied to the semiconductor device manufacturing method provided in this embodiment of the invention. For example, the material contained in the channel layer can be Si. The material contained in the sacrificial layer can be Si. 0.7 Ge 0.3 The material contained in the aforementioned preformed structure can be Si. 0.5 Ge 0.5 Si 0.7 Ge 0.3 Or Ge.

[0088] For example, such as Figures 5 to 17 As shown, forming the pre-formed structure 121 and the stacked structure on the substrate 11 may include the following steps:

[0089] like Figure 5 As shown, along the thickness direction of the substrate 11, a preformed layer 12 and at least one stacked material layer 13 are sequentially formed on the substrate 11.

[0090] Specifically, such as Figures 5 to 17 As shown, the pre-formed layer 12 is a film layer forming the pre-formed structure 121, therefore, the thickness of the pre-formed layer 12 is equal to the thickness of the portion of the pre-formed structure 121 located below at least one layer of the stack. Figures 5 to 17 As shown, the aforementioned at least one layer of laminated material 13 is at least a film layer forming the aforementioned at least one layer of laminate 133, therefore the number of layers of laminated material 13 is equal to the number of layers of laminate 133. The sacrificial material layer 131 included in laminated material layer 13 contains the same material as the sacrificial layer 1311 included in laminate 133. The channel material layer 132 included in laminated material layer 13 contains the same material as the channel layer 1321 included in laminate 133.

[0091] In practical applications, the above-mentioned pre-formed layer and at least one stacked material layer can be sequentially formed on the substrate using processes such as epitaxial growth.

[0092] like Figure 6 As shown, fin-like structures 14 extending along a first direction are formed by etching from the top of at least one layer of stacked material down to a portion of the substrate 11. The first direction can be any direction parallel to the surface of the substrate 11.

[0093] In practical applications, etching can be performed using photolithography and etching processes according to the above etching conditions. Specifically, a photoresist layer can first be formed on the topmost layer of the stacked material. The photoresist layer is then developed and exposed to form a photoresist mask on the topmost layer of the stacked material. The area covered by the photoresist mask is the area where the fin structure will subsequently be formed. Then, under the masking effect of the photoresist mask, etching is performed from the top of at least one layer of the stacked material down to a portion of the substrate to obtain the fin structure. For example, Figure 6 and Figure 7 As shown, the depth to which the substrate 11 is etched is greater than or equal to the thickness of the shallow trench isolation 15.

[0094] like Figures 7 to 10 As shown, a shallow trench isolation 15 is formed on the portion of the substrate 11 exposed outside the fin structure. The portion of the fin structure exposed outside the shallow trench isolation 15 is a fin 141. The fin 141 has a source region forming region 1411 for forming at least a portion of the source region, a drain region forming region 1412 for forming at least a portion of the drain region, and a transition region for forming a channel and an isolation layer. The portion of at least one layer of stacked material located within the transition region 1413 is at least one stacked layer 133.

[0095] In practical applications, physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes can be used to form a dielectric material covering the substrate and fin structure. The dielectric material is then planarized to expose the top of the fin structure. Next, the dielectric material is etched back to obtain shallow trench isolation.

[0096] like Figure 11 As shown, a sacrificial gate 16 and sidewalls 17 extending in a second direction are formed on the outer periphery of the transition zone. The sidewalls 17 are located at least on both sides of the sacrificial gate 16 in the width direction. The second direction is different from the first direction.

[0097] Specifically, the second direction can be any direction parallel to the substrate surface and different from the first direction. Preferably, the second direction is orthogonal to the first direction.

[0098] In practical applications, processes such as chemical vapor deposition (CVD) can be used to deposit the gate material for forming the sacrificial gate on the fins and shallow trench isolation surfaces. Then, dry etching can be used to etch the gate material, retaining only the portion of the gate material located at the outer periphery of the transition region, thus obtaining a sacrificial gate extending along the second direction. The gate material can be an easily removable material such as amorphous silicon or polycrystalline silicon. Figure 11As shown, after forming the sacrificial gate 16, sidewalls 17 can be formed on the sidewalls of the sacrificial gate 16 in the manner described above. The sidewalls 17 can be distributed only on both sides of the sacrificial gate 16 along its width direction. Alternatively, the sidewalls can surround the sidewalls of the sacrificial gate. The material contained in the sidewalls can be an insulating material such as silicon nitride.

[0099] like Figures 12 to 17 As shown, at least the source region forming region is processed to form the source region 18, and at least the drain region forming region is processed to form the drain region 19, thereby obtaining a stacked structure; and the remaining part of the pre-forming layer forms the pre-forming structure 121.

[0100] In practical applications, dry etching or wet etching processes can be used to remove the portion of the fin located within the source and drain formation regions. For example... Figure 12 and Figure 15 As shown, the source region 18 is then epitaxially formed in the source region formation region and the drain region 19 is epitaxially formed in the drain region formation region using processes such as epitaxial growth, thereby obtaining a stacked structure. Alternatively, as... Figure 16 and Figure 17 As shown, ion implantation can be directly performed on the fin located in the source region formation region and the drain region formation region, so that the source region formation region forms the source region 18 and the drain region formation region forms the drain region 19. Specifically, the formation range of the source region and the drain region can be referred to the previous text, and will not be repeated here. The remaining part of the pre-formed layer forms the pre-formed structure 121.

[0101] Furthermore, after forming the source and drain regions and obtaining the pre-formed structure, and before proceeding with subsequent operations, a dielectric material can be formed over the formed structure using physical vapor deposition or chemical vapor deposition. A chemical mechanical polishing process is then used to planarize the dielectric material to expose the top of the sacrificial gate. The remaining portion of the dielectric material on the source and drain regions forms a dielectric layer. The specific materials contained in the dielectric layer can be found above and will not be repeated here.

[0102] like Figures 18 to 20 As shown, after forming the preformed structure 121 and the stacked structure on the substrate 11, before removing the portion of the preformed structure 121 located below at least one stacked layer 133, the manufacturing method of the semiconductor device further includes: removing the sacrificial gate so that the at least one stacked layer 133 covered by the sacrificial gate and the portion of the preformed structure 121 located below at least one stacked layer 133 are exposed, facilitating subsequent removal of the portion of the preformed structure 121 located below at least one stacked layer 133.

[0103] like Figure 21 and Figure 22As shown, the portion of the preformed structure located below at least one layer 133 is removed to form a hollow area (not shown in the figure) below at least one layer 133.

[0104] In practical applications, the materials contained in the preformed structure and the sacrificial layer included in at least one laminate can be the same or different. For example... Figure 21 As shown, when the two contain different materials, only the portion of the pre-formed structure located below at least one layer 133 can be removed. In this case, a hollow area can be formed between the at least one layer 133 and the substrate 11. Figure 22 As shown, when the preformed structure and the sacrificial layer contain the same material, the above steps are as follows: remove the portion of the preformed structure located below at least one layer of the stack and the sacrificial layer to form a hollow area below at least one layer of the stack, and to form a channel 23 by the channel layer included in at least one layer of the stack. That is to say, after the above processing, not only can a hollow area be obtained, but the channel layer can also be released.

[0105] Specifically, the structure to be removed can be directly removed using either dry or wet etching processes (the structure to be removed is the portion of the pre-formed structure located below at least one layer, or the portion of the pre-formed structure located below at least one layer and the sacrificial layer). Alternatively, the structure to be removed can be oxidized first, and then etched away using a wet etching process. The etchant and etching conditions used in the dry and wet etching processes, as well as the oxidation treatment conditions, can be set according to actual conditions and are not specifically limited here.

[0106] For example, the channel layer contains silicon (Si). The sacrificial layer contains silicon (Si). 0.7 Ge 0.3 The material contained in the preformed structure is Si. 0.5 Ge 0.5 In the above case, the portion of the preformed structure located below at least one layer can be oxidized at an oxidation temperature of 650℃ to 850℃ under nitrogen protection. Then, the oxidized portion of the preformed structure located below at least one layer is removed using a solution such as HF.

[0107] like Figures 23 to 32 As shown, an isolation layer 221 is formed at least in the hollowed-out area.

[0108] Specifically, as mentioned above, see [link to relevant documentation]. Figure 31 and Figure 32 If the isolation layer 221 only fills the space between the gate stack structure 24 and the substrate 11, then the isolation layer 221 only needs to be formed in the cut-out area. See Figures 27 to 30If the isolation layer 221 is formed between the gate stack structure 24 and the shallow trench isolation 15, and between the gate stack structure 24 and the substrate 11, then the isolation layer 221 needs to be formed in the cutout area and in the area released by removing the sacrificial gate.

[0109] For example, such as Figures 23 to 32 As shown, forming an isolation layer 221 at least within the hollowed-out area may include the following steps:

[0110] like Figures 23 to 26 As shown, an isolation material layer 22 is formed at least in the cut-out area and part of the gate formation region 21. The gate formation region 21 is the area where the gate stack structure is formed.

[0111] It is understandable that the area where the sacrificial layer is located is part of the gate formation region. Based on this, as... Figure 23 and Figure 24 As shown, if the sacrificial layer 1311 is not removed while removing the portion of the pre-formed structure located below at least one stack 133, then an isolation material layer 22 needs to be formed in the cut-out region and the portion of the gate formation region located outside the region where the sacrificial layer 1311 is located. Figure 25 and Figure 26 As shown, if the sacrificial layer is removed while removing the portion of the pre-formed structure located below at least one stacked layer, an isolation material layer 22 needs to be formed in the cut-out region and the gate formation region. Specifically, chemical vapor deposition or physical vapor deposition processes can be used to form the isolation material filling the aforementioned regions and covering the dielectric layer. The isolation material is then planarized to obtain the isolation material layer 22, ensuring that all regions on the top of the isolation material layer 22 are flush. This allows for consistent etching depths in each region during subsequent etch-back of the isolation material layer 22, facilitating the removal of the sacrificial layer or the formation of the gate stack structure, and improving the yield of the semiconductor device. The isolation material layer 22 contains a dielectric material, including silicon oxide, silicon nitride, and silicon oxycarbide.

[0112] It is worth noting that the spacing between adjacent channel layers and the spacing between the channel layer and the preformed structure are relatively small. If the sacrificial layer and the preformed structure contain the same material, the sacrificial layer will also be removed when the portion of the preformed structure located below at least one layer of the stack is removed. Based on this, an isolation material layer will also be formed between adjacent channel layers and between the channel layer and the cut-out area. When the isolation material layer is subsequently etched back, it is difficult to remove the portion of the isolation material layer located in the above two areas. Therefore, the manufacturing difficulty of semiconductor devices can be reduced by setting the material contained in the preformed layer to be different from the material contained in the sacrificial layer.

[0113] like Figures 27 to 32As shown, the isolation material layer is etched back using a wet etching process or a dry etching process, so that the remaining isolation material layer forms the isolation layer 221.

[0114] In practical applications, such as Figures 27 to 29 As shown, if the top height of the central region 2211 of the isolation layer 221 is equal to the top height of the outer region 2212, then either a wet etching process or a dry etching process can be used to etch back the isolation material layer. Figures 30 to 32 As shown, if the top height of the middle region 2211 of the isolation layer 221 is less than the top height of the outer region 2212, or if the isolation layer 221 is only located between the gate stack structure and the substrate 11, the isolation material layer can be etched back using a dry etching process under the masking effect of the dielectric layer 20 and the channel layer 1321 located at the top.

[0115] Specifically, the etchant and etching conditions used in the aforementioned dry and wet etching processes can be set according to the material contained in the isolation layer. For example, if the isolation layer contains silicon oxide, it can be etched back using an HF solution. As another example, if the isolation layer contains silicon nitride, it can be etched back using hot phosphoric acid (the temperature of which can be set according to actual conditions). Yet another example, if the isolation layer contains silicon oxide, it can be etched back using a fluorine-based gas.

[0116] In addition, the etching time of the dry etching process or the wet etching process, as well as the etching intensity of the etchant used in both processes, can be used to determine whether the isolation material layer should be etched back to the predetermined thickness.

[0117] In one example, where the sacrificial layer and the pre-formed structure contain different materials, after forming an isolation layer on the substrate, forming a gate-around transistor on the substrate includes the step of: removing the sacrificial layer such that at least one layer of the stack includes a channel layer forming a channel. Figures 33 to 36 As shown, a gate stack structure 24 is formed around the outer periphery of the channel 23 to obtain a ring gate transistor 25.

[0118] Specifically, as mentioned earlier, when the sacrificial layer and the pre-formed structure contain different materials, the sacrificial layer is not removed when the portion of the pre-formed structure located below at least one layer of the stack is removed to release the cutout area. Therefore, the sacrificial layer needs to be removed before forming the gate stack structure, so that each channel layer forms a corresponding nanosheet. The sacrificial layer can be removed using processes such as wet etching. Then, a gate stack structure surrounding the outer periphery of the channel can be formed using processes such as chemical vapor deposition.

[0119] In another example, where the sacrificial layer and the pre-formed structure contain the same materials, after forming an isolation layer on the substrate, a gate-around transistor is formed on the substrate, including: Figures 33 to 36 As shown, a gate stack structure 24 is formed around the outer periphery of the channel 23 to obtain a ring gate transistor 25.

[0120] Specifically, as mentioned above, when the sacrificial layer and the preformed structure contain the same material, the sacrificial layer is removed at the same time as the portion of the preformed structure located below at least one layer of the stack is removed to release the cutout area. Therefore, after the isolation layer is formed, the gate stack structure surrounding the outer periphery of the channel can be directly formed.

[0121] The specific structure of the aforementioned gate stack structure and the materials contained in the gate stack structure can be referred to the previous text, and will not be repeated here.

[0122] Compared with the prior art, the semiconductor device manufacturing method provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the above embodiments, and will not be repeated here.

[0123] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0124] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate, A gate-around transistor, wherein the gate-around transistor is formed on the substrate; An isolation layer, the isolation layer being at least filled between the substrate and the gate stack structure of the gate ring transistor, and the isolation layer being at least located below the channel of the gate ring transistor; The area of ​​the isolation layer covering the substrate is less than or equal to the area of ​​the gate stack structure covering the substrate; Each portion of the isolation layer located below the gate stack structure is integrally continuous, and the isolation layer is located below each portion of the channel; The isolation layer is disposed only below the channel and along the width direction of the channel, and the sidewall of the isolation layer is aligned with the sidewall of the channel. Alternatively, if the area of ​​the isolation layer covering the substrate is equal to the area of ​​the gate stack structure covering the substrate, the sidewalls of the isolation layer are aligned with the sidewalls of the gate stack structure along the width direction of the channel.

2. The semiconductor device according to claim 1, characterized in that, The insulating layer contains a dielectric material, which includes silicon oxide, silicon nitride, and silicon oxycarbide; and / or, The thickness of the isolation layer is 3nm~50nm.

3. The semiconductor device according to claim 1, characterized in that, When the area of ​​the isolation layer covering the substrate is equal to the area of ​​the gate stack structure covering the substrate, the isolation layer has a central region and an outer region along the length extension direction of the isolation layer; the central region is the area of ​​the isolation layer located below the channel; the outer regions are located on both sides of the central region; the top height of the central region is greater than or equal to the top height of the outer region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The channel comprises at least one layer of nanosheets spaced apart along the thickness direction of the substrate; the at least one layer of nanosheets contains Si. 1-x Ge x Where 0 ≤ x ≤ 1.

5. A method for manufacturing a semiconductor device, characterized in that, include: Provide a substrate; A gate-ring transistor and an isolation layer are formed on the substrate; The isolation layer is at least filled between the substrate and the gate stack structure of the gate ring transistor, and the isolation layer is at least located below the channel of the gate ring transistor; The area of ​​the isolation layer covering the substrate is less than or equal to the area of ​​the gate stack structure covering the substrate; Each portion of the isolation layer located below the gate stack structure is integrally continuous, and the isolation layer is located below each portion of the channel; The isolation layer is disposed only below the channel and along the width direction of the channel, and the sidewall of the isolation layer is aligned with the sidewall of the channel. Alternatively, if the area of ​​the isolation layer covering the substrate is equal to the area of ​​the gate stack structure covering the substrate, the sidewalls of the isolation layer are aligned with the sidewalls of the gate stack structure along the width direction of the channel.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, Forming the isolation layer on the substrate includes: A preformed structure and a stacked structure are formed on the substrate; the stacked structure includes at least one stacked layer and a source region and a drain region of the gate-around transistor; the at least one stacked layer is located on the preformed structure; the at least one stacked layer is located between the source region and the drain region, and the at least one stacked layer is in contact with the source region and the drain region; each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer; Remove the portion of the preformed structure located below the at least one layer to form a hollow area below the at least one layer; The isolation layer is formed at least within the hollowed-out area.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The source region and the drain region are both located on the substrate; the pre-formed structure is located between the source region and the drain region, and the pre-formed structure is in contact with the source region and the drain region.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the isolation layer at least within the hollowed-out area includes: An isolation material layer is formed at least in the hollowed-out region and part of the gate forming region; the gate forming region is the region where the gate stack structure is formed. The isolation material layer is etched back using a wet etching process or a dry etching process, so that the remaining isolation material layer forms the isolation layer.

9. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the preformed structure and the stacked structure on the substrate includes: Along the thickness direction of the substrate, a pre-formed layer and at least one layer of stacked material are sequentially formed on the substrate; From the top of the at least one layer of stacked material, etching is performed to a portion of the substrate to form a fin-like structure extending along a first direction; Shallow trench isolation is formed on the portion of the substrate exposed outside the fin structure; the portion of the fin structure exposed outside the shallow trench isolation is a fin; the fin has a source region forming region for forming at least a portion of the source region, a drain region forming region for forming at least a portion of the drain region, and a transition region for forming the channel and the isolation layer; the portion of the at least one stacked material layer located within the transition region is the at least one stacked layer; A sacrificial fence and sidewalls extending in a second direction are formed on the outer periphery of the transition zone; the sidewalls are located at least on both sides of the sacrificial fence in the width direction; the second direction is different from the first direction; The source region is processed at least to form the source region, and the drain region is processed at least to form the drain region, thereby obtaining the stacked structure; and the remaining portion of the pre-formed layer forms the pre-formed structure. After forming the pre-formed structure and the stacked structure on the substrate, and before removing the portion of the pre-formed structure located below the at least one stacked layer, the method for manufacturing the semiconductor device further includes: Remove the sacrificial gate.

10. The method for manufacturing a semiconductor device according to claim 6, characterized in that, When the sacrificial layer and the pre-formed structure contain different materials, after forming the isolation layer on the substrate, forming the gate-ring transistor on the substrate includes: Remove the sacrificial layer so that the trench layer included in the at least one layer of the stack forms the trench; The gate stack structure is formed around the outer periphery of the channel to obtain the ring gate transistor.

11. The method for manufacturing a semiconductor device according to claim 6, characterized in that, When the sacrificial layer and the preformed structure contain the same materials, After forming a preformed structure and a stacked structure on the substrate, and before forming the isolation layer at least in the hollowed-out region, the method of manufacturing the semiconductor device includes: removing a portion of the preformed structure located below the at least one stacked layer and the sacrificial layer to form a hollowed-out region below the at least one stacked layer, and causing a channel layer included in the at least one stacked layer to form the channel; After forming the isolation layer on the substrate, forming the ring gate transistor on the substrate includes: forming the gate stack structure surrounding the outer periphery of the channel to obtain the ring gate transistor.

12. A method for manufacturing a semiconductor device according to any one of claims 6 to 11, characterized in that, The channel layer contains Si. 1-x Ge x The sacrificial layer contains Si. 1-y Ge y The material contained in the preformed structure is Si. 1-z Ge z ; Where 0≤x≤1, 0≤y≤1, 0≤z≤1 ≥0.2, and ≥0.25.

Images