Thin film transistor array panel and method of manufacturing the same

Abstract

A thin film transistor array panel and a manufacturing method thereof are provided. The thin film transistor array panel according to an exemplary embodiment of the present application includes an insulating substrate, a gate line disposed on the insulating substrate and including a gate pad portion, a data line crossing the gate line and being insulated, and including a source electrode and a data pad portion, a drain electrode facing the source electrode, an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole, a common electrode disposed on the organic insulating layer, and including a second contact hole, a passivation layer disposed on the common electrode, and including a third contact hole, and a pixel electrode disposed on the passivation layer and being in contact with the drain electrode, wherein the third contact hole is disposed adjacent to one surface of the first contact hole to improve an aperture ratio and for stable electrode connection.

Description

[0001] This application is a divisional application of the invention patent application "Thin Film Transistor Array Panel and Manufacturing Method Thereof", filed on September 10, 2014, with application number 201911147544.X. Technical Field

[0002] Exemplary embodiments of the present invention relate to a thin-film transistor array panel and a method for manufacturing a thin-film transistor array panel. Background Technology

[0003] Liquid crystal displays (LCDs) are one of the most common types of flat panel displays currently in use. An LCD typically consists of two display panels with field-generating electrodes (such as pixel electrodes and common electrodes) and a liquid crystal layer disposed between these two display panels. LCDs generate an electric field in the liquid crystal layer by applying a voltage to the field-generating electrodes, which determines the orientation of the liquid crystal molecules in the liquid crystal layer. This generated electric field is then used to control the polarization of incident light to display images.

[0004] In a liquid crystal display, both field-generating electrodes that generate an electric field in the liquid crystal layer can be located in the thin-film transistor array panel.

[0005] In the case where two field-generating electrodes are arranged in a thin-film transistor array panel, multiple insulating layers are disposed between the thin-film transistor and the field-generating electrodes, and at least one of the multiple insulating layers may be an organic insulating layer. Contact holes for electrically connecting the thin-film transistor and the field-generating electrodes are typically formed in the multiple insulating layers. Summary of the Invention

[0006] This invention aims to effectively prevent short circuits in thin-film transistor array panels by adjusting the position of the contact holes, and to improve the stability of display devices including thin-film transistor array panels.

[0007] An exemplary embodiment of the present invention provides a thin-film transistor array panel, the thin-film transistor array panel comprising: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line intersecting the gate line and insulated therefrom, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, wherein a first contact hole is defined to pass through the organic insulating layer; a common electrode disposed on the organic insulating layer, wherein a second contact hole is defined to pass through the common electrode; a passivation layer disposed on the common electrode, wherein a third contact hole is defined to pass through the passivation layer; and a pixel electrode disposed on the passivation layer and in contact with the drain electrode, wherein the third contact hole is configured to be adjacent to one surface of the first contact hole.

[0008] In an exemplary embodiment, the first contact hole may be smaller than the second contact hole, the third contact hole may be smaller than the second contact hole, and a portion of the third contact hole may be stacked with the drain electrode.

[0009] In an exemplary embodiment, the third contact hole may expose one end of the drain electrode.

[0010] In an exemplary embodiment, the surface of the third contact hole may partially overlap with the organic insulating layer.

[0011] In an exemplary embodiment, the distance A between a surface of the third contact hole that is not superimposed on the organic insulating layer and the surface of the first contact hole facing the surface of the third contact hole, and the distance B between the remaining surfaces of the third contact hole and the surfaces of the first contact hole facing the remaining surfaces of the third contact hole, can satisfy the following inequality: A > 1.2 × B.

[0012] In an exemplary embodiment, the distance between the surface of the third contact hole and the surface of the first contact hole facing the surface of the third contact hole can be in the range of approximately 1 micrometer (μm) to approximately 6 μm.

[0013] In an exemplary embodiment, the length of the overlapping portion of the third contact hole and the drain electrode can be in the range of approximately 1 μm to approximately 6 μm.

[0014] In an exemplary embodiment, the three surfaces of the third contact hole may be stacked with an organic insulating layer.

[0015] In an exemplary embodiment, the drain electrode may extend generally in a direction in which the organic insulating layer and the common electrode are partially superimposed.

[0016] In an exemplary embodiment, the third contact hole may be disposed in a direction opposite to the direction along which the drain electrode extends.

[0017] In an exemplary embodiment, the pixel electrode may be stacked with one surface of the third contact hole.

[0018] In an exemplary embodiment, a portion of the gate pad portion is exposed through a fourth contact hole, which may be defined to pass through an organic insulating layer, and a portion of the data pad portion is exposed through a fifth contact hole, which may be defined to pass through an organic insulating layer.

[0019] In an exemplary embodiment, one of the common electrode and the pixel electrode may be a planar electrode, while the other of the common electrode and the pixel electrode may be a branch electrode.

[0020] An exemplary embodiment of the present invention provides a method for manufacturing a thin-film transistor array panel, the method comprising: forming a gate line and a data line including a drain electrode on an insulating substrate; forming an organic insulating layer on the gate line and the data line, and forming a first contact hole through the organic insulating layer; forming a common electrode on the organic insulating layer, and forming a second contact hole through the common electrode; forming a passivation layer on the common electrode; forming a third contact hole through the passivation layer to expose one end of the drain electrode; and forming a pixel electrode on the passivation layer connected to the drain electrode through the third contact hole, wherein the third contact hole is formed adjacent to a surface of the first contact hole.

[0021] In an exemplary embodiment, the surface of the third contact hole may partially overlap with the organic insulating layer.

[0022] In an exemplary embodiment, the distance A between a surface of the third contact hole that is not superimposed on the organic insulating layer and the surface of the first contact hole facing the surface of the third contact hole, and the distance B between the remaining surfaces of the third contact hole and the surfaces of the first contact hole facing the remaining surfaces of the third contact hole, can satisfy the following inequality: A > 1.2 × B.

[0023] In an exemplary embodiment, the distance between the surface of the third contact hole and the surface of the first contact hole facing the surface of the third contact hole can be in the range of approximately 1 μm to approximately 6 μm.

[0024] In an exemplary embodiment, the length of the overlapping portion of the third contact hole and the drain electrode can be in the range of approximately 1 μm to approximately 6 μm.

[0025] In an exemplary embodiment, the third contact hole may be stacked with three surfaces of the organic insulating layer, and the pixel electrode may be stacked with one surface of the third contact hole.

[0026] In an exemplary embodiment, the drain electrode may extend in a direction in which the organic insulating layer and the common electrode are partially superimposed, and the third contact hole may be disposed in a direction opposite to the direction in which the drain electrode extends.

[0027] According to an exemplary embodiment of the thin-film transistor array panel, as described herein, the contact hole is formed to allow one side of the contact hole to be connected to an electrode during the manufacturing process of the contact hole, thereby effectively preventing short circuits.

[0028] In this embodiment, the width of the light-blocking member covering the gate line is reduced according to the position of the contact hole, thereby providing a display device with improved aperture ratio and transmittance. Attached Figure Description

[0029] The above and other features of the present invention will become clearer from a detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a top view of an exemplary embodiment of a thin-film transistor array panel according to the present invention;

[0031] Figure 2 It is along Figure 1 A sectional view taken from line II-II';

[0032] Figure 3 It is along Figure 1 A sectional view taken from line III-III';

[0033] Figure 4 It is along Figure 1 A sectional view taken by line IV-IV';

[0034] Figure 5 It is along Figure 1 A sectional view taken by line V-V';

[0035] Figure 6 It is along Figure 1 A sectional view taken by line VI-VI';

[0036] Figures 7A to 10B This is a view illustrating an optional exemplary embodiment of a contact hole portion in a thin-film transistor array panel according to the present invention;

[0037] Figure 11 These are images of exemplary embodiments of a thin-film transistor array panel according to the present invention;

[0038] Figure 12 It is an image of a thin-film transistor array panel based on a comparative example;

[0039] Figure 13 These are exemplary embodiments of the thin-film transistor array panel according to the present invention and current confirmation curves of the thin-film transistor array panel according to a comparative example;

[0040] Figure 14 These are exemplary embodiments of the thin-film transistor array panel according to the present invention and current versus voltage graphs of the thin-film transistor array panel according to a comparative example;

[0041] Figure 15 These are current versus time graphs of an exemplary embodiment of a thin-film transistor array panel according to the present invention and a thin-film transistor array panel according to a comparative example. Detailed Implementation

[0042] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout indicate the same elements.

[0043] What will be understood is that when an element is referred to as being "on" another element, the element can be directly on the other element, or there can be an intermediate element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0044] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, the first element, component, region, layer, and / or part discussed below may be referred to as the second element, component, region, layer, and / or part.

[0045] The terminology used herein is used only to describe particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms that include “at least one (at least one).” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. It will also be understood that when the terms “comprising” and / or variations thereof, or “including” and / or variations thereof, are used in this specification, they indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device other than those depicted in the drawings. For example, if the device in one of the drawings is flipped, an element described as being “down” of other elements will subsequently be oriented “up” of other elements. Thus, depending on the specific orientation in the drawings, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” other elements will subsequently be oriented “above” of other elements. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0047] As used herein, “approximately” or “about” includes the value and means an acceptable deviation from the given value, determined by a person skilled in the art, taking into account the measurement under consideration and the errors associated with the measurement of the given quantity (i.e., the limitations of the measurement system). For example, “approximately” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that, unless explicitly defined herein, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted ideally or overly formally.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic representations of idealized embodiments. Thus, variations in shape as shown in the drawings will be anticipated due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For instance, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0050] In the following text, reference will be made to Figures 1 to 6 A detailed description of exemplary embodiments of the thin-film transistor array panel according to the present invention is provided.

[0051] Figure 1 This is a top view of an exemplary embodiment of a thin-film transistor array panel according to the present invention. Figure 2 It is along Figure 1 A sectional view taken from line II-II'. Figure 3 It is along Figure 1 A sectional view taken from line III-III'. Figure 4 It is along Figure 1 A cross-sectional view taken along line IV-IV'. Figure 5 It is along Figure 1 A cross-sectional view taken by the V-V' line. Figure 6 It is along Figure 1 A sectional view taken along line VI-VI'.

[0052] Reference Figures 1 to 6 An exemplary embodiment of the thin-film transistor array panel includes an insulating substrate 110 and a plurality of gate lines 121 disposed on the insulating substrate 110.

[0053] Each gate line 121 includes a plurality of upwardly projecting gate electrodes 124 and a gate pad portion 129 with a wide area for connection to another layer or external driving circuitry. The gate driving circuitry (not shown) that generates the gate signal can be disposed (e.g., mounted) on a flexible printed circuit film (not shown) attached to the insulating substrate 110, or directly mounted on the insulating substrate 110.

[0054] The gate line 121 may have a single-layer structure or a multi-layer structure including two or more conductive layers.

[0055] A gate insulating layer 140 is disposed on the gate line 121. The gate insulating layer 140 may include materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials, such as those used for example, or those that can be formed from them.

[0056] Multiple semiconductors 151 are disposed on the gate insulating layer 140. In an exemplary embodiment of the liquid crystal display according to the present invention, the semiconductors 151 may include protrusions 154. In this embodiment, the protrusions 154 may be disposed only on the gate electrode 124.

[0057] For example, in one exemplary embodiment, semiconductor 151 may include amorphous silicon, polycrystalline silicon, oxide semiconductor or a combination thereof, or may be formed from them.

[0058] Semiconductor 151 includes an end portion 159 disposed below data pad portion 179.

[0059] Multiple ohmic contacts 161, 163, 165, and 169 are disposed on semiconductor 151. Ohmic contacts 163 and 165 may be disposed as a pair, facing each other based on gate electrode 124, on protrusion 154 of semiconductor 151. Ohmic contact 169 is disposed below data pad 179.

[0060] Ohmic contacts 161, 163, 165, and 169 may comprise, or be formed from, materials such as n+ hydrogenated amorphous silicon (in which n-type impurities such as phosphorus are highly doped) or silicides. In optional exemplary embodiments, ohmic contacts 161, 163, 165, and 169 may be omitted. For example, in an exemplary embodiment where semiconductor 151 is an oxide semiconductor, ohmic contacts 161, 163, 165, and 169 may be omitted.

[0061] Data conductors, including multiple data lines 171 and multiple drain electrodes 175, are disposed on ohmic contacts 161, 163, 165 and 169.

[0062] Data lines 171 transmit data signals and extend generally vertically to intersect gate lines 121. Each data line 171 includes a plurality of source electrodes 173 extending toward gate electrode 124 and a wide data pad portion 179 for connection to another layer or external driving circuitry. Data driving circuitry (not shown) that generates data signals may be disposed (e.g., mounted) on a flexible printed circuit film (not shown) attached to insulating substrate 110, or directly mounted on insulating substrate 110.

[0063] The data line 171 may be periodically bent and has an angle relative to the extension direction of the gate line 121. The angle between the extension direction of the gate line 121 and the data line 171 may be equal to or greater than approximately 45°. In an optional exemplary embodiment of the thin-film transistor array panel according to the invention, the data line 171 may extend linearly along a straight line.

[0064] The drain electrode 175 includes a rod-shaped end (facing the source electrode 173 based on the gate electrode 124) and an end having a wide region.

[0065] Data conductors 171 and 175 may have a single-layer structure or a multi-layer structure comprising two or more conductive layers.

[0066] The gate electrode 124, source electrode 173, and drain electrode 175, together with the protrusion 154 of the semiconductor, can define a thin-film transistor (TFT) as a switching element. Except for the protrusion 154 of the semiconductor 151 in which the thin-film transistor is disposed, the semiconductor 151 can have a planar shape that is substantially the same as the shape of the portion of the data line 171, the drain electrode 175, and the ohmic contacts 161, 165, and 169 below the data line 171 and the drain electrode 175.

[0067] A first passivation layer 180x is disposed on the exposed portions of the data line 171, the drain electrode 175, and the semiconductor 151. For example, the first passivation layer 180x may include silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials, or those that can be formed from them.

[0068] An organic insulating layer 80 is disposed on the first passivation layer 180x. The surface of the organic insulating layer 80 may be substantially flat. For example, the organic insulating layer 80 may comprise or be formed of a photosensitive material or a non-photosensitive material.

[0069] In an exemplary embodiment, a first contact hole 185a exposing the drain electrode is defined to penetrate the organic insulating layer 80, and a fourth contact hole 181 and a fifth contact hole 182 are defined to penetrate the organic insulating layer 80 in the gate pad portion 129 and the data pad portion 179, respectively. In this embodiment, contact holes penetrating the organic insulating layer 80 can be formed by removing a portion of the organic insulating layer 80 from the regions corresponding to the gate pad portion 129 and the data pad portion 179. In this process, the organic insulating layer 80 can be applied to the gate pad portion 129 and the data pad portion 179, and then etched to form the fourth contact hole 181, the fifth contact hole 182, etc.

[0070] In an exemplary embodiment, the first contact hole 185a of the organic insulating layer 80 is formed to expose a portion of the drain electrode 175 for physical and electrical connection between the drain electrode 175 and the pixel electrode 191, which will be described below, and as an example of the invention, one end of the drain electrode 175 is exposed.

[0071] Although not shown, in an optional exemplary embodiment of the thin-film transistor array panel according to the present invention, a color filter may be disposed below the organic insulating layer 80. In this embodiment, the thin-film transistor array panel may further include a layer disposed on the organic insulating layer 80. For example, in an exemplary embodiment, the thin-film transistor array panel may further include a capping layer disposed on the color filter to prevent pigment from the color filter from flowing into the liquid crystal layer; for example, the capping layer may include silicon nitride (SiN). x( ) insulating materials or materials that can be formed from them.

[0072] A common electrode 131 is disposed on the organic insulating layer 80. The common electrode 131 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the common electrode 131 may have a planar shape or a plate shape, but the common electrode 131 is not limited thereto. In an optional exemplary embodiment, the common electrode 131 may have a branched shape. In an exemplary embodiment where the common electrode 131 has a branched shape, the pixel electrode 191 may have a planar shape.

[0073] In an exemplary embodiment, the second contact hole 138 is defined to pass through the common electrode 131 at the edge of the common electrode 131 (i.e., the region corresponding to the drain electrode 175), and the second contact hole 138 may correspond to or overlap with the contact holes of the etched organic insulating layer 80. In this embodiment, when viewed from a top view, the second contact hole 138 may be equal to or larger than the first contact hole 185a. (Refer to...) Figure 1 The second contact hole 138 and the first contact hole 185a can be separated by a predetermined value or a larger upper, lower, left and right spacing for the boundaries of each hole.

[0074] The common electrode 131 is connected via another or separate contact hole (not shown) to a common voltage line disposed in the peripheral area surrounding the display area to receive a common voltage.

[0075] The second passivation layer 180y is disposed on a portion of the common electrode 131 and the first passivation layer 180x. For example, the second passivation layer 180y may include silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials, or those that can be formed from them.

[0076] The third contact hole 185b is defined to pass through the second passivation layer 180y. The third contact hole 185b exposes a portion of the drain electrode 175. For example, in an exemplary embodiment, the third contact hole 185b exposes one end of the drain electrode 175 and a portion of the third contact hole 185b overlaps with the drain electrode 175.

[0077] Reference Figure 1 In an exemplary embodiment, the first contact hole 185a and the second contact hole 138 are spaced apart from each other by a predetermined distance in the upper, lower, left, and right directions according to the plane relative to the boundary of each hole. In this embodiment, as Figure 1As shown, the third contact hole 185b is arranged slightly asymmetrically; for example, the third contact hole 185b is configured to be adjacent to a surface of the first contact hole 185a in the downward direction. In this embodiment, the third contact hole 185b may overlap with the boundary of the first contact hole 185a in the downward direction. Here, the surface of the contact hole defined in the layer refers to the inner surface of the layer that defines the boundary between the layer and the contact hole.

[0078] In an exemplary embodiment, such as Figure 3 As shown, the first contact hole 185a is smaller than the second contact hole 138 and the third contact hole 185b is smaller than the second contact hole 138.

[0079] In this embodiment, the third contact hole 185b is configured to expose one end of the drain electrode 175. In this embodiment, the third contact hole 185b is configured to be biased in one direction to expose one end of the drain electrode 175. In this case, one surface of the third contact hole 185b may be disposed outside the first contact hole 185a and superimposed on the organic insulating layer 80.

[0080] In an exemplary embodiment, at least one surface of the third contact hole 185b is superimposed on the organic insulating layer 80; for example, all three surfaces of the third contact hole 185b may be superimposed on the organic insulating layer 80. The remaining surface of the third contact hole 185b is spaced apart from the organic insulating layer 80, and the pixel electrode 191 may be configured to pass through the spaced space of the respective surface and be electrically connected to the drain electrode 175. In this embodiment, the pixel electrode 191 contacts the drain electrode 175 through one surface of the third contact hole 185b.

[0081] In an exemplary embodiment, such as Figure 1 As shown, the drain electrode 175 can extend generally in one direction, namely, the upward direction as described in the specification. The extended portion of the drain electrode 175 can be stacked with the organic insulating layer 80 and the common electrode 131, and the third contact hole 185b can extend in the opposite direction to the stated one direction (i.e., the extension direction of the drain electrode 175) to be stacked with the drain electrode 175.

[0082] In an exemplary embodiment, the interval is defined between a surface of the third contact hole 185b that is not superimposed on the organic insulating layer 80 and a surface of the first contact hole 185a that faces the surface of the third contact hole 185b. In this embodiment, when the distance between the surface of the third contact hole 185b and the surface of the first contact hole 185a facing the surface of the third contact hole 185b is referred to as A, and the distance between the remaining surfaces of the third contact hole 185b and the surfaces of the first contact hole 185a facing the remaining surfaces of the third contact hole 185b is referred to as B, A and B can satisfy the following inequality: A > 1.2 × B.

[0083] Here, as Figure 1 As shown, A represents the interval between the first contact hole 185a and the third contact hole 185b in the extending direction of the drain electrode 175, and the pixel electrode 191 is connected to the drain electrode through the corresponding region.

[0084] Here, B represents the distance between the surface of the third contact hole 185b where no pixel electrode 191 is disposed or stacked with the organic insulating layer 80, and the surface of the first contact hole 185a facing the surface of the third contact hole 185b.

[0085] Here, when viewed from a top view, the distance between these surfaces can be defined as the minimum length between these surfaces.

[0086] For example, in one exemplary embodiment, A can be in the range of approximately 1 micrometer (μm) to approximately 6 μm, but is not limited thereto. In this embodiment, the spacing between the pixel electrode 191, which is connected to the drain electrode 175 via the third contact hole 185b, and the drain electrode 175 can be in the range of approximately 1 μm to approximately 6 μm. When the spacing is too small, the resistance will increase, but the invention is not limited to spacings having this numerical range.

[0087] In an exemplary embodiment, the spacing between a surface of the third contact hole 185b connected to the pixel electrode 191 and the surface of the first contact hole 185a facing the surface of the third contact hole 185b can be approximately 1.2 times larger than the spacing between a surface of the third contact hole 185b and the surface of the first contact hole 185a facing the surface of the third contact hole 185b. The third contact hole 185b is positioned asymmetrically close to either side of the first contact hole 185a.

[0088] Pixel electrode 191 is disposed on the second passivation layer 180y. Pixel electrode 191 may include or be made of a transparent conductive material such as ITO or IZO.

[0089] The pixel electrode 191 includes a plurality of branch electrodes 193 that extend generally parallel to each other and are spaced apart from each other, and an upper horizontal portion and a lower horizontal portion 192 connecting the upper and lower ends of the branch electrodes 193. The branch electrodes 193 of the pixel electrode 191 may be bent along the data line 171. However, in an exemplary embodiment of the thin-film transistor array panel according to the present invention, the data line 171 and the branch electrodes 193 of the pixel electrode 191 may extend in a straight line.

[0090] Here, the pixel electrode 191 is shown to be branched, while the common electrode 131 is planar; however, the invention is not limited thereto. In an alternative exemplary embodiment, the pixel electrode 191 is planar, while the common electrode 131 is branched.

[0091] A fourth contact hole 181, exposing a portion of the gate pad portion 129, is defined within a first passivation layer 180x, a second passivation layer 180y, and a gate insulating layer 140. For example, the number of fourth contact holes 181 can be at least one, and the planar shape of the fourth contact hole 181 can be a polygon, a circle, or an ellipse, such as a quadrilateral. A first connection member 81 is disposed within the fourth contact hole 181. The first connection member 81 can be disposed in the same layer as the pixel electrode 191.

[0092] A fifth contact hole 182, exposing a portion of the data pad portion 179, is defined within a first passivation layer 180x and a second passivation layer 180y. For example, the number of fifth contact holes 182 can be at least one, and the planar shape of the fifth contact holes 182 can be a polygon such as a quadrilateral, a circle, or an ellipse. A second connecting member 82 is disposed within the fifth contact hole 182. The second connecting member 82 can be disposed in the same layer as the pixel electrode 191.

[0093] In an exemplary embodiment, as described above, the thin-film transistor array panel includes a third contact hole defined as biased to one side, i.e., the third contact hole is disposed on the side opposite to the longitudinal direction of the pixel electrode 191, thereby reducing the width of the light-blocking member 220 used to cover the pixel electrode 191, thus improving the aperture ratio and transmittance, and reducing power consumption by improving the aperture ratio and transmittance. In this embodiment, defects during the process of setting the pixel electrode that contacts one surface of the third contact hole can be reduced.

[0094] An exemplary embodiment including an organic insulating layer 80 has been described herein, but the invention is not limited thereto. In alternative exemplary embodiments, the organic insulating layer 80 may be omitted.

[0095] In the following text, reference will be made to Figures 1 to 6 An exemplary embodiment of a method for manufacturing a thin-film transistor array panel according to the present invention is described.

[0096] In an exemplary embodiment, a gate line 121, including a gate electrode 124 and a gate pad portion 129, is formed on an insulating substrate 110. In this embodiment, a common voltage line disposed in a peripheral region may be provided together with the gate line 121. Then, a gate insulating layer 140, a semiconductor 151, and a layer for forming ohmic contacts are sequentially formed (e.g., stacked) on the gate line 121 and the common voltage line. A data conductor including a data line 171 (including a source electrode 173 and a data pad portion 179) and a drain electrode 175 are formed thereon. Then, the layer for forming ohmic contacts is etched using the data conductor as a mask to complete the ohmic contacts 161, 163, 165, and 169, and a portion of the protrusion 154 of the semiconductor 151 is exposed. For example, the gate insulating layer 140 may be made of materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials are formed.

[0097] Next, a first passivation layer 180x is formed (e.g., stacked) on the data conductor. For example, the first passivation layer 180x can be made of materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials are formed.

[0098] Next, an organic insulating layer 80 is formed on the first passivation layer 180x, and a first contact hole 185a is formed through the organic insulating layer 80. The organic insulating layer 80 comprises a photosensitive material and a non-photosensitive material, and the surface of the organic insulating layer 80 can be substantially flat. The organic insulating layer 80 is also provided with a connection to the gate bonding electrode.

[0099] The areas corresponding to disk portion 129 and data pad portion 179.

[0100] According to another exemplary embodiment of the present invention, a color filter may be disposed below the organic insulating layer, and in this embodiment, a cover layer may also be disposed on the organic insulating layer.

[0101] Next, a conductive layer is disposed (e.g., stacked) on the organic insulating layer 80 to form a common electrode 131 including a second contact hole 138. For example, in an exemplary embodiment, the common electrode 131 may be planar in shape.

[0102] Next, a second passivation layer 180y is formed on the common electrode 131, and a third contact hole 185b is formed through the second passivation layer 180y.

[0103] In an exemplary embodiment, the first contact hole 185a is formed smaller than the second contact hole 138, and the third contact hole 185b is formed smaller than the second contact hole 138. In this embodiment, the third contact hole 185b is formed to expose one end of the drain electrode 175, and therefore the third contact hole 185b is formed adjacent to a surface of the first contact hole 185a, that is, biased to one side.

[0104] In this embodiment, the third contact hole 185b is formed biased in one direction to expose one end of the drain electrode 175, and one surface of the third contact hole 185b is disposed outside the first contact hole 185a. The one surface of the third contact hole 185b disposed outside the first contact hole 185a may be stacked with the organic insulating layer 80.

[0105] For example, in one exemplary embodiment, one surface of the third contact hole 185b is superimposed on the organic insulating layer 80. In another exemplary embodiment, three or fewer surfaces of the third contact hole 185b may be superimposed on the organic insulating layer 80. In this embodiment, at least one of the remaining surfaces may be spaced apart from the organic insulating layer 80, and the pixel electrode 191 may be connected to the drain electrode 175 through a corresponding surface.

[0106] In this embodiment, the drain electrode 175 may extend generally in one direction, for example, as Figure 1 As shown in the upper direction. The extended portion of the drain electrode 175 overlaps with portions of the organic insulating layer 80 and the common electrode 131, and the third contact hole 185b is formed to overlap with the drain electrode 175 in another direction (e.g., the lower direction opposite to the extension direction of the drain electrode 175).

[0107] In this embodiment, the interval is defined between a surface of the third contact hole 185b that does not overlap with the organic insulating layer 80 and the surface of the first contact hole 185a that faces said surface. When the distance between said surface of the third contact hole 185b and said surface of the first contact hole 185a is referred to as A, and the distance between the remaining surfaces of the third contact hole 185b and the surface of the first contact hole 185a that faces said surface of the third contact hole 185b is referred to as B, A and B can satisfy the following inequality: A > 1.2 × B.

[0108] Here, as Figure 1 As shown, A represents the spacing between the first contact hole and the third contact hole in the extending direction of the drain electrode 175, and the drain electrode 175 and the pixel electrode 191 are connected to each other through corresponding regions.

[0109] Here, B represents the spacing between one of the remaining surfaces of the third contact hole 185b (where no pixel electrode 191 is disposed or superimposed with the organic insulating layer 80) and the surface of the first contact hole 185a facing the surface of the remaining surface of the third contact hole 185b.

[0110] In an exemplary embodiment, the distance A can be in the range of approximately 1 μm to approximately 6 μm, but is not limited thereto. In this embodiment, the distance between the overlapping portion of the third contact hole 185b and the drain electrode 175 (wherein the pixel electrode 191 connected to the drain electrode 175 through the third contact hole 185b overlaps with the drain electrode 175) can be in the range of approximately 1 μm to approximately 6 μm. When the distance is too small, the resistance will increase, but the spacing is not limited to this numerical range.

[0111] Finally, as Figures 1 to 6 As shown, a pixel electrode 191, a first connecting member 81, and a second connecting member 82 are disposed on the second passivation layer 180y.

[0112] The first connecting member 81 covers the exposed portion of the gate pad portion 129 through the fourth contact hole 181, and the second connecting member 82 covers the exposed portion of the data pad portion 179 through the fifth contact hole 182.

[0113] The pixel electrode 191 covers the exposed portion of the drain electrode 175 through the third contact hole 185b, and is physically or electrically connected to the drain electrode 175.

[0114] According to an exemplary embodiment of the method for manufacturing a thin-film transistor array panel, the third contact hole is formed in the thin-film transistor array panel biased to one side. In this embodiment, the third contact hole can be provided on the opposite side of the pixel electrode 191 in the longitudinal direction, thereby reducing the width of the light-blocking member 220 used to cover the pixel electrode 191. By reducing the width of the light-blocking member 220, the aperture ratio and transmittance are improved, and by improving the aperture ratio and transmittance, power consumption is reduced. Therefore, in this embodiment, defects during the process of forming the pixel electrode that contacts one surface of the third contact hole are reduced.

[0115] In the following text, reference will be made to Figures 7A to 10B The contact hole position relationships of an optional exemplary embodiment of a thin-film transistor array panel are described.

[0116] Figures 7A to 10B This is a view illustrating an optional exemplary embodiment of a contact hole portion in a thin-film transistor array panel according to the present invention.

[0117] Using the above-mentioned description Figures 1 to 6 The exemplary embodiments of the contact hole portion in the thin-film transistor shown herein are designated by the same reference numerals. Figures 7A to 10B The same or similar elements shown in the figures will be omitted or simplified in detailed description below. In each figure, Figure 7A , Figure 8A , Figure 9A and Figure 10A This is a top view of an optional exemplary embodiment of the contact hole portion, while Figure 7B , Figure 8B , Figure 9B and Figure 10B They are respectively along Figure 7A , Figure 8A , Figure 9A and Figure 10A The sectional view taken by line b-b'.

[0118] In an exemplary embodiment, reference is made to... Figure 7A The source electrode 173 (which is part of the data line 171) may be disposed on the same line as the data line 171. The drain electrode 175 extends substantially parallel to the source electrode 173. Therefore, in this embodiment, the drain electrode 175 is substantially parallel to a portion of the data line 171.

[0119] However, the drain electrode 175 may extend in a direction generally perpendicular to the data line 171 to contact the pixel electrode 191 on one side of its extension.

[0120] The gate electrode 124, source electrode 173, and drain electrode 175 together with the semiconductor 154 define the TFT, and the channel of the thin film transistor is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175.

[0121] An exemplary embodiment of the thin-film transistor array panel according to the present invention may include a source electrode 173 disposed on the same line as the data line 171 and a drain electrode 175 extending substantially parallel to the data line 171, so as to increase the width of the thin-film transistor without increasing the area occupied by the data conductor, thereby increasing the aperture ratio of the liquid crystal display.

[0122] In this embodiment, such as Figure 7A As shown, when viewed from a plan view, the first contact hole 185a of the organic insulating layer 80 and the second contact hole 138 of the common electrode 131 can be formed with predetermined intervals relative to all the up, down, left and right directions.

[0123] In this embodiment, such as Figure 7AAs shown, the third contact hole 185b may not have a predetermined (or greater) spacing from the first contact hole 185a and the second contact hole 138 in all the up, down, left, and right directions, and is asymmetrically configured to be slightly biased to one side. In this embodiment, one surface of the third contact hole 185b is formed to overlap with or inside the first contact hole 185a, such that the organic insulating layer 80 can overlap with the third contact hole 185b.

[0124] In this embodiment, such as Figure 7B As shown, pixel electrode 191 is not disposed in one surface of the third contact hole 185b that overlaps with the organic insulating layer 80. Pixel electrode 191 is electrically connected to drain electrode 175 through another surface that overlaps with drain electrode 175 but not with the organic insulating layer 80. In this embodiment, the connection of pixel electrode 191 is interrupted by undercutting of the insulating layer in one surface of the third contact hole. In this embodiment, the distance between the areas where pixel electrode 191 and drain electrode 175 are electrically connected is represented by B' (called resistance margin), and the area where pixel electrode 191 overlaps with the second insulating layer 180y is represented by A' (called contact margin).

[0125] Reference Figure 8A and Figure 8B In an optional exemplary embodiment, the drain electrode 175 can be as follows: Figure 1 The extension shown, the position and size of other constituent elements are similar to Figure 1 The embodiments shown are largely the same. However, in the exemplary embodiment shown in FIG8, the dimensions of the third contact hole 185b are different from those shown in FIG8. Figure 1 The exemplary embodiments shown can be larger. In exemplary embodiments manufactured using exposure apparatus with low resolution, such as... Figure 8A and Figure 8B As shown, the size of the third contact hole 185b has been increased, and with Figure 7A and Figure 7B Unlike the exemplary embodiment shown, the three surfaces of the third contact hole 185b may be stacked with the organic insulating layer 80. In this embodiment, the third contact hole 185b may be formed to overlap with or inside the second contact hole 138 of the common electrode 131, such that one surface of the third contact hole 185b may overlap with the common electrode 131.

[0126] In the exemplary embodiment using the low-resolution exposure apparatus described above, the three surfaces of the third contact hole 185b are stacked with the organic insulating layer 80, and the pixel electrode 191 and the drain electrode 175 are connected to each other through one surface of the third contact hole 185b that is not stacked with the organic insulating layer 80. In this embodiment, one surface of the third contact hole 185b may be stacked with the common electrode 131, and the other three surfaces of the third contact hole 185b may not be stacked with the common electrode 131. In this embodiment, the length of the region where the pixel electrode 191 and the drain electrode 175 are electrically connected is represented by B' (called the resistance margin), and the distance between the pixel electrode 191 and the stacked portion of the second insulating layer 180y is represented by A' (called the contact margin).

[0127] Therefore, the pixel electrode 191 can be connected to the drain electrode 175 on at least one surface of the drain electrode 175, so that it can operate effectively even when defects occur in the process using a low-resolution exposure apparatus.

[0128] In another alternative exemplary embodiment, reference is made to... Figure 9A and Figure 9B The third contact hole 185b can be configured to be offset along a diagonal direction. In an exemplary embodiment, as shown... Figure 9A As shown, the third contact hole 185b can be configured to be diagonally offset along an inclined direction. In this embodiment, the third contact hole 185b can be stacked with the organic insulating layer 80 in its lower left surface, and the pixel electrode 191 can be disposed in the upper right surface of the third contact hole 185b to connect to the drain electrode 175. In this embodiment, the length of the region where the pixel electrode 191 is electrically connected to the drain electrode 175 is represented by B' (called the resistance margin), and the length of the overlapping portion of the pixel electrode 191 and the second insulating layer 180y is represented by A' (called the contact margin).

[0129] Therefore, in such Figure 9A In this embodiment, where the third contact hole 185b is offset diagonally, the pixel electrode 191 is effectively connected to the drain electrode 175 with a predetermined (or greater) resistance margin for efficient operation.

[0130] In another alternative exemplary embodiment, reference is made to... Figure 10A and Figure 10B The width of the drain electrode 175 can be greater than the width of the first contact hole 185a, and an exposure device with low resolution can be used.

[0131] In this embodiment, one surface of the third contact hole 185b overlaps with the common electrode 131, while the other three surfaces of the third contact hole 185b do not overlap with the common electrode 131. In this embodiment, three surfaces of the third contact hole 185b may overlap with the organic insulating layer 80, while the remaining surface of the third contact hole 185b does not overlap with the organic insulating layer 80. In this embodiment, the third contact hole 185b is configured to expose one end of the drain electrode 175.

[0132] The drain electrode 175, exposed through the third contact hole 185b, is connected to the pixel electrode 191 through the remaining surface of the third contact hole 185b that is not superimposed on the organic insulating layer 80. In this embodiment, the length of the region where the pixel electrode 191 is electrically connected to the drain electrode 175 is represented by B' (called the resistance margin), and the length of the superposition portion of the pixel electrode 191 and the second insulating layer 180y is represented by A' (called the contact margin).

[0133] In this embodiment, such as Figure 10A and Figure 10B As shown, the drain electrode and the organic insulating layer are connected to each other through one surface of the third contact hole.

[0134] Next, we will refer to Figure 11 and Figure 12 The aperture ratio of an exemplary embodiment of the thin-film transistor according to the present invention and the aperture ratio of a comparative example are described. Figure 11 These are images of exemplary embodiments of a thin-film transistor array panel according to the present invention. Figure 12 The image is based on a thin-film transistor array panel as shown in the comparative example.

[0135] Reference Figure 11 In an exemplary embodiment, because the width of the light-blocking member formed parallel to the gate line is slightly smaller, the display area displayed by the pixel electrode is large. However, as Figure 12 As shown in the comparative example, the width of the light-blocking member parallel to the gate line is substantially large, resulting in an aperture ratio per pixel area that is similar to that shown in the example. Figure 11 The exemplary embodiments shown are smaller.

[0136] This will be described in detail with reference to Table 1 below.

[0137] Table 1

[0138] Exemplary embodiments of the present invention Comparison Examples Width of the light-blocking component (μm) 22 29.6 Opening ratio (%) 58.25 45.5 Transmittance (%) 4.2 3.4

[0139] As shown in Table 1, in the exemplary embodiment, the width of the light-blocking member is reduced by approximately 7.6 micrometers (μm) compared to the thin-film transistor array panel according to the comparative example. This corresponds to a reduction of approximately 26%, thereby substantially reducing the width of the light-blocking member in the exemplary embodiment.

[0140] In an exemplary embodiment, the aperture ratio increases by about 13% from 45.5% to 58.25% and the transmittance increases from 3.4% to 4.2% compared to the thin-film transistor array panel according to the comparative example.

[0141] Therefore, in an exemplary embodiment of the thin-film transistor array panel according to the present invention, the aperture ratio and transmittance are improved, thereby reducing power consumption.

[0142] Next, we will refer to Figures 13 to 15 Exemplary embodiments of the thin-film transistor array panel according to the present invention and experimental graphs of the thin-film transistor array panel according to a comparative example are described. Figure 13 These are exemplary embodiments of the thin-film transistor array panel according to the present invention and current confirmation diagrams of the thin-film transistor array panel according to a comparative example. Figure 14 These are exemplary embodiments of the thin-film transistor array panel according to the present invention and current-voltage graphs of the thin-film transistor array panel according to a comparative example. Figure 15 These are current versus time graphs of an exemplary embodiment of a thin-film transistor array panel according to the present invention and a thin-film transistor array panel according to a comparative example.

[0143] First, refer to Figure 13 , Figure 13 This is a graph showing the current flow rate based on the number of surfaces of the pixel electrode in contact with the third contact hole. The current flow rate is shown separately according to the contact area and the number of contact surfaces. Examples 1, 1', and 1'" are examples where the number of surfaces of the pixel electrode in contact with the third contact hole is 1, and the pixel electrode contacts one surface of the third contact hole with contact areas of approximately 5μm × 5μm, approximately 6μm × 6μm, and approximately 7μm × 7μm, respectively. Examples 2, 2', and 2'" are examples where the number of surfaces of the pixel electrode in contact with the third contact hole is 2, and the pixel electrode contacts three surfaces of the third contact hole with contact areas of approximately 5μm × 5μm, approximately 6μm × 6μm, and approximately 7μm × 7μm, respectively. Examples 3, 3', and 3'" are examples where the number of surfaces of the pixel electrode in contact with the third contact hole is 3, and the pixel electrode contacts four surfaces of the third contact hole with contact areas of approximately 5μm × 5μm, approximately 6μm × 6μm, and approximately 7μm × 7μm, respectively.

[0144] When the voltage applied to the gate is approximately -6 volts (V), the lower curve represents loff, and when the voltage applied to the gate is approximately 20V, the upper curve represents lon. Figure 13As shown in the graph, although the number or area of ​​contact surfaces differs in each instance, loff and lon are generally consistent. Therefore, in the exemplary embodiment, although the surfaces in contact with the third contact hole are changed as described above, the performance of the display device is not substantially affected.

[0145] also, Figure 14 This illustrates whether defects occur in the contact holes as the applied voltage increases. The bottommost curve (Example 5) of the multiple curves represents an exemplary embodiment of the thin-film transistor array panel according to the present invention. Figure 14 In the examples, Examples 1 and 2, which have the maximum tilt angle, are examples of thin-film transistor array panels according to the comparative example, in which the pixel electrode contacts the contact hole on four surfaces; Example 3, which is an example of a thin-film transistor array panel according to the comparative example, in which the pixel electrode contacts one or more contact holes on one surface; and Example 4, which is an example of a thin-film transistor array panel according to the comparative example, in which the pixel electrode contacts the contact hole on two surfaces.

[0146] In the graph of the thin-film transistor array panel according to the comparative example, as the voltage increases, the current does not increase at voltages higher than a predetermined value, but in the exemplary embodiment, as... Figure 14 As shown in Example 5, even when the voltage increases according to the applied voltage, the current increases uniformly without any specific defects or breaks. That is, according to an exemplary embodiment of the present invention, even when the pixel electrode and the contact hole are in contact on only one surface, the performance of the display device is not abnormal.

[0147] Figure 15 This represents the current flowing over time (t) when a voltage is applied under predetermined conditions. Example 1 is an example where a pixel electrode is in contact with a contact hole on one surface and a voltage of approximately 10V is applied. Example 2 is an example where a pixel electrode is in contact with a contact hole on four surfaces and a voltage of approximately 5V is applied. Example 3 is an example where multiple pixel electrodes are in contact with contact holes on four surfaces and a voltage of approximately 50V is applied. Example 4 is an example where multiple pixel electrodes are in contact with contact holes on one surface and a voltage of approximately 50V is applied.

[0148] Reference Figure 15 Examples 1 and 4, where the pixel electrodes and contact holes are in contact on one surface, exhibit a specific degree of uniform current. In the exemplary embodiments, as shown in Example 4, Example 4 exhibits a slightly lower current compared to the currents of Examples 2 and 3 corresponding to the comparative examples (where the pixel electrodes and contact holes are in contact on four surfaces), but over time, Example 4 presents a generally uniform current.

[0149] Therefore, in an exemplary embodiment of the thin-film transistor array panel according to the present invention, the pixel electrode and the contact hole are in contact on one surface, which can effectively maintain the performance of the display device.

[0150] In an exemplary embodiment of the thin-film transistor array panel according to the present invention, as described herein, the pixel electrode is substantially in contact with the contact hole on one surface, depending on the asymmetrically biased position of the contact hole, so that the pixel electrode can be effectively connected to the drain electrode even with process errors or defects.

[0151] While the invention has been described in conjunction with exemplary embodiments now considered practical, it is to be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A thin-film transistor array panel, the thin-film transistor array panel comprising: Insulating substrate; The gate line and the data line are insulated from each other, wherein the data line includes a source electrode; The drain electrode faces the source electrode. An organic insulating layer is disposed on the data line and the drain electrode, and has a first contact hole; A common electrode is disposed on the organic insulating layer and has a second contact hole; A passivation layer is disposed on the common electrode and has a third contact hole; and A pixel electrode is disposed on the passivation layer and electrically connected to the drain electrode through the third contact hole. In the plan view, the third contact hole overlaps with at least one surface of the second contact hole. The area where the drain electrode contacts the pixel electrode overlaps with the first contact hole, and the passivation layer includes a portion extending to the upper surface of the drain electrode. In the cross-sectional view, the portion of the common electrode is exposed by the third contact hole of the passivation layer.

2. The thin-film transistor array panel according to claim 1, characterized in that, In the plan view, the third contact hole does not overlap with at least one surface of the first contact hole.

3. The thin-film transistor array panel according to claim 1, characterized in that, In the plan view, the surface of the second contact hole does not intersect with the surface of the first contact hole.

4. The thin-film transistor array panel according to claim 1, characterized in that, In the plan view, the first contact hole is smaller than the second contact hole, and In the plan view, the third contact hole is smaller than the second contact hole.

5. The thin-film transistor array panel according to claim 1, characterized in that, The third contact hole is stacked with the drain electrode.

6. The thin-film transistor array panel according to claim 5, characterized in that, The portion of the third contact hole exposes at least a portion of the drain electrode.

7. The thin-film transistor array panel according to claim 6, characterized in that, In the plan view, at least one surface of the third contact hole is separated from the end of the drain electrode.

8. The thin-film transistor array panel according to claim 1, characterized in that, In the plan view, at least one surface of the first contact hole is separated from the end of the drain electrode.

9. The thin-film transistor array panel according to claim 1, characterized in that, In the plan view, the surface of the third contact hole partially overlaps with the organic insulating layer.

10. The thin-film transistor array panel according to claim 1, characterized in that, At least three surfaces of the third contact hole are superimposed on the organic insulating layer.

11. The thin-film transistor array panel according to claim 1, characterized in that, The pixel electrode is stacked on at least one surface of the third contact hole.

12. The thin-film transistor array panel according to claim 11, characterized in that, The pixel electrode does not overlap with at least one surface of the third contact hole.

Images