A silicon-based high electron mobility transistor and its fabrication method

Abstract

This invention discloses a silicon-based high electron mobility transistor and its fabrication method, relating to the field of semiconductor process technology. The silicon-based high electron mobility transistor includes: a substrate; an AlN nucleation layer, a high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer sequentially disposed on the substrate; wherein the AlN nucleation layer includes a roughened first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer, with the first high-temperature AlN nucleation layer disposed on the substrate. The first high-temperature AlN nucleation layer effectively blocks impurities in the substrate. Surface roughening of the first high-temperature AlN nucleation layer releases stress between the substrate and the epitaxial layer. The second high-temperature AlN nucleation layer is disposed on the roughened first high-temperature AlN nucleation layer to further release the stress accumulated in the first high-temperature AlN nucleation layer. This invention solves the technical problem in the prior art where boron atoms diffuse from the silicon substrate to the epitaxial layer, resulting in significant stress between the silicon substrate and the epitaxial layer, leading to a decrease in the crystal quality of the epitaxial layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process technology, specifically to a silicon-based high electron mobility transistor and its fabrication method. Background Technology

[0002] With the development of semiconductor processes and technologies, high electron mobility transistors (HEMTs) have become increasingly popular and are widely used in mobile phones, satellite television, and radar. HEMTs consist of a heterojunction formed by two materials with different band gaps, providing a channel for charge carriers. Gallium nitride (GaN)-based materials possess advantages such as a large band gap, high electron saturation drift velocity, good chemical stability, radiation resistance, high temperature resistance, and ease of heterojunction formation, making them the preferred material for manufacturing HEMT structures. GaN-based heterostructures exhibit high carrier concentration and electron mobility, low on-resistance, and the advantage of a wide band gap allows them to withstand very high operating voltages. Therefore, GaN-based HEMTs are suitable for applications such as high-temperature, high-frequency, high-power devices and low-loss switching devices.

[0003] Currently, common GaN-based high electron mobility transistors typically use silicon (Si) as the substrate material for GaN growth. Due to the good thermal conductivity of Si substrates, large-size epitaxy can be achieved, especially 6-inch, 8-inch, and 12-inch epitaxial wafers, reducing production costs and giving them a strong market competitiveness. In the manufacturing process of high electron mobility crystal devices, boron (B)-doped p-type Si substrates are often chosen to improve conductivity and reduce voltage drop and power consumption on the silicon substrate. However, because the atomic radius of B is smaller than that of Si, B atoms easily diffuse into the epitaxial layer at high temperatures, leading to a decrease in the crystal quality of the epitaxial layer. Simultaneously, the concentration of B atoms in the substrate decreases, resulting in drastic changes in the atomic lattice and lattice mismatch. The stress generated by this mismatch is easily released at the interface between the Si substrate and the epitaxial layer, and with the epitaxial layer penetrating, it increases the leakage current of the device. Furthermore, the significant lattice mismatch between the Si substrate and the GaN epitaxial layer results in substantial stress at the interface, which penetrates and extends throughout the entire epitaxial layer, thus affecting the crystal quality of the epitaxial layer.

[0004] Therefore, existing silicon-based high electron mobility transistors generally suffer from the technical problem of boron atoms diffusing from the silicon substrate to the epitaxial layer, resulting in significant stress between the silicon substrate and the epitaxial layer, which leads to a decrease in the crystal quality of the epitaxial layer. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a silicon-based high electron mobility transistor and a spin-coating method, thereby solving the technical problem in the prior art where boron atoms diffuse from the silicon substrate to the epitaxial layer, resulting in significant stress between the silicon substrate and the epitaxial layer, which leads to a decrease in the crystal quality of the epitaxial layer.

[0006] One aspect of the present invention is to provide a silicon-based high electron mobility transistor, the silicon-based high electron mobility transistor comprising:

[0007] Substrate;

[0008] An AlN nucleation layer, a high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially disposed on the substrate.

[0009] The AlN nucleation layer includes a first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer after roughening treatment, wherein the first high-temperature AlN nucleation layer is disposed on the substrate.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: The silicon-based high electron mobility transistor provided by the present invention has an AlN nucleation layer between the substrate and the high-resistivity buffer layer. This AlN nucleation layer includes a roughened first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer. The first high-temperature AlN nucleation layer is disposed on the substrate. The crystal quality of the first high-temperature AlN nucleation layer is superior to that of the low-temperature grown AlN layer, which can more effectively block impurities in the substrate, improve the crystal quality of the subsequent epitaxial layer, and prevent boron atoms from diffusing into the epitaxial layer, thus avoiding a decrease in the crystal quality of the epitaxial layer. The surface of the first high-temperature AlN nucleation layer is also improved. Roughening treatment can release the stress between the substrate and the epitaxial layer. A second high-temperature AlN nucleation layer is then formed on the first high-temperature AlN nucleation layer after roughening treatment. This further releases the stress accumulated in the first high-temperature AlN nucleation layer, further improving the crystal quality of the subsequent epitaxial layer. This improves the performance of silicon-based high electron mobility transistors and avoids the presence of large stress between the silicon substrate and the epitaxial layer, which extends to the subsequent epitaxial layer and affects its crystal quality. This solves the common technical problem of boron atoms diffusing from the silicon substrate to the epitaxial layer, resulting in large stress between the silicon substrate and the epitaxial layer and a decrease in the crystal quality of the epitaxial layer.

[0011] According to one aspect of the above technical solution, the thickness of the first high-temperature AlN nucleation layer is 100-200 nm, and the thickness of the second high-temperature AlN nucleation layer is 100-200 nm.

[0012] According to one aspect of the above technical solution, the thickness of the first high-temperature AlN nucleation layer after roughening treatment is 2-10 nm, and the shape of the first high-temperature AlN nucleation layer after roughening treatment is an island-shaped triangle.

[0013] According to one aspect of the above technical solution, an Al layer is provided between the substrate and the AlN nucleation layer.

[0014] According to one aspect of the above technical solution, the thickness of the Al layer is 1-5 nm.

[0015] According to one aspect of the above technical solution, the high-resistivity buffer layer is an AlGaN thin film layer with a thickness of 2-4 μm and an Al composition ratio of 0.2-0.8%. The dopant in the high-resistivity buffer layer is carbon with a carbon doping concentration of 10⁻⁶. 19 cm -3 -10 20 cm -3 .

[0016] According to one aspect of the above technical solution, the channel layer is a GaN thin film layer with a thickness of 300-600nm.

[0017] According to one aspect of the above technical solution, the substrate is a p-type doped Si substrate, and the dopant is boron with a boron doping concentration of 10. 18 cm -3 -10 20 cm -3 .

[0018] Another aspect of the present invention is to provide a method for fabricating a silicon-based high electron mobility transistor, characterized in that the fabrication method includes:

[0019] Provide a substrate;

[0020] An Al layer is grown on the substrate;

[0021] An AlN nucleation layer is epitaxially grown on the Al layer, wherein the AlN nucleation layer includes a first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer after roughening treatment, and the first high-temperature AlN nucleation layer is epitaxially grown on the Al layer;

[0022] A high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the AlN nucleation layer.

[0023] To further explain, the AlN nucleation layer growth step includes:

[0024] The temperature was adjusted to between 1100-1200℃ and the pressure was set between 40-70mbar to epitaxially grow a first high-temperature AlN nucleation layer with a thickness of 100-200nm on the Al layer.

[0025] Adjust the temperature to between 1000-1100℃ and introduce Cl2 to roughen the first high-temperature AlN nucleation layer for 1-5 minutes, with a roughening thickness of 2-10nm.

[0026] Adjust the temperature to between 1100-1200℃ and the pressure to between 40-70mbar, and purge with N2 for 10-20 minutes to remove unreacted Cl2 from the reaction chamber.

[0027] The temperature was adjusted to between 1100-1200℃ and the pressure was set between 40-70mbar. A second high-temperature AlN nucleation layer with a thickness of 100-200nm was epitaxially grown on the roughened first high-temperature AlN nucleation layer. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1 This is a schematic diagram of the silicon-based high electron mobility transistor in the first embodiment of the present invention;

[0030] Figure 2 This is a flowchart of the method for fabricating a silicon-based high electron mobility transistor according to the second embodiment of the present invention;

[0031] Component symbol explanation in the attached diagram:

[0032] Substrate 100, Al layer 200, AlN nucleation layer 300, first high-temperature AlN nucleation layer 301, second high-temperature AlN nucleation layer 302, high-resistivity buffer layer 400, channel layer 500, AlN insertion layer 600, AlGaN barrier layer 700, GaN capping layer 800. Detailed Implementation

[0033] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.

[0034] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "upper," "lower," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0035] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0036] Example 1

[0037] Please see Figure 1 The image shows a silicon-based high electron mobility transistor provided in the first embodiment of the present invention. The silicon-based high electron mobility transistor includes a substrate 100. The substrate 100 is a substrate for epitaxial layer growth. Commonly used substrate materials for 100 are sapphire (Al2O3), silicon carbide (SiC), and silicon (Si). Sapphire (Al2O3) itself has poor heat dissipation, making it difficult to achieve large-size epitaxial growth. Therefore, Si substrates are typically used for epitaxial growth of GaN thin films, which have good thermal conductivity and can achieve large-size epitaxy, especially 6-inch, 8-inch, and 12-inch epitaxial wafers, reducing production costs and giving it significant market competitiveness. In this embodiment, the substrate 100 is a P-type doped Si substrate, wherein the Si substrate is a (111) crystal orientation Si substrate, and its dopant is boron (B) with a doping concentration of 10. 18 cm -3 -10 20 cm -3Using a boron-doped Si substrate can improve the conductivity of substrate 100 and reduce its voltage drop and energy consumption. Before growing the epitaxial layer, the surface of substrate 100 usually needs to be pretreated to remove impurities adsorbed on the surface of substrate 100. Specifically, substrate 100 is placed in an MOCVD chamber, the temperature is heated to between 1000-1200℃, the pressure is set to between 50-100 mbar, and H2 is introduced for pretreatment for 5-10 minutes. Among them, metal-organic chemical vapor deposition (MOCVD) uses organic compounds of group III and group II elements and hydrides of group V and VI elements as crystal growth source materials, and performs vapor phase epitaxial growth on substrate 100 through thermal decomposition reaction.

[0038] An Al layer 200 is deposited on the substrate 100 to prepare for the subsequent growth of the AlN nucleation layer 300, thereby improving the crystal quality and surface flatness of the AlN nucleation layer 300. Because Al atoms have a relatively high viscosity and weak lateral migration ability on the substrate 100, and because Al atoms are relatively active, directly growing the AlN thin film layer will easily lead to clustering and difficulty in diffusion. Pre-depositing the Al layer 200 before growing the AlN thin film layer improves the lateral migration ability of Al atoms, resulting in better surface flatness and crystal quality of the AlN thin film layer. Specifically, the temperature is adjusted to between 1000-1100℃, the pressure is set to between 40-70 mbar, an Al source is introduced with a flow rate of 50-200 sccm, and the Al layer 200 with a thickness of 1-5 nm is deposited on the substrate 100.

[0039] An AlN nucleation layer 300 is provided on the Al layer 200. This AlN nucleation layer 300 includes a roughened first high-temperature AlN nucleation layer 301 and a second high-temperature AlN nucleation layer 302. The first high-temperature AlN nucleation layer 301 is disposed on the Al layer 200. High-temperature growth of the AlN thin film improves the crystal quality and flatness of the AlN thin film. The first high-temperature AlN nucleation layer 301 blocks the diffusion of boron atoms on the substrate 100, improving the crystal quality of subsequent epitaxial layers. The roughened first high-temperature AlN nucleation layer 301 forms island-shaped triangular structures, which release stress between the substrate 100 and subsequent epitaxial layers, further improving the crystal quality of subsequent epitaxial layers and preventing stress from penetrating and extending into subsequent epitaxial layers, thus affecting their growth.

[0040] Specifically, firstly, the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar, and a first high-temperature AlN nucleation layer 301 with a thickness of 100-200 nm is epitaxially grown on the Al layer 200; secondly, the temperature is adjusted to between 1000-1100℃, and Cl2 is introduced to roughen the first high-temperature AlN nucleation layer 301 for 1-5 min, with a roughening thickness of 2-10 nm; finally, the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar, and N2 is introduced to purge for 10-20 min to remove unreacted Cl2 from the reaction chamber.

[0041] It should be noted that the thickness of the first high-temperature AlN nucleation layer 301 is 100-200 nm. When the thickness of the first high-temperature AlN nucleation layer 301 is less than 100-200 nm, the crystal quality of the AlN thin film will deteriorate, affecting the growth of subsequent epitaxial layers. When the thickness of the first high-temperature AlN nucleation layer 301 is greater than 100-200 nm, there is a risk of fracture due to the excessive thickness. The roughening thickness of the first high-temperature AlN nucleation layer 301 is 2-10 nm. When the roughening thickness is too high, the island-shaped triangular structures on the first high-temperature AlN nucleation layer 301 will be too large, affecting the growth of the second high-temperature AlN nucleation layer 302 and reducing the crystal quality of the second high-temperature AlN nucleation layer 302, thereby affecting the crystal quality of subsequent epitaxial layers. When the roughening thickness is too low, the stress between the substrate and the epitaxial layer cannot be released, and this stress will penetrate into the subsequent epitaxial layers, directly affecting the crystal quality of the subsequent epitaxial layers.

[0042] In addition, a second high-temperature AlN nucleation layer 302 is provided on the first high-temperature AlN nucleation layer 301 to release the stress accumulated in the first high-temperature AlN nucleation layer 301 and further improve the crystal quality of the subsequent epitaxial layer. The thickness of the second high-temperature AlN nucleation layer 302 is 100-200 nm. Similarly, when the thickness of the second high-temperature AlN nucleation layer 302 is less than 100-200 nm, the crystal quality of the AlN thin film layer will deteriorate, affecting the growth of the subsequent epitaxial layer; when the thickness of the second high-temperature AlN nucleation layer 302 is greater than 100-200 nm, the excessive thickness of the second high-temperature AlN nucleation layer 302 may lead to fracture. Specifically, the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar, and a second high-temperature AlN nucleation layer 302 with a thickness of 100-200 nm is epitaxially grown on the roughened first high-temperature AlN nucleation layer 301.

[0043] In this embodiment, an AlN nucleation layer 300 is provided on the Al layer 200. The AlN nucleation layer 300 includes a roughened first high-temperature AlN nucleation layer 301 and a second high-temperature AlN nucleation layer 302. The first high-temperature AlN nucleation layer 301 blocks the diffusion of boron atoms from the substrate 100, thereby roughening the first high-temperature AlN nucleation layer 301 to release the stress on the substrate 100 and subsequent epitaxial layers, improve the crystal quality of the subsequent epitaxial layers, and thus improve the performance of silicon-based high electron mobility transistors. The second high-temperature AlN nucleation layer 302 is provided on the roughened first high-temperature AlN nucleation layer 301 to further release the stress accumulated in the first high-temperature AlN nucleation layer 301, further improve the crystal quality of the subsequent epitaxial layers, and thus further improve the performance of silicon-based high electron mobility transistors.

[0044] A high-resistivity buffer layer 400 is provided on the second high-temperature AlN nucleation layer 302 to prevent the diffusion of two-dimensional electron gas toward the substrate 100. This high-resistivity buffer layer 400 is an AlGaN thin film with an Al composition ratio of 0.2-0.8%, and the dopant in the high-resistivity buffer layer 400 is carbon with a carbon doping concentration of 10%. 19 cm -3 -10 20 cm -3 Specifically, the temperature is adjusted to between 1000-1200℃ and the pressure is set between 40-70mbar, and an AlGaN thin film layer with a thickness of 2-4μm is epitaxially grown on the second high-temperature AlN nucleation layer 302.

[0045] In addition, a channel layer 500 is provided on the high-resistivity buffer layer 400. This channel layer 500 is a GaN thin film layer, which is used to form a polarization effect with the AlGaN barrier layer 700 to generate a two-dimensional electron gas. Specifically, the temperature is set between 1000-1150℃ and the pressure is adjusted to between 100-300 mbar to grow a GaN thin film layer with a thickness of 300-600 nm on the high-resistivity buffer layer 400.

[0046] An AlN insertion layer 600 is provided on the channel layer 500 to reduce interface scattering between the channel layer 500 and the AlGaN barrier layer 700 and improve electron mobility. Specifically, the temperature is adjusted to between 1050-1150℃ and the pressure is set to between 40-70mbar to grow an AlN insertion layer 600 with a thickness of 0.5-2nm on the channel layer 500.

[0047] An AlGaN barrier layer 700 is provided on the AlN insertion layer 600 to form a polarization effect with the channel layer 500 to generate a two-dimensional electron gas. Specifically, the temperature is set between 1050-1150℃ and the pressure is set between 40-70 mbar, and an AlGaN barrier layer 700 with a thickness of 20-25 nm is epitaxially grown on the AlN insertion layer 600, wherein the Al composition accounts for 0.2-0.25%.

[0048] Naturally, a GaN capping layer 800 is provided on the AlGaN barrier layer 700 to cover it and prevent oxidation. Specifically, the temperature is adjusted to between 050-1150℃ and the pressure is set to between 40-70 mbar, and a GaN capping layer 800 with a thickness of 3-10 nm is epitaxially grown on the AlGaN barrier layer 700. At this point, the epitaxial structure growth is complete, and the temperature of the reaction chamber is reduced to room temperature in a nitrogen atmosphere.

[0049] Compared to existing technologies, the silicon-based high electron mobility transistor provided in this embodiment has the following advantages: The silicon-based high electron mobility transistor provided by this invention has an AlN nucleation layer between the substrate and the high-resistivity buffer layer. This AlN nucleation layer includes a roughened first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer. The first high-temperature AlN nucleation layer is disposed on the substrate. The crystal quality of the first high-temperature AlN nucleation layer is superior to that of the low-temperature grown AlN layer, which can more effectively block impurities in the substrate, improve the crystal quality of the subsequent epitaxial layer, and prevent boron atoms from easily diffusing into the epitaxial layer, thus avoiding a decrease in the crystal quality of the epitaxial layer. The surface roughening treatment of the AlN nucleation layer can release the stress between the substrate and the epitaxial layer. A second high-temperature AlN nucleation layer is then formed on the roughened first high-temperature AlN nucleation layer to further release the stress accumulated in the first high-temperature AlN nucleation layer, thereby further improving the crystal quality of the subsequent epitaxial layer and thus improving the performance of silicon-based high electron mobility transistors. This avoids the existence of large stress between the silicon substrate and the epitaxial layer, which extends through to the subsequent epitaxial layer and affects the crystal quality of the subsequent epitaxial layer. This solves the common technical problem of boron atoms diffusing from the silicon substrate to the epitaxial layer, resulting in large stress between the silicon substrate and the epitaxial layer and a decrease in the crystal quality of the epitaxial layer.

[0050] Example 2

[0051] The second embodiment of the present invention provides a method for fabricating a silicon-based high electron mobility transistor, the method comprising steps S10-S12:

[0052] Step S10: Provide a substrate;

[0053] The substrate is a P-type doped silicon substrate, which is a (111) crystal orientation silicon substrate. The dopant is boron, and the boron doping concentration is 10. 18 cm -3 -10 20 cm -3 P-type doped silicon substrates can improve the substrate's conductivity and reduce voltage drop and energy consumption. Before epitaxial layer growth, the substrate surface needs to be pretreated to remove impurities adsorbed on the substrate surface.

[0054] Specifically, the substrate is placed in the reaction chamber, the temperature is heated to between 1000-1200℃, the pressure is set to between 50-100mbar, and H2 is introduced for pretreatment for 5-10 minutes.

[0055] Step S11: An Al layer is grown on the substrate;

[0056] In this process, pre-depositing an Al layer on the substrate improves the crystal quality and surface smoothness of the subsequent AlN nucleation layer. Because Al atoms have a high viscosity coefficient and weak lateral migration ability on the substrate, and because Al atoms are relatively active, directly growing an AlN thin film layer tends to cause clustering and hinders diffusion. Pre-depositing an Al layer before growing the AlN thin film layer enhances the lateral migration ability of Al atoms, thereby improving the surface smoothness and crystal quality of the AlN thin film layer.

[0057] Specifically, the temperature is adjusted to between 1000-1100℃, the pressure is set to between 40-70mbar, an Al source is introduced with a flow rate of 50-200sccm, and an Al layer is deposited on the substrate with a thickness of 1-5nm.

[0058] Step S12, an AlN nucleation layer is epitaxially grown on the Al layer, wherein the AlN nucleation layer includes a first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer after roughening treatment, and the first high-temperature AlN nucleation layer is epitaxially grown on the Al layer;

[0059] High-temperature epitaxial growth of AlN thin films improves the crystal quality and surface smoothness of the AlN thin film, effectively blocking the diffusion of boron atoms from the substrate. The first high-temperature AlN nucleation layer prevents boron atoms from diffusing into subsequent epitaxial layers, thus avoiding a decrease in the crystal quality of the subsequent epitaxial layers and even significant lattice mismatch. This results in substantial stress between the substrate and the subsequent epitaxial layers, causing lattice dislocations and defects in the subsequent epitaxial layers, affecting the performance of silicon-based high-electron-mobility transistors (HETTs). Roughening the first high-temperature Al nucleation layer helps release the stress between the substrate and the subsequent epitaxial layers, improving the crystal quality of the subsequent epitaxial layers and thus enhancing the performance of the silicon-based HETT. A second high-temperature AlN nucleation layer is then applied to the roughened first high-temperature AlN nucleation layer to further release the stress accumulated in the first high-temperature AlN nucleation layer, further improving the crystal quality of the subsequent epitaxial layers and further enhancing the performance of the silicon-based HETT.

[0060] Specifically, the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar to epitaxially grow a first high-temperature AlN nucleation layer with a thickness of 100-200 nm on the Al layer; the temperature is adjusted to between 1000-1100℃ and Cl2 is introduced to roughen the first high-temperature AlN nucleation layer for 1-5 min, with a roughening thickness of 2-10 nm; the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar, and N2 is introduced to purge for 10-20 min to remove unreacted Cl2 from the reaction chamber; the temperature is adjusted to between 1100-1200℃ and the pressure is set between 40-70 mbar to epitaxially grow a second high-temperature AlN nucleation layer with a thickness of 100-200 nm on the roughened first high-temperature AlN nucleation layer.

[0061] Step S13: A high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the AlN nucleation layer.

[0062] In this process, a high-resistivity buffer layer is epitaxially grown on the second high-temperature AlN nucleation layer. This high-resistivity buffer layer is an AlGaN thin film layer, which is used to block the diffusion of two-dimensional electron gas toward the substrate.

[0063] Specifically, the temperature is adjusted to between 1000-1200℃, and the pressure is set between 40-70 mbar. An AlGaN thin film with a thickness of 2-4 μm is epitaxially grown on the second high-temperature AlN nucleation layer. The Al composition of the AlGaN thin film is 0.2-0.8%, and the dopant is carbon with a carbon doping concentration of 10%. 19 cm -3 -10 20 cm -3 .

[0064] In addition, a channel layer is epitaxially grown on the high-resistivity buffer layer. This channel layer is a GaN thin film layer, which is used to form a polarization effect with the AlGaN barrier layer to generate a two-dimensional electron gas.

[0065] Specifically, the temperature is set between 1000-1150℃ and the pressure is adjusted to between 100-300mbar to grow a GaN thin film layer with a thickness of 300-600nm on the high-resistivity buffer layer.

[0066] An AlN insertion layer is epitaxially grown on the channel layer to reduce interface scattering between the GaN channel layer and the AlGaN barrier layer, thereby improving electron mobility.

[0067] Specifically, the temperature is adjusted to between 1050-1150℃ and the pressure is set to between 40-70mbar to grow an AlN insertion layer with a thickness of 0.5-2nm on the channel layer.

[0068] An AlGaN barrier layer is grown on the AlN insertion layer to form a polarization effect with the channel layer and generate a two-dimensional electron gas.

[0069] Specifically, the temperature is set between 1050-1150℃ and the pressure is set between 40-70mbar, and an AlGaN barrier layer with a thickness of 20-25nm is epitaxially grown on the AlN insertion layer, wherein the Al composition accounts for 0.2-0.25%.

[0070] In addition, a GaN capping layer is epitaxially grown on the AlGaN barrier layer to cover the AlGaN barrier layer and prevent the AlGaN barrier layer from being oxidized.

[0071] Specifically, the temperature is adjusted to between 050-1150℃ and the pressure is set to between 40-70mbar, and a GaN capping layer with a thickness of 3-10nm is epitaxially grown on the AlGaN barrier layer.

[0072] At this point, the epitaxial structure growth is complete, and the temperature of the reaction chamber is reduced to room temperature in a nitrogen atmosphere.

[0073] Compared to existing technologies, the method for fabricating a silicon-based high electron mobility transistor provided in this embodiment has the following advantages: The method involves pre-depositing an Al layer on a substrate to improve the crystal quality and surface flatness of the AlN nucleation layer. An AlN nucleation layer is then epitaxially grown on the Al layer. This Al nucleation layer includes a roughened first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer. High-temperature growth of the first high-temperature AlN nucleation layer improves its crystal quality and surface flatness and effectively blocks boron atoms from the substrate. The first high-temperature AlN nucleation layer diffuses into the subsequent epitaxial layer. Next, the surface of the first high-temperature AlN nucleation layer is roughened to release the stress between the substrate and the subsequent epitaxial layer. Finally, a second high-temperature AlN nucleation layer is epitaxially grown on the roughened first high-temperature AlN nucleation layer to further release the stress accumulated in the first high-temperature AlN nucleation layer and further improve the crystal quality of the subsequent epitaxial layer. This improves the performance of silicon-based high electron mobility transistors and solves the common technical problem of boron atoms diffusing from the silicon substrate into the epitaxial layer, resulting in significant stress between the silicon substrate and the epitaxial layer, leading to a decrease in the crystal quality of the epitaxial layer.

[0074] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0075] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A silicon-based high electron mobility transistor, characterized in that, The silicon-based high electron mobility transistor includes: Substrate; The substrate is sequentially provided with an AlN nucleation layer, a high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer. The AlN nucleation layer comprises a first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer after roughening treatment. The first high-temperature AlN nucleation layer is disposed on the substrate. The growth temperature of the first high-temperature AlN nucleation layer is 1100-1200℃ and the pressure is 40-70mbar. The growth temperature of the second high-temperature AlN nucleation layer is 1100-1200℃ and the pressure is 40-70mbar. The roughening treatment is carried out by introducing Cl2 at a temperature of 1000-1100℃ and a pressure of 40-70mbar to roughen the first high-temperature AlN nucleation layer for 1-5 minutes, followed by purging with N2 for 10-20 minutes to remove unreacted Cl2 in the reaction chamber. The roughening thickness is 2-10nm. The thickness of the first high-temperature AlN nucleation layer is 100-200nm, and the thickness of the second high-temperature AlN nucleation layer is 100-200nm.

2. The silicon-based high electron mobility transistor according to claim 1, characterized in that, The first high-temperature AlN nucleation layer after roughening treatment has an island-shaped triangular shape.

3. The silicon-based high electron mobility transistor according to claim 1, characterized in that, An Al layer is provided between the substrate and the AlN nucleation layer.

4. The silicon-based high electron mobility transistor according to claim 3, characterized in that, The thickness of the Al layer is 1-5 nm.

5. The silicon-based high electron mobility transistor according to claim 1, characterized in that, The high-resistivity buffer layer is an AlGaN thin film with a thickness of 2-4 μm and an Al composition ratio of 0.2-0.8%. The dopant in the high-resistivity buffer layer is carbon with a carbon doping concentration of 10. 19 cm -3 -10 20 cm -3 .

6. The silicon-based high electron mobility transistor according to claim 1, characterized in that, The channel layer is a GaN thin film with a thickness of 300-600 nm.

7. The silicon-based high electron mobility transistor according to claim 1, characterized in that, The substrate is a p-type doped Si substrate, and the dopant is boron with a boron doping concentration of 10. 18 cm -3 -10 20 cm -3 .

8. A method for fabricating a silicon-based high electron mobility transistor, characterized in that, The preparation method includes: Provide a substrate; An Al layer is grown on the substrate; An AlN nucleation layer is epitaxially grown on the Al layer, wherein the AlN nucleation layer includes a first high-temperature AlN nucleation layer and a second high-temperature AlN nucleation layer after roughening treatment, the first high-temperature AlN nucleation layer being epitaxially grown on the Al layer, and the AlN nucleation layer growth step includes: The temperature was adjusted to between 1100-1200℃ and the pressure was set between 40-70mbar to epitaxially grow a first high-temperature AlN nucleation layer with a thickness of 100-200nm on the Al layer. Adjust the temperature to between 1000-1100℃ and introduce Cl2 to roughen the first high-temperature AlN nucleation layer for 1-5 minutes, with a roughening thickness of 2-10nm. Adjust the temperature to between 1100-1200℃ and the pressure to between 40-70mbar, and purge with N2 for 10-20 minutes to remove unreacted Cl2 from the reaction chamber. The temperature was adjusted to between 1100-1200℃ and the pressure was set between 40-70mbar. A second high-temperature AlN nucleation layer with a thickness of 100-200nm was epitaxially grown on the first high-temperature AlN nucleation layer after roughening treatment. A high-resistivity buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN capping layer are sequentially grown on the AlN nucleation layer.

Images