A power VDMOS device resistant to single event gate rupture

Abstract

The application provides a power VDMOS device with anti-single particle effect gate damage, which comprises a first conductive type substrate, an epitaxial layer and a high concentration doped source, a second conductive type buried layer, a well region and a high doped region. A gate dielectric, a gate electrode, a passivation layer and a source metal electrode are formed above the first conductive type epitaxial layer. The second conductive type buried layer is located directly below the gate, covers the whole JFET region and part of the second conductive type well region, and the longitudinal distance between the second conductive type buried layer and the second conductive type well region is greater than half of the JFET width defined by the distance between two adjacent second conductive type well regions. The structure utilizes the electric field shielding and carrier conduction effect of the buried layer, can significantly inhibit the gate degradation caused by irradiation without sacrificing the JFET resistance, and can also reduce the Miller capacitance and improve the high frequency characteristics of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, and relates to a power VDMOS device resistant to single-event gate damage. BACKGROUND

[0002] Vertical double-diffused metal oxide semiconductor (VDMOS) is a representative power device, which is widely used in various power switching systems due to high input impedance, fast switching speed, negative temperature coefficient, good thermal stability, no secondary breakdown and other characteristics.

[0003] The space radiation environment is a complex environment full of various cosmic rays, which mainly includes galactic cosmic rays (GCR) composed of protons and alpha particles, solar cosmic rays (SCR) composed of high-energy and high-flux charged particle streams accelerated by the solar atmosphere, solar wind formed by hot ionized gas flying from the sun to the earth, and Earth radiation belt (Van Allen belt) composed of protons, electrons and a small amount of low-energy heavy ions captured by the geomagnetic field, in addition to the space nuclear explosion environment composed of nuclear radiation, high-energy electromagnetic pulse and nuclear explosion shock wave from ground or high-altitude nuclear weapon explosion, and secondary particles generated by the interaction of the above high-energy particles with the materials constituting the spacecraft.

[0004] Single-event gate rupture (SEGR) mainly refers to the phenomenon that the gate insulating medium is short-circuited due to the incidence of high-energy particles. Its failure mechanism is mainly that a large number of electron-hole pairs are excited in the semiconductor body material when high-energy particles are incident, which causes a transient short circuit under the drain-gate, makes the gate dielectric material bear a larger electric field strength, and leads to permanent performance degradation or even breakdown and burnout of the gate dielectric. In the single-particle experiment of silicon carbide (SiC) VDMOS device, it is also observed that the gate current increases significantly before the device burns out, and permanent performance degradation occurs after stopping irradiation. Irradiation and reliability reinforcement of the gate become the first problem to be faced in the space application of semiconductor devices.

[0005] The common method for SEGR irradiation hardening is to perform selective doping of P-type and N-type well regions in VDMOS to complete the manufacture of the channel region, and then manufacture the gate oxide and polysilicon gate, so as to avoid the high-temperature treatment required by annealing of the gate oxide layer. In addition, directly thickening the gate oxide layer also has obvious anti-SEGR effect, but will have a negative effect on the total dose (TID, Total Ionizing Dose) resistance of the device, which needs to be optimized. In addition, research shows that the anti-SEGR capability will increase with the decrease of the cell JFET width, and the introduction of the P+ region connected to the source in the JFET region below the gate also has a certain gate hardening effect. However, both of these two structures greatly increase the resistance of the JFET region, which is not conducive to the forward characteristics of the device. SUMMARY

[0006] In view of the deficiencies of the above-mentioned existing VDMOS gate irradiation hardening technology, the purpose of the present application is to provide a power VDMOS device structure resistant to single event effect gate damage, which utilizes the electric field shielding and carrier flow guiding effect of the buried layer to significantly inhibit the gate degradation caused by irradiation without sacrificing the JFET resistance, and also reduces the Miller capacitance and improves the high-frequency characteristics of the device.

[0007] The present application adopts the following technical solutions:

[0008] A power VDMOS device resistant to single event effect gate damage, comprising:

[0009] a first conductive type substrate;

[0010] a drain electrode located at the bottom of the first conductive type substrate;

[0011] a first conductive type epitaxial layer drift region located on the first conductive type substrate;

[0012] a second conductive type buried layer located in the first conductive type epitaxial layer drift region;

[0013] a second conductive type well region located in the first conductive type epitaxial layer drift region and close to the upper surface;

[0014] a JFET region located in the first conductive type epitaxial layer drift region and between two adjacent second conductive type well regions;

[0015] a first conductive type source region located in the second conductive type well region and close to the JFET region;

[0016] a second conductive type heavily doped region located in the second conductive type well region and away from the JFET region;

[0017] an isolation gate dielectric layer on part of the second-conductivity-type well region, the first-conductivity-type source region, and the JFET region;

[0018] a gate electrode on the part of the isolation gate dielectric layer;

[0019] a passivation layer on the gate electrode and the isolation gate dielectric layer;

[0020] a source metal electrode on the second-conductivity-type heavily doped region, the passivation layer, and part of the first-conductivity-type source region.

[0021] Further, the first-conductivity-type is N-type and the second-conductivity-type is P-type, or the first-conductivity-type is P-type and the second-conductivity-type is N-type.

[0022] Further, a projection of the second-conductivity-type buried layer in a first direction covers all of the JFET region and part of the second-conductivity-type well region in the active region of the device, and the first direction is the growth direction of the first-conductivity-type epitaxial layer drift region.

[0023] Further, the second-conductivity-type buried layer is a single whole or multiple parallel.

[0024] Further, the second-conductivity-type buried layer is multiple parallel in a first direction.

[0025] Further, the second-conductivity-type buried layer is multiple parallel in a second direction, and the second direction is perpendicular to the first direction.

[0026] Further, the vertical distance between the second-conductivity-type buried layer and the second-conductivity-type well region is not less than half the width of the JFET region.

[0027] Further, the second-conductivity-type buried layer is connected to the source metal electrode through a body contact region and a contact hole at the edge of the active region of the device.

[0028] Advantages of the present application: The present application can effectively suppress the transient high electric field under the gate caused by single particle irradiation by introducing a buried layer covering the entire JFET region, and can reduce the Miller capacitance of the device and improve the high-frequency characteristics. In addition, due to the large longitudinal spacing between the buried layer region and the second-conductivity-type well region, the JFET resistance is not increased by introducing a P-type shielding layer in the traditional structure, and the good forward working characteristics of the device are ensured. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 For Example 1 of the present application, a power VDMOS device resistant to single particle effect gate damage.

[0030] Figure 2A multi-buried layer power VDMOS device against single event gate rupture for example 2 of the present application.

[0031] Figure 3 A multi-buried layer power VDMOS device against single event gate rupture for example 3 of the present application.

[0032] Figure 4 A trench type power VDMOS device against single event gate rupture for example 3 of the present application.

[0033] Explanation of reference signs: 1, first conductive type substrate; 2, first conductive type epitaxial layer drift region; 3, second conductive type buried layer; 4, second conductive type well region; 5, second conductive type heavily doped region; 6, first conductive type source region; 7, isolation gate dielectric layer; 8, gate electrode; 9, passivation layer; 10, source metal electrode. DETAILED DESCRIPTION

[0034] As described in the background, the failure mechanism of single event gate rupture is mainly that a large number of electron-hole pairs are excited in the semiconductor bulk material when high-energy particles are incident, which causes a transient short circuit under the drain-gate, so that the gate dielectric material bears a large electric field intensity, resulting in permanent performance degradation or even breakdown and burnout of the gate dielectric.

[0035] To solve this problem, the present application provides a power VDMOS device against single event gate rupture, by setting a second conductive type buried layer in the first conductive type epitaxial layer drift region, using the electric field shielding and carrier conduction effect of the buried layer, without sacrificing the JFET resistance, the gate degradation caused by irradiation can be significantly inhibited, and the Miller capacitance can be reduced, and the high frequency characteristics of the device can be improved.

[0036] The present application is further described below in conjunction with the embodiments, which are only used to illustrate the present application and do not constitute a limitation on the scope of the claims, and other alternative means that can be thought of by those skilled in the art are within the scope of the claims of the present application.

[0037] It should be further explained that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), if the certain posture changes, the directional indications also change accordingly.

[0038] It should be noted that the structure shown in the embodiment can be modified in detail according to actual conditions. For ease of description, the embodiment is described using only an N-type channel VDMOS; the same applies to a P-channel VDMOS. In the embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0039] The width described in the embodiments refers to the length in the horizontal direction, and the height or depth described refers to the length in the vertical direction.

[0040] Example 1

[0041] like Figure 1 As shown, a power VDMOS device resistant to single event effect gate damage described in the present invention includes a first conductive type substrate 1 and a drain located on the back side of the first conductive type substrate 1, wherein the first conductive type substrate 1 is heavily doped N-type Si.

[0042] On the first conductive type substrate 1 is a first conductive type epitaxial layer drift region 2 , wherein the first conductive type epitaxial layer drift region 2 is lightly doped N-type Si.

[0043] There is a second conductive type buried layer 3 in the first conductive type epitaxial layer drift region 2, wherein the second conductive type buried layer 3 is heavily doped P type. In this embodiment, the second conductive type buried layer 3 is a single entity, and the projection of the second conductive type buried layer 3 in the first direction covers all JFET areas and part of the second conductive type well area in the device active area. The first direction is the growth direction of the first conductive type epitaxial layer drift region.

[0044] A second conductive type well region 4 is provided near the surface of the semiconductor in the drift region 2 of the first conductive type epitaxial layer. A JFET region is provided between two adjacent second conductive type well regions 4 .

[0045] In the second conductivity type well region 4 , a second conductivity type heavily doped region 5 is provided on a side away from the JFET region.

[0046] In the second conductivity type well region 4, a first conductivity type source region 6 is provided on the side close to the JFET region. The two boundaries between the well region 4 and the first conductivity type source region 6 on the side close to the JFET define the channel region of the device.

[0047] An isolation gate dielectric layer 7 covers a portion of the well region 4 , a portion of the first conductivity type source region 6 and the JFET region.

[0048] The isolation gate dielectric layer 7 is covered with a polycrystalline gate electrode 8 .

[0049] The polycrystalline gate electrode 8 is covered with a passivation layer 9 .

[0050] The heavily doped region 5 , the first conductive type source region 6 and the passivation layer 9 are covered with a source metal electrode 10 .

[0051] Example 2

[0052] like Figure 2 The embodiment 2 shown is basically the same as the embodiment 1, and the only difference from the embodiment 1 is that the second conductive type buried layer 3 in the drift region 2 is changed from a single buried layer of the second conductive type buried layer 3 in the embodiment 1 to a multiple buried layer in the embodiment 2, wherein the multiple buried layers are arranged in a second direction, and the second direction is perpendicular to the first direction, so as to change the body electric field distribution and optimize the forward conduction characteristics.

[0053] Example 3

[0054] like Figure 3 The embodiment 3 shown is basically the same as the embodiment 1, and the only difference from the embodiment 1 is that the second conductive type buried layer 3 in the drift region 2 is changed from the single buried layer in the embodiment 1 to the multi-layer buried layer in the embodiment 3, wherein the multiple buried layers are arranged in the first direction to further enhance the electric field shielding capability and strengthen the gate's anti-SEGR capability.

[0055] Example 4

[0056] like Figure 4 The embodiment 4 shown is basically the same as the embodiment 1, and differs from the embodiment 1 mainly in that the planar gate structure is adopted in the embodiment 1, while the trench gate structure is adopted in the embodiment 3. This example only illustrates that the present invention is also applicable to trench structure devices.

[0057] By providing a buried layer beneath the gate that covers the entire JFET region, the present invention provides complete shielding and reinforcement for the gate electrode oxide layer, preventing excessive local electric fields caused by radiation exposure and reducing gate leakage during the initial stages of single-event effects. Furthermore, due to the large vertical distance between the buried layer and the well region, the introduction of the buried layer substantially does not alter the JFET resistance, ensuring good forward characteristics. This structure also reduces the device's Miller capacitance and improves its high-frequency characteristics.

[0058] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A power VDMOS device resistant to single event effect gate damage, characterized in that: include: A first conductive type substrate (1); A drain electrode located at the bottom of the first conductive type substrate (1); a first conductive type epitaxial layer drift region (2) located on the first conductive type substrate (1); a second conductive type buried layer (3) located in the first conductive type epitaxial layer drift region (2), wherein a projection of the second conductive type buried layer (3) in a first direction covers the entire JFET region and a portion of the second conductive type well region (4) in the device active region, the first direction being the growth direction of the first conductive type epitaxial layer drift region (2), and a vertical distance between the second conductive type buried layer (3) and the second conductive type well region (4) is not less than half the width of the JFET region; a second conductive type well region (4) located in the first conductive type epitaxial layer drift region (2) and close to the upper surface; A JFET region located in the drift region (2) of the epitaxial layer of the first conductivity type and between two adjacent well regions (4) of the second conductivity type; Located in the second conductive type well region (4), close to the first conductive type source region (6) of the JFET region; A second conductivity type heavily doped region (5) located in the second conductivity type well region (4) and away from the JFET region; an isolation gate dielectric layer (7) located on a portion of the second conductive type well region (4), the first conductive type source region (6), and the JFET region; a gate electrode (8) located on a portion of the isolation gate dielectric layer (7); a passivation layer (9) located on the gate electrode (8) and the isolation gate dielectric layer (7); A source metal electrode located above the second conductive type heavily doped region (5), the passivation layer (9) and a portion of the first conductive type source region (6).

2. The power VDMOS device resistant to single event gate damage according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

3. The power VDMOS device resistant to single event gate damage according to claim 1, characterized in that: The second conductive type buried layer (3) is a single entity or a plurality of parallel ones.

4. The power VDMOS device resistant to single event gate damage according to claim 3, characterized in that: The second conductive type buried layer (3) is a plurality of layers arranged in parallel in the first direction.

5. The power VDMOS device resistant to single event gate damage according to claim 3, characterized in that: The second conductive type buried layer (3) is a plurality of layers arranged in parallel in a second direction, and the second direction is perpendicular to the first direction.

6. The power VDMOS device resistant to single event gate damage according to claim 1, characterized in that: The second conductive type buried layer (3) is connected to the source metal electrode (10) at the edge of the device active area through a body contact area and a contact hole.

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