Junction field effect transistor and preparation method thereof

Abstract

The present invention relates to a junction field effect transistor and a preparation method thereof, wherein the junction field effect transistor comprises: a substrate of a first conductivity type; at least two layers of well region structures, stacked on the substrate; each layer of the well region structure comprises a first well region of a second conductivity type, and two second well regions located on opposite sides of the first well region; wherein the conductivity type of the second well region is opposite to the second conductivity type and the same as the first conductivity type; a drain and a source, respectively formed on opposite sides of the first well region of the top well region structure; and a gate, formed in the two second well regions of the top well region structure; wherein, in two adjacent layers of the well region structure, the two adjacent first well regions are in contact with each other, and the two second well regions on the same side are connected to each other. While obtaining the same conductivity, the structural design of the junction field effect transistor of the present application can save design size.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a junction field effect transistor and a method for preparing the same. Background Art

[0002] Junction Field-Effect Transistor (JFET) JFET is made by making two highly doped P regions on the same N-type semiconductor and connecting them together. The electrode drawn out is called the gate g, and two electrodes are drawn out at both ends of the N-type semiconductor, called the drain d and the source s respectively.

[0003] However, the current that the conventional junction field effect transistor can carry per unit volume is very limited, resulting in a relatively low conductivity of the conventional junction field effect transistor. Summary of the Invention

[0004] Based on this, it is necessary to provide a junction field effect transistor and a preparation method thereof to address the problem that the conventional junction field effect transistor has low conductivity.

[0005] According to one aspect of the present application, a junction field effect transistor is provided, comprising:

[0006] a substrate of a first conductivity type;

[0007] At least two well region structures are stacked on the substrate; each well region structure includes a first well region of the second conductivity type and two second well regions located on opposite sides of the first well region; wherein the conductivity type of the second well region is opposite to the second conductivity type and the same as the first conductivity type;

[0008] a drain and a source, formed on opposite sides of the first well region of the uppermost well region structure; and

[0009] a gate formed in the two second well regions of the uppermost well region structure;

[0010] Wherein, in two adjacent layers of the well region structure, two adjacent first well regions are in contact with each other, and two second well regions on the same side are connected to each other.

[0011] In one embodiment, the first well region includes a channel region and two drift regions located on opposite sides of the channel region, and a trench located between the drain and the source is formed on the channel region;

[0012] The at least two layers of the well region structures include an A-well region structure located at the uppermost layer and at least one B-well region structure located below the A-well region structure along the stacking direction of the well region structures;

[0013] The drain and the source are respectively formed in the two drift regions of the first well region in the A-well region structure.

[0014] In one embodiment, in the A-well region structure, a shallow trench isolation structure is provided in the trench on the first well region to isolate the drain and the source from each other.

[0015] In one embodiment, two longitudinal ends of the shallow trench isolation structure extend toward opposite sides and respectively contact two second well regions in the A-well region structure to isolate the two second well regions from each other.

[0016] In one embodiment, the gate comprises:

[0017] a polysilicon layer, disposed on the shallow trench isolation structure;

[0018] a gate electrode layer, disposed on a side of the polysilicon layer away from the shallow trench isolation structure;

[0019] A gate connection layer is formed in the two second well regions of the A-well region structure, and the gate connection layer is in contact with the gate electrode layer.

[0020] In one embodiment, it further includes an intermediate substrate layer of the first conductivity type;

[0021] The intermediate substrate layer is formed in the groove on the first well region in the B-well region structure, and the opposite ends of the intermediate substrate layer extend outside the groove to be inserted between the two second well regions on the same side of two adjacent layers of the well region structure.

[0022] In one embodiment, the intermediate substrate layer is doped with first type ions at a first dose, and the first well region in the B-well structure is doped with second type ions at a second dose;

[0023] Wherein, the first dose is greater than the second dose.

[0024] In one embodiment, in two adjacent well region structures, the second well region of one of the well region structures is doped with the first type ions at a third dose, and the second well region of the other well region structure is doped with the first type ions at a fourth dose;

[0025] The third dose and the fourth dose are both set according to the first dose, so that the two second well regions on the same side of two adjacent well region structures are connected via the intermediate substrate layer.

[0026] According to another aspect of the present application, a method for preparing a junction field effect transistor is provided, comprising the following steps:

[0027] providing a substrate of a first conductivity type;

[0028] At least two well region structures are stacked on the substrate, each of the well region structures including a first well region of the second conductivity type and two second well regions located on opposite sides of the first well region; wherein the conductivity type of the second well region is opposite to the second conductivity type and the same as the first conductivity type;

[0029] forming a drain and a source on opposite sides of the first well region of the uppermost well region structure;

[0030] forming gates on the two second well regions of the well region structure in the uppermost layer;

[0031] Wherein, in two adjacent layers of the well region structure, two adjacent first well regions are in contact with each other, and two second well regions on the same side are connected to each other.

[0032] In one embodiment, before forming at least two stacked well region structures on the substrate, the preparation method further includes:

[0033] forming a buried layer of a first conductivity type on the substrate;

[0034] epitaxially forming an epitaxial layer of a first conductivity type on the buried layer;

[0035] Wherein, the thickness of the epitaxial layer is 2 to 10 microns.

[0036] In one embodiment, the at least two layers of the well region structures include an A-well region structure located at the top and at least one B-well region structure located below the A-well region structure along the stacking direction of the well region structures, and the at least two layers of well region structures stacked on the substrate specifically include:

[0037] forming an active region on the substrate;

[0038] Masking and ion implantation are performed on the epitaxial layer through the active area to form the B-well region structure on the epitaxial layer;

[0039] forming an intermediate substrate layer at the trench on the first well region in the B-well region structure;

[0040] Masking and ion implantation are performed on the intermediate substrate layer to form the A-well region structure on the intermediate substrate layer.

[0041] The junction field effect transistor and the preparation method thereof of the present invention have at least the following beneficial effects:

[0042] In the junction field-effect transistor of the present invention, the at least two well regions are provided, which is equivalent to increasing the length of the conductive channel of the junction field-effect transistor, thereby increasing the effective conductive area of ​​the junction field-effect transistor, which can effectively improve the conductivity of the junction field-effect transistor. In other words, while achieving the same conductivity, the structural design of the junction field-effect transistor of the present application can further save design size.

[0043] The method for preparing the junction field effect transistor of the present invention can obtain a junction field effect transistor with a more economical design size. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of a partial structure of a junction field effect transistor in an embodiment of the present application is shown;

[0046] Figure 2 FIG2 shows a top view of a junction field effect transistor in one embodiment of the present application;

[0047] Figure 3 shows a transverse cross-sectional view of a junction field effect transistor in one embodiment of the present application;

[0048] Figure 4 shows a longitudinal cross-sectional view of a junction field effect transistor in one embodiment of the present application;

[0049] Figure 5 A flow chart showing a method for preparing a junction field effect transistor in an embodiment of the present application is shown;

[0050] Figure 6 A flow chart of a method for preparing a junction field effect transistor in another embodiment of the present application is shown.

[0051] Description of reference numerals:

[0052] 10. Junction field-effect transistor; 110. Substrate; 120. Well region structure; 120a. A-well region structure; 120b. B-well region structure; 121. First well region; 1211. Channel region; 1212. Drift region; 1213. Trench; 122. Second well region; 130. Drain; 131. Drain connection layer; 132. Drain electrode layer; 140. Source; 141. Source connection layer; 142. Source electrode layer; 150. Gate; 151. Polysilicon layer; 152. Gate electrode layer; 153. Gate connection layer; 160. Intermediate substrate layer; 170. Shallow trench isolation structure. 181. Buried layer; 182. Epitaxial layer. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0059] In some embodiments, see Figure 1 , combined with reference Figure 2 and Figure 3 The present invention provides a junction field effect transistor 10 , comprising a substrate 110 of a first conductivity type, at least two well region structures 120 , a drain 130 , a source 140 and a gate 150 .

[0060] At least two well region structure layers 120 are stacked on the substrate 110, and each well region structure 120 includes a first well region 121 of the second conductivity type and two second well regions 122 located on opposite sides of the first well region 121, wherein the conductivity type of the second well region 122 is opposite to the second conductivity type and the same as the first conductivity type.

[0061] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0062] In some other embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0063] Specifically, Figure 1 In the illustrated embodiment, the first conductivity type is P-type and the second conductivity type is N-type, that is, the conductivity type of the second well region 122 is P-type and the conductivity type of the first well region 121 is N-type.

[0064] The drain 130 and the source 140 are respectively formed on opposite sides of the first well region 121 of the uppermost well region structure 120 , and the gate 150 is formed in the two second well regions 122 of the uppermost well region structure 120 .

[0065] In the adjacent two-layer well region structure 120 , two adjacent first well regions 121 are in contact with each other, and two second well regions 122 on the same side are connected to each other.

[0066] In the above-mentioned junction field effect transistor 10 , the drain 130 and the source 140 serve as the current input and output terminals of the junction field effect transistor 10 , respectively. The junction field effect transistor 10 can be switched between on and off states by adjusting the voltage of the gate 150 .

[0067] When no negative bias is applied to the gate 150, the current input from the drain 130 (positive electrode) can generate a saturated current between the drain 130 (positive electrode) and the source 140 (negative electrode) due to the conductive effect of the first well region 121 (N-type), causing the junction field effect transistor 10 to turn on. When a negative bias is applied to the gate 150 relative to the source 140, the PN junction depletion layer formed by the first well region 121 (N-type) and the second well region 122 (P-type) in each well region structure 120 is widened, thereby compressing the N-type conductive channel and turning off the junction field effect transistor 10. It can be understood that, under the condition of the same size, the provision of at least two well region structures 120 in the above-mentioned junction field effect transistor 10 is equivalent to increasing the length of the conductive channel of the junction field effect transistor 10, thereby increasing the effective conductive area of ​​the junction field effect transistor 10, which can effectively improve the conductivity of the junction field effect transistor 10. In other words, while achieving the same conductivity, the structural design of the junction field effect transistor 10 of the present application can save more design size.

[0068] In some embodiments, see Figure 1 and Figure 3 , and refer to Figure 4 The first well region 121 includes a channel region 1211 and two drift regions 1212 located on opposite sides of the channel region 1211. A trench 1213 is formed on the channel region 1211 between the drain 130 and the source 140. The at least two-layer well region structure 120 includes an A-well region structure 120a located at the top and at least one B-well region structure 120b located at the bottom side of the A-well region structure 120a. The drain 130 and the source 140 are respectively formed in the two drift regions 1212 of the first well region 121 in the A-well region structure 120a. When no negative bias is applied to the gate 150, current is input from the drain 130 (positive electrode), and holes or electrons can enter the other drift region 1212 through one drift region 1212 and the channel region 1211, so that the drain electrons can be transmitted to the other drift region 1212 and finally reach the source 140 under the action of the drain electric field. At this time, the junction field effect transistor 10 is in the on state.

[0069] In some embodiments, see Figure 1 、 Figure 3 and Figure 4 In the A-well structure 120a, a shallow trench isolation structure 170 is provided in the trench 1213 on the first well region 121 to isolate the drain 130 from the source 140. The shallow trench isolation structure 170 can be used to isolate the drain 130 from the source 140, thereby isolating the active area of ​​the drain 130 from the active area of ​​the source 140, thereby preventing short circuits between the drain 130 and the source 140 and improving the reliability of the junction field-effect transistor 10.

[0070] Alternatively, a shallow trench isolation (STI) process may be used to form the shallow trench isolation structure 170. Specifically, the method of forming the shallow trench isolation structure 170 may include: forming an isolation oxide layer, depositing a nitride, forming a mask layer and an isolation trench, etching the isolation trench, then filling the isolation trench with oxide, and finally removing the nitride and polishing the filled oxide to form the shallow trench isolation structure 170.

[0071] In some embodiments, see Figure 1 and Figure 4 The longitudinal ends of the shallow trench isolation structure 170 extend in opposite directions and contact the two second well regions 122 in the A-well structure 120a, thereby isolating the two second well regions 122 from each other. In this way, the shallow trench isolation structure 170 prevents the positions of the two second well regions 122 in the A-well structure 120a from shifting, thereby improving the reliability of the junction field effect transistor 10.

[0072] In some embodiments, gate 150 includes a polysilicon layer 151, a gate electrode layer 152, and a gate connection layer 153. Polysilicon layer 151 is disposed on shallow trench isolation structure 170, gate electrode layer 152 is disposed on a side of polysilicon layer 151 away from shallow trench isolation structure 170, and gate connection layer 153 is formed in the two second well regions 122 of A-well structure 120a, respectively, and contacts gate electrode layer 152. Forming polysilicon layer 151 on shallow trench isolation structure 170 can, on the one hand, electrically insulate gate 150 from drain 130 and from source 140. On the other hand, it can ensure that gate 150 is formed in the two second well regions 122 of A-well structure 120a, facilitating connection of the two second well regions 122 and leading gate 150 out.

[0073] In some embodiments, the junction field effect transistor 10 further includes an intermediate substrate layer 160 of a first conductivity type, the intermediate substrate layer 160 being formed in a trench 1213 on the first well region 121 in the B-well region structure 120b, and the opposite ends of the intermediate substrate layer 160 extending outside the trench 1213 to be inserted between the two second well regions 122 on the same side of the adjacent two-layer well region structure 120. It can be understood that the intermediate substrate layer 160 is in contact with the two second well regions 122 on the same side of the two adjacent well region structures 120, respectively. In this way, the two second well regions 122 on the same side of the two adjacent well region structures 120 are connected through the intermediate substrate layer 160 to ensure that when the junction field effect transistor 10 is in use, the electrons in the second well region 122 in the top well region structure 120 can flow to the second well regions 122 in other well region structures 120 in sequence, thereby ensuring that when a negative bias is applied to the gate 150 relative to the source 140, the PN junction depletion layer formed by the first well region 121 (N-type) and the second well region 122 (P-type) in each well region structure 120 is widened, which is beneficial to improving the conductivity of the junction field effect transistor 10.

[0074] In some embodiments, intermediate substrate layer 160 is doped with first-type ions at a first dose, and first well region 121 of B-well structure 120b is doped with second-type ions at a second dose, where the first dose is greater than the second dose. The first-type ions and the second-type ions have opposite conductivity types; for example, the first-type ions may be P-type ions and the second-type ions may be N-type ions. Alternatively, the first-type ions may be N-type ions and the second-type ions may be P-type ions.

[0075] In this embodiment, the first type of ions are P-type ions and the second type of ions are N-type ions, that is, P-type ions are doped in the middle substrate layer 160 with a first dose, and N-type ions are doped in the first well region 121 in the B-well region structure 120b with a second dose, so that the first dose is greater than the second dose, which can avoid excessive injection dose of the first well region 121, thereby causing the diffusion length of the first well region 121 to be too long, and avoid the N-type ions in the first well region 121 from "eroding" the P-type ions in the middle substrate layer 160, which can improve the reliability of the junction field effect transistor 10 to a certain extent.

[0076] In this example, see Figure 3 The depth of the trench 1213 on the first well region 121 in the A-well region structure 120 a is smaller than the depth of the trench 1213 on the first well region 121 in the B-well region structure 120 b .

[0077] The A-well region structure 120a is located at the top layer. There is no need to set up an intermediate substrate layer 160 for the groove 1213 on the first well region 121 in the A-well region structure 120a. Based on the structural optimization design, the groove depth of the groove 1213 on the first well region 121 can be made smaller, which can reduce the occupied volume of the junction field effect transistor 10 to a certain extent.

[0078] In some embodiments, in two adjacent well structures 120, the second well region 122 of one well structure 120 is doped with the first type of ions at a third dose, and the second well region 122 of the other well structure 120 is doped with the first type of ions at a fourth dose. The third dose and the fourth dose are both set according to the first dose, so that the two second well regions 122 on the same side of the two adjacent well structures 120 are connected via the intermediate substrate layer 160. The second well regions 122 can be formed using an ion implantation process, and the third dose and the fourth dose are set according to the first dose. It is understood that the relative volume ratio of the two second well regions 122 on the same side of the two adjacent well structures 120 can be controlled so that the two second well regions 122 on the same side of the two adjacent well structures 120 are connected via the intermediate substrate layer 160, thereby avoiding the formation of a fault between the two adjacent well structures 120 that affects the conductivity of the junction field effect transistor 10.

[0079] Optionally, the number of injections corresponding to the two second well regions 122 on the same side of two adjacent well region structures 120 may also be set to better avoid a fault between the two adjacent well region structures 120 .

[0080] See also Figure 5 The present invention provides a method for preparing a junction field effect transistor, comprising the following steps:

[0081] S210: Provide a substrate 110 of a first conductivity type. The substrate 110 may be a silicon wafer substrate.

[0082] S220. At least two layers of well region structures 120 are stacked on the substrate 110, each well region structure 120 includes a first well region 121 of the second conductivity type, and two second well regions 122 located on opposite sides of the first well region 121; wherein the conductivity type of the second well region 122 is opposite to the second conductivity type and the same as the first conductivity type.

[0083] S230 , forming a drain 130 and a source 140 on opposite sides of the first well region 121 of the uppermost well region structure 120 .

[0084] S240 , forming a gate 150 on the two second well regions 122 of the uppermost well region structure 120 .

[0085] In the adjacent two-layer well region structure 120 , two adjacent first well regions 121 are in contact with each other, and two second well regions 122 on the same side are connected to each other.

[0086] In the above example, when a negative bias is applied to the gate 150 relative to the source 140, the PN junction depletion layer formed by the first well region 121 (N-type) and the second well region 122 (P-type) in each layer of the well region structure 120 is widened, thereby compressing the N-type conductive channel, thereby turning off the junction field effect transistor 10. It can be understood that in the above-mentioned junction field effect transistor 10, the provision of at least two layers of well region structures 120 is equivalent to increasing the length of the conductive channel of the junction field effect transistor 10, thereby increasing the effective conductive area of ​​the junction field effect transistor 10, and effectively improving the conductivity of the junction field effect transistor 10. In other words, while achieving the same conductivity, the structural design of the junction field effect transistor 10 of the present application can save design size.

[0087] It should be noted that there is no restriction on the order of the above S210, S220, S230, and S240, that is, any one of them can be executed before or at the same time.

[0088] In some embodiments, see Figure 3 Before step S220 of forming at least two stacked well region structures 120 on the substrate 110, the preparation method further includes:

[0089] forming a buried layer 181 of a first conductivity type on the substrate 110;

[0090] An epitaxial layer 182 of the first conductivity type is epitaxially formed on the buried layer 181 .

[0091] The thickness of epitaxial layer 182 is 2 to 10 microns. If the thickness of epitaxial layer 182 exceeds 1 micron, it will be difficult for ions to penetrate epitaxial layer 182 when forming at least two stacked well region structures 120 on epitaxial layer 182 through ion implantation. If the thickness of epitaxial layer 182 is less than 1 micron, it will be difficult to be compatible with other EPI-BCD processes. Therefore, setting the thickness of epitaxial layer 182 to 2 to 10 microns can not only improve the reliability of junction field effect transistor 10, but also ensure that the preparation method of junction field effect transistor 10 of the present application is compatible with other EPI-BCD processes.

[0092] In some embodiments, a method for preparing the junction field effect transistor 10 includes the following steps:

[0093] S301: Provide a substrate 110 of a first conductivity type. The substrate 110 may be a silicon wafer substrate.

[0094] S302 , performing high-temperature well driving and P-type ion implantation on the substrate 110 to form a buried layer 181 .

[0095] S303 , forming an epitaxial layer 182 on the buried layer 181 by epitaxial growth.

[0096] S304: Active regions are formed on the substrate 110 by exposure (masking) and / or etching processes to form at least two stacked well region structures 120 on the epitaxial layer 182. The active regions include a first active region corresponding to the drain 130 and a second active region corresponding to the source 140.

[0097] S305. Masking and ion implantation are performed on epitaxial layer 182 through the active region to form a B-well region structure 120b on epitaxial layer 182. B-well region structure 120b includes a first well region 121 (a first N-type ion implantation layer) and second well regions 122 (a first P-type ion implantation layer) located on opposite sides of first well region 121. Specifically, first well region 121 may be an N-type ion implantation layer 1, and second well region 122 may be a P-type ion implantation layer 1.

[0098] S306 , performing P-type ion implantation in the trench 1213 on the first well region 121 in the B-well region structure 120 b to form an intermediate substrate layer 160 in the trench 1213 .

[0099] S307. Masking and ion implantation are performed on the intermediate substrate layer 160 to form an A-well region structure 120a on the intermediate substrate layer 160, wherein the A-well region structure 120a includes a first well region 121 and a second well region 122 located on opposite sides of the first well region 121. Specifically, the first well region 121 can be a second N-type ion implantation layer, and the second well region 122 can be a second P-type ion implantation layer.

[0100] S308. A shallow trench isolation (STI) process is performed at the trench 1213 on the first well region 121 in the A-well region structure 120a to form a shallow trench isolation structure 170 at the trench 1213, a gate 150 of a polysilicon structure is formed on the shallow trench isolation structure 170, and gate contact holes are respectively formed in the two second well regions 122 in the A-well region structure 120a. A gate connection layer 153 connected to the gate electrode layer 152 of the gate 150 is formed on the gate contact hole, so that the gate 150 is formed in the two second well regions 122 of the A-well region structure 120a.

[0101] S309: Growing a dielectric ILD layer on the active area to form a drain 130 or a source 140 on the dielectric ILD layer. Specifically, dielectric ILD layers may be grown on the first active area and the second active area, respectively, to form the drain 130 on the dielectric ILD layer in the first active area and the source 140 on the dielectric ILD layer in the second active area. The first active area and the second active area correspond to the two first drift regions 1212 of the first well region 121 in the A-well region structure 120a.

[0102] S310 , forming a drain contact hole on the growth medium ILD layer in the first active region, and forming a source contact hole on the growth medium ILD layer in the second active region.

[0103] S311. The drain connection layer 131 may be inserted into the drain contact hole, and the drain electrode layer 132 may be connected to the end of the drain connection layer 131 away from the drain contact hole to form the drain 130. The source connection layer 141 may be inserted into the source contact hole, and the source electrode layer 142 may be connected to the end of the source connection layer 141 away from the source contact hole to form the source 140. In this way, the drain electrode layer 132 of the drain 130 and the source electrode layer 142 of the source 140 may be used as the current input and output of the junction field effect transistor 10, respectively, so that the current input from the drain 130 (positive electrode) can generate a saturation current between the drain 130 (positive electrode) and the source 140 (negative electrode) under the conductive action of the first well region 121 (N-type), so that the junction field effect transistor 10 is turned on.

[0104] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A junction field effect transistor, characterized in that include: A substrate (110) of a first conductivity type; At least two layers of well region structures (120), stacked on the substrate (110) along the thickness direction of the substrate (110); each layer of the well region structure (120) includes a first well region (121) of a second conductivity type, and two second well regions (122) located on opposite sides of the first well region (121) along the first direction; wherein the conductivity type of the second well region (122) is opposite to the second conductivity type and the same as the first conductivity type; A drain (130) and a source (140) are respectively formed on opposite sides of the first well region (121) of the uppermost well region structure (120) along a second direction, wherein the first direction and the second direction intersect and both intersect with the thickness direction of the substrate (110); and A gate (150) formed on the two second well regions (122) of the uppermost well region structure (120); Among them, in two adjacent layers of the well region structure (120), two adjacent first well regions (121) are in contact with each other, and two second well regions (122) on the same side are connected to each other.

2. The junction field effect transistor according to claim 1, wherein The first well region (121) comprises a channel region (1211) and two drift regions (1212) located on opposite sides of the channel region (1211); a trench (1213) located between the drain (130) and the source (140) is formed on the channel region (1211); The at least two layers of the well region structures (120) include an A-well region structure (120a) located at the uppermost layer and at least one layer of B-well region structure (120b) located below the A-well region structure (120a) along the stacking direction of the well region structure (120); The drain (130) and the source (140) are respectively formed in the two drift regions (1212) of the first well region (121) in the A-well region structure (120a).

3. The junction field effect transistor according to claim 2, wherein: In the A-well region structure (120a), a shallow trench isolation structure (170) is provided in the trench (1213) on the first well region (121) to isolate the drain (130) and the source (140) from each other.

4. The junction field effect transistor according to claim 3, wherein The longitudinal ends of the shallow trench isolation structure (170) extend toward opposite sides and respectively contact the two second well regions (122) in the A-well region structure (120a) to isolate the two second well regions (122) from each other.

5. The junction field effect transistor according to claim 3, wherein The gate (150) comprises: A polysilicon layer (151) is disposed on the shallow trench isolation structure (170); A gate electrode layer (152) is provided on a side of the polysilicon layer (151) away from the shallow trench isolation structure (170); A gate connection layer (153) is formed in the two second well regions (122) of the A well region structure (120a), and the gate connection layer (153) is in contact with the gate electrode layer (152).

6. The junction field effect transistor according to claim 2, wherein: Also included is an intermediate substrate layer (160) of a first conductivity type; The intermediate substrate layer (160) is formed in the groove (1213) on the first well region (121) in the B well region structure (120b), and opposite ends of the intermediate substrate layer (160) extend outside the groove (1213) so as to be inserted between two second well regions (122) on the same side of two adjacent layers of the well region structures (120).

7. The junction field effect transistor according to claim 6, wherein: The intermediate substrate layer (160) is doped with first-type ions at a first dose, and the first well region (121) in the B-well region structure (120b) is doped with second-type ions at a second dose; Wherein, the first dose is greater than the second dose.

8. The junction field effect transistor according to claim 7, wherein: In two adjacent well region structures (120), the second well region (122) of one of the well region structures (120) is doped with first type ions at a third dose, and the second well region (122) of the other well region structure (120) is doped with first type ions at a fourth dose; The third dose and the fourth dose are both set according to the first dose, so that the two second well regions (122) on the same side of two adjacent well region structures (120) are connected by means of the intermediate substrate layer (160).

9. A method for preparing a junction field effect transistor, characterized in that: The steps include: providing a substrate (110) of a first conductivity type; At least two layers of well region structures (120) are stacked and formed on the substrate (110) along the thickness direction of the substrate (110), each of the well region structures (120) comprising a first well region (121) of a second conductivity type, and two second well regions (122) located on opposite sides of the first well region (121) along the first direction; wherein the conductivity type of the second well region (122) is opposite to the second conductivity type and is the same as the first conductivity type; A drain (130) and a source (140) are formed on opposite sides of the first well region (121) of the uppermost well region structure (120) along a second direction; the first direction and the second direction intersect and both intersect with the thickness direction of the substrate (110); forming a gate (150) on the two second well regions (122) of the uppermost well region structure (120); Among them, in two adjacent layers of the well region structure (120), two adjacent first well regions (121) are in contact with each other, and two second well regions (122) on the same side are connected to each other.

10. The method for preparing a junction field effect transistor according to claim 9, wherein: Before forming at least two stacked well region structures (120) on the substrate (110), the preparation method further comprises: forming a buried layer (181) of a first conductivity type on the substrate (110); forming an epitaxial layer (182) of a first conductivity type on the buried layer (181) by epitaxial growth; Wherein, the thickness of the epitaxial layer (182) is 2 to 10 microns.

11. The method for preparing a junction field effect transistor according to claim 10, wherein: The at least two layers of the well region structures (120) include an A well region structure (120a) located at the top layer and at least one layer of B well region structure (120b) located below the A well region structure (120a) along the stacking direction of the well region structure (120), and the at least two layers of well region structures (120) stacked and formed on the substrate (110) specifically include: forming an active region on the substrate (110); Masking and ion implantation are performed on the epitaxial layer (182) through the active region to form the B-well region structure (120b) on the epitaxial layer (182); forming an intermediate substrate layer (160) at the groove (1213) on the first well region (121) in the B-well region structure (120b); Masking and ion implantation are performed on the intermediate substrate layer (160) to form the A-well region structure (120a) on the intermediate substrate layer (160).

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