A vertical series-connected structure high-voltage chip and its manufacturing method

Abstract

The present invention provides a vertical series-connected structure high-voltage chip and a manufacturing method thereof. The method includes: growing a plurality of epitaxial wafers each having a highly doped layer at the PN region, where the highly doped layer close to the substrate in the epitaxial wafer is the first highly doped layer, and the highly doped layer far from the substrate is the second highly doped layer; temporarily bonding the second highly doped layer in the epitaxial wafer to a silicon wafer; removing the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed; performing plasma bombardment activation on one of the epitaxial wafers after substrate removal and another epitaxial wafer, and relatively fitting the first highly doped layer in the epitaxial wafer after substrate removal to the second highly doped layer in another epitaxial wafer, and putting them into a bonding machine for bonding; releasing the temporary bonding of the bonded epitaxial wafer; performing a chip manufacturing process on the epitaxial wafer after releasing the temporary bonding until the high-voltage chip is manufactured. The present invention solves the problem of high process requirements for existing high-voltage chips.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technologies, and particularly to a high-voltage chip with a vertical series structure and a manufacturing method thereof. Background Art

[0002] In the LED chip industry, high-voltage chips are a new variety. A relatively common method is to connect packaged low-power LED chips in series, or to perform series integration during the manufacturing of LED chips.

[0003] High-voltage chips formed by connecting chips at the packaging end are relatively large in size. High-voltage chips with series integration at the LED chip end use small chips to achieve the function of high-voltage chips by laterally connecting each electrode. However, this method has high requirements for the grooving process, connecting electrodes, and insulation effect at the chip end. At the same time, there is a problem that the recombination efficiency of existing laterally connected high-voltage chips is slightly low. Summary of the Invention

[0004] Based on this, an object of the present invention is to provide a high-voltage chip with a vertical series structure and a manufacturing method thereof, so as to fundamentally solve the problem of high process requirements for existing high-voltage chips.

[0005] According to an embodiment of the present invention, a manufacturing method of a high-voltage chip with a vertical series structure includes:

[0006] Growing a plurality of epitaxial wafers each having a highly doped layer at the PN region, where the highly doped layer close to the substrate in the epitaxial wafer is the first highly doped layer, and the highly doped layer far from the substrate is the second highly doped layer;

[0007] Temporarily bonding the second highly doped layer in the epitaxial wafer to a silicon wafer;

[0008] Removing the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed;

[0009] Performing plasma bombardment activation on one epitaxial wafer after removing the substrate and another epitaxial wafer, and relatively bonding the first highly doped layer in the epitaxial wafer after removing the substrate to the second highly doped layer in another epitaxial wafer, and putting them into a bonding machine for bonding;

[0010] Releasing the temporary bonding of the bonded epitaxial wafer;

[0011] Performing chip manufacturing processes on the epitaxial wafer after releasing the temporary bonding until a high-voltage chip is manufactured and completed.

[0012] In addition, according to the manufacturing method of a high-voltage chip with a vertical series structure in the above embodiment of the present invention, it may further have the following additional technical features:

[0013] Further, before the step of performing chip manufacturing processes on the epitaxial wafer after releasing the temporary bonding, at least one of the following steps is further performed:

[0014] Ion bombardment activation is performed on the epitaxial wafer after removing another substrate and the epitaxial wafer after releasing the temporary bonding, and the first high-doped layer in the epitaxial wafer after removing the substrate is relatively bonded to the second high-doped layer in the epitaxial wafer after releasing the temporary bonding, and then it is placed in a bonding machine for re-bonding;

[0015] Release the temporary bonding of the epitaxial wafer after re-bonding.

[0016] Further, before the step of releasing the temporary bonding of the bonded epitaxial wafer, at least one of the following steps is also performed:

[0017] Remove the substrate in the bonded epitaxial wafer until the first high-doped layer is exposed;

[0018] Perform plasma bombardment activation on the epitaxial wafer after bonding and removing the substrate and another epitaxial wafer, and the first high-doped layer in the epitaxial wafer after bonding and removing the substrate is relatively bonded to the second high-doped layer in another epitaxial wafer, and then it is placed in a bonding machine for bonding.

[0019] Further, the step of temporarily bonding the second high-doped layer in the epitaxial wafer to the silicon wafer includes:

[0020] Apply wax on the surface of the second high-doped layer in the epitaxial wafer and / or the surface of the silicon wafer;

[0021] Align the epitaxial wafer and the silicon wafer and place them in a temporary bonding machine for pressure bonding, where the bonding pressure is 3000 kgf to 6000 kgf, and the temporary bonding temperature is determined according to the hot melt flow point temperature of the wax used.

[0022] Further, the step of performing plasma bombardment activation on the epitaxial wafer after removing one substrate and another epitaxial wafer includes:

[0023] Use a plasma cleaner to perform plasma bombardment activation on the epitaxial wafer after removing the substrate and another epitaxial wafer, where the bombarding ions are Ar ions and the bombardment time is 5 to 20 min;

[0024] Among them, the bonding pressure for bonding the first high-doped layer in the epitaxial wafer after removing the substrate and the second high-doped layer in another epitaxial wafer is 12000 kgf, the bonding time is 60 to 120 min, and the bonding temperature is determined according to the temperature at which the wax used does not have hot melt flow.

[0025] Further, the doping concentrations of the first high-doped layer and the second high-doped layer in the grown epitaxial wafer are both greater than 1e19, and the thickness reaches 5000 Å.

[0026] Further, after the step of growing multiple epitaxial wafers each having a high-doped layer at the PN region, the following is also included:

[0027] The epitaxial wafer is organically cleaned to remove surface impurities and dirt;

[0028] The second highly doped layer in the epitaxial wafer after organic cleaning is polished to a thickness greater than or equal to 50 Å and less than or equal to 100 Å.

[0029] Further, the step of removing the substrate in the epitaxial wafer after temporary bonding until the first highly doped layer is exposed includes:

[0030] The substrate in the epitaxial wafer after temporary bonding is removed;

[0031] The first highly doped layer exposed in the epitaxial wafer after substrate removal is polished to a thickness greater than or equal to 50 Å and less than or equal to 100 Å.

[0032] A vertical series structure high-voltage chip according to an embodiment of the present invention includes:

[0033] A GaAs substrate, a buffer layer, a cutoff layer, and an epitaxial structure stacked at least twice repeatedly on the GaAs substrate;

[0034] The epitaxial structure includes a highly doped N-type contact layer, an N-type transition layer, an N-type current spreading layer, an N-type confinement layer, an N-type blocking layer, a multi-quantum well layer, a P-type blocking layer, a P-type confinement layer, a P-type transition layer, and a highly doped P-type current spreading layer stacked in sequence.

[0035] In addition, a vertical series structure high-voltage chip according to the above embodiment of the present invention may further have the following additional technical features:

[0036] The buffer layer is a GaAs layer, the cutoff layer is a GaInP layer, the highly doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current spreading layer is an AlGaInP layer, the N-type confinement layer is an AlInP layer, the N-type blocking layer is an AlGaInP layer, the P-type blocking layer is an AlGaInP layer, the P-type confinement layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the highly doped P-type current spreading layer is a GaP layer;

[0037] The doping concentrations of the highly doped N-type contact layer and the highly doped P-type current spreading layer are both greater than 1e19, and the thicknesses are both greater than or equal to 50 Å and less than or equal to 100 Å.

[0038] Compared with the prior art: By adopting temporary bonding, the epitaxial layer can be transferred onto the silicon wafer, preventing the epitaxial layer from cracking and facilitating the next bonding process; by means of vertical bonding, multiple epitaxial wafers can be connected in series in the vertical direction, thereby forming a high-voltage chip with a vertical structure, greatly reducing the chip area and solving the existing difficulties in grooving the chip, growing the insulating layer, and fabricating the connecting electrodes, thus solving the problem of high process requirements for existing high-voltage chips. At the same time, by performing high doping treatment on the PN regions of the epitaxial wafers, a tunneling junction can be formed after the epitaxial wafers are bonded, enabling carriers to migrate longitudinally through the tunneling effect, improving the chip recombination efficiency, and solving the problem of slightly lower recombination efficiency of high-voltage chips with a lateral series structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of the method for fabricating a high-voltage chip with a vertical series structure in the first embodiment of the present invention;

[0040] Figure 2 It is a flowchart of the method for fabricating a high-voltage chip with a vertical series structure in the second embodiment of the present invention;

[0041] Figure 3 It is a flowchart of the method for fabricating a high-voltage chip with a vertical series structure in the third embodiment of the present invention;

[0042] Figure 4 It is a schematic structural diagram of a high-voltage chip with a vertical series structure in the fourth embodiment of the present invention;

[0043] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. SPECIFIC EMBODIMENTS

[0044] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0045] It should be noted that when an element is referred to as being "fixedly provided on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0047] Embodiment 1

[0048] Please refer to Figure 1 , which shows the method for fabricating a vertical series-connected structure high-voltage chip in the first embodiment of the present invention. The method specifically includes steps S01 to S05.

[0049] Step S01: Grow a plurality of epitaxial wafers each having a highly doped layer at the PN region, where the highly doped layer close to the substrate in the epitaxial wafer is the first highly doped layer, and the highly doped layer far from the substrate is the second highly doped layer.

[0050] Among them, in one embodiment of the present invention, the epitaxial wafer can be an ordinary epitaxial wafer in the prior art, which only requires high doping treatment for both the P layer and the N layer in the epitaxial wafer. At this time, it is required that the doping concentration in the highly doped film layer is greater than 1e19, and the thickness reaches about 5000 Å (angstrom, 1 Å = 10^-10 m).

[0051] Specifically, in one example of the present invention, taking a red-yellow GaAs (gallium arsenide) epitaxial wafer as an example, the growth process of the red-yellow GaAs epitaxial wafer is shown. First, a double-sided polished N-type GaAs single crystal wafer is used as the substrate, and then MOCVD (Metal-organic Chemical Vapor Deposition) is used to sequentially deposit and grow a GaAs buffer layer, a GaInP (indium gallium phosphide) cutoff layer, an N-type GaAs contact layer, an N-type GaInP transition layer, an N-type AlGaInP (aluminum indium gallium phosphide) current spreading layer, an N-type AlInP (aluminum indium phosphide) confinement layer, an N-type AlGaInP blocking layer, an MQW multi-quantum well layer, a P-type AlGaInP blocking layer, a P-type AlInP confinement layer, a P-type AlGaInP transition layer, and a P-type GaP (gallium phosphide) extended current layer on the upper surface of the GaAs substrate, and finally the red-yellow GaAs epitaxial wafer is grown.

[0052] Specifically, during the growth of the epitaxial wafer, high doping treatment is performed on both the P layer and the N layer, that is, both its N-type GaAs contact layer and P-type GaP extended current layer are highly doped or heavily doped, while the doping concentrations of the existing ordinary-doped N-type GaAs contact layer and P-type GaP extended current layer are generally around 1e15 to 1e18. Therefore, when the grown epitaxial wafer is a GaAs epitaxial wafer, the first highly doped layer close to the substrate is the N-type GaAs contact layer (i.e., the GaAs layer), and the second highly doped layer far from the substrate is the P-type GaP extended current layer (i.e., the GaP layer).

[0053] It should be noted that in other examples of the present invention, the specific structure in the epitaxial wafer can have more or fewer or different-order or different material-component film layers compared to this example, which is set according to actual usage needs and is not specifically limited here. However, the structure of the epitaxial wafer can always be generally simplified to a substrate, an N-type highly doped layer, an N layer, an MQW multi-quantum well layer, a P layer, and a P-type highly doped layer. At this time, the N-type highly doped layer is the GaAs layer, and the P-type highly doped layer is the GaP layer.

[0054] It can be understood that in other embodiments of the present invention, other types of substrates can also be used to generate corresponding epitaxial wafers, such as GaN (gallium nitride) epitaxial wafers; other types of substrates can also be used, such as P-type substrates, so that a structure of a P-type highly doped layer, a P layer, an MQW multi-quantum well layer, an N layer, and an N-type highly doped layer is grown on the P-type substrate. At this time, the first highly doped layer close to the substrate is the P-type highly doped layer, and the second highly doped layer far from the substrate is the N-type highly doped layer. Therefore, in the embodiments of the present invention, the specific types and kinds of the first highly doped layer and the second highly doped layer are not clearly specified, and are determined according to the actual usage and production requirements in accordance with the positional relationship with the substrate, and are not limited here.

[0055] Furthermore, during the doping process, the N layer is usually doped with doping impurities containing Si (silicon) or C (carbon) elements, and the P layer is usually doped with doping impurities containing Mg (magnesium) or Zn (zinc) elements. Specifically, for example, during the growth of the epitaxy, SiH4 (silane) is introduced for N layer doping, and Cp2Mg (bis(cyclopentadienyl)magnesium, Mg(C5H5)2) is introduced for P layer doping.

[0056] Furthermore, after the step S01, the following steps are also included:

[0057] The epitaxial wafer is organically cleaned to remove surface impurities and dirt;

[0058] The second highly doped layer in the epitaxial wafer after organic cleaning is polished to a thickness greater than or equal to 50 Å and less than or equal to 100 Å.

[0059] Specifically, by performing organic cleaning on the grown epitaxial wafer, the surface impurities and dirt of the epitaxial wafer can be removed, the purity of the surface of the epitaxial wafer can be improved, and at the same time, the second highly doped layer in the epitaxial wafer after organic cleaning is polished until the remaining thickness of the polished second highly doped layer is greater than or equal to 50 Å and less than or equal to 100 Å, so as to not only maintain the purity and flatness of the second highly doped layer, but also provide a suitable thickness dimension for subsequent bonding processes.

[0060] Step S02: Temporarily bond the second highly doped layer in the epitaxial wafer to the silicon wafer.

[0061] Among them, the above-mentioned temporary bonding of the second highly doped layer in the epitaxial wafer to the silicon wafer can be achieved through the following steps:

[0062] Apply wax on the surface of the second highly doped layer in the epitaxial wafer and / or the surface of the silicon wafer;

[0063] Align the epitaxial wafer and the silicon wafer and place them in a temporary bonding machine for pressure bonding, where the bonding pressure is 3000 kgf to 6000 kgf, and the temporary bonding temperature is determined according to the hot melt flow point temperature of the wax used.

[0064] Specifically, apply high-temperature wax on the surface of the silicon wafer or the epitaxial wafer, or apply high-temperature wax on both wafers. Further, align the silicon wafer and the epitaxial wafer and place them in a temporary bonding machine for pressure bonding. The temperature is mainly based on the flow point of the temporary bonding wax used. It should be noted that the high-temperature wax can withstand a certain degree of temperature. For example, when the flow point temperature of the high-temperature wax is 270 °C, the temporary bonding temperature can be set to 250 - 260 °C, and the pressure is 3000 kgf to 6000 kgf (kilogram-force). At this time, the epitaxial wafer and the silicon wafer are temporarily bonded through the high-temperature wax.

[0065] It should be noted that since the epitaxial layer after removing the substrate of the epitaxial wafer is very thin, generally only a few microns or a dozen microns, when the substrate is removed, the epitaxial layer cannot effectively exist alone and is easily broken. At this time, the temporary bonding of the epitaxial wafer to the silicon wafer through high-temperature wax enables the epitaxial layer to be effectively carried on the silicon wafer (or the epitaxial layer is supported by the silicon wafer). Therefore, by transferring the epitaxial layer to the silicon wafer, the epitaxial layer can be prevented from breaking, so that subsequent processes such as substrate removal and bonding can be conveniently and effectively carried out.

[0066] Step S03: Remove the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed.

[0067] Among them, since the epitaxial wafer and the silicon wafer are temporarily bonded by high-temperature wax, at this time, the substrate in the epitaxial wafer after temporary bonding in step S02 can be effectively removed. The substrate is usually removed by using ammonia water and hydrogen peroxide. As described above, there may still be a buffer layer and a cutoff layer between the substrate and the first highly doped layer. Therefore, it is necessary to remove the substrate until the first highly doped layer is exposed, that is, it is also necessary to remove the buffer layer and the cutoff layer to expose the first highly doped layer.

[0068] Specifically, the above step S03 further specifically includes:

[0069] Removing the substrate in the epitaxial wafer after temporary bonding;

[0070] Polishing the first highly doped layer exposed in the epitaxial wafer after substrate removal to a thickness greater than or equal to 50 Å and less than or equal to 100 Å.

[0071] That is to say, after removing the substrate in the epitaxial wafer after temporary bonding until the first highly doped layer is exposed, the exposed first highly doped layer is polished until the remaining thickness of the first highly doped layer is greater than or equal to 50 Å and less than or equal to 100 Å, so as to not only maintain the purity and flatness of the first highly doped layer, but also provide a suitable thickness dimension for subsequent bonding processing.

[0072] Step S04, performing plasma bombardment activation on one of the epitaxial wafers after substrate removal and another epitaxial wafer, and relatively fitting the first highly doped layer in the epitaxial wafer after substrate removal with the second highly doped layer in the other epitaxial wafer, and putting them into a bonding machine for bonding.

[0073] Among them, bonding refers to a technology in which two pieces of clean-surface, atomically flat homogeneous or heterogeneous semiconductor materials are directly bonded under certain conditions after surface cleaning and activation treatment, and the wafers are bonded into one body through van der Waals forces, molecular forces or even atomic forces.

[0074] Among them, in an embodiment of the present invention, the above-mentioned performing plasma bombardment activation on one of the epitaxial wafers after substrate removal and another epitaxial wafer specifically includes: using a plasma cleaner to perform plasma bombardment activation on the epitaxial wafer after substrate removal and another epitaxial wafer, where the bombarding ions are Ar ions and the bombardment time is 5 - 20 min.

[0075] Among them, the bonding pressure for bonding the first highly doped layer in the epitaxial wafer after substrate removal with the second highly doped layer in the other epitaxial wafer is 12000 kgf, the bonding time is 60 - 120 min, and the bonding temperature is determined according to the temperature at which the used wax will not melt and flow.

[0076] Specifically, a plasma cleaner is used to perform plasma bombardment activation on the epitaxial wafer after the substrate obtained in step S03 is removed and the epitaxial wafer after polishing the second highly doped layer in step S01. At this time, Ar ions bombard the two epitaxial wafers for 5-20 minutes to achieve the activation treatment. Then, the first highly doped layer in the epitaxial wafer after the substrate obtained in step S03 is removed is relatively bonded to the second highly doped layer in the epitaxial wafer after polishing the second highly doped layer in step S01 and placed in a bonding machine for bonding. At this time, the bonding temperature needs to be controlled within the temperature range where the high-temperature wax will not melt and flow to cause debonding. For example, the flow point temperature of the high-temperature wax mentioned above is 270 °C, so the bonding temperature can be set at 200 °C, the pressure is 12000 kgf, and the time is 60-120 minutes. Therefore, the high-temperature wax always remains in a solid state and still maintains the temporary bonding with the silicon wafer, so that the problem of debonding between the epitaxial wafer and the silicon wafer caused by excessive bonding temperature will not occur.

[0077] At this time, after the epitaxial wafer after the substrate is removed in the embodiment of the present invention is bonded to another epitaxial wafer, the bonding forms a structure similar to a PN junction. Specifically, the N-layer structure of the epitaxial wafer after the substrate of the first highly doped layer (such as the GaAs layer in the example) is removed, and the P-layer structure of the other epitaxial wafer of the second highly doped layer (such as the GaP layer in the example). The GaAs layer in the N layer is connected to the GaP layer in the P layer, and together with the original N-layer structure and P-layer structure, a new PN junction is formed. Therefore, an interband tunneling junction can be formed between the first highly doped layer in the epitaxial wafer after the substrate is removed and the second highly doped layer in the other epitaxial wafer. Among them, interband tunneling means that electrons move from the valence band of the p-type semiconductor layer, pass through the forbidden band, and finally reach the conduction band of the n-type semiconductor layer. At this time, carriers can perform longitudinal migration through the tunneling effect. At the same time, combined with the characteristics of high doping in the embodiment of the present invention, the recombination efficiency can be improved, and the problem of slightly low recombination efficiency of the high-voltage chip with a lateral series structure is solved.

[0078] Step S05: Release the temporary bonding of the bonded epitaxial wafer.

[0079] Among them, after the bonding of the epitaxial wafer in step S04 above is completed, the temperature can be increased accordingly, so that when the temperature reaches the flow point of the high-temperature wax, the high-temperature wax changes from a solid state during temporary bonding to a liquid state, so as to release or disconnect the temporary bonding between the silicon wafer and the epitaxial wafer, and thus separate the epitaxial wafer from the silicon wafer, thereby completing the vertical series process between the two epitaxial wafers.

[0080] Step S06: Perform chip manufacturing processes on the epitaxial wafer after the temporary bonding is released until the high-voltage chip is manufactured and completed.

[0081] Among them, in the embodiment of the present invention, the series connection process of the vertical series structure epitaxial wafer is completed, and the normal chip manufacturing process can be continued until the chip end is completed to obtain a high-voltage core. At this time, the epitaxial wafer is processed through substrate removal, photolithography, etching, coating, evaporation, thinning and other processes to produce N electrodes, P electrodes and the like. Among them, it should be pointed out that the main protection point of the embodiment of the present invention is to obtain the "epitaxial wafer" of the vertical series structure through the process of the chip end, and the subsequent process steps of making electrodes and the like are no different from ordinary chip processes, so they are not described in detail. The specific process steps can refer to any existing process steps that can be used for implementation, and are not specifically limited here.

[0082] Therefore, the overall process in the embodiment of the present invention is generally as follows:

[0083] Step a: growing an epitaxial wafer. It is required to perform high doping in the PN region until the doping concentration of the first high-doping layer and the second high-doping layer reaches at least 1e19, and the thickness reaches about 5000A.

[0084] Step b: organically clean the epitaxial wafer to remove surface impurities and dirt, and then polish the second high-doped layer of the epitaxial wafer, so that the remaining thickness of the second high-doped layer after polishing reaches ≤100A and ≥50A.

[0085] Step c: temporarily bonding the second highly doped layer of the polished epitaxial wafer to the silicon wafer using liquid high-temperature wax.

[0086] Step d: removing the substrate of the temporarily bonded epitaxial wafer until the first highly doped layer is exposed, and polishing the exposed first highly doped layer, wherein the remaining thickness of the first highly doped layer after polishing reaches ≤100A and ≥50A.

[0087] Step e, subjecting one of the epitaxial wafers with the substrate removed in step d and the epitaxial wafer polished in step b to plasma bombardment activation, and then placing the first highly doped layer in the epitaxial wafer with the substrate removed and the second highly doped layer in the polished epitaxial wafer relatively together and placing them into a bonding machine for bonding.

[0088] Step f, releasing the temporary bonding of the high temperature wax from the bonded epitaxial wafer, so as to separate the epitaxial wafer from the silicon wafer;

[0089] Step g: subjecting the epitaxial wafer after temporary bonding to the existing chip manufacturing process.

[0090] In summary, in the method for fabricating a high-voltage chip with a vertical series structure in the above embodiments of the present invention, by using temporary bonding, the epitaxial layer can be transferred onto the silicon wafer, preventing the epitaxial layer from cracking and facilitating the next bonding process; through the vertical bonding method, multiple epitaxial wafers can be connected in series in the vertical direction to form a high-voltage chip with a vertical structure, greatly reducing the chip area and solving the existing difficulties in grooving the chip, growing the insulating layer, and fabricating the connecting electrodes, thereby solving the problem of high process requirements for existing high-voltage chips. At the same time, by performing high-doping treatment on the PN regions of the epitaxial wafers, a tunneling junction can be formed after bonding the epitaxial wafers, enabling carriers to migrate longitudinally through the tunneling effect, improving the recombination efficiency of the chip, and solving the problem of slightly lower recombination efficiency of high-voltage chips with a lateral series structure.

[0091] Embodiment 2

[0092] Please refer to Figure 2 , which shows the method for fabricating a high-voltage chip with a vertical series structure in the second embodiment of the present invention. The method specifically includes steps S11 to S18.

[0093] Step S11: Grow multiple epitaxial wafers each having a highly doped layer at the PN region. Among them, the first highly doped layer is closer to the substrate in the epitaxial wafer, and the second highly doped layer is farther from the substrate.

[0094] Step S12: Temporarily bond the second highly doped layer in the epitaxial wafer to the silicon wafer.

[0095] Step S13: Remove the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed.

[0096] Step S14: Perform plasma bombardment activation on one of the epitaxial wafers after removing the substrate and another epitaxial wafer, and bond the first highly doped layer in the epitaxial wafer after removing the substrate to the second highly doped layer in the other epitaxial wafer relatively, and then put them into a bonding machine for bonding.

[0097] Step S15: Release the temporary bonding of the bonded epitaxial wafers.

[0098] Among them, the specific processes of steps S11 - S15 are substantially the same as those in the foregoing embodiments, and can be specifically referred to as described in the foregoing embodiments, and will not be specifically limited herein.

[0099] Step S16: Perform ion bombardment activation on the other epitaxial wafer after removing the substrate and the epitaxial wafer after releasing the temporary bonding, and bond the first highly doped layer in the epitaxial wafer after removing the substrate to the second highly doped layer in the epitaxial wafer after releasing the temporary bonding relatively, and then put them into a bonding machine for re-bonding.

[0100] Among them, since the epitaxial wafer in step S15 exposes the polished second highly doped layer after the temporary bonding is released, and in step S12, multiple epitaxial wafers can be respectively temporarily bonded to the corresponding silicon wafers and the substrate removal in step S13 can be continued. At this time, the epitaxial wafer in step S15 is ion-bombarded and activated with another epitaxial wafer with the substrate removed obtained in step S13, and the re-bonding of the bonding machine is continued, so that a series-connected three-layer epitaxial structure can be bonded.

[0101] Step S17, release the temporary bonding of the re-bonded epitaxial wafer.

[0102] Correspondingly, since the epitaxial wafer removed from the substrate obtained in step S13 is taken in the above step S16, there is still a temporary bonding between the epitaxial wafer and the silicon wafer. Therefore, after the re-bonding in step S16 is completed, the temporary bonding of the re-bonded epitaxial wafer needs to be released.

[0103] It should be noted that the above steps S16 and S17 are executed at least once. That is to say, when the above steps S16 and S17 are only executed once, a series-connected three-layer epitaxial structure is bonded. When steps S16 and S17 are repeatedly executed twice, a series-connected four-layer epitaxial structure is obtained. That is to say, the high-voltage chip produced in the foregoing embodiment is a series-connected double-layer one, while the high-voltage chip produced in this embodiment is a high-voltage chip with at least three layers and not limited to three layers. For example, the specific number of series connections is set according to the required power. For example, for a 5W high-voltage chip, 5 1W epitaxial structures can be connected in series. At this time, five layers need to be vertically connected in series. That is to say, steps S16 and S17 need to be executed three times. It should be noted that it is not that the more the number of vertical series connections, the better. The more the number of vertical series connections, the more likely problems such as low recombination efficiency will occur, and corresponding optimizations need to be made to the epitaxial wafer and chip design. Therefore, the execution times of steps S16 and S17 are set according to the number of series connections required for actual use.

[0104] Step S18, perform chip manufacturing processes on the epitaxial wafer after the temporary bonding is released until the high-voltage chip is manufactured and completed.

[0105] Among them, the specific process of this step S18 is generally the same as that of the foregoing embodiment, and can be specifically referred to as described in the foregoing embodiment, and will not be specifically limited here.

[0106] Therefore, the overall process in the embodiment of the present invention is generally as follows:

[0107] Step a, grow an epitaxial wafer, requiring high doping in the PN region until the doping concentrations of the first highly doped layer and the second highly doped layer both reach at least 1e19, and the thicknesses both reach about 5000A.

[0108] Step b: Perform an organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and then polish the second highly doped layer of the epitaxial wafer. The remaining thickness of the polished second highly doped layer reaches ≤100 Å and ≥50 Å.

[0109] Step c: Use liquid high-temperature wax to temporarily bond the second highly doped layer of the polished epitaxial wafer to the silicon wafer.

[0110] Step d: Remove the substrate of the temporarily bonded epitaxial wafer until the first highly doped layer is exposed, and polish the exposed first highly doped layer. The remaining thickness of the polished first highly doped layer reaches ≤100 Å and ≥50 Å.

[0111] Step e: Plasma bombard and activate the epitaxial wafer with the substrate removed in step d and the polished epitaxial wafer in step b. Then, place the first highly doped layer in the epitaxial wafer with the substrate removed and the second highly doped layer in the polished epitaxial wafer opposite to each other and put them into a bonding machine for bonding.

[0112] Step f: Release the temporary bonding of the high-temperature wax on the bonded epitaxial wafer to separate the epitaxial wafer from the silicon wafer;

[0113] Step g: Plasma bombard and activate the epitaxial wafer with the substrate removed in another step d and the epitaxial wafer with the temporary bonding released in step f, and place the first highly doped layer in the epitaxial wafer after the substrate is removed and the second highly doped layer in the epitaxial wafer after the temporary bonding is released opposite to each other and put them into a bonding machine for re-bonding;

[0114] Step h: Release the temporary bonding of the high-temperature wax on the re-bonded epitaxial wafer to separate the epitaxial wafer from the silicon wafer;

[0115] Step i: Perform the existing chip manufacturing process on the epitaxial wafer after the temporary bonding is released.

[0116] Embodiment III

[0117] Please refer to Figure 3 , which shows the method for manufacturing a vertical series structure high-voltage chip in the third embodiment of the present invention. The method specifically includes steps S21 to S28.

[0118] Step S21: Grow multiple epitaxial wafers each having a highly doped layer at the PN region, where the one closer to the substrate in the epitaxial wafer is the first highly doped layer, and the one farther from the substrate is the second highly doped layer.

[0119] Step S22: Temporarily bond the second highly doped layer in the epitaxial wafer to the silicon wafer.

[0120] Step S23: Remove the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed.

[0121] Step S24: Plasma bombardment activation is performed on the epitaxial wafer after removing one of the substrates and another epitaxial wafer. The first highly doped layer in the epitaxial wafer after substrate removal is relatively bonded to the second highly doped layer in the other epitaxial wafer, and then it is placed in a bonding machine for bonding.

[0122] Among them, the specific processes of steps S11 - S24 are generally the same as those in the foregoing embodiments, and can be specifically referred to as described in the foregoing embodiments, and will not be specifically limited herein.

[0123] Step S25: The substrate in the bonded epitaxial wafer is removed until the first highly doped layer is exposed.

[0124] Among them, in the embodiment of the present invention, since the epitaxial wafer has both bonding and temporary bonding, and at this time it has sufficient thickness to achieve substrate removal, so the substrate in the bonded epitaxial wafer can be removed first to expose its first highly doped layer. At the same time, the first highly doped layer is polished until the remaining thickness of the first highly doped layer is greater than or equal to 50 Å and less than or equal to 100 Å.

[0125] Step S26: Plasma bombardment activation is performed on the epitaxial wafer after bonding and substrate removal and another epitaxial wafer. The first highly doped layer in the epitaxial wafer after bonding and substrate removal is relatively bonded to the second highly doped layer in the other epitaxial wafer, and then it is placed in a bonding machine for bonding.

[0126] Among them, in the embodiment of the present invention, since the substrate in the epitaxial wafer is removed in step S25 to expose the first highly doped layer, at this time, plasma bombardment activation and bonding treatment can be performed on the epitaxial wafer after bonding and substrate removal and another epitaxial wafer polished for the second highly doped layer.

[0127] It should be noted that steps S25 and S26 are executed at least once. That is to say, when steps S25 and S26 are only executed once, a series-connected three-layer epitaxial structure is obtained. When steps S25 and S26 are repeatedly executed twice, a series-connected four-layer epitaxial structure is obtained. That is to say, the high-voltage chip produced in the foregoing embodiment is a series-connected two-layer high-voltage chip, while the high-voltage chip produced in this embodiment is a high-voltage chip with at least three layers and not limited to three layers. For example, the specific number of series connections is set according to the required power. For example, for a 5W high-voltage chip, 5 1W epitaxial structures can be connected in series. At this time, five layers need to be vertically connected in series, that is to say, steps S25 and S26 need to be executed three times. It should be noted that the more the number of vertical series connections is not necessarily better. The more the number of vertical series connections, the more likely problems such as low recombination efficiency will occur, and corresponding optimizations need to be made to the epitaxial wafer and chip design. Therefore, the number of executions of steps S25 and 26 is set according to the actual required number of series connections.

[0128] Step S27: Demount the temporary bonding of the bonded epitaxial wafer.

[0129] Among them, after the required number of layers of epitaxial wafers are connected in series, by controlling the temperature to reach the flow point of the high-temperature wax, the high-temperature wax changes from a solid state during temporary bonding to a liquid state, so as to release or disconnect the temporary bonding between the silicon wafer and the epitaxial wafer. Finally, the temporary bonding with the silicon wafer is released, separating the multiple epitaxial wafers from the silicon wafer, thus completing the vertical series connection process between multiple epitaxial wafers.

[0130] Step S28: Perform chip manufacturing processes on the epitaxial wafer after the temporary bonding is released until a high-voltage chip is manufactured and completed.

[0131] Among them, the specific process of this step S28 is generally the same as that of the foregoing embodiment, and it can be specifically referred to as described in the foregoing embodiment, and no specific limitation is made here.

[0132] Therefore, the overall process in the embodiment of the present invention is generally as follows:

[0133] Step a: Grow an epitaxial wafer, requiring high doping in the PN region until the doping concentrations of the first high-doping layer and the second high-doping layer both reach at least 1e19, and the thicknesses both reach about 5000 Å.

[0134] Step b: Perform organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and then polish the second high-doping layer of the epitaxial wafer. The remaining thickness of the polished second high-doping layer reaches ≤100 Å and ≥50 Å.

[0135] Step c: Use liquid high-temperature wax to temporarily bond the second high-doping layer of the polished epitaxial wafer to the silicon wafer.

[0136] Step d: Remove the substrate of the temporarily bonded epitaxial wafer until the first high-doping layer is exposed, and polish the exposed first high-doping layer. The remaining thickness of the polished first high-doping layer reaches ≤100 Å and ≥50 Å.

[0137] Step e: Perform plasma bombardment activation on the epitaxial wafer with the substrate removed in step d and the epitaxial wafer polished in step b, and then place the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the polished epitaxial wafer opposite to each other and put them into a bonding machine for bonding.

[0138] Step f: Remove the substrate of the bonded epitaxial wafer in step e until the first high-doping layer is exposed, and polish the exposed first high-doping layer. The remaining thickness of the polished first high-doping layer reaches ≤100 Å and ≥50 Å.

[0139] Step g: Plasma bombardment activation is performed on the epitaxial wafer after bonding and substrate removal in step f and the polished epitaxial wafer in step b again. The first highly doped layer in the epitaxial wafer after bonding and substrate removal is relatively attached to the second highly doped layer in the polished epitaxial wafer, and then it is placed in a bonding machine for bonding.

[0140] Step h: The temporary bonding of the high-temperature wax on the bonded epitaxial wafer in step g is released to separate the epitaxial wafer from the silicon wafer.

[0141] Step i: The existing chip manufacturing process is performed on the epitaxial wafer after the temporary bonding is released.

[0142] Example 4

[0143] On the other hand, the present invention also provides a vertical series structure high-voltage chip. Please refer to Figure 4 , which shows the vertical series structure high-voltage chip in the fourth embodiment of the present invention. The vertical series structure high-voltage chip is manufactured according to the manufacturing method in the foregoing method embodiment. The vertical series structure high-voltage chip includes:

[0144] A GaAs substrate 100, a buffer layer 200, a cutoff layer 300, and an epitaxial structure 400 stacked at least twice repeatedly on the GaAs substrate 100.

[0145] The epitaxial structure 400 includes a highly doped N-type contact layer 401, an N-type transition layer 402, an N-type current spreading layer 403, an N-type confinement layer 404, an N-type blocking layer 405, a multi-quantum well layer 406, a P-type blocking layer 407, a P-type confinement layer 408, a P-type transition layer 409, and a highly doped P-type current spreading layer 410 stacked in sequence.

[0146] Among them, in an embodiment of the present invention, the buffer layer 200 is a GaAs layer, the cutoff layer 300 is a GaInP layer, the highly doped N-type contact layer 401 is a GaAs layer, the N-type transition layer 402 is a GaInP layer, the N-type current spreading layer 403 is an AlGaInP layer, the N-type confinement layer 404 is an AlInP layer, the N-type blocking layer 405 is an AlGaInP layer, the P-type blocking layer 407 is an AlGaInP layer, the P-type confinement layer 408 is an AlInP layer, the P-type transition layer 409 is an AlGaInP layer, and the highly doped P-type current spreading layer 410 is a GaP layer; the doping concentrations of the highly doped N-type contact layer 401 and the highly doped P-type current spreading layer 410 are both greater than 1e19, and the thicknesses are both greater than or equal to 50 Å and less than or equal to 100 Å.

[0147] In summary, the vertical series-connected structure high-voltage chip in the above embodiments of the present invention enables multiple epitaxial wafers to be connected in series in the vertical direction by bonding in the vertical direction, thereby forming a high-voltage chip with a vertical structure, greatly reducing the chip area and solving the difficulties of existing chip grooving, insulating layer growth, and connection electrode fabrication, thus solving the problem of high process requirements for existing high-voltage chips. At the same time, by performing high doping treatment on the PN regions of each epitaxial wafer to obtain a highly doped N-type contact layer and a highly doped P-type current spreading layer, a tunneling junction can be formed after the epitaxial wafers are bonded, enabling carriers to migrate longitudinally through the tunneling effect, improving the chip recombination efficiency, and solving the problem of slightly lower recombination efficiency of the lateral series-connected structure high-voltage chip.

[0148] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0149] The above-described embodiments merely represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A method for fabricating a high-voltage chip with a vertical series structure, characterized in that, The method includes: Growing a plurality of epitaxial wafers each having a highly doped layer at the PN region, where the highly doped layer closer to the substrate in the epitaxial wafer is the first highly doped layer, and the highly doped layer away from the substrate is the second highly doped layer; Temporarily bonding the second highly doped layer in the epitaxial wafer to a silicon wafer; Removing the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed; Performing plasma bombardment activation on one of the substrate-removed epitaxial wafers and another epitaxial wafer, and relatively fitting the first highly doped layer in the substrate-removed epitaxial wafer and the second highly doped layer in the other epitaxial wafer, and placing them in a bonding machine for bonding; Releasing the temporary bonding of the bonded epitaxial wafer; Performing a chip manufacturing process on the epitaxial wafer after releasing the temporary bonding until a high-voltage chip is manufactured and completed.

2. The method for fabricating a high-voltage chip with a vertical series structure according to claim 1, wherein Before the step of performing the chip manufacturing process on the epitaxial wafer after releasing the temporary bonding, at least one of the following steps is further performed: Performing ion bombardment activation on the epitaxial wafer after removing another substrate and the epitaxial wafer after releasing the temporary bonding, and relatively fitting the first highly doped layer in the substrate-removed epitaxial wafer and the second highly doped layer in the epitaxial wafer after releasing the temporary bonding, and placing them in a bonding machine for re-bonding; Releasing the temporary bonding of the re-bonded epitaxial wafer.

3. The method for fabricating a high-voltage chip with a vertical series structure according to claim 1, wherein Before the step of releasing the temporary bonding of the bonded epitaxial wafer, at least one of the following steps is further performed: Removing the substrate in the bonded epitaxial wafer until the first highly doped layer is exposed; Performing plasma bombardment activation on the bonded and substrate-removed epitaxial wafer and another epitaxial wafer, and relatively fitting the first highly doped layer in the bonded and substrate-removed epitaxial wafer and the second highly doped layer in the other epitaxial wafer, and placing them in a bonding machine for bonding.

4. The method for fabricating a high-voltage chip with a vertical series structure according to claim 1, wherein The step of temporarily bonding the second highly doped layer in the epitaxial wafer to the silicon wafer includes: Waxing the surface of the second highly doped layer in the epitaxial wafer and / or the surface of the silicon wafer; Aligning the epitaxial wafer and the silicon wafer and placing them in a temporary bonding machine for pressure bonding, where the bonding pressure is 3000 kgf to 6000 kgf, and the temporary bonding temperature is determined according to the hot melt flow point temperature of the wax used.

5. The method for fabricating a high-voltage chip with a vertical series structure according to claim 1, characterized in that, The step of performing plasma bombardment activation on one of the substrate-removed epitaxial wafers and another epitaxial wafer includes: Using a plasma cleaner to perform plasma bombardment activation on the substrate-removed epitaxial wafer and another epitaxial wafer, where the bombarding ion is an Ar ion and the bombardment time is 5 to 20 min; Among them, the bonding pressure for bonding the first highly doped layer in the substrate-removed epitaxial wafer and the second highly doped layer in the other epitaxial wafer is 12000 kgf, the bonding time is 60 to 120 min, and the bonding temperature is determined according to the temperature at which the wax used does not undergo hot melt flow.

6. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein The doping concentrations of the first highly doped layer and the second highly doped layer in the grown epitaxial wafer are both greater than 1e19, and the thickness reaches 5000 Å.

7. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 6, characterized in that After the step of growing a plurality of epitaxial wafers each having a highly doped layer at the PN region, the following is further included: Performing organic cleaning on the epitaxial wafer to remove surface impurities and dirt; Performing polishing treatment on the second highly doped layer in the epitaxial wafer after organic cleaning until the thickness is greater than or equal to 50 Å and less than or equal to 100 Å.

8. The method for fabricating a high-voltage chip with a vertical series structure according to claim 6, wherein The step of removing the substrate in the temporarily bonded epitaxial wafer until the first highly doped layer is exposed includes: Remove the substrate in the epitaxial wafer after temporary bonding; Polish the first highly doped layer exposed in the epitaxial wafer after substrate removal to a thickness greater than or equal to 50 Å and less than or equal to 100 Å.

9. A vertical series-connected high-voltage chip, characterized in that, The vertical series-connected structure high-voltage chip is fabricated by the method for fabricating a vertical series-connected structure high-voltage chip according to any one of claims 1 to 8, and includes: A GaAs substrate, a buffer layer, a cutoff layer, and an epitaxial structure stacked at least twice repeatedly, which are sequentially stacked on the GaAs substrate; The epitaxial structure includes a highly doped N-type contact layer, an N-type transition layer, an N-type current spreading layer, an N-type confinement layer, an N-type blocking layer, a multi-quantum well layer, a P-type blocking layer, a P-type confinement layer, a P-type transition layer, and a highly doped P-type current spreading layer stacked in sequence.

10. The vertical series-connected structure high-voltage chip according to claim 9, wherein The buffer layer is a GaAs layer, the cutoff layer is a GaInP layer, the highly doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current spreading layer is an AlGaInP layer, the N-type confinement layer is an AlInP layer, the N-type blocking layer is an AlGaInP layer, the P-type blocking layer is an AlGaInP layer, the P-type confinement layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the highly doped P-type current spreading layer is a GaP layer; The doping concentrations of the highly doped N-type contact layer and the highly doped P-type current spreading layer are both greater than 1e19, and the thicknesses are both greater than or equal to 50 Å and less than or equal to 100 Å.

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