Current blocking layer, method for preparing current blocking layer and LED chip

Abstract

The present invention provides a current blocking layer, a preparation method of the current blocking layer and an LED chip, wherein the preparation method comprises providing a P-type layer required for growth, and at the same time, using nano-imprinting to make a nano-scale line width mask layer, depositing an insulating film layer on the P-type layer, and performing a masking process on the insulating film layer through the nano-scale line width mask layer to obtain a patterned insulating film layer, processing the non-mask portion in the patterned insulating film layer to a predetermined thickness, and removing the residual glue to obtain a thin-layer patterned insulating film layer, dividing the thin-layer patterned insulating film layer into a working area and a non-working area through a secondary mask, and removing the thin-layer patterned insulating film layer in the non-working area, and at the same time, removing the residual glue in the thin-layer patterned insulating film layer in the working area to obtain the current blocking layer. The present invention can prepare a current blocking layer with a nano-scale line width while ensuring a low production cost.

Description

Technical Field

[0001] The invention relates to the technical field of LEDs, and in particular to a current blocking layer, a method for preparing the current blocking layer, and an LED chip. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor electronic component that can emit light. Due to its small size, high brightness and low energy consumption, it has attracted the attention of more and more researchers.

[0003] Traditional LED chips are usually equipped with a current blocking layer. The existence of the current blocking layer makes most of the injected current flow to the active area outside the electrode, increasing the lateral transport of the current, effectively reducing the proportion of the current directly below the electrode in the total injected current, and also reducing the thermal effect caused by this part of the current, thereby improving the light extraction efficiency of the LED and effectively improving the performance of the LED chip.

[0004] With the development of society, people are pursuing higher and higher performance of LED chips, so they have also put forward new requirements for the current blocking layer, that is, to prepare a current blocking layer with a higher resolution and nanowire width. In order to prepare the current blocking layer, the usual method is to use a coating machine, an exposure machine, and a developing machine to make a photoresist mask pattern, and then produce the pattern through a chemical wet etching process. However, the current blocking layer prepared by this method is too expensive and has a low resolution, and it is impossible to effectively realize product commercialization. Summary of the invention

[0005] Based on this, the purpose of the present invention is to provide a current blocking layer, a method for preparing the current blocking layer and an LED chip, so as to prepare a current blocking layer with a nanometer line width while ensuring a low production cost.

[0006] According to an embodiment of the present invention, a method for preparing a current blocking layer comprises:

[0007] Providing a P-type layer required for growth, and at the same time, using nano-imprinting to make a mask layer with nano-scale line width;

[0008] Depositing an insulating film layer on the P-type layer, and performing a masking process on the insulating film layer through the nanoscale line width mask layer to obtain a patterned insulating film layer;

[0009] Processing the non-mask portion of the patterned insulating film layer to a predetermined thickness and removing the residual adhesive to obtain a thin patterned insulating film layer;

[0010] The thin layer patterned insulating film layer is divided into a working area and a non-working area by a secondary mask, and the thin layer patterned insulating film layer in the non-working area is removed. At the same time, the residual glue in the thin layer patterned insulating film layer in the working area is removed to obtain the current blocking layer.

[0011] Preferably, the step of providing a P-type layer required for growth and simultaneously using nano-imprinting to make a mask layer with a nano-scale line width specifically includes:

[0012] The soft template colloid is made by a mixing machine, the mixing time is 20min to 60min, and the standing time is 4h to 8h;

[0013] Putting the soft template colloid into a soft template making machine to prepare a soft template, wherein the preparation temperature is 100° C. to 150° C., the amount of the colloid is 50 g to 100 g, and the number of degassing is 10 to 50 times;

[0014] The soft template is placed in an imprinting machine to prepare the nanoscale line width mask layer, wherein the conditions are set as a temperature of 40°C to 80°C, a primary pressure of 0.5Kpa to 3Kpa, a secondary pressure of 10Kpa to 20Kpa, a boost position of 30mm to 40mm, an exposure time of 20s to 60s, a speed change position of 10mm to 20mm, an imprinting time of 30s to 120s, and a pattern height of the nanoscale line width mask layer of 20nm to 100nm.

[0015] Preferably, the insulating film layer is deposited to a thickness of 700A to 10000A, and during the deposition process, the film stress is changed by alternating high and low radio frequencies, wherein the radio frequency power is set to 50W to 200W, and the temperature is set to a low temperature of 150°C to 250°C or a high temperature of 300°C to 450°C.

[0016] Preferably, the non-mask portion processing process is a wet or dry etching process.

[0017] Preferably, when removing the residual glue, the residual glue is removed by an organic solvent.

[0018] Preferably, before the step of dividing the thin patterned insulating film layer into a working area and a non-working area through a secondary mask, removing the thin patterned insulating film layer in the non-working area, and removing the residual glue in the thin patterned insulating film layer in the working area to obtain the current blocking layer, the step further includes:

[0019] A photoresist mask is prepared, wherein the photoresist mask is used to protect a partial area of ​​the thin patterned insulating film layer, and the protected area is the working area.

[0020] Preferably, the process for removing the thin patterned insulating film layer in the non-working area is a BOE wet etching process.

[0021] According to a current blocking layer in an embodiment of the present invention, the current blocking layer is prepared by the above-mentioned method for preparing the current blocking layer, and the current blocking layer includes a P-type layer protection portion and a current guiding portion extending outward from a side of the P-type layer protection portion away from the P-type layer, and the current guiding portion is perpendicular to the P-type layer protection portion.

[0022] Preferably, the height of the current guiding portion is 20 nm to 100 nm.

[0023] An LED chip according to an embodiment of the present invention includes the above-mentioned current blocking layer.

[0024] Compared with the prior art: an insulating film layer is deposited on the provided P-type layer, and a nano-scale line width mask layer is made by nano-imprinting, and a mask treatment is performed on the insulating film layer once, and the pattern of the mask layer is copied on the insulating film layer to obtain a patterned insulating film layer, and then the non-mask portion in the patterned insulating film layer is processed to a predetermined thickness, and then a secondary mask treatment is performed, and the obtained thin layer of patterned insulating film layer in the non-working area is removed, and the thin layer of patterned insulating film layer in the retained working area is subjected to residual glue removal treatment, thereby completing the preparation of the nano-scale line width current blocking layer. Specifically, the cost of the conventional current blocking layer with nano-scale line width produced by selecting an exposure machine is extremely expensive, because the exposure machine itself is a high-precision and advanced equipment, while in the present invention, the exposure machine technology is only used in the secondary mask treatment process, which greatly reduces the use time of the exposure machine, thereby ensuring the low-cost production of the nano-scale line width current blocking layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a current blocking layer in Embodiment 1 of the present invention;

[0026] Figure 2 This is a flow chart of a method for preparing a current blocking layer proposed in Embodiment 2 of the present invention;

[0027] Figure 3 This is a rendering of the effect of the mask layer made by nanoimprinting proposed in the second embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0029] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0031] The current blocking layer is an indispensable part of the LED chip. If there is no current blocking layer on the positive electrode of the LED chip, the chip will have uneven current distribution, current crowding effect, electrode burning and other phenomena. Due to the insulation of sapphire, the N electrode and P electrode of the traditional LED are made on the same side of the chip's light-emitting surface, and the current needs to flow horizontally. The problem with this structure is that the conductivity of the Mg-doped P-type GaN layer is much lower than that of the N-type GaN layer. The resistance when the current flows horizontally is high, so that the area with high current density is mainly concentrated below and near the positive electrode, and the current crowding effect occurs around the positive electrode, affecting the uniformity of LED light emission and heat generation, the stability of far-field emission, and the reliability of the LED. The current crowding effect will also cause the LED's internal quantum efficiency to decrease due to excessive current density in some parts of the LED. In addition, the metal electrode is opaque and will absorb part of the light energy. The stronger the light emission of the active area at the bottom of the electrode, the stronger the light absorption effect of the metal electrode will be, which will reduce the light extraction efficiency of the LED.

[0032] Therefore, directly below the P electrode, a transparent conductive film (TCF), also known as a transparent electrode, is mainly applied to the ITO film. An insulating layer medium (such as SiO2) is designed between the P-GaN to act as a current blocking layer (CBL). The current blocking layer can block the current from flowing directly to the bottom of the P electrode, reducing the current density in the active area below and near the P electrode, alleviating the current crowding effect near the P electrode, and more current will diffuse out. The internal quantum efficiency and light output efficiency of the LED will be improved.

[0033] Embodiment 1

[0034] See also Figure 1, shown is a schematic structural diagram of the current blocking layer in Embodiment 1 of the present invention, including a P-type layer protection portion 12 and a current guiding portion 11 extending outward from a side of the P-type layer protection portion 12 away from the P-type layer, and the current guiding portion 11 is perpendicular to the P-type layer protection portion 12.

[0035] Among them, the material of the current blocking layer is SiO2, SiN X 、TiO X , Al2O3 and one or more insulating materials, the P-type layer is a P-type GaN layer, the current blocking layer is deposited before the P-type GaN layer and is located in the middle of the P-type GaN layer. Specifically, the P-type layer protection portion 12 is in contact with the P-type GaN layer, blocking the current from flowing directly to the bottom of the P-type GaN layer, thereby reducing the current density in the active area below and near the P-type GaN layer.

[0036] In the present embodiment, the current guiding part 11 is a plurality of columns arranged in an array, and the height of the columns is 20 nm to 100 nm. It should be noted that the shape of the columns can change the light output angle of the light source and improve the light extraction rate.

[0037] Embodiment 2

[0038] See also Figure 2 and Figure 3 , Figure 2 A method for preparing a current blocking layer proposed in the second embodiment of the present invention is used to prepare the current blocking layer in the first embodiment above. Figure 3 This is a rendering of a mask layer made by nanoimprinting according to the second embodiment of the present invention. The method specifically includes steps S21 to S24, wherein:

[0039] Step S21, providing a P-type layer required for growth, and at the same time, using nano-imprinting to make a mask layer with a nano-scale line width.

[0040] It should be noted that the production of LED chips usually starts with the growth of epitaxial wafers, and generally the epitaxial layer is grown epitaxially on a substrate such as a sapphire substrate. In this embodiment, the nanoscale line width mask layer for preparing the current blocking layer needs to be prepared in advance, and the nanoscale line width mask layer is used after the growth of the P-type GaN layer is completed.

[0041] Specifically, the preparation method of the nanoscale line width mask layer is as follows: first, the colloidal raw material is put into a mixer, and a soft template colloidal is produced by the mixer, wherein the stirring time of the mixer is set to 20min to 60min, and after the stirring is completed, it needs to be left to stand for 4h to 8h before it can be put into the next process, and then 50g to 100g of the soft template colloidal ... ~50 times, finally, the soft template is placed in the imprint machine to prepare a nanoscale line width mask layer, wherein the conditions are set as a temperature of 40°C ~ 80°C, a primary pressure of 0.5Kpa ~ 3Kpa, a secondary pressure of 10Kpa ~ 20Kpa, a boost position of 30mm ~ 40mm, an exposure time of 20s ~ 60s, a speed change position of 10mm ~ 20mm, and an imprint time of 30s ~ 120s, to obtain a nanoscale line width mask layer with a pattern height of 20nm ~ 100nm.

[0042] Step S22 , depositing an insulating film layer on the P-type layer, and performing a masking process on the insulating film layer through the nanoscale line width mask layer to obtain a patterned insulating film layer.

[0043] In this embodiment, a PECVD (plasma enhanced chemical vapor deposition) device is used to deposit an insulating film layer of 700A to 10000A on the P-type layer, wherein the insulating film layer material is SiO2, SiN X 、TiO X , Al2O3 and other one or more insulating materials. During the deposition process, the film stress is changed by the alternating use of high and low radio frequencies. Specifically, the radio frequency power is set to 50W~200W, and the temperature is set to a low temperature of 150℃~250℃ or a high temperature of 300℃~450℃.

[0044] In addition, the insulating film layer is masked once by using the prefabricated nanometer-scale line width mask layer, and the pattern of the nanometer-scale line width mask layer is copied onto the insulating film layer, so that the insulating film layer has a morphology, that is, a patterned insulating film layer.

[0045] Step S23 , processing the non-mask portion of the patterned insulating film layer to a predetermined thickness, and removing the residual adhesive to obtain a thin patterned insulating film layer.

[0046] It should be noted that in order to make the columnar shape of the current blocking layer more ideal, the non-mask portion, that is, the non-columnar area, needs to be processed, that is, a wet or dry etching process is used to partially etch it so that a pattern is made, wherein there needs to be a residue at the bottom of the patterned insulating film layer to protect the P-type GaN layer. If a wet etching process is used to etch the non-mask portion, the corrosion rate of the solution on the patterned insulating film layer must be tested first to ensure that the ideal thickness of the bottom of the patterned insulating film layer is etched. If a dry etching process is used to etch the non-mask portion, the dry etching rate also needs to be determined in order to subsequently locate the stopping point of the residual patterned insulating film thickness.

[0047] In addition, after etching is completed, it is necessary to use EKC solvent or SPM solvent to remove the remaining photoresist to obtain a thin patterned insulating film layer.

[0048] In step S24, the thin layer patterned insulating film is divided into a working area and a non-working area through a secondary mask, and the thin layer patterned insulating film in the non-working area is removed. Meanwhile, the residual glue in the thin layer patterned insulating film in the working area is removed to obtain the current blocking layer.

[0049] It can be understood that before the secondary masking, a pre-prepared photoresist mask is required, and the photoresist mask is used to make the pattern through a conventional coating machine, exposure machine and developer, and is mainly used to protect part of the thin-layer patterned insulating film layer. The protected area is the working area, and the unprotected area is the non-working area. Specifically, the thin-layer patterned insulating film layer in the non-working area is removed by BOE wet etching, wherein the residual glue in the thin-layer patterned insulating film layer in the working area is removed by EKC solvent or SPM solvent to obtain a current blocking layer with a columnar pattern.

[0050] In summary, the current blocking layer and the preparation method of the current blocking layer in the embodiments of the present invention deposit an insulating film layer on the provided P-type layer, and use nanoimprinting to make a nanoscale line width mask layer, perform a mask treatment on the insulating film layer, and copy the pattern of the mask layer on the insulating film layer to obtain a patterned insulating film layer, and then process the non-mask portion of the patterned insulating film layer to a predetermined thickness, and then perform a secondary mask treatment, and the obtained thin layer of patterned insulating film layer in the non-working area is removed, and the thin layer of patterned insulating film layer in the retained working area is subjected to residual glue removal treatment, thus completing the preparation of the nanoscale line width current blocking layer. Specifically, the cost of the traditional current blocking layer with nanoscale line width produced by selecting an exposure machine is extremely expensive, because the exposure machine itself is a high-precision and advanced equipment, while in the present invention, the exposure machine technology is only used in the secondary mask treatment process, which greatly reduces the use time of the exposure machine, thereby ensuring the low-cost production of the nanoscale line width current blocking layer.

[0051] Embodiment 3

[0052] The third embodiment of the present invention provides an LED chip, comprising the current blocking layer in the first embodiment above, and the current blocking layer can be manufactured by the method for preparing the current blocking layer in the second embodiment above.

[0053] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a current blocking layer, characterized in that: The preparation method comprises: Providing a P-type layer required for growth, and at the same time, using nano-imprinting to make a mask layer with nano-scale line width; Depositing an insulating film layer on the P-type layer, and performing a masking process on the insulating film layer through the nanoscale line width mask layer to obtain a patterned insulating film layer; Processing the non-mask portion of the patterned insulating film layer to a predetermined thickness and removing the residual adhesive to obtain a thin patterned insulating film layer; The thin layer patterned insulating film layer is divided into a working area and a non-working area by a secondary mask, and the thin layer patterned insulating film layer in the non-working area is removed. At the same time, the residual glue in the thin layer patterned insulating film layer in the working area is removed to obtain the current blocking layer.

2. The method for preparing a current blocking layer according to claim 1, characterized in that: The step of providing a P-type layer required for growth and simultaneously making a mask layer with a nanometer line width by nanoimprinting specifically includes: The soft template colloid is made by a mixing machine, the mixing time is 20min to 60min, and the standing time is 4h to 8h; Putting the soft template colloid into a soft template making machine to prepare a soft template, wherein the preparation temperature is 100° C. to 150° C., the amount of the colloid is 50 g to 100 g, and the number of degassing is 10 to 50 times; The soft template is placed in an imprinting machine to prepare the nanoscale line width mask layer, wherein the conditions are set as a temperature of 40°C to 80°C, a primary pressure of 0.5Kpa to 3Kpa, a secondary pressure of 10Kpa to 20Kpa, a boost position of 30mm to 40mm, an exposure time of 20s to 60s, a speed change position of 10mm to 20mm, an imprinting time of 30s to 120s, and a pattern height of the nanoscale line width mask layer of 20nm to 100nm.

3. The method for preparing a current blocking layer according to claim 1, characterized in that: The thickness of the deposited insulating film layer is 700A~10000A, and during the deposition process, the film stress is changed by alternating high and low radio frequencies, wherein the radio frequency power is set to 50W~200W, and the temperature is set to a low temperature of 150℃~250℃ or a high temperature of 300℃~450℃.

4. The method for preparing a current blocking layer according to claim 1, characterized in that: The non-mask portion processing process is a wet or dry etching process.

5. The method for preparing a current blocking layer according to claim 1, characterized in that: When removing the residual glue, the residual glue is removed by an organic solvent.

6. The method for preparing a current blocking layer according to claim 1, characterized in that: The step of dividing the thin patterned insulating film layer into a working area and a non-working area by a secondary mask, removing the thin patterned insulating film layer in the non-working area, and removing the residual glue in the thin patterned insulating film layer in the working area to obtain the current blocking layer also includes: A photoresist mask is prepared, wherein the photoresist mask is used to protect a partial area of ​​the thin patterned insulating film layer, and the protected area is the working area.

7. The method for preparing a current blocking layer according to claim 1, characterized in that: The process for removing the thin patterned insulating film layer in the non-working area is a BOE wet etching process.

8. A current blocking layer, characterized in that: The current blocking layer is prepared by the preparation method of the current blocking layer according to any one of claims 1 to 7, wherein the current blocking layer comprises a P-type layer protection portion and a current guiding portion extending outward from a side of the P-type layer protection portion away from the P-type layer, and the current guiding portion is perpendicular to the P-type layer protection portion.

9. The current blocking layer according to claim 8, characterized in that: The height of the current guiding portion is 20 nm to 100 nm.

10. An LED chip, characterized in that: The invention comprises the current blocking layer as described in any one of claims 8 to 9.

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