A voltage regulator circuit with current limiting function for high-performance power management

Abstract

This invention discloses a voltage regulator circuit with current limiting function for high-performance power management, comprising a current limiting stage, an amplification stage, a buffer stage, and an output stage. The output terminal of the amplification stage is the input terminal of the buffer stage, and the output terminal of the buffer stage is the input terminal of the output stage. The output terminal of the output stage is connected to one input terminal of the amplification stage after passing through a voltage divider resistor. The other input terminal of the amplification stage is an external reference voltage. The output terminal of the current limiting stage is connected to the input terminal of the buffer stage. This invention utilizes a feedback loop to achieve a stable low-voltage output. In power management circuits, when the power supply voltage is high, the voltage regulator circuit of this invention can generate a stable low-voltage output to provide power to other modules, thereby reducing chip size and simplifying the structure.

Description

Technical Field

[0001] This invention belongs to the field of power management, and specifically relates to a voltage regulator circuit with current limiting function for high-performance power management, which is mainly used in DC / DC converters with high input voltage. Background Technology

[0002] A voltage regulator circuit with current limiting for high-performance power management is a regulated output circuit unaffected by changes in the input power supply voltage. Currently, most voltage regulator circuits have a narrow input range, failing to meet high voltage withstand requirements. A wider input voltage range expands the application range of voltage regulators, making them suitable not only for DC / DC regulators, constant current regulators, and battery chargers, but also for industrial products. In some harsh application conditions, instantaneous high voltages can occur externally to the power supply system, thus placing stringent demands on the reliability of power management circuits. High-voltage regulator circuits, as the most commonly used modules in high-voltage power management chips, are widely used due to their advantages such as small area, low power consumption, and low output ripple. Therefore, a voltage regulator circuit capable of withstanding high voltage and achieving a stable output voltage is essential in high-voltage power management circuits. Voltage regulator circuits with current limiting for high-performance power management are used in integrated circuit chips due to their ease of implementation, high integration, and small chip footprint. Summary of the Invention

[0003] Based on the negative feedback characteristics, a voltage regulator circuit with current limiting function for high-performance power management is designed. This circuit can generate a stable output voltage when the power supply voltage is high, providing power voltage for the low-voltage domain module. The current limiting function can prevent the output CMOS transistor of the voltage regulator from being damaged due to excessive current.

[0004] This invention discloses a voltage regulator circuit with current limiting function for high-performance power management, comprising four stages: a current limiting stage, an amplification stage, a buffer stage, and an output stage. The output terminal of the amplification stage is the input terminal of the buffer stage, and the output terminal of the buffer stage is the input terminal of the output stage. The output terminal of the output stage is connected to one input of the amplification stage after passing through a voltage divider resistor. The other input of the amplification stage is an external reference voltage. The output terminal of the current limiting stage is connected to the input terminal of the buffer stage. The current limiting stage includes P-type MOSFETs MP7, MP8, and MP9, transistors Q1 and Q2, and bias currents I1 and I2 to provide voltage drop. The source of P-type MOSFET MP7 is connected to the power supply VDD, and its gate and drain are connected. The gate and drain of P-type MOSFET MP8 are connected. The source of the P-type MOSFET MP7 is connected to its gate and drain. The gate and drain of MP9 are connected together, and the source of MP8 is connected to its gate and drain. The gate and drain of MP9 are connected to the bias current source I1 and to the base of transistor Q. The collector of transistor Q1 is connected to the power supply VDD, and the emitter is connected to the bias current I2 and to the base of transistor Q2. The collector of transistor Q2 is connected to the power supply VDD, and the emitter is connected to the X terminal. The amplification stage includes the input pair P-type MOSFETs MP1 and MP2, P-type MOSFETs MP3 and MP4 for current mirroring, N-type MOSFETs MN1, MN2, MN5, and MN6, and bias currents I4 and I5 for reducing channel modulation effects. MN3 and MN4; The amplification stage includes input pair P-type MOSFETs MP1 and MP2 and bias current I3, P-type MOSFETs MP3 and MP4 for current mirroring, N-type MOSFETs MN1, MN2, MN5, and MN6 and bias currents I4 and I5, N-type MOSFETs MN3 and MN4 for reducing channel modulation effect. The source of P-type MOSFET MP1 is connected to the source of MP2 and to the bias current source I3. The gate of P-type MOSFET MP1 is connected to the feedback voltage Vfb, and its drain is connected to the drain of N-type MOSFET MN2 and to the source of N-type MOSFET MN3. The gate of P-type MOSFET MP2 is connected to the external reference voltage VREF, and its drain is connected to the N-type MOSFET MN3. The drain of MOSFET MN5 is connected to the source of N-type MOSFET MN4. The gate of N-type MOSFET MN4 is connected to the gate of MN3 and connected to the external bias voltage Vb. The source of P-type MOSFET MP3 is connected to the power supply VDD, the gate and drain are connected, and the drain of N-type MOSFET MN3 is connected. The source of P-type MOSFET MP4 is connected to the power supply VDD, the gate is connected to the gate of MP3, the drain is connected to the drain of N-type MOSFET MN4, and connected to the X terminal. The gate and drain of N-type MOSFET MN1 are connected, and a bias current I4 is connected between it and the power supply VDD. The gate and drain of N-type MOSFET MN6 are connected, and a bias current I5 is connected between it and the power supply VDD.The buffer stage includes a bias current I6 and a P-type MOSFET MP5. The buffer stage includes the P-type MOSFET MP5 and a bias current source I6 connected to the power supply VDD. The base of the P-type MOSFET MP5 is connected to the X terminal, the drain is connected to the bias current I6, and the drain is grounded.

[0005] When the output current is less than the current limit, the voltage at point X is higher, and the base voltage of transistor Q2 is lower than the voltage at point X, so transistor Q2 does not conduct. When the output current is higher than the set current limit, the voltage at point X is lower, transistor Q2 conducts, and current enters the loop, thus achieving the current limiting effect.

[0006] The output stage includes a P-type MOSFET MP6, a feedback resistor Rf1, and a voltage divider resistor Rf2. A Miller compensation capacitor Cc and a resistor Rc are located between the output VREG terminal and the X terminal. The output stage also includes an output P-type MOSFET MP6, a feedback resistor Rf1, a voltage divider resistor Rf2, and an output capacitor Cc. L Compensation resistor R C and compensation capacitor C C The source of P-type MOSFET MP6 is connected to the power supply VDD, the gate is connected to the source of P-type MOSFET MP5, and the drain is connected to the feedback resistor Rf1, which forms the regulated output terminal VREG, and is connected to the output capacitor C. L Output capacitor C L The other end is grounded, the other end of the feedback resistor Rf1 is connected to the Vfb terminal, and connected to one end of the voltage divider resistor Rf2. The other end of the voltage divider resistor Rf2 is grounded, and a compensation resistor R is connected between the VREG terminal and the X terminal. C and compensation capacitor C C Compensation resistor R C One end is connected to terminal X, and the other end is connected to the compensation capacitor C. C Terminal connection, compensation capacitor C C The other end is connected to the output VREG terminal.

[0007] This invention employs a high-voltage PMOS transistor in its power output stage to achieve low dropout voltage, low noise, and adaptability to a wide input voltage range. The invention utilizes Miller compensation capacitors and resistors to achieve excellent phase margin, ensuring system stability and enabling stable output voltage under varying power supply voltages and load currents. The current-limiting current used in this invention is primarily applied in voltage regulator circuits employing PMOS transistors as the output stage. It limits the output current of the output stage during system startup and overcurrent events, thereby protecting the chip from damage. Attached Figure Description

[0008] Figure 1 This is the circuit schematic diagram of the present invention. Detailed Implementation

[0009] Referring to the accompanying drawings, this invention comprises four stages: a current-limiting stage, an amplification stage, a buffer stage, and an output stage. The output terminal of the amplification stage is the input terminal of the buffer stage, and the output terminal of the buffer stage is the input terminal of the output stage. The output terminal of the output stage is connected to one input terminal of the amplification stage via a voltage divider resistor. The other input terminal of the amplification stage is an external reference voltage. The output terminal of the current-limiting stage is connected to the input terminal of the buffer stage.

[0010] The voltage regulator circuit of this invention is a negative feedback circuit. The amplifier stage circuit feeds back the voltage V to the negative input terminal. fb The difference between the input voltage and the reference voltage VREF is amplified to obtain the output signal X. This signal then passes through a buffer stage and then to the output stage, where it is further divided to obtain V. fb This feedback is then fed back to the input of the amplifier stage, forming a negative feedback system. After frequency compensation, the negative feedback system can produce a stable output.

[0011] Miller compensation capacitor C C and compensation resistor R C The function of the Miller compensation capacitor Cc is to shift the dominant pole of the loop to the X terminal, ensuring the stability of the loop. The compensation resistor R... C The presence of this will adjust the phase margin within a reasonable range.

[0012] With the reference power supply REF, and through the loop, the output voltage VREG can be stabilized at a certain voltage value, which is...

[0013]

[0014] The frequency compensation principle is as follows: Due to the large output impedance of the amplifier stage and the large input parasitic capacitance of the power stage, a low-frequency pole will be generated at the output of the amplifier stage. In addition, a pole will also exist at the output of the voltage regulator circuit, and this pole changes with the load. A low-frequency pole and a changing pole can easily cause system instability. Therefore, a buffer stage is introduced between the output of the amplifier stage and the input of the power stage. The buffer stage has a small input parasitic capacitance and a small output impedance, thus preventing the formation of a high-frequency pole, and the buffer can better drive the power stage. With the buffer stage, the system only has one output pole that could potentially become a low-frequency pole. To further ensure the stability of the negative feedback system, a Miller compensation capacitor C is added. C The Miller compensation resistor Rc and the Miller compensation capacitor Cc together with the output impedance of the amplifier stage form the low-frequency pole. At the same time, the presence of the Miller compensation capacitor Cc pushes the output pole to a higher frequency. The Miller compensation resistor Rc introduces a zero to compensate for the output pole, thereby achieving excellent frequency compensation and ensuring the stable output of the voltage regulation system.

Claims

1. A voltage regulator circuit with current limiting function for high-performance power management, characterized in that, It consists of four stages: a current-limiting stage, an amplification stage, a buffer stage, and an output stage. The output of the amplification stage is the input of the buffer stage, and the output of the buffer stage is the input of the output stage. The output of the output stage is connected to one input of the amplification stage via a voltage divider resistor. The other input of the amplification stage is an external reference voltage. The output of the current-limiting stage is connected to the input of the buffer stage. The current-limiting stage includes P-type MOSFETs MP7, MP8, and MP9 to provide voltage drop, transistors Q1 and Q2, and bias currents I1 and I2. The source of P-type MOSFET MP7 is connected to the power supply VDD, and its gate and drain are connected. The gate and drain of P-type MOSFET MP8 are connected, and its source is connected to the gate and drain of MP7. The gate and drain of MP9 are connected, and its source is connected to the gate and drain of MP8. The gate and drain of the P-type MOSFET MP9 are connected to the bias current source I1 and to the base of transistor Q. The collector of transistor Q1 is connected to the power supply VDD, and its emitter is connected to the bias current I2 and to the base of transistor Q2. The collector of transistor Q2 is connected to the power supply VDD, and its emitter is connected to the X terminal. The amplification stage includes input pairs of P-type MOSFETs MP1 and MP2, P-type MOSFETs MP3 and MP4 for current mirroring, N-type MOSFETs MN1, MN2, MN5, and MN6, and bias currents I4 and I5, and N-type MOSFETs MN3 and MN4 for reducing channel modulation effects. The amplification stage includes... Input transistors P-type MOSFETs MP1 and MP2 and bias current I3; P-type MOSFETs MP3 and MP4 for current mirroring; N-type MOSFETs MN1, MN2, MN5, and MN6 and bias currents I4 and I5; N-type MOSFETs MN3 and MN4 for reducing channel modulation effect. The source of P-type MOSFET MP1 is connected to the source of MP2 and to the bias current source I3. The gate of P-type MOSFET MP1 is connected to the feedback voltage Vfb, and its drain is connected to the drain of N-type MOSFET MN2 and the source of N-type MOSFET MN3. The gate of P-type MOSFET MP2 is connected to the external reference voltage VREF, and its drain is connected to the N-type MOSFET MN3. The drain of transistor 5 is connected to the source of N-type MOSFET MN4. The gate of N-type MOSFET MN4 is connected to the gate of MN3 and connected to the external bias voltage Vb. The source of P-type MOSFET MP3 is connected to the power supply VDD, the gate and drain are connected, and the drain of N-type MOSFET MN3 is connected. The source of P-type MOSFET MP4 is connected to the power supply VDD, the gate is connected to the gate of MP3, the drain is connected to the drain of N-type MOSFET MN4, and connected to the X terminal. The gate and drain of N-type MOSFET MN1 are connected, and a bias current I4 is connected between it and the power supply VDD. The gate and drain of N-type MOSFET MN6 are connected, and a bias current I5 is connected between it and the power supply VDD. The buffer stage includes a bias current I6 and a P-type MOS transistor MP5. The buffer stage includes a buffer transistor P-type MOS transistor MP5 and a bias current source I6 connected to the power supply VDD. The base of the P-type MOS transistor MP5 is connected to the X terminal, the drain is connected to the bias current I6, and the drain is grounded.

2. The voltage regulator circuit with current limiting function for high-performance power management according to claim 1, characterized in that, When the output current is less than the current limit, the voltage at point X is higher, and the base voltage of transistor Q2 is lower than the voltage at point X, so transistor Q2 does not conduct. When the output current is higher than the set current limit, the voltage at point X is lower, transistor Q2 conducts, and current enters the loop, thus achieving the current limiting effect.

3. A voltage regulator circuit with current limiting function for high-performance power management according to claim 1, characterized in that, The output stage includes a P-type MOSFET MP6, a feedback resistor Rf1, and a voltage divider resistor Rf2. A Miller compensation capacitor Cc and a resistor Rc are located between the output VREG terminal and the X terminal. The output stage also includes an output P-type MOSFET MP6, a feedback resistor Rf1, a voltage divider resistor Rf2, and an output capacitor Cc. L Compensation resistor R C and compensation capacitor C C The source of P-type MOSFET MP6 is connected to the power supply VDD, the gate is connected to the source of P-type MOSFET MP5, and the drain is connected to the feedback resistor Rf1, which forms the regulated output terminal VREG, and is connected to the output capacitor C. L Output capacitor C L The other end is grounded, the other end of the feedback resistor Rf1 is connected to the Vfb terminal, and connected to one end of the voltage divider resistor Rf2. The other end of the voltage divider resistor Rf2 is grounded, and a compensation resistor R is connected between the VREG terminal and the X terminal. C and compensation capacitor C C Compensation resistor R C One end is connected to terminal X, and the other end is connected to the compensation capacitor C. C Terminal connection, compensation capacitor C C The other end is connected to the output VREG terminal.

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