Synchronous carrier DPWM midpoint voltage balancing method, system and related components

Abstract

The present application discloses a synchronous carrier DPWM midpoint voltage balancing method, system and related components, which relate to the field of converters and are applied to three-level converter modulation, including: obtaining the current synchronous carrier DPWM type; obtaining the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculating the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage; judging whether the absolute value of the voltage difference is greater than the deviation threshold; if so, determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference; determining the three-phase modulation wave according to the zero-sequence component to control the three-level converter. The present application is used to control a three-level converter. When the absolute value of the voltage difference is greater than the deviation threshold, that is, when a midpoint voltage deviation occurs, the zero-sequence component is determined according to the current synchronous carrier DPWM type and the voltage difference, and the three-phase modulation wave is determined by the zero-sequence component, thereby eliminating the midpoint voltage deviation and achieving midpoint voltage balance.

Description

Technical Field

[0001] The present invention relates to the field of converters, and in particular to a synchronous carrier DPWM midpoint voltage balancing method, system and related components. Background Art

[0002] The three-level neutral point clamped (NPC) converter is the most commonly used three-level converter. Its main circuit topology is as follows: Figure 1 Due to the advantages of low device voltage stress, simple structure and control, and easy bidirectional energy flow, three-level converters have been widely used in photovoltaic and wind power generation, variable frequency speed regulation, metallurgical mining and other fields.

[0003] The three-level converter outputs three levels from high to low, which can be defined as P level, O level, and N level respectively. The space vector of the three-level converter is summarized as Figure 2 . Figure 2 Each space vector can be classified into zero vector, P-type small vector, N-type small vector, medium vector and large vector, as shown in Table 1 below, where zero vectors OOO / PPP / NNN are mutually redundant zero vectors, and P-type small vectors and N-type small vectors at the same position are mutually redundant small vectors.

[0004] Table 1 Types of voltage space vectors for three-level converters

[0005]

[0006] Synchronous DPWM (Discontinuous Pulse Width Modulation) is a commonly used synchronous modulation strategy for three-level converters. Regarding the research on synchronous DPWM, the paper "Space-vector-based synchronized three-level discontinuous PWM for medium-voltage high-power VSI" (Beig AR, Kanukollu S, Hosani KA, et al. [J]. IEEE Transactions on Industrial Electronics, 2014, 61 (8): 3891-3901.) proposed a method by clamping the phase voltage at the P or N level. Figure 3The four types of synchronous DPWM are shown and are defined as synchronous DPWM 1, synchronous DPWM 2, synchronous DPWM 3 and synchronous DPWM 4. These four types of synchronous DPWM can eliminate the harmonics of multiples of 3 and even harmonics in the line voltage, thereby improving the quality of the output waveform, but the phase voltage under its action has a two-level jump, which threatens the safe operation of the three-level converter. To overcome this defect, the patent "Synchronous carrier DPWM method for avoiding two-level jumps of phase voltage of three-level inverter" (Zhang Bo. [P]. Invention Patent, 2019, CN 201911186556.3) proposes synchronous carrier DPWM1, synchronous carrier DPWM 2, synchronous carrier DPWM 3 and synchronous carrier DPWM 4 to avoid two-level jumps of phase voltage of three-level inverter. The four types of synchronous carrier DPWM simplify the calculation and avoid two-level jumps of phase voltage while ensuring the symmetry of the output waveform, so they are more suitable for high-power three-level converters. In addition, the paper "Research on Improved Synchronous Discontinuous Carrier Pulse Width Modulation Strategy for Three-Level Inverter" (Gao Zhan, Li Yaohua, Ge Qiongxuan, et al. [J]. Proceedings of the CSEE, 2020, 40(17): 5620-5636) proposed a method by clamping the phase voltage at the zero level. Figure 4 The synchronous carrier DPWM A, synchronous carrier DPWM B, synchronous carrier DPWM C, synchronous carrier DPWM D, synchronous carrier DPWM E, synchronous carrier DPWM F and synchronous carrier DPWM G shown can all satisfy waveform symmetry and reduce switching frequency.

[0007] However, in addition to reducing the switching frequency and maintaining waveform symmetry, midpoint voltage balance control is also a key issue for high-power three-level converters. Traditional pulse width modulation can control the midpoint voltage balance by redistributing the action time of redundant small vectors, while synchronous carrier DPWM only uses specific small vectors or specific zero vectors in each sampling cycle. It does not have redundant small vectors and redundant zero vectors, and cannot use the existing method of redistributing the action time of redundant small vectors to control the midpoint voltage balance.

[0008] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve. Summary of the invention

[0009] In view of this, the object of the present invention is to provide a synchronous carrier DPWM midpoint voltage balancing method, system and related components capable of achieving midpoint voltage balancing control. The specific scheme is as follows:

[0010] A synchronous carrier DPWM midpoint voltage balancing method is applied to a modulation process of a three-level converter, comprising:

[0011] Get the current synchronous carrier DPWM type;

[0012] Obtaining an upper bridge arm voltage and a lower bridge arm voltage on a DC side, and calculating a voltage difference between the upper bridge arm voltage and the lower bridge arm voltage;

[0013] Determining whether the absolute value of the voltage difference is greater than a deviation threshold;

[0014] If so, determining a zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference;

[0015] Determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter;

[0016] The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G.

[0017] Preferably, the synchronous carrier DPWM midpoint voltage balancing method further includes:

[0018] Determine whether the current synchronous carrier DPWM type needs to obtain operating parameters;

[0019] If yes, obtaining the corresponding operating parameters according to the current synchronous carrier DPWM type;

[0020] Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference includes:

[0021] The zero-sequence component is determined according to the current synchronous carrier DPWM type, the operating parameter and the sign of the voltage difference.

[0022] Preferably, if the current synchronous carrier DPWM type is any one of DPWM1, DPWM2, DPWM3, and DPWM4, the operating parameters include a current modulation ratio; if the current modulation ratio is not less than a preset modulation ratio, the operating parameters also include a current target current and a current phase angle;

[0023] Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference includes:

[0024] When the current modulation ratio is less than the preset modulation ratio, if the sign of the voltage difference is positive, the zero-sequence component is determined to be 1-Vmax; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmin-1;

[0025] When the current modulation ratio is not less than the preset modulation ratio, determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in a target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0026] If yes, then the zero-sequence component is determined to be -Umin;

[0027] If not, then determine that the zero-sequence component is 1-Umax;

[0028] Wherein, Vmin is the minimum value of the three-phase sinusoidal modulation wave, Vmax is the maximum value of the three-phase sinusoidal modulation wave, Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after the three-phase sinusoidal modulation wave is processed, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulation wave;

[0029] The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively;

[0030] When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter;

[0031] When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0032] When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0033] Preferably, if the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWM C, and DPWM D, the operating parameters include the current target current and the current phase angle;

[0034] Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference includes:

[0035] Determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in the target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0036] If yes, then the zero-sequence component is determined to be -Umin;

[0037] If not, then determine that the zero-sequence component is 1-Umax;

[0038] Wherein, Umin is the minimum value of the processed modulated wave, Umax is the maximum value of the processed modulated wave, the processed modulated wave is the modulated wave after processing the three-phase sinusoidal modulated wave, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulated wave;

[0039] The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively;

[0040] When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter;

[0041] When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0042] When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0043] Preferably, if the current synchronous carrier is any one of DPWM E, DPWM F, and DPWM G, the process of determining the zero-sequence component according to the type of the current synchronous carrier DPWM and the sign of the voltage difference includes:

[0044] If the sign of the voltage difference is positive, the zero-sequence component is determined to be -Vmin; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmax;

[0045] Among them, Vmin is the minimum value of the three-phase sinusoidal modulation wave, and Vmax is the maximum value of the three-phase sinusoidal modulation wave.

[0046] Preferably, the process of determining the three-phase modulation wave according to the zero-sequence component to control the three-level converter includes:

[0047] A three-phase modulation wave after a sampling point is determined according to the zero-sequence component to control the three-level converter.

[0048] Preferably, the process of obtaining the current synchronous carrier DPWM type includes:

[0049] According to the phase voltage clamping state, the current synchronous carrier DPWM type is determined.

[0050] Correspondingly, the present application also discloses a synchronous carrier DPWM midpoint voltage balancing system, which is applied to the modulation process of a three-level converter, including:

[0051] The first module is used to obtain the current synchronous carrier DPWM type;

[0052] The second module is used to obtain the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculate the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage;

[0053] A judging module, used to judge whether the absolute value of the voltage difference is greater than a deviation threshold, and if so, trigger a determining module;

[0054] The determination module is used to determine the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference;

[0055] An action module, used for determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter;

[0056] The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G.

[0057] Correspondingly, the present application also discloses a synchronous carrier DPWM midpoint voltage balancing device, comprising:

[0058] Memory for storing computer programs;

[0059] A processor is used to implement the steps of the synchronous carrier DPWM midpoint voltage balancing method as described in any one of the above items when executing the computer program.

[0060] Correspondingly, the present application also discloses a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the synchronous carrier DPWM midpoint voltage balancing method as described in any one of the above items are implemented.

[0061] The present application discloses a synchronous carrier DPWM midpoint voltage balancing method, which is applied to the modulation process of a three-level converter, including: obtaining the current synchronous carrier DPWM type; obtaining the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculating the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage; judging whether the absolute value of the voltage difference is greater than a deviation threshold; if so, determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference; determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter; wherein the current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G. In the present application, when the absolute value of the voltage difference is greater than the deviation threshold, that is, when a midpoint voltage deviation occurs, the zero-sequence component is determined according to the current synchronous carrier DPWM type and the voltage difference, and the three-phase modulation wave is determined by the zero-sequence component, thereby eliminating the midpoint voltage deviation and achieving midpoint voltage balance. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0063] Figure 1 It is a main circuit topology diagram of a three-level converter in the prior art;

[0064] Figure 2 A spatial vector diagram of a three-level converter in the prior art;

[0065] Figure 3 It is the phase voltage clamping state diagram of synchronous carrier DPWM 1-4;

[0066] Figure 4 It is the phase voltage clamping state diagram of the synchronous carrier DPWM AG;

[0067] Figure 5 A flowchart of the steps of a synchronous carrier DPWM midpoint voltage balancing method in an embodiment of the present invention;

[0068] Figure 6a-6c , Figure 7-Figure 16 They are schematic diagrams of simulation experimental results of synchronous carrier DPWM 1-4 and DPWM AG;

[0069] Fig.171 is a structural distribution diagram of a synchronous carrier DPWM midpoint voltage balance system in an embodiment of the present invention. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Traditional pulse width modulation can control the midpoint voltage balance by redistributing the action time of redundant small vectors, while synchronous carrier DPWM only uses specific small vectors or specific zero vectors in each sampling cycle. It does not have redundant small vectors and redundant zero vectors, and cannot use the existing method of redistributing the action time of redundant small vectors to control the midpoint voltage balance.

[0072] When the absolute value of the voltage difference is greater than the deviation threshold, that is, when a midpoint voltage deviation occurs, the present application determines the zero-sequence component according to the current synchronous carrier DPWM type and the voltage difference, and determines the three-phase modulation wave with the zero-sequence component, thereby eliminating the midpoint voltage deviation and achieving midpoint voltage balance.

[0073] The embodiment of the present invention discloses a synchronous carrier DPWM midpoint voltage balancing method, which is applied to the modulation process of a three-level converter. Figure 5 As shown, including:

[0074] S1: Get the current synchronous carrier DPWM type;

[0075] S2: Obtain the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculate the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage;

[0076] It can be understood that the DC side here refers to the DC side of the three-level converter.

[0077] S3: Determine whether the absolute value of the voltage difference is greater than the deviation threshold;

[0078] S4: If yes, determine the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference;

[0079] S5: determining a three-phase modulation wave according to the zero-sequence component to control a three-level converter;

[0080] It can be understood that if the absolute value of the voltage difference is not greater than the deviation threshold, the midpoint voltage is balanced at this time, and step S4 does not need to be executed. The original control strategy is executed to determine the three-phase modulation wave with the original zero-sequence component to control the three-level converter. The deviation threshold is a parameter set in advance and can be selected according to the actual working conditions.

[0081] The present application controls the midpoint voltage balance while retaining the synchronous carrier DPWM to reduce the switching frequency and maintain the three-phase symmetry and half-wave symmetry of the output voltage waveform, thereby improving the safety and reliability of the three-level converter and reducing the harm of the midpoint voltage imbalance. In addition, the implementation of the present application does not require a PI controller, and the calculation is simple and the application is convenient.

[0082] The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G.

[0083] Based on the above eleven optional synchronous carrier DPWM types, step S1 specifically includes: determining the current synchronous carrier DPWM type according to the phase voltage clamping state. It can be understood that the phase voltage clamping states corresponding to the eleven synchronous carrier DPWM types are already in Figure 3 and Figure 4 It is shown in the figure. According to the current phase voltage clamping state, the current synchronous carrier DPWM type can be found. Specifically:

[0084] 1) For synchronous carrier DPWM 1, the A-phase voltage is clamped at the P level in the phase angle region of 60 to 120 degrees, and at the N level in the phase angle region of 240 to 300 degrees; the B-phase voltage is clamped at the P level in the phase angle region of 180 to 240 degrees, and at the N level in the phase angle region of 0 to 60 degrees; the C-phase voltage is clamped at the P level in the phase angle region of 300 to 360 degrees, and at the N level in the phase angle region of 120 to 180 degrees;

[0085] 2) For synchronous carrier DPWM 2, the A-phase voltage is clamped at the P level in the phase angle region of 90 to 150 degrees, and is clamped at the N level in the phase angle region of 270 to 330 degrees; the B-phase voltage is clamped at the P level in the phase angle region of 210 to 270 degrees, and is clamped at the N level in the phase angle region of 30 to 90 degrees; the C-phase voltage is clamped at the P level in the phase angle region of 330 to 30 degrees, and is clamped at the N level in the phase angle region of 150 to 210 degrees;

[0086] 3) For synchronous carrier DPWM 3, the A-phase voltage is clamped at the P level in the phase angle region of 30 to 90 degrees, and is clamped at the N level in the phase angle region of 210 to 270 degrees; the B-phase voltage is clamped at the P level in the phase angle region of 150 to 210 degrees, and is clamped at the N level in the phase angle region of 330 to 30 degrees; the C-phase voltage is clamped at the P level in the phase angle region of 270 to 330 degrees, and is clamped at the N level in the phase angle region of 90 to 150 degrees;

[0087] 4) For synchronous carrier DPWM 4, the A-phase voltage is clamped at the P level in the phase angle region of 30 to 60 degrees and 120 to 150 degrees, and is clamped at the N level in the phase angle region of 210 to 240 degrees and 300 to 330 degrees; the B-phase voltage is clamped at the P level in the phase angle region of 150 to 180 degrees and 240 to 270 degrees, and is clamped at the N level in the phase angle region of 60 to 90 degrees and 330 to 360 degrees; the C-phase voltage is clamped at the P level in the phase angle region of 0 to 30 degrees and 270 to 300 degrees, and is clamped at the N level in the phase angle region of 90 to 120 degrees and 180 to 210 degrees;

[0088] 5) For synchronous carrier DPWM A, the A-phase voltage is clamped at 0 level in the phase angle region of 330 to 30 degrees and 150 to 210 degrees, the B-phase voltage is clamped at 0 level in the phase angle region of 90 to 150 degrees and 270 to 330 degrees, and the C-phase voltage is clamped at 0 level in the phase angle region of 30 to 90 degrees and 210 to 270 degrees;

[0089] 6) For synchronous carrier DPWM B, the A-phase voltage is clamped at the 0 level in the phase angle regions of 60 to 90 degrees, 150 to 180 degrees, 240 to 270 degrees, and 330 to 360 degrees, the B-phase voltage is clamped at the 0 level in the phase angle regions of 0 to 30 degrees, 90 to 120 degrees, 180 to 210 degrees, and 270 to 300 degrees, and the C-phase voltage is clamped at the 0 level in the phase angle regions of 30 to 60 degrees, 120 to 150 degrees, 210 to 240 degrees, and 300 to 330 degrees;

[0090] 7) For synchronous carrier DPWM C, the A-phase voltage is clamped at the 0 level in the phase angle regions of 0 to 30 degrees, 90 to 120 degrees, 180 to 210 degrees, and 270 to 300 degrees, the B-phase voltage is clamped at the 0 level in the phase angle regions of 30 to 60 degrees, 120 to 150 degrees, 210 to 240 degrees, and 300 to 330 degrees, and the C-phase voltage is clamped at the 0 level in the phase angle regions of 60 to 90 degrees, 150 to 180 degrees, 240 to 270 degrees, and 330 to 360 degrees;

[0091] 8) For synchronous carrier DPWM D, the A-phase voltage is clamped at 0 level in the phase angle region of 60 to 120 degrees and 240 to 300 degrees, the B-phase voltage is clamped at 0 level in the phase angle region of 0 to 60 degrees and 180 to 240 degrees, and the C-phase voltage is clamped at 0 level in the phase angle region of 120 to 180 degrees and 300 to 360 degrees;

[0092] 9) For synchronous carrier DPWM E, the A-phase voltage is clamped at 0 level in the phase angle regions of 30 to 60 degrees, 120 to 150 degrees, 210 to 240 degrees, and 300 to 330 degrees, the B-phase voltage is clamped at 0 level in the phase angle regions of 60 to 90 degrees, 150 to 180 degrees, 240 to 270 degrees, and 330 to 360 degrees, and the C-phase voltage is clamped at 0 level in the phase angle regions of 0 to 30 degrees, 90 to 120 degrees, 180 to 210 degrees, and 270 to 300 degrees;

[0093] 10) For synchronous carrier DPWM F, the A-phase voltage is clamped at 0 level in the phase angle region of 30 to 90 degrees and 210 to 270 degrees, the B-phase voltage is clamped at 0 level in the phase angle region of 330 to 30 degrees and 150 to 210 degrees, and the C-phase voltage is clamped at 0 level in the phase angle region of 90 to 150 degrees and 270 to 330 degrees;

[0094] 11) For the synchronous carrier DPWM G, the A-phase voltage is clamped at the 0 level in the phase angle region of 90 to 150 degrees and 270 to 330 degrees, the B-phase voltage is clamped at the 0 level in the phase angle region of 30 to 90 degrees and 210 to 270 degrees, and the C-phase voltage is clamped at the 0 level in the phase angle region of 330 to 30 degrees and 150 to 210 degrees.

[0095] Further, step S4 is a process of determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference. When the current synchronous carrier DPWM type is different, the principle of determining the zero-sequence component is different. Generally, the eleven synchronous carrier DPWM types are divided into three categories, among which DPWM 1-DPWM 4 with a modulation ratio less than a preset modulation ratio is one category, DPWM AD and DPWM 1-4 with a modulation ratio not less than a preset modulation ratio are one category, and DPWM EG is one category. The specific zero-sequence component determination process can be described in the following embodiments.

[0096] Further, step S5 specifically includes: determining the three-phase modulation wave after the sampling point according to the zero-sequence component to control the three-level converter. It can be understood that when the absolute value of the voltage difference is greater than the deviation threshold, that is, the midpoint voltage is unbalanced, the original zero-sequence component needs to be switched to a new zero-sequence component, thereby realizing the control from the original three-phase modulation wave to the new three-phase modulation wave, and the switching moment is the sampling point, and the selection of the sampling point is as follows:

[0097] When Carr_up=1 and Carr_dn=0, the peak value of the triangular carrier is selected as the sampling point;

[0098] When Carr_up=0 and Carr_dn=-1, the triangular carrier zero point is selected as the sampling point.

[0099] Among them, Carr_up is the upper triangular carrier per unit value of the three-level converter, and its value range is 0 to 1; Carr_dn is the lower triangular carrier per unit value of the three-level converter, and its value range is -1 to 0.

[0100] Among them, the calculation process of determining the three-phase modulation wave according to the zero-sequence component is as follows:

[0101]

[0102] Among them, Z0 is the zero sequence component, V sa is the original A-phase sinusoidal modulation wave, V sb is the original B-phase sinusoidal modulation wave, V sc is the original C-phase sinusoidal modulation wave, V ma is the A-phase modulation wave after injection of Z0, V mb is the B-phase modulation wave after injection of Z0, V mc is the C phase modulation wave after Z0 is injected. ma 、V mb 、V mc By comparing with the upper triangle carrier per unit value and the lower triangle carrier per unit value of the three-level converter and controlling the switching state of each device of the three-level converter according to the comparison result, the midpoint voltage can be controlled to restore balance.

[0103] The present application discloses a synchronous carrier DPWM midpoint voltage balancing method, which is applied to the modulation process of a three-level converter, including: obtaining the current synchronous carrier DPWM type; obtaining the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculating the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage; judging whether the absolute value of the voltage difference is greater than a deviation threshold; if so, determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference; determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter; wherein the current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G. In the present application, when the absolute value of the voltage difference is greater than the deviation threshold, that is, when a midpoint voltage deviation occurs, the zero-sequence component is determined according to the current synchronous carrier DPWM type and the voltage difference, and the three-phase modulation wave is determined by the zero-sequence component, thereby eliminating the midpoint voltage deviation and achieving midpoint voltage balance.

[0104] The embodiment of the present invention discloses a specific synchronous carrier DPWM midpoint voltage balancing method. Compared with the previous embodiment, this embodiment further illustrates and optimizes the technical solution.

[0105] Specifically, if the current synchronous carrier is any one of DPWM E, DPWM F, and DPWM G, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference includes:

[0106] If the sign of the voltage difference is positive, the zero-sequence component is determined to be -Vmin, and if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmax;

[0107] Among them, Vmin is the minimum value of the three-phase sinusoidal modulation wave, and Vmax is the maximum value of the three-phase sinusoidal modulation wave.

[0108] It is understandable that for the other two categories, other auxiliary judgment conditions need to be added. Therefore, the synchronous carrier DPWM midpoint voltage balancing method also includes:

[0109] Determine whether the current synchronous carrier DPWM type needs to obtain operating parameters;

[0110] If yes, obtain the corresponding operating parameters according to the current synchronous carrier DPWM type;

[0111] Correspondingly, step S4 is a process of determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference, including:

[0112] The zero-sequence component is determined according to the current synchronous carrier DPWM type, operating parameters and the sign of the voltage difference.

[0113] If the current synchronous carrier DPWM type is any one of DPWM 1-4, it is necessary to obtain operating parameters, which at least include the current modulation ratio. If the current modulation ratio is not less than the preset modulation ratio, it is necessary to obtain other operating parameters, which include the current target current and the current phase angle.

[0114] If the current synchronous carrier DPWM type is any of DPWM AD, it is necessary to obtain the operating parameters, which include the current target current and the current phase angle;

[0115] If the current synchronous carrier DPWM type is any one of DPWM EG, the zero-sequence component can be directly determined without obtaining the operating parameters.

[0116] Therefore, if the current synchronous carrier DPWM type is any of DPWM1, DPWM2, DPWM3, and DPWM4, the operating parameters include the current modulation ratio; if the current modulation ratio is not less than the preset modulation ratio, the operating parameters also include the current target current and the current phase angle;

[0117] The process of obtaining the current modulation ratio includes: Mi = VL-L / Vdc, where Mi is the modulation ratio, the value range is 0 to 1, VL-L is the fundamental amplitude of the output line voltage of the three-level converter, and Vdc is the DC side voltage of the three-level converter. The preset modulation ratio can be set according to the working conditions, and the value range is also between 0 and 1, and can usually be set to 0.5.

[0118] Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, operating parameters and the sign of the voltage difference includes:

[0119] When the current modulation ratio is less than the preset modulation ratio, if the sign of the voltage difference is positive, the zero-sequence component is determined to be 1-Vmax; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmin-1;

[0120] When the current modulation ratio is not less than the preset modulation ratio, determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in the target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0121] If so, the zero-sequence component is determined to be -Umin;

[0122] If not, the zero-sequence component is determined to be 1-Umax;

[0123] Among them, Vmin is the minimum value of the three-phase sinusoidal modulation wave, Vmax is the maximum value of the three-phase sinusoidal modulation wave, Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after processing the three-phase sinusoidal modulation wave. The processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulation wave; at this time, no adjustment is made to the positive value.

[0124] The target phase angle area includes three target phase angle partitions, which are:

[0125] 0°-60°, 120°-180° and 240°-300°;

[0126] If the current phase angle is between 60°-120° or 240°-300°, the current target current is the A-phase current of the three-level converter;

[0127] If the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0128] If the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0129] Similarly, if the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWM C, and DPWM D, the operating parameters include the current target current and the current phase angle;

[0130] Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, operating parameters and the sign of the voltage difference includes:

[0131] Determine whether a first condition is met, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in the target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0132] If so, the zero-sequence component is determined to be -Umin;

[0133] If not, the zero-sequence component is determined to be 1-Umax;

[0134] Wherein, Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after processing the three-phase sinusoidal modulation wave, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulation wave;

[0135] The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively;

[0136] If the current phase angle is between 60°-120° or 240°-300°, the current target current is the A-phase current of the three-level converter;

[0137] If the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0138] If the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0139] Obviously, the determination of the zero-sequence component when DPWM 1-4 and the current modulation ratio is not less than the preset modulation ratio is the same as the determination of the zero-sequence component when DPWM AD is used.

[0140] Specifically, the zero-sequence component values for each case are shown in Table 1 below:

[0141] Table 1 Zero-sequence component values

[0142]

[0143] The embodiment of the present invention discloses a specific synchronous carrier DPWM neutral point voltage balancing method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution.

[0144] Specifically, during the implementation of the synchronous carrier DPWM neutral point voltage balancing method, each parameter can be calculated by per-unit value. Given that Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after processing the three-phase sinusoidal modulation wave. At this time, the processing under per-unit value is mainly to add 1 to the negative value of the three-phase sinusoidal modulation wave.

[0145] Specifically, for the convenience of calculation, the signs of the voltage difference and the target current can be recorded by means of flag values. For example:

[0146] When Vdc_up - Vdc_dn > NVL, let NVflag = 1;

[0147] When Vdc_up - Vdc_dn < -NVL, let NVflag = -1;

[0148] When -NVL < Vdc_up and Vdc_dn < NVL, let NVflag = 0.

[0149] Among them, Vdc_up represents the capacitor voltage of the upper bridge arm on the DC side of the three-level converter, simply referred to as the upper bridge arm voltage, Vdc_dn represents the capacitor voltage of the lower bridge arm on the DC side of the three-level converter, simply referred to as the lower bridge arm voltage, NVL is the unbalanced neutral point voltage limit value, that is, the deviation threshold, and NVflag represents the neutral point voltage balance flag bit. When the absolute value of the voltage difference is greater than the deviation threshold, if the sign of the voltage difference is positive, NVflag is 1, if the sign of the voltage difference is negative, NVflag is -1, and if the absolute value of the voltage difference is not greater than the deviation threshold, NVflag is 0, and the zero-sequence component maintains its original state.

[0150] Similarly, the sign of the current target current can also be recorded by means of flag values. For example:

[0151] If the current phase is between 60 and 120 degrees or 240 and 300 degrees, the current target current is the A-phase current Ia of the three-level converter. If Ia > 0, let Inflag = 1, otherwise let Inflag = -1;

[0152] If the current phase is between 120 and 180 degrees or between 300 and 360 degrees, the current target current is the C-phase current Ic of the three-level converter. If Ic>0, set Inflag=1, otherwise set Inflag=-1;

[0153] If the current phase is between 180 and 240 degrees or between 0 and 60 degrees, the current target current is the B-phase current Ib of the three-level converter. If Ib>0, Inflag=1, otherwise Inflag=-1.

[0154] Among them, Inflag is used as the current target current flag bit, indicating the sign of the current target current. If the current target current is positive, Inflag is 1, otherwise Inflag is -1.

[0155] Furthermore, when judging the first condition, there is a judgment on whether the sign of the voltage difference is the same as the sign of the current target current. At this time, it can be determined by whether the product of NVflag and Inflag is positive. If NVflag*Inflag>0, the signs are the same, otherwise the signs are opposite.

[0156] The embodiment of the present invention discloses a specific synchronous carrier DPWM midpoint voltage balancing method. Compared with the previous embodiment, this embodiment further illustrates and optimizes the technical solution.

[0157] The embodiment of the present invention uses PSIM software to build a three-level converter model, and uses simulation to verify the effectiveness of the three-level converter synchronous carrier DPWM midpoint voltage balancing method of the present invention. The simulation conditions of the embodiment are: the simulation step size is set to 1us, the DC side voltage is set to 5000V, the DC side capacitance is 16.2mF, and the fundamental frequency is set to 50Hz.

[0158] See also Figure 6a , Figure 6b , Figure 6c , the corresponding simulation conditions are the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 18, the modulation ratio is 0.85, the power factor is 0.6, and the simulation results of the synchronous carrier DPWM 1; among them, Figure 6a The upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, the phase voltage and the modulation wave of the DC side when the method of this embodiment is not implemented, Figure 6b After implementing the method of this embodiment, the DC side upper bridge arm capacitor voltage and lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag are: Figure 6c is the line voltage FFT analysis result. Figure 6aIt can be seen that when the modulation strategy of the three-level converter is synchronous carrier DPWM 1, if the method is not implemented to balance the midpoint voltage, the deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side will always exist, causing the switching device to withstand excessive voltage, endangering the safe operation of the three-level converter. Figure 6a and Figure 6b After adding the midpoint voltage balance control method of the present invention, the synchronous carrier DPWM 1 switches the zero-sequence component according to the midpoint voltage flag, and can control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to gradually restore the balance while reducing the switching frequency, thereby reducing the harm of midpoint voltage imbalance and improving the safety and reliability of the three-level converter. In addition, Figure 6c It is shown that the method of the present application can eliminate the harmonics of multiples of three and even harmonics in the line voltage while balancing the midpoint voltage. The corresponding output voltage waveform satisfies half-wave symmetry and three-phase symmetry, retaining the advantages of the original DPWM.

[0159] See also Figure 7 As shown, Figure 7 The simulation conditions are that the initial voltage of the upper bridge arm capacitor on the DC side is 500V, the initial voltage of the lower bridge arm capacitor is 4500V, the carrier ratio is 12, the modulation ratio is 0.35, the power factor is 0.8, and the DC side upper bridge arm capacitor voltage and lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag are analyzed when the synchronous carrier DPWM2 implements the method of the present application. Figure 7 After the method of the present application is implemented at the starting point, the synchronous carrier DPWM 2 switches the zero-sequence component according to the midpoint voltage flag, which can effectively control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to restore balance, thereby improving the safety of the three-level converter. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM 2, the method of the present application always clamps the phase voltage at the N level, thereby reducing the switching frequency while balancing the midpoint voltage, and retaining the advantages of the original DPWM.

[0160] See also Figure 8 As shown, Figure 8 The simulation conditions are that the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 6, the modulation ratio is 0.4, the power factor is 0.95, and the DC side upper bridge arm capacitor voltage and lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the synchronous carrier DPWM3 when implementing the method of the present application. Figure 8It can be seen that when there is a deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, the method of the present application is implemented on the synchronous carrier DPWM 3, which can effectively control the midpoint voltage to restore balance, thereby improving the safety of the three-level converter. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM3, the method of the present application always clamps the phase voltage at the P level, so the method of the present application can reduce the switching frequency while balancing the midpoint voltage, retaining the advantages of the original DPWM.

[0161] See also Fig. 9 As shown, Fig. 9 The simulation conditions are that the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 24, the modulation ratio is 0.7, the power factor is 0.4, and the synchronous carrier DPWM4 is used to analyze the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side when implementing the method of the present application. Fig. 9 , the method of the present application is implemented on the synchronous carrier DPWM 4, which can effectively control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to restore balance. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM 4, the method of the present application can clamp the phase voltage at the P level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0162] See also Fig.10 As shown, Fig.10 The simulation conditions are that the initial voltage of the upper bridge arm capacitor on the DC side is 500V, the initial voltage of the lower bridge arm capacitor is 4500V, the carrier ratio is 30, the modulation ratio is 0.4, the power factor is 0.8, and the synchronous carrier DPWM A is used to calculate the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side after implementing the method of the present application. Fig.10 It can be seen that when there is a deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, the midpoint voltage can be effectively controlled to restore balance by implementing the method of the present application on the synchronous carrier DPWM A. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM A, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0163] See also Fig.11 As shown, Fig.11 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 6, the modulation ratio is 0.45, the power factor is 0.6, and the synchronous carrier DPWM B is used to analyze the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side after implementing the method of this application. Fig.11, the method of the present application is implemented on the synchronous carrier DPWM B, which can effectively control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to restore balance. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM B, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0164] See also Fig.12 As shown, Fig.12 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 12, the modulation ratio is 0.4, the power factor is 0.4, and the synchronous carrier DPWM C is used to calculate the DC side upper bridge arm capacitor voltage and lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag after implementing the method of the present application. Fig.12 It can be seen that when there is a deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, the method of the present application can be implemented on the synchronous carrier DPWM C to effectively control the midpoint voltage to restore balance. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM C, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0165] See also Fig.13 As shown, Fig.13 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 500V, the initial voltage of the lower bridge arm capacitor is 4500V, the carrier ratio is 24, the modulation ratio is 0.3, the power factor is 0.95, and the synchronous carrier DPWM D is used to analyze the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side after implementing the method of this application. Fig.13 , the method of the present application is implemented on the synchronous carrier DPWM D, which can effectively control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to restore balance. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM D, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0166] See also Fig.14 As shown, Fig.14 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 500V, the initial voltage of the lower bridge arm capacitor is 4500V, the carrier ratio is 12, the modulation ratio is 0.3, the power factor is 0.95, and the synchronous carrier DPWM E is used to calculate the DC side upper bridge arm capacitor voltage and lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag after implementing the method of the present application. Fig.14It can be seen that when there is a deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, the midpoint voltage can be effectively controlled to restore balance by implementing the method of the present application on the synchronous carrier DPWM E. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM E, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0167] See also Fig.15 As shown, Fig.15 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 4500V, the initial voltage of the lower bridge arm capacitor is 500V, the carrier ratio is 12, the modulation ratio is 0.45, the power factor is 0.95, and the synchronous carrier DPWM F is used to analyze the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side after implementing the method of this application. Fig.15 , the method of the present application is implemented on the synchronous carrier DPWM F, which can effectively control the DC side upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage to restore balance. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM F, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0168] See also Fig.16 As shown, Fig.16 The simulation environment is that the initial voltage of the upper bridge arm capacitor on the DC side is 500V, the initial voltage of the lower bridge arm capacitor is 4500V, the carrier ratio is 18, the modulation ratio is 0.35, the power factor is 0.6, and the synchronous carrier DPWM G is used to calculate the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage, phase voltage, modulation wave and midpoint voltage flag of the DC side after implementing the method of the present application. Fig.16 It can be seen that when there is a deviation between the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, the midpoint voltage can be effectively controlled to restore balance by implementing the method of the present application on the synchronous carrier DPWM G. In addition, in the process of balancing the midpoint voltage of the synchronous carrier DPWM G, the method of the present application can clamp the phase voltage at the 0 level, thereby reducing the switching frequency and retaining the advantages of the original DPWM.

[0169] Further analysis Figure 6b to Figure 16The embodiment results show that for synchronous carrier DPWM 1, synchronous carrier DPWM 2, synchronous carrier DPWM 3, synchronous carrier DPWM 4, synchronous carrier DPWM A, synchronous carrier DPWM B, synchronous carrier DPWM C, synchronous carrier DPWM D, synchronous carrier DPWM E, synchronous carrier DPWM F and synchronous carrier DPWM G, the method of the present application can effectively control the midpoint voltage balance of the synchronous carrier DPWM under different deviation directions of the upper bridge arm capacitor voltage and the lower bridge arm capacitor voltage on the DC side, different carrier ratios, different modulation ratios and different power factors. In addition, the method of the present application switches the zero-sequence component according to the midpoint voltage flag, and uses the zero-sequence component to obtain a three-phase modulation wave, thereby controlling the midpoint voltage balance. It does not require a PI controller in the balance control process, and has the advantages of simple calculation and convenient application.

[0170] Correspondingly, the embodiment of the present application also discloses a synchronous carrier DPWM midpoint voltage balancing system, which is applied to the modulation process of a three-level converter, see Fig.17 As shown, including:

[0171] The first module 1 is used to obtain the current synchronous carrier DPWM type;

[0172] The second module 2 is used to obtain the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculate the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage;

[0173] A judging module 3 is used to judge whether the absolute value of the voltage difference is greater than a deviation threshold, and if so, trigger a determining module 4;

[0174] The determination module 4 is used to determine the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference;

[0175] An action module 5, configured to determine a three-phase modulation wave according to the zero-sequence component to control the three-level converter;

[0176] The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G.

[0177] When the absolute value of the voltage difference is greater than the deviation threshold, that is, when a midpoint voltage deviation occurs, the present application determines the zero-sequence component according to the current synchronous carrier DPWM type and the voltage difference, and determines the three-phase modulation wave with the zero-sequence component, thereby eliminating the midpoint voltage deviation and achieving midpoint voltage balance.

[0178] In some specific embodiments, the synchronous carrier DPWM midpoint voltage balancing system further includes a third module, which is used to:

[0179] Determine whether the current synchronous carrier DPWM type needs to obtain operating parameters;

[0180] If yes, obtaining the corresponding operating parameters according to the current synchronous carrier DPWM type;

[0181] Accordingly, the determining module 4 is specifically used for:

[0182] The zero-sequence component is determined according to the current synchronous carrier DPWM type, the operating parameter and the sign of the voltage difference.

[0183] In some specific embodiments, if the current synchronous carrier DPWM type is any one of DPWM1, DPWM2, DPWM3, and DPWM4, the operating parameters include a current modulation ratio; if the current modulation ratio is not less than a preset modulation ratio, the operating parameters also include a current target current and a current phase angle;

[0184] Accordingly, the determining module 4 is specifically used for:

[0185] When the current modulation ratio is less than the preset modulation ratio, if the sign of the voltage difference is positive, the zero-sequence component is determined to be 1-Vmax; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmin-1;

[0186] When the current modulation ratio is not less than the preset modulation ratio, determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in a target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0187] If yes, then the zero-sequence component is determined to be -Umin;

[0188] If not, then determine that the zero-sequence component is 1-Umax;

[0189] Wherein, Vmin is the minimum value of the three-phase sinusoidal modulation wave, Vmax is the maximum value of the three-phase sinusoidal modulation wave, Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after the three-phase sinusoidal modulation wave is processed, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulation wave;

[0190] The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively;

[0191] When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter;

[0192] When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0193] When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0194] In some specific embodiments, if the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWMC, and DPWM D, the operating parameters include a current target current and a current phase angle;

[0195] Accordingly, the determining module 4 is specifically used for:

[0196] Determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in the target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region;

[0197] If yes, then the zero-sequence component is determined to be -Umin;

[0198] If not, then determine that the zero-sequence component is 1-Umax;

[0199] Wherein, Umin is the minimum value of the processed modulated wave, Umax is the maximum value of the processed modulated wave, the processed modulated wave is the modulated wave after processing the three-phase sinusoidal modulated wave, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulated wave;

[0200] The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively;

[0201] When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter;

[0202] When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter;

[0203] When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

[0204] In some specific embodiments, if the current synchronous carrier is any one of DPWM E, DPWM F, and DPWM G, the process in which the determination module 4 determines the zero-sequence component according to the type of the current synchronous carrier DPWM and the sign of the voltage difference includes:

[0205] If the sign of the voltage difference is positive, the zero-sequence component is determined to be -Vmin; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmax;

[0206] Among them, Vmin is the minimum value of the three-phase sinusoidal modulation wave, and Vmax is the maximum value of the three-phase sinusoidal modulation wave.

[0207] In some specific embodiments, the action module 5 is specifically used to:

[0208] A three-phase modulation wave after a sampling point is determined according to the zero-sequence component to control the three-level converter.

[0209] In some specific embodiments, the first module 1 is specifically used for:

[0210] According to the phase voltage clamping state, the current synchronous carrier DPWM type is determined.

[0211] Correspondingly, the embodiment of the present application further discloses a synchronous carrier DPWM midpoint voltage balancing device, comprising:

[0212] Memory for storing computer programs;

[0213] A processor is used to implement the steps of the synchronous carrier DPWM midpoint voltage balancing method as described in any of the above embodiments when executing the computer program.

[0214] Correspondingly, an embodiment of the present application further discloses a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the carrier DPWM modulation method in any of the above embodiments are implemented.

[0215] For details about the synchronous carrier DPWM midpoint voltage balancing method, please refer to the relevant description in the above embodiment, which will not be repeated here.

[0216] Among them, the synchronous carrier DPWM midpoint voltage balancing device and the readable storage medium described in this embodiment have the same technical effects as the synchronous carrier DPWM midpoint voltage balancing method described in the above embodiments, and will not be repeated here.

[0217] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0218] The above is a detailed introduction to a synchronous carrier DPWM midpoint voltage balancing method, system and related components provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A synchronous carrier DPWM midpoint voltage balancing method, characterized in that: The modulation process applied to the three-level converter includes: Get the current synchronous carrier DPWM type; Obtaining an upper bridge arm voltage and a lower bridge arm voltage on a DC side, and calculating a voltage difference between the upper bridge arm voltage and the lower bridge arm voltage; Determining whether the absolute value of the voltage difference is greater than a deviation threshold; If so, determining a zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference; Determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter; The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G; and further includes: Determine whether the current synchronous carrier DPWM type needs to obtain operating parameters; If yes, obtaining the corresponding operating parameters according to the current synchronous carrier DPWM type; Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference includes: Determine the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference; wherein: If the current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, and DPWM 4, it is necessary to obtain operating parameters, and the operating parameters at least include the current modulation ratio. If the current modulation ratio is not less than the preset modulation ratio, other operating parameters are obtained, and the obtained operating parameters include the current target current and the current phase angle; If the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWM C, and DPWM D, it is necessary to obtain operating parameters, which include the current target current and the current phase angle; If the current synchronous carrier DPWM type is any one of DPWM E, DPWM F, and DPWM G, the zero-sequence component can be directly determined without obtaining the operating parameters.

2. The synchronous carrier DPWM midpoint voltage balancing method according to claim 1, characterized in that: If the current synchronous carrier DPWM type is any one of DPWM1, DPWM2, DPWM3, and DPWM4, the operating parameters include the current modulation ratio; if the current modulation ratio is not less than the preset modulation ratio, the operating parameters also include the current target current and the current phase angle; Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference includes: When the current modulation ratio is less than the preset modulation ratio, if the sign of the voltage difference is positive, the zero-sequence component is determined to be 1-Vmax; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmin-1; When the current modulation ratio is not less than the preset modulation ratio, determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in a target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region; If yes, then the zero-sequence component is determined to be -Umin; If not, then determine that the zero-sequence component is 1-Umax; Wherein, Vmin is the minimum value of the three-phase sinusoidal modulation wave, Vmax is the maximum value of the three-phase sinusoidal modulation wave, Umin is the minimum value of the processed modulation wave, Umax is the maximum value of the processed modulation wave, and the processed modulation wave is the modulation wave after the three-phase sinusoidal modulation wave is processed, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulation wave; The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively; When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter; When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter; When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

3. The synchronous carrier DPWM midpoint voltage balancing method according to claim 1, characterized in that: If the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWM C, and DPWM D, the operating parameters include the current target current and the current phase angle; Accordingly, the process of determining the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference includes: Determining whether a first condition is satisfied, the first condition comprising: the sign of the voltage difference is the same as the sign of the current target current and the current phase angle is in the target phase angle region, or the sign of the voltage difference is opposite to the sign of the current target current and the current phase angle is not in the target phase angle region; If yes, then the zero-sequence component is determined to be -Umin; If not, then determine that the zero-sequence component is 1-Umax; Wherein, Umin is the minimum value of the processed modulated wave, Umax is the maximum value of the processed modulated wave, the processed modulated wave is the modulated wave after processing the three-phase sinusoidal modulated wave, and the processing includes: adding a reference voltage value to the negative value of the three-phase sinusoidal modulated wave; The target phase angle region includes three target phase angle partitions, and the three target phase angle partitions are 0°-60°, 120°-180° and 240°-300° respectively; When the current phase angle is between 60° and 120° or between 240° and 300°, the current target current is the A-phase current of the three-level converter; When the current phase angle is between 120° and 180° or between 300° and 360°, the current target current is the C-phase current of the three-level converter; When the current phase angle is between 180° and 240° or between 0° and 60°, the current target current is the B-phase current of the three-level converter.

4. The synchronous carrier DPWM midpoint voltage balancing method according to claim 1, characterized in that: If the current synchronous carrier is any one of DPWM E, DPWM F, and DPWM G, the process of determining the zero-sequence component according to the type of the current synchronous carrier DPWM and the sign of the voltage difference includes: If the sign of the voltage difference is positive, the zero-sequence component is determined to be -Vmin; if the sign of the voltage difference is negative, the zero-sequence component is determined to be -Vmax; Among them, Vmin is the minimum value of the three-phase sinusoidal modulation wave, and Vmax is the maximum value of the three-phase sinusoidal modulation wave.

5. The synchronous carrier DPWM midpoint voltage balancing method according to any one of claims 1 to 4, characterized in that: The process of determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter includes: A three-phase modulation wave after a sampling point is determined according to the zero-sequence component to control the three-level converter.

6. The synchronous carrier DPWM midpoint voltage balancing method according to claim 5, characterized in that: The process of obtaining the current synchronous carrier DPWM type includes: According to the current phase voltage clamping state, the current synchronous carrier DPWM type is determined.

7. A synchronous carrier DPWM midpoint voltage balance system, characterized in that: The modulation process applied to the three-level converter includes: The first module is used to obtain the current synchronous carrier DPWM type; The second module is used to obtain the upper bridge arm voltage and the lower bridge arm voltage on the DC side, and calculate the voltage difference between the upper bridge arm voltage and the lower bridge arm voltage; A judging module, used for judging whether the absolute value of the voltage difference is greater than a deviation threshold, and if so, triggering a determining module; The determination module is used to determine the zero-sequence component according to the current synchronous carrier DPWM type and the sign of the voltage difference; An action module, used for determining a three-phase modulation wave according to the zero-sequence component to control the three-level converter; The current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, DPWM 4, DPWM A, DPWM B, DPWM C, DPWM D, DPWM E, DPWM F, and DPWM G; wherein: The judging module is further used to judge whether the current synchronous carrier DPWM type needs to obtain operating parameters; If yes, obtaining the corresponding operating parameters according to the current synchronous carrier DPWM type; Accordingly, the determining module is used to: Determine the zero-sequence component according to the current synchronous carrier DPWM type, the operating parameters and the sign of the voltage difference; wherein: If the current synchronous carrier DPWM type is any one of DPWM 1, DPWM 2, DPWM 3, and DPWM 4, it is necessary to obtain operating parameters, and the operating parameters at least include the current modulation ratio. If the current modulation ratio is not less than the preset modulation ratio, other operating parameters are obtained, and the obtained operating parameters include the current target current and the current phase angle; If the current synchronous carrier DPWM type is any one of DPWM A, DPWM B, DPWM C, and DPWM D, it is necessary to obtain operating parameters, which include the current target current and the current phase angle; If the current synchronous carrier DPWM type is any one of DPWM E, DPWM F, and DPWM G, the zero-sequence component can be directly determined without obtaining the operating parameters.

8. A synchronous carrier DPWM midpoint voltage balancing device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the synchronous carrier DPWM midpoint voltage balancing method as claimed in any one of claims 1 to 6 when executing the computer program.

9. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the synchronous carrier DPWM midpoint voltage balancing method according to any one of claims 1 to 6 are implemented.

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