Input stage circuit and amplifier

Abstract

The present invention discloses an input stage circuit and an amplifier. The input stage circuit includes: an input ESD protection circuit, a DC clamping circuit, and an AC clamping circuit that are connected. The AC clamping circuit includes an auxiliary source follow circuit and a high-pass filter circuit that are connected to the input ESD protection circuit and the DC clamping circuit. The DC clamping circuit, the auxiliary source follow circuit, and the high-pass filter circuit are used to reduce the equivalent input capacitance of the input ESD protection circuit. According to the input stage circuit of the embodiment of the present invention, through the DC clamping circuit and the AC clamping circuit, the voltages across the parasitic capacitances of the respective devices of the input ESD protection circuit follow each other, suppressing the charging and discharging of these parasitic capacitances during signal input, reducing the equivalent input capacitance of the input stage circuit, and greatly improving the closed-loop bandwidth, stability, and noise performance of the transimpedance amplifier.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an input-stage circuit and an amplifier. Background Art

[0002] The input capacitance of an amplifier comes from the parasitic capacitance of the internal input ESD protection circuit and the parasitic capacitances between the gate and source, gate and drain, gate and substrate, and drain and source of the input-stage MOS transistors. In the transimpedance closed-loop application of a high-speed, low-noise amplifier, a large input capacitance will limit the closed-loop bandwidth, stability, and noise performance of the transimpedance amplifier.

[0003] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of implication that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0004] An object of the present invention is to provide an input-stage circuit and an amplifier, which can improve the closed-loop bandwidth, stability, and noise performance of a transimpedance amplifier.

[0005] To achieve the above object, an embodiment of the present invention provides an input-stage circuit, including: an input ESD protection circuit, a DC clamping circuit, and an AC clamping circuit connected in sequence. The AC clamping circuit includes an auxiliary source follow circuit and a high-pass filter circuit connected to the input ESD protection circuit and the DC clamping circuit. The DC clamping circuit, the auxiliary source follow circuit, and the high-pass filter circuit are used to reduce the equivalent input capacitance of the input ESD protection circuit.

[0006] In one or more embodiments of the present invention, the DC clamping circuit includes a unit buffer. The negative input terminal of the unit buffer is connected to the output terminal and is connected to the auxiliary source follow circuit and the input ESD protection circuit through the high-pass filter circuit. The auxiliary source follow circuit is simultaneously connected to the positive input terminal of the unit buffer and the input ESD protection circuit.

[0007] In one or more embodiments of the present invention, the high-pass filter circuit includes a capacitor C and a resistor R1. One end of the capacitor C is connected to the auxiliary source follow circuit, the other end is connected to one end of the resistor R1 and the input ESD protection circuit, and the other end of the resistor R1 is connected to the output terminal of the unit buffer.

[0008] In one or more embodiments of the present invention, the input ESD protection circuit includes diode V1, diode V2, diode V3, and diode V4. The anode of diode V1 is connected to the cathode of diode V2 and to the high-pass filter circuit. The anode of diode V2 is connected to the cathode of diode V3 and to the Pin input terminal Input, as well as to the positive input terminal of the auxiliary source follow circuit and the unit buffer. The anode of diode V3 is connected to the cathode of diode V4 and to the high-pass filter circuit. The anode of diode V4 is grounded. The cathode of diode V1 is connected to the power supply AVDD.

[0009] In one or more embodiments of the present invention, the input stage circuit further includes a signal input circuit connected to the input ESD protection circuit. The signal input circuit includes a main source follow circuit, a first sub-source follow circuit and a second sub-source follow circuit connected to the main source follow circuit. The first sub-source follow circuit and the second sub-source follow circuit are used to reduce the equivalent input capacitance of the main source follow circuit.

[0010] In one or more embodiments of the present invention, the main source follow circuit includes PMOS transistor PM0, current source circuit lp1, and current source circuit ln2;

[0011] The source of PMOS transistor PM0 is connected to the first sub-source follow circuit, the current source circuit lp1, and the output terminal OUTPUT. The current source circuit lp1 is also connected to the power supply AVDD. The drain of PMOS transistor PM0 is connected to the first sub-source follow circuit and the current source circuit ln2. The current source circuit ln2 is grounded to AVSS. The gate of PMOS transistor PM0 is connected to the input terminal INPUT and the second sub-source follow circuit. The substrate of PMOS transistor PM0 is connected to the second sub-source follow circuit.

[0012] In one or more embodiments of the present invention, the first sub-source follow circuit includes NMOS transistor NM1 and current source circuit ln1;

[0013] The drain of the NMOS transistor NM1 is connected to the power supply AVDD. The source of the NMOS transistor NM1 is connected to the current source circuit ln1 and the drain of the PMOS transistor PM0. The current source circuit ln1 is grounded to AVSS at the same time. The substrate of the NMOS transistor NM1 is grounded to AVSS or connected to the source of the NMOS transistor NM1. The gate of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM0.

[0014] In one or more embodiments of the present invention, the first sub-source follow circuit further includes a PMOS transistor PM3, a resistor R2, and a current source circuit lp3;

[0015] The current source circuit lp3 is connected between the drain of the NMOS transistor NM1 and the power supply AVDD. The source of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM1. The gate of the PMOS transistor PM3 is connected to the source of the NMOS transistor NM1. The drain of the PMOS transistor PM3 is grounded to AVSS through the resistor R2. The substrate of the PMOS transistor PM3 is connected to the power supply AVDD or connected to the source of the PMOS transistor PM3.

[0016] In one or more embodiments of the present invention, the second sub-source follow circuit includes a PMOS transistor PM6, a current source circuit lp2, and a current source circuit ln3;

[0017] The source of the PMOS transistor PM6 is connected to the substrate of the PMOS transistor PM0 and the current source circuit lp2. The current source circuit lp2 is connected to the power supply AVDD at the same time. The gate of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM0. The drain of the PMOS transistor PM6 is connected to the current source circuit ln3. The current source circuit ln3 is grounded to AVSS at the same time. The substrate of the PMOS transistor PM6 is connected to the source of the PMOS transistor PM6 or connected to the power supply AVDD.

[0018] In one or more embodiments of the present invention, the second sub-source follow circuit further includes an NMOS transistor NM4, a resistor R3, and a current source circuit ln4;

[0019] The source of the NMOS transistor NM4 is connected to the power supply AVDD through the resistor R3. The gate of the NMOS transistor NM4 is connected to the source of the PMOS transistor PM6. The source of the NMOS transistor NM4 is connected to the current source circuit ln4 and the drain of the PMOS transistor PM6. The substrate of the NMOS transistor NM4 is grounded to AVSS or connected to the source of the NMOS transistor NM4.

[0020] In one or more embodiments of the present invention, the circuit structures of the auxiliary source follow circuit and the main source follow circuit are the same, and the equivalent input capacitance of the auxiliary source follow circuit is reduced by the same connection method as that of the first sub-source follow circuit and the second sub-source follow circuit.

[0021] The present invention also provides an amplifier, including the input stage circuit described above.

[0022] Compared with the prior art, for the input stage circuit and the amplifier according to the embodiments of the present invention, through the DC clamping circuit and the AC clamping circuit, the voltages across the parasitic capacitances of the respective devices of the input ESD protection circuit follow each other, suppressing the charging and discharging of these parasitic capacitances during signal input, reducing the equivalent input capacitance of the input stage circuit, and greatly improving the closed-loop bandwidth, stability and noise performance of the transimpedance amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a system diagram of an input stage circuit according to an embodiment of the present invention.

[0024] Figure 2 is a circuit schematic diagram of an input ESD protection circuit, a DC clamping circuit and an AC clamping circuit according to an embodiment of the present invention.

[0025] Figure 3 is a first circuit schematic diagram of a signal input circuit according to an embodiment of the present invention;

[0026] Figure 4 is a second circuit schematic diagram of a signal input circuit according to an embodiment of the present invention;

[0027] Figure 5 is a first specific circuit schematic diagram of a signal input circuit according to an embodiment of the present invention;

[0028] Figure 6 is a second specific circuit schematic diagram of a signal input circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0030] Unless otherwise clearly stated, throughout the specification and claims, the term "comprise" or its variations such as "comprises" or "comprising" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0031] Example 1

[0032] As Figure 1 、 Figure 2 and Figure 3 shown, an input-stage circuit includes: an input ESD protection circuit 10, a DC clamping circuit, an AC clamping circuit, and a signal input circuit 20 that are connected. The DC clamping circuit includes a unit buffer. The AC clamping circuit includes an auxiliary source follow circuit and a high-pass filter circuit 30. The signal input circuit 20 includes a main source follow circuit 21, a first sub-source follow circuit 22 and a second sub-source follow circuit 23 that are connected to the main source follow circuit 21.

[0033] Among them, the DC clamping circuit and the AC clamping circuit are used to reduce the equivalent input capacitance of the input ESD protection circuit 10. By the DC clamping circuit and the AC clamping circuit, the voltages across the parasitic capacitances of the devices of the input ESD protection circuit 10 follow each other, that is, the voltage difference across the parasitic capacitances of the devices of the input ESD protection circuit 10 can be kept constant, thereby reducing the capacitance effect. The first sub-source follow circuit 22 and the second sub-source follow circuit 23 are used to reduce the equivalent input capacitance of the main source follow circuit 21.

[0034] As Figure 2 shown, the negative input terminal of the unit buffer is connected to the output terminal and is connected to the auxiliary source follow circuit and the input ESD protection circuit 10 through the high-pass filter circuit 30. The auxiliary source follow circuit is simultaneously connected to the input ESD protection circuit 10 and the positive input terminal of the unit buffer.

[0035] As Figure 2 shown, the input ESD protection circuit 10 includes a diode V1, a diode V2, a diode V3, and a diode V4. The anode of the diode V1 is connected to the cathode of the diode V2. The anode of the diode V2 is connected to the cathode of the diode V3 and is connected to the Pin input terminal Input. The anode of the diode V3 is connected to the cathode of the diode V4, and the anode of the diode V4 is grounded. The cathode of the diode V1 is connected to the power supply AVDD.

[0036] The high-pass filter circuit 30 includes a capacitor C and a resistor R1. Specifically, one end of the capacitor C is connected to the auxiliary source follow circuit, and the other end is connected to one end of the resistor R1, the anode of the diode V1, and the cathode of the diode V2. The other end of the resistor R1 is connected to the output end of the unit buffer. The positive input end of the unit buffer is connected to the anode of the diode V2 and the cathode of the diode V3.

[0037] In this embodiment, the unit buffer is used to make the DC voltage of each node between the serially connected diodes V1, V2, V3, and V4 equal to the DC voltage of the input signal. The auxiliary source follow circuit and the high-pass filter circuit 30 are used to make the AC voltage of each node between the serially connected diodes V1, V2, V3, and V4 equal to the AC voltage of the input signal.

[0038] In summary, through the combined clamping of the auxiliary source follow circuit, the unit buffer, and the high-pass filter circuit 30 composed of the capacitor C and the resistor R1, the voltage difference between the two ends (the upper plate and the lower plate) of each parasitic capacitor between the diodes V1, V2, V3, and V4 is kept constant during the input signal process, that is, the voltages at the two ends (the upper plate and the lower plate) of each parasitic capacitor follow each other.

[0039] As Figure 3 shown, the main source follow circuit 21 includes a PMOS transistor PM0, a current source circuit lp1, and a current source circuit ln2.

[0040] Specifically, the source of the PMOS transistor PM0 is connected to the first sub-source follow circuit 21, the current source circuit lp1, and the output terminal OUTPUT. The current source circuit lp1 is also connected to the power supply AVDD. The drain of the PMOS transistor PM0 is connected to the first sub-source follow circuit 22 and the current source circuit ln2. The current source circuit ln2 is grounded to AVSS. The gate of the PMOS transistor PM0 is connected to the input terminal INPUT and the second sub-source follow circuit 23. The substrate of the PMOS transistor PM0 is connected to the second sub-source follow circuit 23.

[0041] In this embodiment, the current source circuit lp1 includes one or two PMOS transistors. As Figure 5 shown, when there are two PMOS transistors, the two PMOS transistors are the PMOS transistor PM01 and the PMOS transistor PM02 respectively.

[0042] Specifically, the source of PMOS transistor PM01 is connected to power supply AVDD, and the drain of PMOS transistor PM01 is connected to the source of PMOS transistor PM02. The substrates of PMOS transistor PM01 and PMOS transistor PM02 are both connected to the source of PMOS transistor PM01. The drain of PMOS transistor PM02 is connected to output terminal OUTPUT and the source of PMOS transistor PM0. When only one PMOS transistor is used, only PMOS transistor PM02 needs to be removed.

[0043] In other embodiments, more than two PMOS transistors can be used or a current source circuit lp1 with other structures can be adopted.

[0044] In this embodiment, current source circuit ln2 includes one or two NMOS transistors. As Figure 5 shown, when there are two NMOS transistors, the two NMOS transistors are NMOS transistor NM01 and NMOS transistor NM02 respectively.

[0045] Specifically, the drain of NMOS transistor NM01 is connected to the drain of PMOS transistor PM0, the source of NMOS transistor NM01 is connected to the drain of NMOS transistor NM02, the source of NMOS transistor NM02 is grounded to AVSS, and the substrates of NMOS transistor NM01 and NMOS transistor NM02 are both connected to the source of NMOS transistor NM02. When only one NMOS transistor is used, only NMOS transistor NM01 needs to be removed.

[0046] In other embodiments, more than two NMOS transistors can be used or a current source circuit ln2 with other structures can be adopted.

[0047] As Figure 3 shown, the first sub-source follow circuit 22 includes NMOS transistor NM1 and current source circuit ln1.

[0048] The drain of NMOS transistor NM1 is connected to power supply AVDD, the source of NMOS transistor NM1 is connected to current source circuit ln1 and the drain of PMOS transistor PM0, and current source circuit ln1 is grounded to AVSS at the same time. The gate of NMOS transistor NM1 is connected to the source of PMOS transistor PM0. Among them, the function of NMOS transistor NM1 is to reduce the capacitance effect between the gate and drain of PM0.

[0049] As Figure 3 、 Figure 4 and Figure 6 shown, the substrate of NMOS transistor NM1 is connected to the source of NMOS transistor NM1, that is, the voltage between the substrate and source of NMOS transistor NM1 is 0V, so as to reduce the body bias effect of NMOS transistor NM1.

[0050] As Figure 5As shown, the substrate of the NMOS transistor NM1 can be grounded to AVSS.

[0051] In this embodiment, the current source circuit ln1 includes one or two NMOS transistors. As Figure 5 shown, when two NMOS transistors are used, the two NMOS transistors are NMOS transistor NM2 and NMOS transistor NM3 respectively.

[0052] The drain of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM1, and the source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM3. The source of the NMOS transistor NM3 is grounded to AVSS, and the substrates of the NMOS transistor NM2 and the NMOS transistor NM3 are both connected to the source of the NMOS transistor NM3. When only one NMOS transistor is used, only the NMOS transistor NM2 needs to be removed.

[0053] In other embodiments, more than two NMOS transistors can be used or a current source circuit ln1 with other structures can be adopted.

[0054] As Figure 4 shown, in another embodiment, the first sub-source follow circuit 22 further includes a PMOS transistor PM3, a resistor R2, and a current source circuit lp3.

[0055] The current source circuit lp3 is connected between the drain of the NMOS transistor NM1 and the power supply AVDD. The source of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM1, the gate of the PMOS transistor PM3 is connected to the source of the NMOS transistor NM1, and the drain of the PMOS transistor PM3 is grounded to AVSS through the resistor R2. Among them, the function of the PMOS transistor PM3 is to reduce the capacitance effect between the gate and the drain of the NMOS transistor NM1.

[0056] As Figure 4 shown, the substrate of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM3, that is, the voltage between the source and the substrate of the PMOS transistor PM3 is 0V, so as to reduce the body bias effect of the PMOS transistor PM3.

[0057] As Figure 5 shown, the substrate of the PMOS transistor PM3 can be connected to the power supply AVDD.

[0058] In this embodiment, the current source circuit lp3 includes one or two PMOS transistors. As Figure 5 shown, when two PMOS transistors are used, the PMOS transistors include PMOS transistor PM1 and PMOS transistor PM2.

[0059] Specifically, the source of PMOS transistor PM1 is connected to power supply AVDD, the drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM2, the substrates of PMOS transistor PM1 and PMOS transistor PM2 are both connected to the source of PMOS transistor PM1, and the drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM1. When only one PMOS transistor is used, only PMOS transistor PM2 needs to be removed.

[0060] In other embodiments, more than two PMOS transistors can be used or a current source circuit lp3 with other structures can be adopted.

[0061] Such as Figure 3 shown, the second sub-source follow circuit 23 includes PMOS transistor PM6, current source circuit lp2, and current source circuit ln3.

[0062] Specifically, the source of PMOS transistor PM6 is connected to the substrate of PMOS transistor PM0 and current source circuit lp2, current source circuit lp2 is also connected to power supply AVDD, the gate of PMOS transistor PM6 is connected to the gate of PMOS transistor PM0, the drain of PMOS transistor PM6 is connected to current source circuit ln3, and current source circuit ln3 is also grounded to AVSS. Among them, PMOS transistor PM6 is used to reduce the capacitive effect between the gate and substrate of PMOS transistor PM0.

[0063] Such as Figure 3 and Figure 4 shown, the substrate of PMOS transistor PM6 is connected to the source of PMOS transistor PM6, that is, the voltage between the substrate and source of PMOS transistor PM6 is 0V, thereby reducing the body bias effect of PMOS transistor PM6.

[0064] Such as Figure 5 shown, the substrate of PMOS transistor PM6 can also be connected to power supply AVDD.

[0065] In this embodiment, current source circuit lp2 includes one or two PMOS transistors. Such as Figure 5 shown, when two PMOS transistors are used, the two PMOS transistors are PMOS transistor PM4 and PMOS transistor PM5 respectively.

[0066] Specifically, the source of PMOS transistor PM4 is connected to power supply AVDD, the drain of PMOS transistor PM4 is connected to the source of PMOS transistor PM5, the substrates of PMOS transistor PM4 and PMOS transistor PM5 are both connected to the source of PMOS transistor PM4. The drain of PMOS transistor PM5 is connected to the source of PMOS transistor PM6. When only one PMOS transistor is used, only PMOS transistor PM5 needs to be removed.

[0067] In other embodiments, more than two PMOS transistors may be employed or a current source circuit lp2 having other structures may be used.

[0068] In the present embodiment, the current source circuit ln3 includes one or two NMOS transistors. As Figure 5 shown, when two NMOS transistors are used, the two NMOS transistors are NMOS transistor NM5 and NMOS transistor NM6, respectively.

[0069] Specifically, the drain of NMOS transistor NM5 is connected to the drain of PMOS transistor PM6, the source of NMOS transistor NM5 is connected to the drain of NMOS transistor NM6, and the source of NMOS transistor NM6 is grounded to AVSS. The substrates of NMOS transistor NM5 and NMOS transistor NM6 are both connected to the source of NMOS transistor NM6. When only one NMOS transistor is used, only NMOS transistor NM5 needs to be removed.

[0070] In other embodiments, more than two NMOS transistors may be employed or a current source circuit ln3 having other structures may be used.

[0071] As Figure 4 shown, in another embodiment, the second sub source follow circuit further includes NMOS transistor NM4, resistor R3, and current source circuit ln4.

[0072] The source of NMOS transistor NM4 is connected to power supply AVDD through resistor R3, the gate of NMOS transistor NM4 is connected to the source of PMOS transistor PM6, and the source of NMOS transistor NM4 is connected to current source circuit ln4 and the drain of PMOS transistor PM6. Among them, the function of NMOS transistor NM4 is to reduce the capacitance effect between the gate and the substrate of PMOS transistor PM6.

[0073] As Figure 4 and Figure 6 shown, the substrate of NMOS transistor NM4 is connected to the source of NMOS transistor NM4, that is, the voltage between the substrate and the source of NMOS transistor NM4 is 0V, thereby reducing the body bias effect of NMOS transistor NM4.

[0074] As Figure 5 shown, the substrate of NMOS transistor NM4 may be grounded to AVSS.

[0075] In the present embodiment, the current source circuit ln4 includes one or two NMOS transistors. As Figure 5 shown, when two NMOS transistors are used, the two NMOS transistors are NMOS transistor NM7 and NMOS transistor NM8, respectively.

[0076] Specifically, the drain of NMOS transistor NM7 is connected to the source of NMOS transistor NM4. The source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM8, and the source of NMOS transistor NM8 is grounded to AVSS. The substrates of NMOS transistor NM7 and NMOS transistor NM8 are both connected to the source of NMOS transistor NM8. When only one NMOS transistor is used, only NMOS transistor NM7 needs to be removed.

[0077] In other embodiments, more than two NMOS transistors or a current source circuit ln4 with other structures can be used.

[0078] In this embodiment, the gate-drain voltage V gd , gate-substrate voltage V gb and drain-source voltage V ds of PMOS transistor PM0 in the main source follow circuit 21 are clamped by the first sub-source follow circuit 22 and the second sub-source follow circuit 23, respectively, to ensure that the gate-drain voltage V gd , gate-substrate voltage V gb , and drain-source voltage V ds of PMOS transistor PM0 remain unchanged during the input of the input signal. The connection mode of PMOS transistor PM0 in the main source follow circuit 21 in the circuit is a voltage follower structure, so its gate-source voltage V gs also remains unchanged during operation.

[0079] In this embodiment, the circuit structures of the auxiliary source follow circuit and the main source follow circuit 21 are the same, and the input equivalent capacitance of the auxiliary source follow circuit is reduced by the same connection method as that of the first sub-source follow circuit 22 and the second sub-source follow circuit 23. That is, the auxiliary source follow circuit and the main source follow circuit 21 share the first sub-source follow circuit 22 and the second sub-source follow circuit 23. Of course, in other embodiments, the sub-source follow circuit can also be set separately to reduce the input equivalent capacitance of the auxiliary source follow circuit.

[0080] Combined with Figure 4 , Figure 5 , Figure 6 and Figure 2 shown, the input terminal INPUT of the auxiliary source follow circuit is connected to the high-pass filter circuit 30, and the output terminal OUTPUT is connected to the positive pole of the unit buffer.

[0081] In addition, it should be noted that the PMOS transistor and the NMOS transistor in this embodiment are only an application mode of a component. In other embodiments, the two MOS transistors can be used interchangeably.

[0082] Other embodiments also disclose an amplifier, including the above input stage circuit.

[0083] The foregoing description of the specific exemplary embodiments of the present invention is for purposes of illustration and exemplification. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many changes and variations are possible in light of the above teaching. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical applications, so that those skilled in the art can implement and utilize the various different exemplary embodiments of the present invention, as well as various different selections and changes. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. An input-stage circuit, characterized in that, Comprising: Connected input ESD protection circuit, DC clamping circuit and AC clamping circuit. The AC clamping circuit includes an auxiliary source follow circuit and a high-pass filter circuit connected to the input ESD protection circuit and the DC clamping circuit. The DC clamping circuit, the auxiliary source follow circuit and the high-pass filter circuit are used to reduce the equivalent input capacitance of the input ESD protection circuit; The DC clamping circuit includes a unit buffer. The negative input terminal of the unit buffer is connected to the output terminal and is connected to the auxiliary source follow circuit and the input ESD protection circuit through the high-pass filter circuit. The auxiliary source follow circuit is simultaneously connected to the input ESD protection circuit and the positive input terminal of the unit buffer; The input ESD protection circuit includes diodes V1, V2, V3 and V4. The anode of diode V1 is connected to the cathode of diode V2 and is connected to the high-pass filter circuit. The anode of diode V2 is connected to the cathode of diode V3 and is connected to the Pin input terminal Input, as well as the positive input terminals of the auxiliary source follow circuit and the unit buffer. The anode of diode V3 is connected to the cathode of diode V4 and is connected to the high-pass filter circuit. The anode of diode V4 is grounded, and the cathode of diode V1 is connected to the power supply AVDD; The auxiliary source follow circuit includes a PMOS transistor PM0, a current source circuit lp1 and a current source circuit ln2; The source of the PMOS transistor PM0 is connected to the current source circuit lp1 and the output terminal OUTPUT. The output terminal OUTPUT is connected to the positive input terminal of the unit buffer. The current source circuit lp1 is simultaneously connected to the power supply AVDD. The drain of the PMOS transistor PM0 is connected to the current source circuit ln2. The current source circuit ln2 is grounded to AVSS. The gate of the PMOS transistor PM0 is connected to the input terminal INPUT. The input terminal INPUT is connected to the high-pass filter circuit.

2. The input stage circuit according to claim 1, wherein The high-pass filter circuit includes a capacitor C and a resistor R1. One end of the capacitor C is connected to the auxiliary source follow circuit, the other end is connected to one end of the resistor R1 and the input ESD protection circuit. The other end of the resistor R1 is connected to the output terminal of the unit buffer.

3. The input stage circuit according to claim 1, wherein The input stage circuit further includes a signal input circuit connected to the input ESD protection circuit. The signal input circuit includes a main source follow circuit, a first sub-source follow circuit and a second sub-source follow circuit connected to the main source follow circuit. The first sub-source follow circuit and the second sub-source follow circuit are used to reduce the equivalent input capacitance of the main source follow circuit.

4. The input stage circuit according to claim 3, characterized in that, The circuit structures of the main source follow circuit and the auxiliary source follow circuit are the same; The source of the PMOS transistor PM0 is connected to the first sub-source follow circuit, the current source circuit lp1 and the output terminal OUTPUT. The current source circuit lp1 is also connected to the power supply AVDD. The drain of the PMOS transistor PM0 is connected to the first sub-source follow circuit and the current source circuit ln2. The current source circuit ln2 is grounded to AVSS. The gate of the PMOS transistor PM0 is connected to the input terminal INPUT and the second sub-source follow circuit. The substrate of the PMOS transistor PM0 is connected to the second sub-source follow circuit.

5. The input stage circuit according to claim 4, wherein The first sub-source follow circuit includes an NMOS transistor NM1 and a current source circuit ln1; The drain of the NMOS transistor NM1 is connected to the power supply AVDD. The source of the NMOS transistor NM1 is connected to the current source circuit ln1 and the drain of the PMOS transistor PM0. The current source circuit ln1 is also grounded to AVSS. The substrate of the NMOS transistor NM1 is grounded to AVSS or connected to the source of the NMOS transistor NM1. The gate of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM0.

6. The input stage circuit according to claim 5, characterized in that, The first sub-source follow circuit further includes a PMOS transistor PM3, a resistor R2 and a current source circuit lp3; The current source circuit lp3 is connected between the drain of the NMOS transistor NM1 and the power supply AVDD. The source of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM1. The gate of the PMOS transistor PM3 is connected to the source of the NMOS transistor NM1. The drain of the PMOS transistor PM3 is grounded to AVSS through the resistor R2. The substrate of the PMOS transistor PM3 is connected to the power supply AVDD or connected to the source of the PMOS transistor PM3.

7. The input stage circuit according to claim 4, characterized in that, The second sub-source follow circuit includes a PMOS transistor PM6, a current source circuit lp2 and a current source circuit ln3; The source of the PMOS transistor PM6 is connected to the substrate of the PMOS transistor PM0 and the current source circuit lp2, the current source circuit lp2 is simultaneously connected to the power supply AVDD, the gate of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM0, the drain of the PMOS transistor PM6 is connected to the current source circuit ln3, the current source circuit ln3 is simultaneously grounded to AVSS, and the substrate of the PMOS transistor PM6 is connected to the source of the PMOS transistor PM6 or connected to the power supply AVDD.

8. The input stage circuit according to claim 7, characterized in that, The second sub-source follow circuit further includes an NMOS transistor NM4, a resistor R3, and a current source circuit ln4; The source of the NMOS transistor NM4 is connected to the power supply AVDD through the resistor R3, the gate of the NMOS transistor NM4 is connected to the source of the PMOS transistor PM6, the source of the NMOS transistor NM4 is connected to the current source circuit ln4 and the drain of the PMOS transistor PM6, and the substrate of the NMOS transistor NM4 is grounded to AVSS or connected to the source of the NMOS transistor NM4.

9. The input stage circuit according to claim 4, wherein The circuit structures of the auxiliary source follow circuit and the main source follow circuit are the same, and the equivalent input capacitance of the auxiliary source follow circuit is reduced by the same connection method as that of the first sub-source follow circuit and the second sub-source follow circuit.

10. An amplifier, characterized in that, It includes the input stage circuit according to any one of claims 1 to 9.

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