A charge pump phase-locked loop

Abstract

The present invention relates to a charge pump phase-locked loop, belonging to the technical field of phase-locked loop circuit structures. The charge pump phase-locked loop provided by the present invention, during the locking process, uses a frequency discriminator and phase detector module to identify the phase error between the reference signal and the feedback signal, and then controls the charging and discharging of the charge pump module through this phase error information, thereby controlling the output signal. After the output signal is input into the voltage-controlled oscillator module, the control of the output signal frequency is achieved, and thus it can effectively accelerate the control of the charge pump charging and discharging by the error information, more quickly adjust the output frequency of the voltage-controlled oscillator module, accelerate the elimination speed of the phase or frequency error between the feedback signal and the reference signal, and accelerate the locking process of the charge pump phase-locked loop. Moreover, by adjusting the delay signals in the delay module and the frequency detection module, the flexibility and configurability of the charge pump phase-locked loop can be greatly improved, while power consumption is saved and unnecessary power consumption waste is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of phase-locked loop circuit structure, and in particular to a charge pump phase-locked loop. Background Art

[0002] The phase-locked loop is a key component of the SoC chip. Its main function is to provide clocks that meet the requirements of different subsystems. For example, it is used in low-frequency double data rate synchronous dynamic random access memory (Double Data Rate, DDR). The performance of the phase-locked loop determines the working stability of the entire system and the quality of various indicators. Therefore, the phase-locked loop needs to respond quickly and correctly to unpredictable phase fluctuations and transient overshoots. Research on fast-locking phase-locked loops is very necessary.

[0003] Therefore, providing a phase-locked loop with advantages such as fast locking speed, strong flexibility, and low power consumption has become a technical problem that needs to be urgently solved in the field. Summary of the invention

[0004] In view of the technical problems existing in the above-mentioned prior art, the present invention provides a charge pump phase-locked loop.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A charge pump phase-locked loop, comprising: a frequency detector module, a charge pump module, a delay module, a filter module, a cavity oscillator module, a frequency detection module and a frequency divider module;

[0007] The first output end of the frequency detector module is connected to the first input end of the charge pump module and the first input end of the delay module respectively; the second output end of the frequency detector module is connected to the second input end of the charge pump module and the second input end of the delay module respectively; the first output end of the delay module is connected to the third input end of the charge pump module; the second output end of the delay module is connected to the fourth input end of the charge pump module; the output end of the charge pump module is connected to the input end of the filter module; the output end of the filter module is connected to the input end of the pressure chamber oscillator module; the output end of the pressure chamber oscillator module is respectively connected to the input end of the frequency detection module and the input end of the frequency divider module; the output end of the frequency detection module is connected to the fifth input end of the charge pump module; the output end of the frequency divider module is connected to the second input end of the frequency detector module; the first input end of the frequency detector module is a signal receiving end.

[0008] Preferably, the charge pump module comprises: a first charge pump unit, a second charge pump unit and a third charge pump unit;

[0009] The first output terminal of the frequency discriminator and phase detector module is connected to the first input terminal of the first charge pump unit; the second output terminal of the frequency discriminator and phase detector module is connected to the second input terminal of the first charge pump unit; the first output terminal of the delay module is connected to the first input terminal of the second charge pump module; the second output terminal of the delay module is connected to the second input terminal of the second charge pump module; the output terminal of the frequency detection module is connected to the input terminal of the third charge pump module; the output terminals of the first charge pump unit, the second charge pump unit, and the third charge pump unit are all connected to the input terminal of the filter module.

[0010] Preferably, both the first charge pump unit and the second charge pump unit include a PMOS transistor, a first switch, a second switch, and an NMOS transistor connected in series in sequence;

[0011] The first output terminal of the frequency discriminator and phase detector module is connected to the first switch in the first charge pump unit; the second output terminal of the frequency discriminator and phase detector module is connected to the second switch in the first charge pump unit;

[0012] The first output terminal of the delay module is connected to the first switch in the second charge pump unit; the second output terminal of the delay module is connected to the second switch in the second charge pump unit.

[0013] Preferably, the third charge pump unit includes an NMOS transistor, a third switch, a fourth switch, and an NMOS transistor connected in series in sequence;

[0014] The output terminal of the frequency detection module is connected to the third switch.

[0015] Preferably, the delay module includes a first delay unit and a second delay unit;

[0016] The input terminal of the first delay unit is connected to the first output terminal of the frequency discriminator and phase detector module; the output terminal of the first delay unit is connected to the first input terminal of the second charge pump unit; the input terminal of the second delay unit is connected to the second output terminal of the frequency discriminator and phase detector module; the output terminal of the second delay unit is connected to the second input terminal of the second charge pump unit.

[0017] Preferably, both the first delay unit and the second delay unit include a delay subunit and an AND gate.

[0018] Preferably, in the first delay unit, the input terminal of the delay subunit and the first input terminal of the AND gate are both connected to the first output terminal of the frequency discriminator and phase detector module, the output terminal of the delay subunit is connected to the second input terminal of the AND gate, and the output terminal of the AND gate is connected to the first input terminal of the second charge pump unit;

[0019] Preferably, in the second delay unit, the input end of the delay sub-unit and the first input end of the AND gate are both connected to the second output end of the frequency discriminator and phase detector module, the output end of the delay sub-unit is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the second input end of the second charge pump unit.

[0020] Preferably, the frequency detection module includes: a first flip-flop, a first inverter, a second flip-flop, a second inverter, and a delay chain;

[0021] The input end of the first flip-flop is connected to the output end of the pressure chamber oscillator module; the output end of the first flip-flop is connected to the input end of the first inverter; the output end of the first inverter is connected to the first input end of the second flip-flop; the output end of the second flip-flop is connected to the input end of the second inverter; the output end of the second inverter is connected to the fifth input end of the charge pump module; the input end of the delay chain is connected to the output end of the first flip-flop; the output end of the delay chain is connected to the second input end of the second flip-flop.

[0022] Preferably, the filter module includes: a first capacitor, a resistor, and a second capacitor;

[0023] One end of the resistor and one end of the second capacitor are both connected to the output end of the charge pump module; the other end of the resistor is connected to one end of the first capacitor; the other end of the second capacitor and the other end of the first capacitor are both grounded.

[0024] According to the specific embodiments provided by the present invention, the following technical effects are disclosed by the present invention:

[0025] For the charge pump phase-locked loop provided by the present invention, during the locking process, the frequency discriminator and phase detector module is used to identify the phase error between the reference signal and the feedback signal, and then the charge and discharge of the charge pump module is controlled through this phase error information, and further the output signal is controlled. After the output signal is input to the pressure chamber oscillator module, the control of the output signal frequency is realized, and thus the control of the charge and discharge of the charge pump by the error information can be effectively accelerated, the output frequency of the pressure chamber oscillator module can be adjusted faster, the elimination speed of the phase or frequency error between the feedback signal and the reference signal can be accelerated, and the locking process of the charge pump phase-locked loop can be accelerated. Moreover, by adjusting the delay signals in the delay module and the frequency detection module, the flexibility and configurability of the charge pump phase-locked loop can be greatly improved, while the power consumption is saved and unnecessary power consumption waste is avoided. Description of the Drawings

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 Structural schematic diagram of the charge pump phase-locked loop provided by the present invention;

[0028] Figure 2 Structural schematic diagram of the frequency detection module provided by the embodiment of the present invention;

[0029] Figure 3 Locking time simulation diagram provided by the embodiment of the present invention;

[0030] Figure 4 Vctrl analysis diagram provided by the embodiment of the present invention.

[0031] Symbol description:

[0032] 1 Phase frequency detector module, 2 Charge pump module, 2-1 First charge pump unit, 2-2 Second charge pump unit, 2-3 Third charge pump unit, 3 Delay module, 3-1 First delay unit, 3-2 Second delay unit, 4 Filter module, 5 Voltage controlled oscillator module, 6 Frequency detection module, 6-1 First flip-flop, 6-2 First inverter, 6-3 Second flip-flop, 6-4 Second inverter, 6-5 Delay chain, 7 Divider module. Detailed implementation manners

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0034] The object of the present invention is to provide a charge pump phase-locked loop with advantages such as fast locking speed, strong flexibility, and power consumption saving, so as to effectively accelerate the control of the charge and discharge of the charge pump by error information, more quickly adjust the output frequency of the VCO, accelerate the elimination of the phase or frequency error between the feedback signal and the reference signal, and accelerate the locking process of the charge pump phase-locked loop.

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0036] As Figure 1As shown, the charge pump phase-locked loop provided by the present invention includes: a frequency discriminator and phase detector module 1, a charge pump module 2, a delay module 3, a filter module 4, a voltage-controlled oscillator module 5, a frequency detection module 6, and a frequency divider module 7.

[0037] The first output terminal of the frequency discriminator and phase detector module 1 is respectively connected to the first input terminal of the charge pump module 2 and the first input terminal of the delay module 3. The second output terminal of the frequency discriminator and phase detector module 1 is respectively connected to the second input terminal of the charge pump module 2 and the second input terminal of the delay module 3. The first output terminal of the delay module 3 is connected to the third input terminal of the charge pump module 2. The second output terminal of the delay module 3 is connected to the fourth input terminal of the charge pump module 2. The output terminal of the charge pump module 2 is connected to the input terminal of the filter module 4. The output terminal of the filter module 4 is connected to the input terminal of the voltage-controlled oscillator module 5. The output terminal of the voltage-controlled oscillator module 5 is respectively connected to the input terminal of the frequency detection module 6 and the input terminal of the frequency divider module 7. The output terminal of the frequency detection module 6 is connected to the fifth input terminal of the charge pump module 2. The output terminal of the frequency divider module 7 is connected to the second input terminal of the frequency discriminator and phase detector module 1. The first input terminal of the frequency discriminator and phase detector module 1 is the signal receiving terminal.

[0038] Among them, the charge pump module 2 includes: a first charge pump unit 2-1, a second charge pump unit 2-2, and a third charge pump unit 2-3.

[0039] The first output terminal of the frequency discriminator and phase detector module 1 is connected to the first input terminal of the first charge pump unit 2-1. The second output terminal of the frequency discriminator and phase detector module 1 is connected to the second input terminal of the first charge pump unit 2-1. The first output terminal of the delay module 3 is connected to the first input terminal of the second charge pump module 2. The second output terminal of the delay module 3 is connected to the second input terminal of the second charge pump module 2. The output terminal of the frequency detection module 6 is connected to the input terminal of the third charge pump module 2. The output terminals of the first charge pump unit 2-1, the second charge pump unit 2-2, and the third charge pump unit 2-3 are all connected to the input terminal of the filter module 4.

[0040] To achieve precise control of the discharge time, the control principles of the above three charge pump units are basically the same. However, the structure of the third charge pump unit 2-3 is different from that of the first charge pump unit 2-1 and the second charge pump unit 2-2. Specifically: The first charge pump unit 2-1 and the second charge pump unit 2-2 each include a PMOS transistor, a first switch, a second switch, and an NMOS transistor connected in series in sequence. The first output terminal of the phase frequency detector module 1 is connected to the first switch in the first charge pump unit 2-1. The second output terminal of the phase frequency detector module 1 is connected to the second switch in the first charge pump unit 2-1. The first output terminal of the delay module 3 is connected to the first switch in the second charge pump unit 2-2. The second output terminal of the delay module 3 is connected to the second switch in the second charge pump unit 2-2. The third charge pump unit 2-3 includes an NMOS transistor, a third switch, a fourth switch, and an NMOS transistor connected in series in sequence. The output terminal of the frequency detection module 6 is connected to the third switch.

[0041] Among them, the first charge pump unit 2-1 and the second charge pump unit 2-2 adopt a drain-switching charge pump. The upper and lower switches are a PMOS and an NMOS respectively. When the control signal of the PMOS switch is low, the switch closes; when the control signal of the PMOS switch is high, the switch opens. When the control signal of the NMOS switch is high, the switch closes; when the control signal of the NMOS switch is low, the switch opens. Different from the first charge pump unit 2-1 and the second charge pump unit 2-2, the third charge pump unit 2-3 adopts an NMOS-switching charge pump. The upper and lower switches are both NMOS. If the control signal of the switch is at a high level, the switch closes; if it is at a low level, the switch opens.

[0042] To achieve precise control of the phase-locked loop, the delay module 3 adopted in the present invention includes a first delay unit 3-1 and a second delay unit 3-2.

[0043] The input terminal of the first delay unit 3-1 is connected to the first output terminal of the phase frequency detector module 1. The output terminal of the first delay unit 3-1 is connected to the first input terminal of the second charge pump unit 2-2. The input terminal of the second delay unit 3-2 is connected to the second output terminal of the phase frequency detector module 1. The output terminal of the second delay unit 3-2 is connected to the second input terminal of the second charge pump unit 2-2.

[0044] Among them, the first delay unit 3-1 and the second delay unit 3-2 both include a delay subunit and an AND gate. In the first delay unit 3-1, the input end of the delay subunit and the first input end of the AND gate are both connected to the first output end of the frequency discriminator and phase detector module 1. The output end of the delay subunit is connected to the second input end of the AND gate. The output end of the AND gate is connected to the first input end of the second charge pump unit 2-2. In the second delay unit 3-2, the input end of the delay subunit and the first input end of the AND gate are both connected to the second output end of the frequency discriminator and phase detector module 1. The output end of the delay subunit is connected to the second input end of the AND gate. The output end of the AND gate is connected to the second input end of the second charge pump unit 2-2.

[0045] Further, as Figure 2 shown, the frequency detection module 6 provided by the present invention includes: a first flip-flop 6-1, a first inverter 6-2, a second flip-flop 6-3, a second inverter 6-4, and a delay chain 6-5.

[0046] The input end of the first flip-flop 6-1 is connected to the output end of the pressure chamber oscillator module 5. The output end of the first flip-flop 6-1 is connected to the input end of the first inverter 6-2. The output end of the first inverter 6-2 is connected to the first input end of the second flip-flop 6-3. The output end of the second flip-flop 6-3 is connected to the input end of the second inverter 6-4. The output end of the second inverter 6-4 is connected to the fifth input end of the charge pump module 2. The input end of the delay chain 6-5 is connected to the output end of the first flip-flop 6-1. The output end of the delay chain 6-5 is connected to the second input end of the second flip-flop 6-3.

[0047] The function of the frequency detection module 6 with the above structure is to detect the difference between the output frequency CLK of the pressure chamber oscillator module 5 and the frequency of the delay chain 6-5, so that the third charge pump unit 2-3 works continuously from power-on, accelerating the rise of the output signal Vctrl until the output frequency of the pressure chamber oscillator module 5 rises to twice the frequency of the delay chain 6-5, and then disconnecting the third charge pump unit 2-3 to accelerate the locking speed of the phase-locked loop. OUT The input of the frequency detection module 6 is the signal CLK

[0048] OUT OUT , and the output is the signal F OUT . The input D and CLK of the first flip-flop 6-1 are respectively connected to the output QN of the first flip-flop 6-1 and the output CLK of the pressure chamber oscillator module 5 OUT , and at this time, the frequency of the other output Q of the first flip-flop 6-1 is CLK OUTHalf of the frequency. After passing through the first inverter 6-2 and the delay chain 6-5, Q outputs signals CLK_1 and CLK_2 respectively. The signals CLK_1 and CLK_2 are connected to the input D and CLK of the second flip-flop 6-3 respectively. The output Q of the first flip-flop 6-1 is connected to the output F after passing through the second inverter 6-4 OUT .

[0049] Based on this structure, the working principle of the frequency detection module 6 is as follows:

[0050] The delay chain 6-5 is a key part of the frequency detection module 6. The frequency corresponding to its delay is compared with the magnitude of the input signal CLK OUT When the phase-locked loop circuit just starts, since the output signal Vctrl does not rise fast enough and the output signal Vctrl is small, the frequency of the voltage-controlled oscillator module 5 is small. At this time, the frequency of the input signal CLK OUT is less than the frequency of the delay chain 6-5. After the frequency of the input signal CLK OUT passes through the first flip-flop 6-1, the frequency of the output Q of the first flip-flop 6-1 is half of the CLK OUT frequency. The signal Q passes through the first inverter 6-2 and the delay chain 6-5 respectively to generate signals CLK_1 and CLK_2. The signals CLK_1 and CLK_2 are used as the input D and CLK of the second flip-flop 6-3. Since the sampling signal CLK_2 of the second flip-flop 6-3 samples the signal of CLK_1 at the rising edge, it is always low level. Therefore, the output Q of the second flip-flop 6-3 always remains low level. After Q passes through the second inverter 6-4, the output is F OUT , F OUT always remains high level. Since F OUT always remains high level, the switch S of the third charge pump unit 2-3 5 is always in the closed state under the control of the high level. At this time, the signal I CP3 charges the signal I CP . After the signal I CP increases, the output signal Vctrl rises after passing through the filter module 4, and the output frequency CLK of the voltage-controlled oscillator module 5 OUT increases. Until the output frequency CLK of the voltage-controlled oscillator module 5 OUT increases to twice the frequency corresponding to the delay chain 6-5, the working state of the frequency detection module 6 enters the second part.

[0051] The second part is as follows: When the output frequency CLK of the voltage-controlled oscillator module 5 OUTWhen it increases to twice the frequency corresponding to the delay chain 6-5, the signals CLK_1 and CLK_2 serve as the input D and CLK of the second flip-flop 6-3. Since the signal of CLK_1 sampled by the sampling signal CLK_2 of the second flip-flop 6-3 at the rising edge is always high level, the output Q of the second flip-flop 6-3 always remains high level. After Q passes through the second inverter 6-4, F is output. OUT , F OUT always remains low level. Since F OUT always remains low level, the switch S of the third charge pump unit 2-3 5 is always in the off state under the control of the low level, and the third charge pump unit 2-3 stops working at this time.

[0052] It can be seen from the working principle of the above frequency detection module 6 that this module has great flexibility. According to the magnitude of the delay of the delay chain, the working time of the third charge pump unit 2-3 can be controlled, thereby adjusting the locking time.

[0053] Furthermore, the adopted filter module 4 includes: a first capacitor, a resistor, and a second capacitor.

[0054] One end of the resistor and one end of the second capacitor are both connected to the output end of the charge pump module 2. The other end of the resistor is connected to one end of the first capacitor. The other ends of the second capacitor and the first capacitor are both grounded.

[0055] Based on the above description, the present invention takes the first charge pump unit 2-1 as a fine-tuning charge pump, which is always in the working state before the phase-locked loop completes the locking operation. Among them, as Figure 1 shown, the inputs of the first charge pump unit 2-1 are the UP signal and the DN signal, and the output is the I CP1 signal. The UP signal and the DN signal respectively control the opening and closing of the first switch S 1 and the second switch S 2 of the first charge pump unit 2-1, and further control the charging and discharging time. If the first switch S 1 is closed and the second switch S 2 is open, the first charge pump unit 2-1 charges the I UP through the charging current source I CP1 , so that the I CP1 rises. If the first switch S 1 is open and the second switch S 2 is closed, the first charge pump unit 2-1 discharges the I DN through the discharging current source I CP1 , so that the I CP1 falls.

[0056] Take the second charge pump unit 2-2 as a coarse-tuning charge pump, as Figure 1As shown, only in F DIV Signal and F REF The frequency or phase error of the signal is greater than the delay τ e When the second charge pump unit 2-2 works, until the signal F DIV and F REF The error is less than τ e After that, the second charge pump unit 2-2 stops working. The input signals of the second charge pump unit 2-2 are UPN and DNN, and the output signal is I CP2 The generation of UPN and DNN is that the UP and DN signals are generated by the delay module 3. The function of the delay module 3 is to delay the UP and DN signals by τ e After the delay, UPN and DNN are output, which are used to control the coarse-adjustment charge switch, and play the role of coarse-adjustment charge pump and fine-adjustment charge pump when the phase error is greater than τ e The two devices work simultaneously in different situations, thereby accelerating the locking process.

[0057] During the setting process, the start time of the third charge pump unit 2-3 is synchronized with the phase-locked loop circuit until the output frequency CLK of the cavity oscillator module is OUT When the frequency increases to twice the frequency corresponding to the delay chain 6-5 in the frequency detection module 6, the third charge pump unit 2-3 stops working. The input of the third charge pump unit 2-3 is the output signal F of the frequency detection module 6. OUT , output signal F OUT Control switch switch S 5 (i.e. the third switch) is opened or closed, switch S 6 (i.e. the fourth switch) is always in the disconnected state, and the output is I CP3 Signal.

[0058] The function of the third charge pump unit 2-3 is to switch S 5 Closed, so that the signal I CP3 With signal I CP1 ,I CP2 Together we form I CP , thereby increasing the signal I CP , signal I CP After passing through the filter module 4, the output signal Vctrl increases, and then the output frequency CLK of the cavity oscillator module OUT The final result is that due to the action of the third charge pump unit 2-3, the output signal Vctrl can be quickly adjusted to a certain value, the time for the output signal Vctrl to increase is reduced, and the locking process is accelerated. At the same time, due to the delay chain in the frequency detection module 6, the working time of the third charge pump unit 2-3 can be adjusted by adjusting the size of the delay to select the speed of the accelerated locking, thereby increasing the flexibility of the overall circuit.

[0059] Based on this, the working principle of the obtained phase-locked loop is as follows:

[0060] The frequency discriminator and phase discriminator module 1 discriminates the frequency and phase errors of signal F DIV and signal F REF and outputs UP and DN to control the switches S 1 and switch S 2 to open and close respectively, thereby controlling the charging and discharging time. If switch S 1 closes switch S 2 and opens, the first charge pump unit 2-1 charges I UP through the charging current source I CP1 so that I CP1 rises. If switch S 1 opens switch S 2 and closes, the first charge pump unit 2-1 discharges I DN through the discharging current source I CP1 so that I CP1 falls. The first charge pump unit 2-1 outputs I CP1 . The working principles of the three charge pumps are the same, and so on.

[0061] Meanwhile, UPN and DNN respectively control the switches S 3 and switch S 4 of the second charge pump unit 2-2 to open and close respectively, thereby controlling the charging and discharging time. The second charge pump unit 2-2 outputs I CP2 . The switch S 6 of the third charge pump unit 2-3 always remains open. The open or closed state of the switch S 5 of the third charge pump unit 2-3 is controlled by the output F OUT of the frequency detection module 6. The third charge pump unit 2-3 outputs I CP3 . I CP1 , I CP2 and I CP3 are added and output as I CP . I CP is used as the input of the filter module 4 to generate the output Vctrl of the filter module 4. The output Vctrl controls the output CLK OUT of the voltage-controlled oscillator module 5. The output CLK OUT is respectively input to the frequency detection module 6 and the frequency divider module 7. The frequency detection module 6 outputs F OUT . The signal F OUT is input to the switch S 5 of the third charge pump unit 2-3. The frequency divider module 7 outputs the signal F DIV . F DIV and FREF The two signals go through the above process again to identify and adjust the phase error until F DIV and F REF The frequency and phase errors of the two signals are eliminated or there is a fixed phase error, such as 100 ps, and then this phase-locked loop finishes its operation.

[0062] The principles of the three charge pump modules in this phase-locked loop design are the same, but their functions and input signals are different, so they will not be elaborated again. Among them, the experimental results obtained by using the charge pump phase-locked loop provided by the present invention are as Figure 3 and Figure 4 shown.

[0063] From the simulation results as Figure 3 and Figure 4 shown, the time when the signal Vctrl starts to become stable is 4 us, the locking time is 4 us, and the signal vctrl rises relatively fast within 0.5 us, achieving the effect that Vctrl described by this charge pump rises relatively fast in the initial stage of the charge pump power-on and has a short locking time.

[0064] Based on the above description, the charge pump phase-locked loop provided by the present invention also has the following advantages compared with the prior art:

[0065] 1. Compared with the traditional phase-locked loop circuit, the charge pump phase-locked loop designed by the present invention adds a coarse-tuning charge pump (i.e., the second charge pump unit) and a third charge pump unit. The outputs I CP2 and I CP3 of these two charge pump units are injected into I CP , increasing or decreasing I CP1 on the basis of I CP . After passing through the filter module, the generated output signal also increases or decreases, and the output frequency of the voltage-controlled oscillator module also increases or decreases accordingly, greatly accelerating the process of adjusting the frequency or phase error between the input signals, and thus accelerating the frequency locking process of the charge pump phase-locked loop.

[0066] 2. For the charge pump phase-locked loop designed by the present invention, the working time of the second charge pump unit is determined by the delay τ e in the delay module. Only when the phase error between the inputs is greater than the delay τ e will the second charge pump unit work, so that the working time of the second charge pump unit can be correspondingly reduced or increased by increasing or decreasing the delay τ e . The working time of the third charge pump unit is determined by the delay of the delay chain, and the working time of the third charge pump unit can be correspondingly reduced or increased by increasing or decreasing the delay of the delay chain. Therefore, the working states of the second and third charge pump units can be adjusted by adjusting the delay τ eFlexible control of the delay chain greatly improves the flexibility and configurability of the charge pump phase-locked loop, while saving power consumption and avoiding unnecessary power waste.

[0067] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0068] Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method of the present invention and its core idea. At the same time, for those of ordinary skill in the art, based on the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A charge pump phase-locked loop, characterized in that, it includes: a frequency discriminator and phase detector module, a charge pump module, a delay module, a filter module, a voltage-controlled oscillator module, a frequency detection module and a frequency divider module; The first output terminal of the frequency discriminator and phase detector module is respectively connected to the first input terminal of the charge pump module and the first input terminal of the delay module; the second output terminal of the frequency discriminator and phase detector module is respectively connected to the second input terminal of the charge pump module and the second input terminal of the delay module; the first output terminal of the delay module is connected to the third input terminal of the charge pump module; the second output terminal of the delay module is connected to the fourth input terminal of the charge pump module; the output terminal of the charge pump module is connected to the input terminal of the filter module; the output terminal of the filter module is connected to the input terminal of the voltage-controlled oscillator module; the output terminal of the voltage-controlled oscillator module is respectively connected to the input terminal of the frequency detection module and the input terminal of the frequency divider module; the output terminal of the frequency detection module is connected to the fifth input terminal of the charge pump module; the output terminal of the frequency divider module is connected to the second input terminal of the frequency discriminator and phase detector module; the first input terminal of the frequency discriminator and phase detector module is the signal receiving end.

2. The charge pump phase-locked loop according to claim 1, characterized in that, the charge pump module includes: a first charge pump unit, a second charge pump unit and a third charge pump unit; The first output terminal of the frequency discriminator and phase detector module is connected to the first input terminal of the first charge pump unit; the second output terminal of the frequency discriminator and phase detector module is connected to the second input terminal of the first charge pump unit; the first output terminal of the delay module is connected to the first input terminal of the second charge pump module; the second output terminal of the delay module is connected to the second input terminal of the second charge pump module; the output terminal of the frequency detection module is connected to the input terminal of the third charge pump module; the output terminals of the first charge pump unit, the second charge pump unit and the third charge pump unit are all connected to the input terminal of the filter module.

3. The charge pump phase-locked loop according to claim 2, characterized in that, both the first charge pump unit and the second charge pump unit include a PMOS transistor, a first switch, a second switch and an NMOS transistor connected in series in sequence; The first output terminal of the frequency discriminator and phase detector module is connected to the first switch in the first charge pump unit; the second output terminal of the frequency discriminator and phase detector module is connected to the second switch in the first charge pump unit; The first output terminal of the delay module is connected to the first switch in the second charge pump unit; the second output terminal of the delay module is connected to the second switch in the second charge pump unit.

4. The charge pump phase-locked loop according to claim 2, characterized in that, the third charge pump unit includes an NMOS transistor, a third switch, a fourth switch and an NMOS transistor connected in series in sequence; The output terminal of the frequency detection module is connected to the third switch.

5. The charge pump phase-locked loop according to claim 2, characterized in that, The delay module includes a first delay unit and a second delay unit; The input end of the first delay unit is connected to the first output end of the frequency discriminator and phase detector module; the output end of the first delay unit is connected to the first input end of the second charge pump unit; the input end of the second delay unit is connected to the second output end of the frequency discriminator and phase detector module; the output end of the second delay unit is connected to the second input end of the second charge pump unit.

6. The charge pump phase-locked loop according to claim 5, characterized in that both the first delay unit and the second delay unit include a delay sub-unit and an AND gate.

7. The charge pump phase-locked loop according to claim 6, characterized in that In the first delay unit, the input end of the delay sub-unit and the first input end of the AND gate are both connected to the first output end of the frequency discriminator and phase detector module, the output end of the delay sub-unit is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the first input end of the second charge pump unit.

8. The charge pump phase-locked loop according to claim 6, characterized in that In the second delay unit, the input end of the delay sub-unit and the first input end of the AND gate are both connected to the second output end of the frequency discriminator and phase detector module, the output end of the delay sub-unit is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the second input end of the second charge pump unit.

9. The charge pump phase-locked loop according to claim 1, characterized in that The frequency detection module includes: a first flip-flop, a first inverter, a second flip-flop, a second inverter and a delay chain; The input end of the first flip-flop is connected to the output end of the pressure chamber oscillator module; the output end of the first flip-flop is connected to the input end of the first inverter; the output end of the first inverter is connected to the first input end of the second flip-flop; the output end of the second flip-flop is connected to the input end of the second inverter; the output end of the second inverter is connected to the fifth input end of the charge pump module; the input end of the delay chain is connected to the output end of the first flip-flop; the output end of the delay chain is connected to the second input end of the second flip-flop.

10. The charge pump phase-locked loop according to claim 1, characterized in that The filter module includes: a first capacitor, a resistor and a second capacitor; One end of the resistor and one end of the second capacitor are both connected to the output end of the charge pump module; the other end of the resistor is connected to one end of the first capacitor; the other end of the second capacitor and the other end of the first capacitor are both grounded.

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