Continuous system address resolution method, device, electronic device and storage medium

Abstract

The present invention provides a method, device, electronic device and storage medium for resolving a continuous system address. The method comprises: when receiving a continuous system address, obtaining system level information; obtaining the logical address range of each object in the first level based on the continuous system address and the system level information; when sequentially obtaining the logical address range of each object in the second level, ..., and the Nth level of the system, obtaining the logical address range of each object in the current level based on the logical address range of the previous level and the system level information; wherein N is the number of levels, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object. When resolving a continuous system address, the algorithm consumes a fixed amount of time, and the time does not increase with the increase of the continuous system address range, which effectively improves the efficiency of resolving the continuous system address.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, in particular to the field of memory address technology, and specifically to a continuous system address resolution method, device, electronic device and storage medium. Background Art

[0002] The multi-level memory interleaving technology is to evenly interleave accesses to all memory channels, so that the memory channel bandwidth can be fully utilized while also reducing the access load of each memory stick. Memory interleaving technology can be implemented at multiple hardware levels, and the interleaving granularity often has multiple configuration options. Currently supported memory interleaving includes but is not limited to processor interleaving, memory controller interleaving, memory channel interleaving, and memory particle bit width set interleaving. For example, when a system supports 4K-Byte granularity channel interleaving, the system address will jump to the next channel every time the size increases by 4K-Byte. For the internal address of the channel, if it also supports the interleaving of a set of memory particle bit widths with a granularity of 256Byte (also called a rank, a rank represents a set of memory particle bit widths. Specifically, when the particle bit width × the number of particles = 64 bits, the particle constitutes a rank), a memory particle bit width set will jump every 256Byte. If Figure 1 As shown in the figure, when the user inputs a system address to the processor, it is parsed to a specific memory controller, channel, memory, and memory particle bit width set in sequence according to the address mapping logic in the processor. Due to the existence of multi-level memory interleaving technology, different system addresses will be distributed almost randomly on different memory particle bit width sets.

[0003] At present, processor manufacturers only provide a single-point resolution method from a system memory address to a memory address. When the processor wants to access a memory system address, the processor will locate the specific row and column position on a specific memory bar according to the single-point conversion logic, and then read the memory data. When the processor detects a memory error, it will also use the single-point resolution logic to locate the specific memory location of the error, thereby improving the reliability of the system. However, it is currently very difficult to resolve continuous system addresses. For any address in a continuous range of system addresses, it will go through multiple levels of interleaving such as processor interleaving, memory channel interleaving, and memory particle bit width set interleaving, as well as the influence of some other hardware configurations of the memory controller, and finally resolve to a specific memory particle bit width set in a nearly random manner. For continuous system addresses, each address is scanned in a loop, and then the above-mentioned single-point resolution method provided by the processor manufacturer is used. Although the resolution of the system continuous address can be finally completed, the performance efficiency will be very low, and the time consumed by the algorithm of the single-point resolution method will increase linearly with the expansion of the address range. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method, device, electronic device and storage medium for resolving a continuous system address, so as to solve the problem of low efficiency of single-point resolution of continuous addresses in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a continuous system address resolution method, comprising the following steps: when receiving a continuous system address, obtaining system hierarchy information; obtaining the logical address range of each object in the first hierarchy based on the continuous system address and the system hierarchy information; when successively obtaining the logical address range of each object in the second hierarchy, ..., and Nth hierarchy of the system, obtaining the logical address range of each object in the current hierarchy based on the logical address range of the previous hierarchy and the system hierarchy information; wherein N is the number of hierarchies, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object.

[0006] In one embodiment of the present invention, the system layer information includes the number of layers, the interleaving enablement state of each layer, the interleaving granularity of each layer, and the number of objects included in each layer.

[0007] In one embodiment of the present invention, the method of obtaining the logical address range of each object in the first layer based on the continuous system address and the system layer information includes: obtaining the starting address of the first object in the first layer based on the starting address of the continuous system address; obtaining the starting address of the second object, ..., and the Mth object in the first layer by sequentially increasing the corresponding address according to the starting address; obtaining the ending address of the first object in the first layer based on the ending address of the continuous system address; obtaining the ending address of the second object, ..., and the Mth object in the first layer by sequentially decreasing the corresponding address according to the ending address, wherein M is the number of objects in the first layer.

[0008] In one embodiment of the present invention, the sequentially increasing by starting address includes: when the first-level interleaving enable state is disabled, the system configuration of each object and the continuous system address are sequentially increased by the starting address; when the first-level interleaving enable state is enabled, the interleaving granularity of the first level and the continuous system address are sequentially increased by the starting address; the sequentially decreasing by ending address includes: when the first-level interleaving enable state is disabled, the system configuration of each object and the continuous system address are sequentially decreased by the starting address; when the first-level interleaving enable state is enabled, the interleaving granularity of the first level and the continuous system address are sequentially decreased by the starting address.

[0009] In one embodiment of the present invention, when objects in the first level are scanned repeatedly or the start address of an acquired object exceeds the end address of the continuous system address, the start address scanning of the first level is terminated and the acquisition of the start addresses of the objects in the first level is completed.

[0010] In one embodiment of the present invention, when the scan finds that the object in the first level is repeated or the end address of an acquired object exceeds the start address of the continuous system address, the end address scan of the first level is terminated and the acquisition of the end addresses of each object in the first level is completed.

[0011] In one embodiment of the present invention, the method of obtaining the logical address range of each object in the current level based on the logical address range of the previous level and the system level information includes: obtaining the starting address of the first object in the current level based on the starting address in the logical address range of the previous level; obtaining the starting addresses of the second object, ..., and Kth objects in the current level by sequentially increasing the corresponding addresses according to the starting address; obtaining the ending address of the first object in the current level based on the ending address in the logical address range of the previous level; obtaining the ending addresses of the second object, ..., and Kth objects in the current level by sequentially decreasing the corresponding addresses according to the ending address, wherein K is the number of objects in the current level.

[0012] In one embodiment of the present invention, the sequentially increasing by starting address includes: when the interleaving enable state of the current level is not enabled, the system configuration of each object and the logical address of the previous level are sequentially increased by the starting address; when the interleaving enable state of the current level is enabled, the interleaving granularity of the current level and the logical address of the previous level are sequentially increased by the starting address; the sequentially decreasing by the ending address includes: when the interleaving enable state of the current level is not enabled, the system configuration of each object and the logical address of the previous level are sequentially decreased by the starting address; when the interleaving enable state of the current level is enabled, the interleaving granularity of the current level and the logical address of the previous level are sequentially decreased by the starting address.

[0013] In one embodiment of the present invention, when it is found that the object in the current level is repeated or the starting address of an object obtained exceeds the ending address in the logical address range of the previous level, the starting address scanning of the current level is terminated and the acquisition of the starting addresses of the objects in the current level is completed.

[0014] In one embodiment of the present invention, when it is found that the object in the current level is repeated or the end address of an acquired object exceeds the start address in the logical address range of the previous level, the end address scan of the current level is terminated and the acquisition of the end addresses of the objects in the current level is completed.

[0015] In one embodiment of the present invention, it also includes: detecting whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of the level; in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of the level, incrementing the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of the level.

[0016] In one embodiment of the present invention, it also includes: detecting whether the address corresponding to the first decrement of the end address is an integer multiple of the interleaving granularity of the level; in response to the address corresponding to the first decrement of the end address is not an integer multiple of the interleaving granularity of the level, decrementing the address corresponding to the first decrement of the decrementing address to an integer multiple of the interleaving granularity of the level.

[0017] An embodiment of the present invention also provides a continuous system address resolution device, including: a system hierarchy information acquisition module, used to acquire system hierarchy information when receiving a continuous system address; a logical address range acquisition module, used to acquire the logical address range of each object in the first hierarchy based on the continuous system address and the system hierarchy information, and when sequentially acquiring the logical address range of each object in the second hierarchy, ..., and Nth hierarchy of the system, acquire the logical address range of each object in the current hierarchy based on the logical address range of the previous hierarchy and the system hierarchy information; wherein N is the number of hierarchies, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object.

[0018] In one embodiment of the present invention, the logical address range acquisition module includes: a starting address acquisition unit, which acquires the starting address of the first object of the first level based on the starting address of the continuous system address, and acquires the starting addresses of the second object, ..., and the Mth object in the first level by sequentially increasing the corresponding address according to the starting address, and acquires the starting address of the first object of the current level based on the starting address in the logical address range of the previous level, and acquires the starting addresses of the second object, ..., and the Kth object in the current level by sequentially increasing the corresponding address according to the starting address, M is the number of objects in the first level, and K is the number of objects in the current level; an ending address acquisition unit, which is used to acquire the ending address of the first object of the first level based on the ending address of the continuous system address, and acquires the ending addresses of the second object, ..., and the Mth object in the first level by sequentially decreasing the corresponding address according to the ending address, and acquires the ending address of the first object of the current level based on the ending address in the logical address range of the previous level, and acquires the ending addresses of the second object, ..., and the Kth object in the current level by sequentially decreasing the corresponding address according to the ending address.

[0019] In one embodiment of the present invention, in the starting address acquisition unit: when the first-level interleaving enable state is not enabled, based on the system configuration of each object and the continuous system address, the starting address is incremented in sequence; when the first-level interleaving enable state is enabled, based on the interleaving granularity of the first level and the continuous system address, the starting address is incremented in sequence; when the interleaving enable state of the current level is not enabled, based on the system configuration of each object and the logical address of the previous level, the starting address is incremented in sequence; when the interleaving enable state of the current level is enabled: based on the interleaving granularity of the current level and the logical address of the previous level, the starting address is incremented in sequence. The addresses are incremented sequentially; in the end address acquisition unit: when the first-level interleaving enable state is not enabled, the system configuration based on each object and the continuous system addresses are decremented sequentially from the starting address; when the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are decremented sequentially from the starting address; when the interleaving enable state of the current level is not enabled, the system configuration based on each object and the logical address of the previous level are decremented sequentially from the starting address; when the interleaving enable state of the current level is enabled, the interleaving granularity based on the current level and the logical address of the previous level are decremented sequentially from the starting address.

[0020] In one embodiment of the present invention, the logical address range acquisition module further includes: a starting address scanning unit, which is used to scan and acquire the starting addresses of the second object, ..., and the Mth object in the first level. When the object in the first level is scanned to be repeated or the starting address of a certain object obtained exceeds the end address of the continuous system address, the starting address scanning of the first level is terminated to complete the acquisition of the starting addresses of each object in the first level, and is used to sequentially scan and acquire the starting addresses of the second object, ..., and the Kth object in the current level. When the object in the current level is scanned to be repeated or the starting address of a certain object obtained exceeds the end address in the logical address range of the previous level, the starting address scanning of the current level is terminated to complete the acquisition of the starting addresses of the current level. Acquisition of the starting address of each object in the present level; an end address scanning unit, used to sequentially scan and acquire the end addresses of the second object, ..., Mth object in the first level, and when it is scanned that the object in the first level is repeated or the end address of a certain object acquired exceeds the starting address of the continuous system address, the end address scanning of the first level is terminated, and the acquisition of the end addresses of each object in the first level is completed; and used to sequentially scan and acquire the end addresses of the second object, ..., Kth object in the present level, and when it is scanned that the object in the present level is repeated or the end address of a certain object acquired exceeds the starting address in the logical address range of the previous level, the end address scanning of the present level is terminated, and the acquisition of the end addresses of each object in the present level is completed.

[0021] In one embodiment of the present invention, the logical address range acquisition module also includes: a multiple detection unit, used to detect whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of the level, and whether the address corresponding to the first decrement of the ending address is an integer multiple of the interleaving granularity of the level; a multiple adjustment unit, used to increase the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first decrement of the ending address is not an integer multiple of the interleaving granularity of the level, or to decrement the address corresponding to the first decrement of the decrementing address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first decrement of the ending address is not an integer multiple of the interleaving granularity of the level.

[0022] To achieve the above object, the present invention further provides a storage medium storing program instructions, which, when executed by a processor, implement the steps of the continuous system address resolution method as described above.

[0023] To achieve the above objectives, the present invention also provides an electronic device, including a memory for storing a computer program; a processor connected to the memory and used to run the computer program to implement the steps of the continuous system address resolution method as described above.

[0024] As described above, a method, device, electronic device and storage medium for continuous system address resolution of the present invention have the following beneficial effects:

[0025] When the present invention parses the continuous system address, the algorithm consumes a fixed time, and the time will not increase with the increase of the continuous system address range, thereby effectively improving the efficiency of the continuous system address parsing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is an architectural diagram of single-point system address resolution in the prior art;

[0027] Figure 2 Shown is a schematic diagram of the application of the continuous system address resolution method of the present invention;

[0028] Figure 3 It is a schematic diagram showing the overall flow of the continuous system address resolution method of the present invention;

[0029] Figure 4 It is a flowchart showing the method for obtaining the starting address of each object in the first level in the continuous system address resolution method of the present invention;

[0030] Figure 5 It is a flowchart showing the method for obtaining the end address of each object in the first level in the continuous system address resolution method of the present invention;

[0031] Figure 6 It is a flow chart showing the method for resolving addresses of continuous systems in the present invention to obtain the starting addresses of the objects in the second level ... the Nth level;

[0032] Figure 7 It is a flowchart showing the method for resolving the address of the continuous system of the present invention for obtaining the end address of each object in the second level ... the Nth level;

[0033] Figure 8 It is a flowchart showing the overall implementation of the continuous system address resolution method of the present invention;

[0034] Fig. 9 Shown is a specific address resolution example diagram of the continuous system address resolution method of the present invention;

[0035] Fig.10 It is a principle structure block diagram of the continuous system address resolution device of the present invention;

[0036] Fig.11 Shown is a principle structure block diagram of a logic address range acquisition module in a continuous system address resolution device of the present invention;

[0037] Fig.12 It is a preferred principle structure block diagram of a logic address range acquisition module in the continuous system address resolution device of the present invention;

[0038] Fig.13 Another preferred principle structure block diagram of a logic address range acquisition module in the continuous system address resolution device of the present invention is shown;

[0039] Fig.14 It is a schematic diagram showing the principle structure of an electronic device of the present invention in one embodiment.

[0040] Component number description

[0041] 10 Electronic devices

[0042] 101 Processor

[0043] 102 Memory

[0044] 100 Continuous System Address Resolution Device

[0045] 110 System level information acquisition module

[0046] 120 Logical address range acquisition module

[0047] 121 Start address acquisition unit

[0048] 122 End address acquisition unit

[0049] 123 Start address scanning unit

[0050] 124 End address scan unit

[0051] 125 times detection unit

[0052] 126 multiple adjustment units

[0053] 20 Memory

[0054] 310 First Channel

[0055] 311 The first memory particle width set

[0056] 312 The set of second memory particle width

[0057] 320 Second Channel

[0058] 321 The set of the first memory particle width

[0059] 322 The set of second memory particle width

[0060] Steps S100 to S300

[0061] Steps S210 to S240

[0062] Steps S310 to S340 DETAILED DESCRIPTION

[0063] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0064] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] In the process of performing single-point resolution on each system address in the continuous system addresses using the existing technology:

[0066] 1) Each system address will be parsed layer by layer (layers include but are not limited to channels and memory particle width sets (ranks), where rank is the last layer) until it is parsed to a memory particle width set (rank) on a certain channel (channel). During the parsing process, a logical address can be calculated at each layer.

[0067] 2) Regardless of whether the hierarchical interleaving of each layer is enabled or not, and how large the interleaving granularity is, the logical addresses calculated from the continuous system memory addresses at each layer grow linearly, that is, the logical addresses of the layers such as the set of channel and memory particle widths are continuous.

[0068] 3) When the single-point address increases continuously to the end address, or when the resolved hierarchical objects are repeated cyclically, it means that all hierarchical objects have been scanned.

[0069] The continuous system address resolution method, device, electronic device and storage medium of the present invention are used to solve the problem of low efficiency of single-point resolution of continuous addresses in the prior art.

[0070] Figure 2 It is a schematic diagram showing the application of the continuous system address resolution method of the present invention. Figure 2 As shown, a continuous system address may be resolved to continuous channel logical addresses on three different channels (e.g., channel 1 and channel 2 of memory controller 1, channel 1 of memory controller 2) in two memory controllers (memory controller 1 and memory controller 2), and then resolved to the set addresses of continuous memory particle bit widths of four different sets of memory particle bit widths (set 1 of continuous memory particle bit widths of memory 1 of channel 1 of memory controller 1, set 1 and set 2 of continuous memory particle bit widths of memory 1 of channel 2 of memory controller 1, set 1 of continuous memory particle bit widths of memory 2 of channel 1 of memory controller 2). It should be noted that Figure 2 As an example only, the continuous system addresses in this application can be resolved to any one or more suitable sets of memory controllers, channels, or memory particle widths.

[0071] Based on the characteristics of the above-mentioned single-point resolution process, this embodiment proposes an optimized method for resolving addresses within a continuous system.

[0072] The principles and implementation methods of the continuous system address resolution method, device, electronic device and storage medium of this embodiment will be explained in detail below, so that those skilled in the art can understand the continuous system address resolution method, device, electronic device and storage medium of this embodiment without creative work.

[0073] Example 1

[0074] This embodiment provides a continuous system address resolution method. Figure 3 The following is an overall flow chart of the continuous system address resolution method of this embodiment. Figure 3 As shown, the continuous system address resolution method of this embodiment includes the following steps:

[0075] Step S100, upon receiving the continuous system address, obtaining system level information;

[0076] Step S200, obtaining a logical address range of each object in the first layer based on the continuous system address and the system layer information;

[0077] Step S300, based on the logical address range of the previous level and the system level information, obtain the logical address range of each object in the current level, and successively obtain the logical address range of each object in the second level, ..., and Nth level of the system, where N is the number of levels and N is an integer greater than or equal to 2.

[0078] The above steps S100 to S300 in the continuous system address resolution method of this embodiment are described in detail below.

[0079] Step S100, when receiving the continuous system address, obtaining system level information.

[0080] In this embodiment, the system layer information includes but is not limited to the number of layers, the interleaving enablement state of each layer, the interleaving granularity of each layer, and the number of objects included in each layer.

[0081] Specifically, in some embodiments, the system hierarchy may include, for example, two hierarchies, memory channels and memory granule bit width sets (ranks). In some embodiments, the system hierarchy may include one or more hierarchies. The hierarchical interleaving enable state includes interleaving enabled and interleaving disabled, wherein when interleaving is disabled, the logical address range of the system configuration of each object in the hierarchy is obtained, and the number of objects in each hierarchy is obtained, such as how many channels the system memory has and how many memory granule bit width sets each channel has.

[0082] Step S200: acquiring a logical address range of each object in a first layer based on the continuous system addresses and the system layer information.

[0083] In this embodiment, the input of the first level is the continuous system address. Specifically, in this embodiment, the start address and the end address of each object in the first level are obtained based on the continuous system address and the system level information respectively.

[0084] like Figure 4As shown, the obtaining of the starting address in the logical address range of each object in the first level based on the continuous system address and the system level information includes:

[0085] Step S210: acquiring a start address of a first object of a first level based on a start address of the continuous system addresses.

[0086] Specifically, the starting address of the first interleaving-enabled object is calculated based on the starting address of the continuous system address and the single-point address resolution logic. The single-point address resolution logic adopts any single-point address resolution method in the prior art. No further details are given here.

[0087] In this embodiment, M is the number of objects in the first level, and K is the number of objects in the second level, ..., or any level in the Nth level. It should be noted that the value of K may be the same or different for each level in the second level, ..., or each level in the Nth level.

[0088] Step S220 , obtaining the starting addresses of the second object, ..., and the Mth object in the first level by increasing the corresponding addresses in sequence according to the starting address, where M is the number of objects in the first level.

[0089] Specifically, the step of increasing the starting address in sequence includes:

[0090] 1) when the first-level interleaving enable state is disabled, based on the system configuration of each object and the continuous system addresses, the starting addresses are incremented in sequence;

[0091] 2) When the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are incremented in sequence according to the starting address.

[0092] Among them, in this embodiment, the starting addresses of the first object, ..., Mth object in the first level are scanned in sequence to obtain, and when the object in the first level is scanned to be repeated or the starting address of an object obtained exceeds the end address of the continuous system address, the starting address scanning of the first level is terminated, and the acquisition of the starting addresses of each object in the first level is completed.

[0093] In particular, in the continuous system address resolution method of this embodiment, it also includes: detecting whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of this level; in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of this level, incrementing the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of this level.

[0094] That is, in this embodiment, if hierarchical interleaving is enabled and the starting address is not an integer multiple of the interleaving granularity, when the continuous system address is incremented for the first time, the incremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0095] For example, the first-level interleaving granularity is 4K-Byte, the starting address of the continuous system address is 10K, and the starting address 10K is not an integer multiple of the interleaving granularity 4K-Byte. The first increment increases to the next integer multiple address 12K, so that the first increment address is an integer multiple of the interleaving granularity. Then, the starting address of the second object is calculated based on the first increment address and the single-point address resolution logic.

[0096] In this embodiment, if Figure 5 As shown, the acquiring the end address in the logical address range of each object in the first level based on the continuous system address and the system level information includes:

[0097] Step S230, obtaining the end address of the first object of the first level based on the end address of the continuous system addresses. Specifically, obtaining the end address of the first interleaving-enabled object based on the end address of the continuous system addresses and the single-point address resolution logic calculation.

[0098] Step S240, obtaining the end addresses of the second object, ..., and the Mth object in the first level by sequentially decreasing the corresponding addresses according to the end addresses.

[0099] Specifically, the step of decreasing in order according to the end address includes:

[0100] 1) When the first-level interleaving enable state is disabled, the system configuration of each object and the continuous system addresses are decreased in sequence according to the starting address;

[0101] 2) When the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are decreased in sequence according to the starting address.

[0102] Among them, in this embodiment, the end addresses of the first object, ..., Mth object in the first level are scanned and acquired in sequence. When the object in the first level is scanned to be repeated or the end address of an acquired object exceeds the starting address of the continuous system address, the end address scanning of the first level is terminated, and the acquisition of the end addresses of each object in the first level is completed.

[0103] In particular, in the continuous system address resolution method of this embodiment, it also includes: detecting whether the address corresponding to the first decrement of the end address is an integer multiple of the interleaving granularity of this level; in response to the address corresponding to the first decrement of the end address is not an integer multiple of the interleaving granularity of this level, decrementing the address corresponding to the first decrement of the decrementing address to an integer multiple of the interleaving granularity of this level.

[0104] That is, in this embodiment, if hierarchical interleaving is enabled and the end address is not an integer multiple of the interleaving granularity, when the continuous system address is decremented for the first time, the decremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0105] For example, the first-level interleaving granularity is 4K-Byte, and the end address of the continuous system address + 1 is 22K, which is not an integer multiple of the interleaving granularity of 4K-Byte. The first decremented address is decremented to an integer multiple of the interleaving granularity of 20K, so the end address of the next scan is 22K-1. Then, the end address of the second object is calculated based on the first decremented address and the single-point address resolution logic.

[0106] It should be noted that, in this embodiment, when obtaining the logical address range of each object in the first level, step S210 can be executed first: obtain the starting address of the first object in the first level, and then execute step 230, or step S230 can be executed first: obtain the ending address of the first object in the first level, and then execute step S210. In addition, step S210 and step S230 can also be executed at the same time: obtain the starting address and ending address of the first object in the first level at the same time.

[0107] Similarly, when obtaining the logical address range of the second object,..., Mth object in the first level, you can first obtain the starting address of each object and then obtain the ending address of each object, or you can first obtain the ending address of each object and then obtain the starting address of each object, or you can simultaneously execute the process of obtaining the starting address and ending address of each object.

[0108] Step S300, based on the logical address range of the previous layer and the system layer information, the logical address range of each object in the current layer (the second layer, ..., any layer of the Nth layer) is obtained, so as to sequentially obtain the logical address range of each object in the second layer, ..., and the Nth layer of the system, where N is the number of layers and N is an integer greater than or equal to 2. For example, based on the logical address range of the i-1th layer and the system layer information, the logical address range of each object in the i layer is obtained, where i=2, 3, ..., N.

[0109] In this embodiment, the inputs of the second level, . . . , and the Nth level are the logical address ranges of the previous level.

[0110] like Figure 6 As shown, when the interleaving enable state of the current level is enabled, the starting address in the logical address range of each object in the current level is obtained based on the logical address range of the previous level and the system level information, including:

[0111] Step S310 , obtaining a start address of a first object at the current level based on a start address in a logical address range at an upper level.

[0112] Specifically, the start address of the first interleaving-enabled object in the current level is calculated based on the start address in the logical address range of the previous level and the single-point address resolution logic.

[0113] Step S320, obtaining the starting addresses of the second object, ..., and the Kth object in the current level by increasing the corresponding addresses in sequence according to the starting address, where K is the number of objects in the current level.

[0114] Specifically, the step of increasing the starting address in sequence includes:

[0115] 1) When the interleaving enable state of the current level is disabled, the logical address of the previous level is incremented in sequence according to the starting address based on the system configuration of each object;

[0116] 2) When the interleaving enable state of the current level is enabled, the interleaving granularity of the current level and the logical address of the previous level are incremented in sequence according to the starting address;

[0117] Among them, in this embodiment, the starting addresses of the first object, ..., Kth object in this level are scanned in sequence to obtain, and when it is scanned that the object in this level is repeated or the starting address of an object obtained exceeds the end address in the logical address range of the previous level, the starting address scanning of this level is terminated, and the acquisition of the starting addresses of each object in this level is completed.

[0118] In particular, in the continuous system address resolution method of this embodiment, it also includes: detecting whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of this level; in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of this level, incrementing the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of this level.

[0119] That is, in this embodiment, if hierarchical interleaving is enabled and the starting address is not an integer multiple of the interleaving granularity, when the starting address of the previous level is incremented for the first time, the incremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0120] For example, the second-level interleaving granularity is 4K-Byte, and the starting address of the first level is 10K. The starting address 10K is not an integer multiple of the interleaving granularity 4K-Byte. The first increment increases to the next integer multiple address 12K, so that the first increment address is an integer multiple of the interleaving granularity. Then, the starting address of the second object in the second level is calculated based on the first increment address and the single-point address resolution logic.

[0121] In this embodiment, if Figure 7 As shown, when the interleaving enable state of the current level is enabled, the step of obtaining the end address in the logical address range of each object in the current level based on the logical address range of the previous level and the system level information includes:

[0122] Step S330, obtaining the end address of the first object of the current level based on the end address in the logical address range of the previous level. Specifically, the end address in the logical address range of the previous level and the single-point address resolution logic calculate the end address of the first interleaving-enabled object.

[0123] Step S340, obtaining the end addresses of the second object, ..., and the Kth object in the current level by sequentially decreasing the corresponding addresses according to the end address.

[0124] Specifically, the step of decreasing in order according to the end address includes:

[0125] 1) When the interleaving enable state of the current level is disabled, the logical address of the previous level is decremented in sequence according to the starting address based on the system configuration of each object;

[0126] 2) When the interleaving enable state of the current layer is enabled, the interleaving granularity based on the current layer and the logical address of the previous layer are decreased in sequence according to the starting address.

[0127] Among them, in this embodiment, the end addresses of the first object, ..., and the Kth object in the current level (the second level, ..., any level in the Nth level) are scanned in sequence to obtain, and when the object in the current level is scanned to be repeated or the end address of an object obtained exceeds the starting address in the logical address range of the previous level, the end address scanning of the current level is terminated, and the acquisition of the end addresses of each object in the current level is completed.

[0128] In particular, in the continuous system address resolution method of this embodiment, it also includes: detecting whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of this level; in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of this level, incrementing the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of this level.

[0129] That is, in this embodiment, if hierarchical interleaving is enabled and the end address is not an integer multiple of the interleaving granularity, when the end address of the previous level is decremented for the first time, the decremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0130] For example, the second-level interleaving granularity is 4K-Byte, and the end address of the previous level + 1 is 22K, which is not an integer multiple of the interleaving granularity of 4K-Byte. The first decremented address is decremented to an integer multiple of the interleaving granularity of 20K, so the end address of the next scan is 22K-1. Then, the end address of the second object is calculated based on the first decremented address and the single-point address resolution logic.

[0131] It should be noted that, in this embodiment, when obtaining the logical address range of each object in this layer, step S310 can be executed first: obtain the starting address of the first object in this layer, and then execute step 330, or step S330 can be executed first: obtain the ending address of the first object in this layer, and then execute step S310. In addition, step S310 and step S330 can also be executed at the same time: obtain the starting address and ending address of the first object in this layer at the same time.

[0132] Similarly, when obtaining the logical address range of the second object, ..., Kth object in this level, you can first obtain the starting address of each object and then obtain the ending address of each object, or you can first obtain the ending address of each object and then obtain the starting address of each object, or you can simultaneously perform the process of obtaining the starting address and ending address of each object.

[0133] In order to enable those skilled in the art to further understand the continuous system address resolution method of this embodiment, the implementation process of the continuous system address resolution method of this embodiment is described below with a specific example.

[0134] like Figure 8 As shown, continuous system address range input is received, and system level information is read and obtained: the number of levels, the interleaving size granularity when each level of interleaving is enabled, the address configuration range when interleaving is not enabled, and other information are obtained.

[0135] Get the logical address range of each level. The first level is the continuous system address range of the input, and the other levels are the logical address range of the output of the previous level.

[0136] For each level, get the start address and end address of each object respectively. The two can be done in sequence or at the same time.

[0137] When obtaining the starting address of each object, the starting address of an object in the hierarchy is obtained according to the single-point address resolution logic, and it is determined whether the hierarchical objects begin to repeat. If so, the subsequent process is terminated to obtain the starting address of each object in the current hierarchy. If not, it is continued to determine whether interleaving is enabled in the current hierarchy. If interleaving is enabled, the input address is gradually increased in interleaving granularity. If interleaving is not enabled, it jumps to the configuration address starting logic position of the next object, and then detects whether the incremented address exceeds the end address. If so, the starting address configuration of each object in the layer is terminated. If not, the starting address of the next object in the hierarchy is continued to be obtained according to the single-point address resolution logic. The above process is repeated to complete the acquisition of the starting addresses of each object in the hierarchy.

[0138] When obtaining the end address of an object, the end address of an object in the hierarchy is obtained according to the single-point address resolution logic, and it is determined whether the hierarchical objects begin to repeat. If so, the subsequent process is terminated to obtain the end address of each object in this hierarchy. If not, it is continued to determine whether interleaving is enabled for this hierarchy. If interleaving is enabled, the input address is gradually reduced by the interleaving granularity. If interleaving is not enabled, it jumps to the configuration address end logic position of the next object, and then detects whether the decremented address exceeds the starting address. If so, the end address configuration of each object in this layer is terminated. If not, the end address of the next object in this hierarchy is continued to be obtained according to the single-point address resolution logic, and the above process is repeated to complete the acquisition of the end address of each object in this hierarchy.

[0139] After the start address and the end address of each object in the hierarchy are obtained, the acquisition of the logical address range of each object in the hierarchy is completed.

[0140] Then repeat the above process to carry out the logical address range of each object in the next level until the logical address range of all levels in the system is completed, and obtain the logical address range of the set of memory particle widths.

[0141] like Fig. 9 As shown, a specific address resolution example of applying the continuous system address resolution method in this embodiment is shown.

[0142] Assume that a system has two memory channels, each channel is connected to a 16GB 2-rank memory 20, and the interleaving enable states of the memory channel level and the memory particle set (rank) level are both enabled. Now we want to calculate the logical address range of the set of each memory particle bit width in the continuous system address range [10K, 22K-1].

[0143] The first step is to obtain system level information. The system includes a channel level and a collection level of memory particle bit width. The number of system levels is 2, and the interleaving enable status of each level is enabled. The system enables two-level interleaving of memory channels (channel) and collections (ranks) of memory particle bit widths. The channel level is the first level, and the collection level of memory particle bit widths is the second level. The number of channels in the channel level is 2, including the first channel 310 and the second channel 320, and the interleaving granularity is 4K-Byte. The number of collections of memory particle bit widths in the collection level of memory particle bit widths is 4, and the interleaving granularity is 10K-Byte.

[0144] The second step is to obtain the logical address range of each object in the first level based on the continuous system address and the system level information. Calculate the starting and ending logical address ranges of each object in the first channel 310 and the second channel 320 levels, and obtain the logical address range of the first channel 310 [6K, 12K-1], and obtain the logical address range of the second channel 320 [4K, 10K-1]. The specific process is as follows:

[0145] 1) Calculate the starting address of the channel level. According to the starting address 10K in the continuous system address, the starting address 6K of the first channel 310 is obtained. The continuous system address is incremented to an integer multiple of the interleaving granularity size of the channel level 12K, and the 12K system address is calculated to obtain the starting address 4K of the second channel 320. All objects at the channel level are scanned, and the scan ends.

[0146] 2) Calculate the end address of the first channel 310. According to the end address 22K-1 in the continuous system address, the end address 10K-1 of the second channel 320 is obtained. The system end address is decremented to an integer multiple of the interleaving granularity size 20K-1 at the channel level, and the 20K-1 system address is calculated to obtain the end address 12K-1 of the first channel 310. All objects at the channel level are scanned, and the scan ends.

[0147] The third step is to obtain the logical address range of each object in the second level based on the logical address range of the first level and the system level information. Calculate the logical address range of each object in the set level of memory particle width, obtain the address range of the set 311 of the first memory particle width of the first channel 310 [6K, 10K-1], obtain the address range of the set 312 of the second memory particle width of the first channel 310 [0K, 2K-1], and obtain the address range of the set 321 of the first memory particle width of the second channel 320 [4K, 10K-1]. The specific process is as follows:

[0148] 1) Calculate the starting address of the set of bit widths of each memory particle corresponding to the first channel 310. According to the starting position 6K of the first channel 310, the starting address of the set 311 of the first memory particle bit width of the first channel 310 is 6K. The starting address of the first channel 310 is incremented by an integer multiple of the interleaving granularity size of the set level of the memory particle bit width to 10K, and the starting address of the set 312 of the second memory particle bit width of the first channel 310 is calculated to be 0K according to the 10K address in the first channel 310. The two sets of memory particle bit widths of the first channel in the second level are scanned, and the scan ends.

[0149] 2) Calculate the end address of the set of bit widths of each memory particle corresponding to the first channel 310. According to the end address 12K-1 of the first channel 310, the end address of the set 312 of the second memory particle bit width of the first channel 310 is 2K-1. The end address of the first channel 310 is reduced to an integer multiple of the interleaving granularity size of the set level of the memory particle bit width to 10K-1, and according to the address 10K-1, the end address of the set 311 of the first memory particle bit width of the first channel 310 is 10K-1. The two sets of memory particle bit widths of the first channel in the second level are scanned, and the scan is completed.

[0150] 3) Calculate the starting address of the set of bit widths of each memory particle corresponding to the second channel 320. According to the starting address 4K of the second channel 320, the starting address of the set 321 of the first memory particle width of the second channel 320 is 4K. The starting address of the second channel 320 is incremented by the interleaving granularity to 10K, which exceeds the end address 10K-1 of the second channel 320. There is no need to continue scanning the set 322 of the second memory particle width of the second channel 320, and the scanning ends.

[0151] 4) Calculate the end address of the set of bit widths of each memory particle corresponding to the second channel 320. According to the end address 10K-1 of the second channel 320, the end address of the set 321 of the first memory particle width of the second channel 320 is obtained as 10K-1. The end address of the second channel 320 is incremented to the interleaving granularity size of -1. If it exceeds the start address 0 of the second channel 320, there is no need to continue scanning the set 322 of the second memory particle width of the second channel 320, and the scanning ends.

[0152] Therefore, when the continuous system address resolution method of this embodiment resolves the continuous system address, the algorithm consumes a fixed time, and the time will not increase as the continuous system address range increases, which effectively improves the efficiency of the continuous system address resolution.

[0153] Example 2

[0154] This embodiment provides a continuous system address resolution device. Fig.10The following is a block diagram showing the principle structure of the continuous system address resolution device 100 of this embodiment. Fig.10 As shown, the continuous system address resolution device 100 in this embodiment includes: a system level information acquisition module 110 and a logical address range acquisition module 120 .

[0155] In this embodiment, the system level information acquisition module 110 is used to acquire system level information when receiving continuous system addresses.

[0156] In this embodiment, the system layer information includes but is not limited to the number of layers, the interleaving enablement state of each layer, the interleaving granularity of each layer, and the number of objects included in each layer.

[0157] Specifically, the number of levels in the address resolution process of a given system is obtained, such as two levels consisting of memory channels (channels) and a set (rank) of memory particle widths. For each level, the interleaving enable state (interleaving enabled or interleaving not enabled) and the interleaving granularity (specific size value) are obtained. Among them, when interleaving is not enabled, the logical address range of each object system configuration of the level is obtained, and the number of objects of each level is obtained, such as how many channels the system memory has and how many memory particle widths each channel has.

[0158] In this embodiment, the logical address range acquisition module 120 acquires the logical address range of each object in the first layer based on the continuous system address and the system layer information, and when sequentially acquiring the logical address range of each object in the second layer, ..., and Nth layer of the system, acquires the logical address range of each object in the current layer based on the logical address range of the previous layer and the system layer information; wherein N is the number of layers, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object.

[0159] Specifically, as shown in FIG11 , in this embodiment, the logic address range acquisition module 120 includes: a start address acquisition unit 121 and an end address acquisition unit 122 .

[0160] In this embodiment, M is the number of objects in the first level, and K is the number of objects in any level of the second level, ..., and the Nth level. It should be noted that the value of K for each level in the second level, ..., and the Nth level can be the same or different.

[0161] In this embodiment, the starting address acquisition unit 121 acquires the starting address of the first object of the first level based on the starting address of the continuous system address, acquires the starting addresses of the second object, ..., and the Mth object in the first level by sequentially increasing the corresponding addresses according to the starting address, and acquires the starting address of the first object of the current level based on the starting address in the logical address range of the previous level, acquires the starting addresses of the second object, ..., and the Kth object in the current level by sequentially increasing the corresponding addresses according to the starting address, where M is the number of objects in the first level, and K is the number of objects in the current level.

[0162] Specifically, in the starting address obtaining unit 121:

[0163] When the first-level interleaving enable state is disabled, based on the system configuration of each object and the continuous system addresses, the starting address is incremented in sequence;

[0164] When the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are incremented in sequence according to the starting address;

[0165] When the interleaving enable state of the current level is disabled, the logical addresses of the previous level are incremented in sequence according to the starting address based on the system configuration of each object;

[0166] When the interleaving enabling state of the current level is enabled: the interleaving granularity based on the current level and the logical address of the previous level are incremented in sequence according to the starting address.

[0167] In this embodiment, the end address acquisition unit 122 is used to acquire the end address of the first object of the first level based on the end address of the continuous system address, and acquire the end addresses of the second object, ..., and Mth object in the first level by sequentially decreasing the corresponding addresses of the end addresses, and acquire the end address of the first object of the current level based on the end address in the logical address range of the previous level, and acquire the end addresses of the second object, ..., and Kth object in the current level by sequentially decreasing the corresponding addresses of the end addresses.

[0168] Specifically, in the end address obtaining unit 122:

[0169] When the first-level interleaving enable state is disabled, the system configuration of each object and the continuous system addresses are decremented in sequence according to the starting address;

[0170] When the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are decreased in sequence according to the starting address;

[0171] When the interleaving enable state of the current level is disabled, the logical addresses of the previous level are sequentially decreased according to the starting address based on the system configuration of each object;

[0172] When the interleaving enabling state of the current level is enabled, the interleaving granularity based on the current level and the logical address of the previous level are decreased in sequence according to the starting address.

[0173] In this embodiment, the input of the first level is the continuous system address. Specifically, in this embodiment, the start address and the end address of each object in the first level are obtained based on the continuous system address and the system level information respectively.

[0174] As shown in FIG12 , in this embodiment, the logic address range acquisition module 120 further includes: a start address scanning unit 123 and an end address scanning unit 124 .

[0175] In this embodiment, the starting address scanning unit 123 is used to scan and obtain the starting addresses of the first object, ..., Mth object in the first level. When it is scanned that the object in the first level is repeated or the starting address of a certain object obtained exceeds the end address of the continuous system address, the starting address scanning of the first level is terminated and the acquisition of the starting addresses of each object in the first level is completed. The unit is also used to sequentially scan and obtain the starting addresses of the first object, ..., Kth object in the current level (any level in the second level, ..., Nth level). When it is scanned that the object in the current level is repeated or the starting address of a certain object obtained exceeds the end address in the logical address range of the previous level, the starting address scanning of the current level is terminated and the acquisition of the starting addresses of each object in the current level (any level in the second level, ..., Nth level) is completed.

[0176] That is to say, in this embodiment, if hierarchical interleaving is enabled and the starting address is not an integer multiple of the interleaving granularity, when the continuous system address is incremented for the first time, the incremented address is padded to an address that is an integer multiple of the interleaving granularity, or when the starting address of the previous level is incremented for the first time, the incremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0177] In this embodiment, the end address scanning unit 1245 is used to sequentially scan and obtain the end addresses of the first object, ..., Mth object in the first level. When the object in the first level is scanned to be repeated or the end address of an object obtained exceeds the starting address of the continuous system address, the end address scanning of the first level is terminated and the acquisition of the end addresses of each object in the first level is completed. The end address scanning unit 1245 is used to sequentially scan and obtain the end addresses of the first object, ..., Kth object in the current level. When the object in the current level is scanned to be repeated or the end address of an object obtained exceeds the starting address in the logical address range of the previous level, the end address scanning of the current level is terminated and the acquisition of the end addresses of each object in the current level is completed.

[0178] In this embodiment, if hierarchical interleaving is enabled and the end address is not an integer multiple of the interleaving granularity, when the continuous system address is decremented for the first time, the decremented address is padded to an address that is an integer multiple of the interleaving granularity, or when the end address of the previous level is decremented for the first time, the decremented address is padded to an address that is an integer multiple of the interleaving granularity.

[0179] As shown in FIG13 , in this embodiment, the logic address range acquisition module 120 further includes: a multiple detection unit 125 and a multiple adjustment unit 126 .

[0180] In this embodiment, the multiple detection unit 125 is used to detect whether the address corresponding to the first increment of the start address is an integer multiple of the hierarchical interleaving granularity, and whether the address corresponding to the first decrement of the end address is an integer multiple of the hierarchical interleaving granularity.

[0181] In this embodiment, the multiple adjustment unit 126 is used to increase the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of the level, or to decrease the address corresponding to the first decrement of the decrementing address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first decrement of the ending address is not an integer multiple of the interleaving granularity of the level.

[0182] The technical features specifically implemented by the continuous system address resolution device 100 of this embodiment are substantially the same as the principles of the continuous system address resolution method in Embodiment 1, and the technical contents that are common between the method and the device will not be repeated.

[0183] Example 3

[0184] like Fig.14As shown, this embodiment further provides an electronic device 10, which includes a memory 102 for storing a computer program; and a processor 101 for running the computer program to implement the steps of the continuous system address resolution method as described in Example 1.

[0185] The memory 102 is connected to the processor 101 through a device bus and communicates with each other. The memory 102 is used to store computer programs, and the processor 101 is used to run computer programs so that the user terminal 200 executes the continuous system address resolution method. The continuous system address resolution method has been described above and will not be repeated here.

[0186] It should be noted that the device bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The device bus can be divided into an address bus, a data bus, a control bus, etc. The communication interface is used to realize the communication between the database access device and other devices (such as a client, a read-write library, and a read-only library). The memory 102 may include a random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage.

[0187] The above-mentioned processor 101 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0188] Example 4

[0189] This embodiment provides a storage medium storing program instructions, which, when executed by a processor, implement the steps of the continuous system address resolution method described in Embodiment 1. Embodiment 1 has already described the continuous system address resolution method, which will not be described again.

[0190] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the method embodiments in Example 1 are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0191] In summary, when resolving continuous system addresses, the algorithm of the present invention consumes a fixed amount of time, and the time does not increase as the range of continuous system addresses increases, thereby effectively improving the efficiency of resolving continuous system addresses. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0192] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for continuous system address resolution, characterized in that: The following steps are involved: Upon receiving a continuous system address, obtaining system level information; The system layer information includes the number of layers, the interleaving enablement state of each layer, the interleaving granularity of each layer, and the number of objects included in each layer; Acquire a logical address range of each object in the first hierarchy based on the continuous system addresses and the system hierarchy information; When sequentially acquiring the logical address range of each object in the second level, ..., and Nth level of the system, the logical address range of each object in the current level is acquired based on the logical address range of the previous level and the system level information; wherein N is the number of levels, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object.

2. The continuous system address resolution method according to claim 1, characterized in that: The acquiring the logical address range of each object in the first layer based on the continuous system address and the system layer information comprises: Acquire a start address of a first object of a first level based on a start address of the continuous system addresses; Obtain the starting addresses of the second object, ..., and the Mth object in the first level by increasing the corresponding addresses in sequence according to the starting addresses; Acquire an end address of a first object of a first level based on an end address of the continuous system addresses; The end addresses of the second object, ..., and the Mth object in the first level are obtained by decreasing the corresponding addresses in sequence according to the end address, where M is the number of objects in the first level.

3. The continuous system address resolution method according to claim 2, characterized in that: The step of increasing the starting address in sequence includes: When the first-level interleaving enable state is disabled, based on the system configuration of each object and the continuous system addresses, the starting address is incremented in sequence; When the first-level interleaving enable state is enabled, the interleaving granularity based on the first level and the continuous system addresses are incremented in sequence according to the starting address; The step of decreasing the end address in sequence includes: When the first-level interleaving enable state is disabled, the system configuration of each object and the continuous system addresses are decremented in sequence according to the starting address; When the first-level interleaving enabling state is enabled, the interleaving granularity based on the first level and the continuous system addresses are sequentially decreased according to the starting address.

4. The continuous system address resolution method according to claim 2 or 3, characterized in that: When it is found that the object in the first level is repeated or the start address of a certain object obtained exceeds the end address of the continuous system address, the start address scanning of the first level is ended and the acquisition of the start addresses of each object in the first level is completed.

5. The continuous system address resolution method according to claim 2 or 3, characterized in that: When the object in the first level is repeated or the end address of an acquired object exceeds the start address of the continuous system address, the end address scanning of the first level is terminated, and the acquisition of the end addresses of the objects in the first level is completed.

6. The continuous system address resolution method according to claim 1, characterized in that: The acquiring the logical address range of each object in the current level based on the logical address range of the previous level and the system level information includes: Obtaining the starting address of the first object at the current level based on the starting address in the logical address range of the previous level; The starting addresses of the second, ..., and Kth objects in this level are obtained by increasing the corresponding addresses in sequence according to the starting address; Obtaining the end address of the first object at the current level based on the end address in the logical address range of the previous level; The end addresses of the second, ..., Kth objects in this level are obtained by decreasing the corresponding addresses in sequence according to the end address, where K is the number of objects in this level.

7. The continuous system address resolution method according to claim 6, characterized in that: The step of increasing the starting address in sequence includes: When the interleaving enable state of the current level is disabled, the logical addresses of the previous level are incremented in sequence according to the starting address based on the system configuration of each object; When the interleaving enable state of the current level is enabled, the interleaving granularity based on the current level and the logical address of the previous level are incremented in sequence according to the starting address; The step of decreasing the end address in sequence includes: When the interleaving enable state of the current level is disabled, the logical addresses of the previous level are sequentially decreased according to the starting address based on the system configuration of each object; When the interleaving enable state of the current level is enabled, the interleaving granularity based on the current level and the logical address of the previous level are decreased in sequence according to the starting address.

8. The continuous system address resolution method according to claim 6 or 7, characterized in that: When it is found that the object in this level is repeated or the start address of an object obtained exceeds the end address in the logical address range of the previous level, the start address scanning of this level is terminated and the acquisition of the start addresses of the objects in this level is completed.

9. The continuous system address resolution method according to claim 6 or 7, characterized in that: When the object in the current level is repeated or the end address of an object obtained exceeds the start address in the logical address range of the previous level, the end address scanning of the current level is terminated and the acquisition of the end addresses of the objects in the current level is completed.

10. The continuous system address resolution method according to claim 3 or 7, characterized in that: Also includes: Detecting whether the address corresponding to the first increment of the starting address is an integer multiple of the interleaving granularity of the level; In response to the address corresponding to the first increment of the start address not being an integer multiple of the hierarchical interleaving granularity, the address corresponding to the first increment of the start address is incremented to an integer multiple of the hierarchical interleaving granularity.

11. The continuous system address resolution method according to claim 3 or 7, characterized in that: Also includes: Detecting whether the address corresponding to the first decrement of the end address is an integer multiple of the interleaving granularity of the level; In response to the address corresponding to the first decrease of the end address not being an integer multiple of the hierarchical interleaving granularity, the address corresponding to the first decrease of the end address is decreased to an integer multiple of the hierarchical interleaving granularity.

12. A continuous system address resolution device, characterized in that: include: A system level information acquisition module, used to acquire system level information when receiving a continuous system address; The system layer information includes the number of layers, the interleaving enablement state of each layer, the interleaving granularity of each layer, and the number of objects included in each layer; A logical address range acquisition module is used to acquire the logical address range of each object in the first layer based on the continuous system address and the system layer information, and when sequentially acquiring the logical address range of each object in the second layer, ..., and the Nth layer of the system, acquire the logical address range of each object in the current layer based on the logical address range of the previous layer and the system layer information; wherein N is the number of layers, N is an integer greater than or equal to 2, and the logical address range of the object includes the starting address and the ending address of the object.

13. The continuous system address resolution device according to claim 12, characterized in that: The logical address range acquisition module includes: a starting address obtaining unit, which obtains a starting address of a first object of a first level based on a starting address of the continuous system address, obtains starting addresses of a second object, ..., an Mth object in the first level in sequence according to the starting address, and obtains a starting address of the first object of the current level based on a starting address in a logical address range of a previous level; The starting address is incremented by the corresponding address in sequence according to the starting address to obtain the starting address of the second object, ..., and the Kth object in this level, where M is the number of objects in the first level, and K is the number of objects in this level; An end address acquisition unit is used to acquire the end address of the first object of the first level based on the end address of the continuous system address, and acquire the end addresses of the second object, ..., and Mth object in the first level by sequentially decreasing the corresponding addresses of the end addresses, and acquire the end address of the first object of the current level based on the end address in the logical address range of the previous level, and acquire the end addresses of the second object, ..., and Kth object in the current level by sequentially decreasing the corresponding addresses of the end addresses.

14. The continuous system address resolution device according to claim 13, characterized in that: The starting address acquisition unit, when the first-level interleaving enable state is not enabled, based on the system configuration of each object and the continuous system address, increases in sequence according to the starting address; when the first-level interleaving enable state is enabled, based on the interleaving granularity of the first level and the continuous system address, increases in sequence according to the starting address; when the interleaving enable state of the current level is not enabled, based on the system configuration of each object and the logical address of the previous level, increases in sequence according to the starting address; when the interleaving enable state of the current level is enabled: based on the interleaving granularity of the current level and the logical address of the previous level, increases in sequence according to the starting address; When the first-level interleaving enable state is not enabled, the end address acquisition unit decreases in sequence from the starting address based on the system configuration of each object and the continuous system addresses; when the first-level interleaving enable state is enabled, the end address acquisition unit decreases in sequence from the starting address based on the interleaving granularity of the first level and the continuous system addresses; when the current-level interleaving enable state is not enabled, the end address acquisition unit decreases in sequence from the starting address based on the system configuration of each object and the logical address of the previous level; when the current-level interleaving enable state is enabled, the end address acquisition unit decreases in sequence from the starting address based on the interleaving granularity of the current level and the logical address of the previous level.

15. The continuous system address resolution device according to claim 13, characterized in that: The logical address range acquisition module also includes: a start address scanning unit, used to scan and obtain the start addresses of the second object, ..., and the Mth object in the first level, and when it is found that the object in the first level is repeated or the start address of a certain object obtained exceeds the end address of the continuous system address, the start address scanning of the first level is terminated, and the start address acquisition of each object in the first level is completed; and used to sequentially scan and obtain the start addresses of the second object, ..., and the Kth object in the current level, and when it is found that the object in the current level is repeated or the start address of a certain object obtained exceeds the end address in the logical address range of the previous level, the start address scanning of the current level is terminated, and the start address acquisition of each object in the current level is completed; An end address scanning unit is used to sequentially scan and obtain the end addresses of the second object, ..., Mth object in the first level. When it is scanned that the object in the first level is repeated or the end address of a certain object obtained exceeds the starting address of the continuous system address, the end address scanning of the first level is terminated and the acquisition of the end addresses of each object in the first level is completed. The unit is also used to sequentially scan and obtain the end addresses of the second object, ..., Kth object in the current level. When it is scanned that the object in the current level is repeated or the end address of a certain object obtained exceeds the starting address in the logical address range of the previous level, the end address scanning of the current level is terminated and the acquisition of the end addresses of each object in the current level is completed.

16. The continuous system address resolution device according to claim 13, characterized in that: The logical address range acquisition module also includes: A multiple detection unit, used to detect whether the address corresponding to the first increment of the start address is an integer multiple of the interleaving granularity of the level, and whether the address corresponding to the first decrement of the end address is an integer multiple of the interleaving granularity of the level; A multiple adjustment unit is used to increase the address corresponding to the first increment of the starting address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first increment of the starting address is not an integer multiple of the interleaving granularity of the level, or to decrease the address corresponding to the first decrement of the ending address to an integer multiple of the interleaving granularity of the level in response to the address corresponding to the first decrement of the ending address is not an integer multiple of the interleaving granularity of the level.

17. A storage medium storing program instructions, characterized in that: When the program instructions are executed by a processor, the steps of the continuous system address resolution method according to any one of claims 1 to 11 are implemented.

18. An electronic device, characterized in that: It comprises a memory for storing a computer program; and a processor connected to the memory for running the computer program to implement the steps of the continuous system address resolution method as claimed in any one of claims 1 to 11.

Images