A timing calculation method for FPGA chip integrating large IP core

Abstract

The present invention provides a timing calculation method for an FPGA chip integrated with a large IP core, the method comprising: obtaining port information of multiple ports of the IP module, wherein each port of the IP module is coupled with a winding module of an FPGA system; determining the winding coordinates of each port of the IP module according to the obtained port information, and saving the winding coordinates of each port as a data file; for each of the multiple ports, calculating the delay information of the port connected to other logic resource modules according to the winding coordinates of the port. The accuracy of the delay calculation of the FPGA chip is effectively improved, the error is reduced, and the performance after the integration of the IP and the FPGA chip is effectively guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of FPGA, and in particular to a timing calculation method for an FPGA chip integrating a large IP. Background Art

[0002] When the IP integrated in the FPGA system is relatively large, the IP has multiple ports that need to be connected to other logic units of the FPGA. The connection between the multiple ports of the IP and other logic units is achieved through XBAR (winding module). XBAR can be understood as the connection resource inside the FPGA. Because, in the existing software architecture, there is only one coordinate corresponding to an IP, and only one corresponding XBAR coordinate can be obtained. When there is only one XBAR corresponding to the IP, when calculating the delay between the IP and other logic units of the FPGA, the calculation result will have a large error. Summary of the invention

[0003] In view of this, the embodiment of the present application provides a timing calculation method for an FPGA chip integrated with a large IP core, which effectively improves the accuracy of the delay calculation of the FPGA chip, reduces errors, and effectively guarantees the performance after the IP core is integrated with the FPGA chip.

[0004] In a first aspect, an embodiment of the present application provides a timing calculation method for an FPGA chip integrating a large IP core, the method being applied to an FPGA chip, the FPGA chip including at least one IP module and at least one other logic resource module, the method comprising:

[0005] For any one of the at least one IP module, obtaining port information of a plurality of ports in the IP module for connecting with other logic resource modules; wherein any one of the plurality of ports is connected with other logic resource modules through a wiring module;

[0006] Determining a winding coordinate of each of the plurality of ports according to the port information;

[0007] For each of the multiple ports, delay information of the connection between the port and other logic resource modules is calculated according to the winding coordinates of the port.

[0008] Optionally, the port includes an input port and an output port of the IP module.

[0009] Optionally, the winding coordinate of the port includes an X value and a Y value, and the X value of the winding coordinate corresponding to each port in the multiple ports of the same IP module is the same.

[0010] Optionally, after determining the winding coordinates of each of the multiple ports according to the acquired port information, the method further includes:

[0011] saving the winding coordinates of each of the plurality of ports as a data file;

[0012] When calculating the timing of the FPGA chip, the data file is stored in the memory.

[0013] Optionally, store the data file into memory, including:

[0014] For multiple ports of the same IP module, the port name of each of the multiple ports and the Y value of the winding coordinate of each port are saved in the memory.

[0015] Optionally, when the source or target in any connection relationship on the FPGA chip is a port of the IP module, the Y value of the winding coordinate of the port corresponding to the source or target is searched in the memory, and the delay information of the connection is determined based on the Y value; wherein, any connection relationship includes a source and a target, and the direction of the connection relationship is from the source to the target.

[0016] The embodiment of the present application provides a timing calculation method for an FPGA chip integrated with a large IP core. In one embodiment, when a large IP module is integrated on the FPGA chip, the XBAR coordinates corresponding to each port in the IP module are pre-calculated and stored. When performing timing analysis on the FPGA chip, the delay when each port in the IP module is connected to other modules is calculated by using the pre-stored XBAR coordinates corresponding to each port of the IP module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 It is a structural schematic diagram of an FPGA chip;

[0019] Figure 2 A schematic diagram of connecting the IP module on the FPGA chip with other logic units;

[0020] Figure 3 A flowchart of a method for performing timing analysis on an FPGA chip is provided in the present application. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

[0022] In the description of the present application, terms such as "center", "up", "down", "front", "back", "left", "right", "east", "south", "west", "north", "vertical", "horizontal", "top", "bottom", "inside" and "outside" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0023] Figure 1 Figure 1 is a schematic diagram of the structure of an FPGA chip. Figure 1 As shown, the FPGA chip includes an IP module and at least one other logic resource module. Specifically, the other logic resource modules may be: a programmable logic block (CLB), an input / output unit (IOB), a clock management module (DCM), and an embedded RAM (BRAM).

[0024] Programmable logic blocks are the basic logic units inside FPGAs, and their number and characteristics vary depending on the device. Generally, each CLB consists of several lookup tables and additional logic (such as multiplexers, triggers, carry logic, arithmetic logic, etc.), which can be used to implement combinational logic and sequential logic, and can also be configured as distributed RAM and distributed ROM.

[0025] The programmable input / output unit, referred to as the I / O unit, is the interface between the FPGA chip and the external circuit, and is used to complete the driving and matching requirements of the input / output signals under different electrical characteristics.

[0026] The clock management module is mainly used to eliminate clock delay, frequency synthesis, and clock phase adjustment. It can provide accurate clock synthesis and reduce clock jitter.

[0027] Embedded block RAM is the most commonly used functional block inside FPGA besides logic resources. It is integrated inside FPGA in the form of hard core and becomes the most important storage resource of FPGA.

[0028] Embedded dedicated IP modules refer to soft-core IP or hard-core IP provided by FPGA manufacturers, which are pre-designed, rigorously tested and optimized, such as DLL, PLL, DSP or MicroBlaze processor, Nios processor and other soft cores, dedicated multipliers, floating-point units, serial-parallel transceivers SERDES or PowerPC, ARM and other hard cores.

[0029] The modules / units on the FPGA chip are interconnected. The interconnection between the modules / units is achieved through the connection resources XBAR inside the FPGA chip.

[0030] When designing FPGA chips, they are usually designed in columns, that is, when an IP module is integrated into an FPGA chip, it can be considered that the IP module only occupies one unit in the horizontal direction of the chip, but occupies multiple units in the vertical direction. When the IP module integrated on the FPGA chip is large, multiple ports in the IP module need to be connected to other logic units on the FPGA chip. At this time, multiple ports of the IP module only correspond to one coordinate. This will cause inaccurate delays when the IP module is connected to the logic unit during timing analysis of the FPGA chip, which will affect the subsequent layout performance of the chip.

[0031] Figure 2 This is a schematic diagram of connecting the IP module on the FPGA chip with other logic units. Figure 2 It can be seen that the IP module occupies multiple units in the vertical direction of the FPGA chip. That is, the IP module occupies multiple XBAR wiring resources in the vertical direction. If the IP module is considered to have only one position coordinate when performing timing analysis on the PFGA chip, then even if the value of this position coordinate in the vertical direction is the middle value of the IP module in the vertical direction, a large error will still occur when performing timing analysis on the FPGA chip.

[0032] Figure 3 The present invention provides a flowchart of a method for timing analysis of FPGA chips. The method is mainly used when a large IP module is integrated on the FPGA chip. The connection between the IP module on the FPGA chip and other logic units is analyzed for delay. Figure 3 The method includes: step S301-step S303.

[0033] Step S301, obtaining port information of multiple ports in the IP module for connecting with other logic resource modules.

[0034] When the IP module integrated on the FPGA chip is relatively large, many ports on the IP module need to be connected to other logic units. The interconnection between the IP module and other logic units is achieved through the wiring resources XBAR inside the FPGA chip. The wiring resources XBAR are the connection points between the modules and are evenly distributed in the FPGA module.

[0035] In a possible example, the plurality of ports connected to other logic resource modules include ports connected to other modules as input ports or output ports of an IP module.

[0036] Step S302: determining the routing coordinates of each of the multiple ports in the IP module for connecting with other logic resource modules according to the acquired port information.

[0037] When an IP module is integrated on an FPGA chip, the port information of each port on the IP module is saved. In a possible example, the port information includes: port name, winding coordinates corresponding to the port, whether to connect to other logic resource modules, and the module name of the connected logic resource module (or the port name of the port on the module for connection).

[0038] In a possible example, all ports connected to XBAR in the IP module can be found in a pre-generated hardware architecture (some models and connection relationships composed of Verilog) through tools written in C and Python. Then the port information of these ports is obtained, and the XBAR coordinates connected to the port are found. Among them, the X values ​​of the XBAR coordinates corresponding to multiple ports of the same IP module are the same, and the Y values ​​are within a certain range.

[0039] After obtaining the XBAR coordinates corresponding to the multiple ports, the Y value of the XBAR coordinate corresponding to each of the multiple ports is saved in the same data file. The content saved in the data file includes the module name, the port name, and the corresponding XBAR Y coordinate value.

[0040] Step S303: for each of the multiple ports, calculate the delay information when the port is connected to other logic resource modules according to the winding coordinates of the port.

[0041] Before calculating the timing of the FPGA chip, that is, before the layout algorithm is executed, the layout module reads a pre-saved data file and saves the port information in the data file into the memory.

[0042] When an IP module on an FPGA chip is connected to other logic resource modules through a port, a connection relationship is generated. Each connection relationship has a source and a target. The direction of each connection relationship is from the source to the target. When the layout algorithm is executed for the FPGA chip, the layout algorithm will process all the connection relationships to ensure that the clock constraints are met.

[0043] When the source or target in a connection relationship is a port of an IP module, the Y value of the XBAR corresponding to the port can be found in the memory, and then the XBAR coordinates (including X value and Y value) corresponding to the port can be obtained. The delay of each connection relationship on the FPGA chip is calculated by obtaining the XBAR coordinates. And the layout of other logic resource modules is adjusted by the obtained delay. In an embodiment of the present application, when a large IP module is integrated on the FPGA chip, the XBAR coordinates corresponding to each port in the IP module are pre-calculated and stored. When performing timing analysis on the FPGA chip, the delay when each port in the IP module is connected to other modules is calculated by the XBAR coordinates corresponding to each port of the IP module stored in advance, so that the obtained delay information is more accurate. Furthermore, in the present invention application, there is no need to change the software architecture on the FPGA chip.

[0044] It should be noted that, although only one IP module is integrated on the FPGA chip in the embodiment of the present application, the number of IP modules integrated on the FPGA chip is not limited in the embodiment of the present application. When multiple IP modules are integrated on the FPGA chip, the process of performing timing analysis on each IP module is the same as step S301 to step S303.

[0045] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A timing calculation method for an FPGA chip integrating a large IP core, characterized in that: The method is applied to an FPGA chip, the FPGA chip includes at least one IP module and at least one other logic resource module, the modules are interconnected by a connection resource XBAR inside the FPGA chip, and the method includes: For any one of the at least one IP module, obtain port information of a plurality of ports in the IP module for connecting with other logic resource modules; wherein any one of the plurality of ports is connected with other logic resource modules through a wiring module XBAR; Determine a winding coordinate of each of the plurality of ports according to the port information, the winding coordinate being an XBAR coordinate connected to the port; For each of the multiple ports, delay information of the connection between the port and other logic resource modules is calculated according to the winding coordinates of the port.

2. The method according to claim 1, characterized in that The ports include input ports and output ports of the IP module.

3. The method according to claim 1, characterized in that The winding coordinates of the port include an X value and a Y value, and the X value of the winding coordinates corresponding to each port in the multiple ports of the same IP module is the same.

4. The method according to claim 1, characterized in that After determining the winding coordinates of each of the plurality of ports according to the port information, the method further comprises: saving the winding coordinates of each of the plurality of ports as a data file; When calculating the timing of the FPGA chip, the data file is stored in the memory.

5. The method according to claim 4, characterized in that The step of storing the data file in the memory comprises: For multiple ports of the same IP module, the port name of each port in the multiple ports and the Y value of the winding coordinate of each port are saved in the memory.

6. The method according to claim 5, characterized in that When the source or target in any connection relationship on the FPGA chip is a port of an IP module, the Y value of the winding coordinate of the port corresponding to the source or target is searched in the memory, and the delay information of the connection is determined according to the Y value; Any one of the connection relationships includes a source and a target, and the direction of the connection relationship is from the source to the target.

Images