Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes dummy memory cells connected to dummy word lines and normal memory cells connected to normal word lines. The peripheral circuit performs an erase operation on the memory block. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on a first dummy memory cell connected to a first dummy word line among the dummy word lines in response to an erase command for the memory block, and to perform the pre-program operation on a second dummy memory cell connected to a second dummy word line among the dummy word lines after the pre-program operation on the first dummy memory cell. The control logic controls the peripheral circuit to perform the erase operation on the normal memory cells.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0001138, filed on January 5, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic devices, and more specifically to semiconductor memory devices and methods of operating thereof. Background Technology

[0004] Semiconductor memory devices can be formed as two-dimensional structures in which strings are arranged parallel to a horizontal semiconductor substrate, or as three-dimensional structures in which strings are arranged perpendicular to a horizontal semiconductor substrate. Three-dimensional memory devices are semiconductor memory devices designed to overcome the integration limitations of two-dimensional semiconductor memory devices, and can include multiple memory cells vertically stacked on a semiconductor substrate. Summary of the Invention

[0005] Some embodiments relate to a semiconductor memory device with improved reliability and a method of operating the semiconductor device.

[0006] According to one embodiment of this disclosure, a semiconductor memory device includes: a memory block including dummy memory cells connected to dummy word lines and normal memory cells connected to normal word lines; peripheral circuitry configured to perform an erase operation on the memory block; and control logic configured to control the operation of the peripheral circuitry. The control logic is configured to control the peripheral circuitry to: perform a pre-programming operation on a first dummy memory cell connected to a first dummy word line in response to an erase command for the memory block; perform a pre-programming operation on a second dummy memory cell connected to a second dummy word line after the pre-programming operation on the first dummy memory cell; and perform an erase operation on the normal memory cell.

[0007] A memory block may include a drain-select transistor connected to a bit line and a source-select transistor connected to a common source line. A first dummy memory cell may be located between a normal memory cell and a drain-select transistor, and a second dummy memory cell may be located between a normal memory cell and a source-select transistor.

[0008] During the pre-programming operation of the first dummy memory cell, the control logic can control the peripheral circuitry to: apply a ground voltage to the common source line, apply a programming pass voltage to the second dummy word line and the normal word line, and apply a first programming pulse to the first dummy word line.

[0009] During the pre-programming operation of the second dummy memory cell, the control logic controls the peripheral circuitry to: apply a ground voltage to the common source line, apply a programming pass voltage to the first dummy word line and the normal word line, and apply a second programming pulse to the second dummy word line.

[0010] The first programming pulse can have the same voltage amplitude as the second programming pulse.

[0011] The first programming pulse can have a higher voltage than the second programming pulse.

[0012] The first programming pulse can have a lower voltage than the second programming pulse.

[0013] During the erase operation of a normal memory cell, the control logic can control the peripheral circuitry to: apply erase disable voltage to the first dummy word line and the second dummy word line, apply erase enable voltage to the normal word line, and apply erase voltage to the common source line.

[0014] During an erase operation on a normal memory cell, the control logic can control the peripheral circuitry to: float the first and second dummy word lines, apply an erase enable voltage to the normal word lines, and apply an erase voltage to the common source line.

[0015] After performing a pre-programming operation on the second dummy memory cell, the control logic can control the peripheral circuitry to perform a pre-programming operation on the third dummy memory cell connected to the third dummy word line.

[0016] A memory block may include a drain-select transistor connected to a bit line and a source-select transistor connected to a common source line. A first dummy memory cell may be located between a normal memory cell and a drain-select transistor, a second dummy memory cell may be located between normal memory cells, and a third memory cell may be located between a normal memory cell and a source-select transistor.

[0017] According to another embodiment of this disclosure, there is a method for operating a semiconductor memory device, the semiconductor memory device including a plurality of memory blocks, each memory block including a first dummy memory cell connected to a first dummy word line, a second dummy memory cell connected to a second dummy word line, and a normal memory cell connected to a normal word line. The method includes: receiving an erase command; pre-programming the first dummy memory cell included in a selected memory block corresponding to the erase command; pre-programming the second dummy memory cell included in the selected memory block; and erasing the normal memory cell included in the selected memory block.

[0018] Preprogramming the first dummy memory cell may include: applying a ground voltage to a common source line connected to the selected memory block; applying a programming pass voltage to a second dummy word line and a normal word line; and applying a first programming pulse to the first dummy word line.

[0019] Preprogramming the second dummy memory cell may include: applying a ground voltage to a common source line connected to the selected memory block; applying a programming pass voltage to the first dummy word line and the normal word line; and applying a second programming pulse to the second dummy word line.

[0020] The first dummy memory cell can be a drain-side dummy memory cell, and the second dummy memory cell can be a source-side dummy memory cell.

[0021] The first dummy memory cell can be a source-side dummy memory cell, and the second dummy memory cell can be a drain-side dummy memory cell.

[0022] Erasing a normal memory cell may include: applying an erase enable voltage to a normal word line and an erase disable voltage to a dummy word line; and applying an erase voltage to a common source line.

[0023] Erasing a normal memory cell may include: applying an erase enable voltage to a normal word line and floating a dummy word line; and applying an erase voltage to a common source line.

[0024] The semiconductor memory device may further include a third dummy memory cell connected to a third dummy word line. The method may further include pre-programming the third dummy memory cell included in the selected memory block after pre-programming the second dummy memory cell and before erasing the normal memory cell.

[0025] The first dummy memory cell can be a drain-side dummy memory cell, the second dummy memory cell can be a dummy memory cell located between normal memory cells, and the third dummy memory cell can be a source-side dummy memory cell. Attached Figure Description

[0026] Exemplary embodiments are described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be achievable by those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between those two elements, or there may be one or more intervening elements. Throughout the accompanying drawings, similar reference numerals refer to similar elements.

[0028] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0029] Figure 2 It is a diagram. Figure 1 A diagram of one embodiment of the memory cell array shown.

[0030] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks shown.

[0031] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of one of the memory blocks shown.

[0032] Figure 5 This is a flowchart illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0033] Figure 6 This is a timing diagram illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0034] Figure 7A It is a diagram. Figure 5 A flowchart of one embodiment of step S130 is shown.

[0035] Figure 7B It is a diagram. Figure 5 A flowchart of one embodiment of step S150 is shown.

[0036] Figure 8 It is a diagram. Figure 5 A flowchart of one embodiment of step S170 is shown.

[0037] Figure 9 This is a timing diagram illustrating an operation method of a semiconductor memory device according to another embodiment of the present disclosure.

[0038] Figure 10 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0039] Figure 11A It is a diagram. Figure 5 A flowchart of another embodiment of step S130 shown.

[0040] Figure 11B It is a diagram. Figure 5 A flowchart of another embodiment of step S150 shown.

[0041] Figure 12 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0042] Figure 13 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0043] Figure 14A It is a diagram. Figure 5 A flowchart of another embodiment of step S130 shown.

[0044] Figure 14B It is a diagram. Figure 5 A flowchart of another embodiment of step S150 shown.

[0045] Figure 15 It is a diagram. Figure 2 A circuit diagram of another embodiment of one of the memory blocks shown.

[0046] Figure 16 This is a flowchart illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0047] Figure 17A It is a diagram. Figure 16 A flowchart of one embodiment of step S230 is shown.

[0048] Figure 17B It is a diagram. Figure 16 A flowchart of one embodiment of step S250 is shown.

[0049] Figure 17C It is a diagram. Figure 16 A flowchart of one embodiment of step S260 is shown.

[0050] Figure 18 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0051] Figure 19 This is a block diagram illustrating a memory system, which includes... Figure 1 The semiconductor memory device shown.

[0052] Figure 20 It is a diagram. Figure 19 A block diagram illustrating an application example of the memory system shown.

[0053] Figure 21This is a block diagram illustrating a computing system, which includes a reference... Figure 20 The memory system described. Detailed Implementation

[0054] The specific structural and functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. The embodiments presented in this disclosure may be implemented in various forms and should not be construed as being limited as set forth herein.

[0055] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0056] refer to Figure 1 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150.

[0057] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to read / write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells and are configured as non-volatile memory cells with a vertical channel structure. Memory cell array 110 may be configured as a memory cell array with a two-dimensional structure. In some embodiments, memory cell array 110 may be configured as a memory cell array with a three-dimensional structure. Each memory cell among the multiple memory cells included in memory cell array 110 may store at least 1 bit of data. In one embodiment, each memory cell among the multiple memory cells included in memory cell array 110 may be a single-level cell (SLC) storing 1 bit of data. In another embodiment, each memory cell among the multiple memory cells included in memory cell array 110 may be a multi-level cell (MLC) storing 2 bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a three-level cell (TLC) storing 3 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a four-level cell (QLC) storing 4 bits of data. In some embodiments, the memory cell array 110 may include a plurality of memory cells, each storing 5 or more bits of data.

[0058] Address decoder 120, read / write circuitry 130, and voltage generator 150 operate as peripheral circuitry for driving memory cell array 110. This peripheral circuitry operates under the control of control logic 140. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 operates under the control of control logic 140. Address decoder 120 receives addresses through input / output buffers (not shown) in semiconductor memory device 100.

[0059] Address decoder 120 decodes the block address in the received address. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during the read voltage application operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block, and applies a pass voltage Vpass generated by voltage generator 150 to other unselected word lines. Moreover, during the program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word line of the selected memory block, and applies a pass voltage Vpass to other unselected word lines.

[0060] Address decoder 120 decodes the column address in the received address. Address decoder 120 transmits the decoded column address to read / write circuit 130.

[0061] Read and programming operations on the semiconductor memory device 100 are performed on a page-by-page basis. Addresses received in response to requests for read and programming operations include block address, row address, and column address. Address decoder 120 selects a memory block and a word line based on the block address and row address. The column address is decoded by address decoder 120 to be provided to read / write circuitry 130.

[0062] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0063] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation and as a "write circuit" during a write operation. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. To sense the threshold voltage of the memory cells during a read operation or a programming verification operation, the multiple page buffers PB1 to PBm latch the sensed data by continuously supplying a sensed current to the bit lines connected to the memory cells while sensing changes in the amount of current flowing according to the programming state of the corresponding memory cell through a sense node. The read / write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0064] During a read operation, the read / write circuit 130 temporarily stores the read data by sensing the data in the memory cell, and then outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0065] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 controls the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110. Control logic 140 controls voltage generator 150 to generate various voltages used in programming operations on memory cell array 110. Furthermore, control logic 140 controls address decoder 120 to transmit the voltages generated by voltage generator 150 via global lines to local lines of the memory block targeted for operation. Simultaneously, control logic 140 controls read / write circuitry 130 to read data from the selected page of the memory block via bit lines BL1 to BLm during a read operation, and then stores the read data in page buffers PB1 to PBm. Furthermore, control logic 140 controls read / write circuitry 130 to program the data stored in page buffers PB1 to PBm into the selected page during a programming operation. Control logic 140 can be implemented in hardware, software, or a combination of hardware and software. For example, control logic 140 can be control logic circuitry operating according to an algorithm, and / or a processor executing control logic code.

[0066] In response to a control signal output from control logic 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors for receiving internal power voltages, and under the control of control logic 140, multiple voltages are generated by selectively activating these multiple pump capacitors.

[0067] Address decoder 120, read / write circuit 130, and voltage generator 150 can be used as peripheral circuitry for performing read, write, and erase operations on memory cell array 110. This peripheral circuitry performs read, write, and erase operations on memory cell array 110 under the control of control logic 140.

[0068] Figure 2 It is a diagram. Figure 1 A diagram of one embodiment of the memory cell array 110 shown.

[0069] refer to Figure 2 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. The structure of each memory block will be referenced. Figure 3 and Figure 4 To describe in more detail.

[0070] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLK1 to BLKz shown (let's call it memory block BLK1).

[0071] refer to Figure 3 The first memory block BLK1 may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the first memory block BLK1, m cell strings are arranged in the row direction (i.e., the +X direction). Although Figure 3 The diagram illustrates two unit strings arranged in the column direction (i.e., the +Y direction), but this is for ease of description and to illustrate that three unit strings can be arranged in the column direction.

[0072] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, at least one source-side dummy memory cell SDC1 and SDC2, a first normal memory cell MC1 to an nth normal memory cell MCn, a pipe transistor PT, at least one drain-side dummy memory cell DDC1 and DDC2, and at least one drain select transistor DST.

[0073] The select transistors SST and DST, the dummy memory cells SDC1, SDC2, DDC1 and DDC2, and the normal memory cells MC1 to MCn can have similar structures to each other. In one embodiment, each of the select transistors SST and DST, the dummy memory cells SDC1, SDC2, DDC1 and DDC2, and the normal memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer.

[0074] The source selection transistor SST of each cell string is connected between the common source line CSL and the source-side dummy memory cells SDC1 and SDC2.

[0075] In one embodiment, source-select transistors of cell strings arranged in the same row are connected to source-select lines extending in the row direction, and source-select transistors of cell strings arranged in different rows are connected to different source-select lines. Figure 3 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors of cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0076] Two source-side dummy memory cells, SDC1 and SDC2, can be configured in each cell string. However, this is merely illustrative, and it will be understood that three or more source-side dummy memory cells can be configured in each cell string. The source-side dummy memory cells SDC1 and SDC2 of each cell string are connected in series between the source select transistor SST and the normal memory cells MC1 to MCp. The gate of the first source-side dummy memory cell SDC1 in each cell string is connected to the first source-side dummy word line SDWL1. The gate of the second source-side dummy memory cell SDC2 in each cell string is connected to the second source-side dummy word line SDWL2.

[0077] The first normal memory cell MC1 to the nth normal memory cell MCn of each cell string are connected between the source-side dummy memory cells SDC1 and SDC2 and the drain-side dummy memory cells DDC1 and DDC2.

[0078] The first normal memory cells MC1 to the nth normal memory cell MCn can be divided into: first normal memory cells MC1 to the pth normal memory cell MCp, and the (p+1)th normal memory cells MCp+1 to the nth normal memory cells MCn. The first normal memory cells MC1 to the pth normal memory cell MCp are arranged sequentially in opposite directions in the +Z direction and are connected in series between the source-side dummy memory cells SDC1 and SDC2 and the channel transistor PT. The (p+1)th normal memory cells MCp+1 to the nth normal memory cell MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain-side dummy memory cells DDC1 and DDC2. The first normal memory cells MC1 to the pth normal memory cell MCp and the (p+1)th normal memory cells MCp+1 to the nth normal memory cell MCn are connected through the channel transistor PT. The gate electrodes of the first normal memory cells MC1 to the nth normal memory cell MCn in each cell string are respectively connected to the first normal word line WL1 to the nth normal word line WLn.

[0079] Data can be stored in the first normal memory unit MC1 to the nth normal memory unit MCn via the first bit line BL1 to the mth bit line BLm. Data stored in the first normal memory unit MC1 to the nth normal memory unit MCn can be read via the first bit line BL1 to the mth bit line BLm.

[0080] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0081] Two drain-side dummy memory cells, DDC1 and DDC2, are provided in each cell string. However, this is merely illustrative, and it will be understood that three or more drain-side dummy memory cells can be provided in each cell string. The drain-side dummy memory cells DDC1 and DDC2 of each cell string are connected in series between the drain select transistor DST and the normal memory cells MCp+1 to MCn. The gate of the first drain-side dummy memory cell DDC1 of each cell string is connected to the first drain-side dummy word line DDWL1. The gate of the second drain-side dummy memory cell DDC2 of each cell string is connected to the second drain-side dummy word line DDWL2.

[0082] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the drain-side dummy memory cells DDC1 and DDC2. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0083] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 3 In the diagram, cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. Cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0084] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0085] Dummy memory cells SDC1, SDC2, DDC1, and DDC2 are configured to stably control the voltage or current of the corresponding cell string. For example, source-side dummy memory cells SDC1 and SDC2 can be configured to reduce the electric field between the source select transistor SST and the normal memory cells MC1 to MCp. Similarly, drain-side dummy memory cells DDC1 and DDC2 can be configured to reduce the electric field between the drain select transistor DST and the normal memory cells MCp+1 to MCn. Increasing the number of dummy memory cells improves the operational reliability of memory block BLK1. Conversely, it increases the size of memory block BLK1. Conversely, decreasing the number of dummy memory cells decreases the size of memory block BLK1. Conversely, it may degrade the operational reliability of memory block BLK1.

[0086] To efficiently control dummy memory cells SDC1, SDC2, DDC1, and DDC2, the desired threshold voltages for each dummy memory cell are required. Before erasing memory block BLK1, pre-programming operations can be performed on all or some of the dummy memory cells SDC1, SDC2, DDC1, and DDC2.

[0087] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLK1', one of the memory blocks BLK1 to BLKz shown.

[0088] refer to Figure 4The first memory block BLK1' may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes, stacked on a substrate (not shown) below the memory block BLK1': at least one source selection transistor SST, at least one source-side dummy memory cells SDC1 and SDC2, first normal memory cells MC1 to nth normal memory cells MCn, at least one drain-side dummy memory cells DDC1 and DDC2, and at least one drain selection transistor DST.

[0089] The source select transistor SST of each cell string is connected between the common source line CSL and the source-side dummy memory cells SDC1 and SDC2. The source select transistors of cell strings arranged in the same row (e.g., CS11' to CS1m') are connected to the same source select line (e.g., SSL1). The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2.

[0090] The source-side dummy memory cells SDC1 and SDC2 of each cell string are connected in series between the source select transistor SST and the normal memory cells MC1 to MCn. Source-side dummy memory cells at the same height are connected to the same source-side dummy word line. The gates of the first source-side dummy memory cell SDC1 and the second source-side dummy memory cell SDC2 are connected to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, respectively.

[0091] The first normal memory cell MC1 to the nth normal memory cell MCn in each cell string are connected in series between the source-side dummy memory cells SDC1 and SDC2 and the drain-side dummy memory cells DDC1 and DDC2. The gates of the first normal memory cells MC1 to the nth normal memory cell MCn are connected to the first normal word line WL1 to the nth normal word line WLn.

[0092] The drain-side dummy memory cells DDC1 and DDC2 of each cell string are connected in series between the drain select transistor DST and the normal memory cells MC1 to MCn. Drain-side dummy memory cells at the same height are connected to the same source-side dummy word line. The first drain-side dummy memory cell DDC1 and the second drain-side dummy memory cell DDC2 are connected to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, respectively.

[0093] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the drain-side dummy memory cells DDC1 and DDC2. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select lines extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0094] therefore, Figure 4 The memory block BLKl' has the same Figure 3 The circuitry of memory block BLK1 is similar to that of other circuits, except that... Figure 4 The pipe transistor PT is excluded from each unit string.

[0095] In the following text, for ease of description, we will refer to... Figure 3 The memory block BLKl shown is used to describe an embodiment of this disclosure.

[0096] Figure 5 This is a flowchart illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0097] refer to Figure 5 The method of operating a semiconductor memory device includes: step S110 of receiving an erase command, step S130 of pre-programming a first dummy memory cell among the dummy memory cells included in the selected memory block, step S150 of pre-programming a second dummy memory cell among the dummy memory cells included in the selected memory block, and step S170 of erasing normal memory cells included in the selected memory block.

[0098] In step S110, the semiconductor memory device 100 may receive an erase command from outside the semiconductor memory device 100. More specifically, the semiconductor memory device 100 may receive the erase command from a controller. The semiconductor memory device 100 may receive the address of the memory block selected as the erase target along with the erase command.

[0099] In step S130, a first dummy memory cell among the dummy memory cells included in the memory block selected as the erasure target can be pre-programmed. That is, in step S130, a pre-programming operation can be performed on some of the dummy memory cells among the plurality of dummy memory cells included in the memory block selected as the erasure target. For this purpose, the semiconductor memory device 100 can apply a programming pulse to a dummy word line connected to the first dummy memory cell within a word line connected to the selected memory block. In one embodiment, a verification operation can be performed on the first dummy memory cell. In another embodiment, a verification operation can be omitted for the first dummy memory cell. In step S130, the programming pulse applied to the dummy word line connected to the first dummy memory cell can have a voltage level that sets a threshold voltage of the first dummy memory cell to a target threshold voltage.

[0100] In step S150, a second dummy memory cell among the dummy memory cells included in the memory block selected as the erasure target can be pre-programmed. The second dummy memory cell can be a different dummy memory cell from the first dummy memory cell. For this purpose, the semiconductor memory device 100 can apply a programming pulse to a dummy word line connected to the second dummy memory cell within a word line connected to the selected memory block. In one embodiment, a verification operation can be performed on the second dummy memory cell. In another embodiment, a verification operation can be omitted for the second dummy memory cell. In step S150, the programming pulse applied to the dummy word line connected to the second dummy memory cell can have a voltage level that sets a threshold voltage of the second dummy memory cell to a target threshold voltage.

[0101] In step S170, normal memory cells included in the selected memory block can be erased. For this purpose, the semiconductor memory device 100 can apply an erase voltage VERS to the common source line CSL. The semiconductor memory device 100 can control the source select transistor SST and drain select transistor DST to be in a floating state. Furthermore, the semiconductor memory device 100 can apply an erase enable voltage (e.g., ground voltage) to the normal word lines connected to the selected memory block. Moreover, the semiconductor memory device 100 can apply an erase disable voltage to the dummy word lines connected to the selected memory block. Subsequently, the potential level of the channel can increase according to the potential level of the common source line CSL, and according to the potential level of the channel, the potential levels of the source select line and drain select line, which are connected to multiple source select transistors and multiple drain select transistors in a floating state, can increase due to coupling phenomena.

[0102] Data stored in normal memory cells is erased by increasing the potential level of the channel. That is, due to FN tunneling, electrons stored in the charge storage layer of normal memory cells are decapitated by the potential level of the channel. This will be described in more detail. Depending on the difference between the increased potential level of the channel and the potential level of the local word line with a ground level, electrons stored in the charge storage layer of the memory cell escape and are then decapitated, or hot holes generated in the channel are introduced into the charge storage layer of the memory cell, causing electrons stored in the charge storage layer to be decapitated.

[0103] After erasing the data of a normal memory cell via an erase operation, the erase voltage VERS applied to the common source line CSL is blocked, and the potential of the common source line CSL is discharged. When an erase voltage VERS with a high voltage level is applied to the common source line CSL during the erase operation, the source selection transistor is in a floating state. Therefore, a gate-introduced drain leakage (GIDL) current is generated due to the voltage difference with the source side, and hot holes are generated and then introduced in the channel direction. As a result, the channel potential can increase.

[0104] Figure 6 This is a timing diagram illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure. Figure 7A It is a diagram. Figure 5 A flowchart of one embodiment of step S130 is shown. Figure 7B It is a diagram. Figure 5 A flowchart of one embodiment of step S150 is shown. Figure 8 It is a diagram. Figure 5 A flowchart of one embodiment of step S170 is shown. Referring hereafter, it will be noted together with the following text. Figure 6 , Figure 7A , Figure 7B and Figure 8 To describe a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0105] refer to Figure 6 The operation of a semiconductor memory device can be divided into a pre-programming step and an erasure step. The pre-programming step can be performed in time periods t1 to t4, and the erasure step can be performed in time periods t5 to t6.

[0106] During time periods t1 to t2, a programming pulse VPGM can be applied to the first dummy word line among the dummy word lines connected to the selected memory block. Specifically, the first dummy word line can be the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2. Accordingly, during time periods t1 to t2, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 connected to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 can be increased. Simultaneously with the application of the programming pulse VPGM to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the programming pulse VPGM is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the ground voltage VSS can be applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t1 to t2, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2, and the normal memory cells MC1 to MCn, may not increase. Figure 5 The step S130 shown can correspond to Figure 6 The operations during the time period t1 to t2 are shown.

[0107] refer to Figure 7A , Figure 5 The step S130 shown may include: step S131 of applying a ground voltage VSS to the common source line CSL, step S133 of applying a programming pass voltage to the source-side dummy word line and normal word line, and step S135 of applying a programming pulse to the drain-side dummy word line.

[0108] refer to Figure 6 During the time periods t1 to t2, a ground voltage VSS is applied to the common source line CSL (S131), a ground voltage VSS is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, and normal word lines WL1 to WLn (S133), and a programming pulse VPGM is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 (S135). The "programming pass voltage" in step S133 is the voltage applied to the word lines, and can be a voltage that does not change the threshold voltage of the memory cell. Figure 6 In the example shown, the programming is illustrated through the ground voltage VSS.

[0109] During time periods t3 to t4, a programming pulse VPGM can be applied to a second dummy word line among the dummy word lines connected to the selected memory block. Specifically, the second dummy word line can be a first source-side dummy word line SDWL1 and a second source-side dummy word line SDWL2. Accordingly, during time periods t3 to t4, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2 connected to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 can be increased. Simultaneously with the application of the programming pulse VPGM to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the programming pulse VPGM is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, the ground voltage VSS can be applied to the first drain-side dummy word line DDWL1, the second drain-side dummy word line DDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t3 to t4, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 and the normal memory cells MC1 to MCn may not increase. Figure 5 The step S150 shown can correspond to Figure 6 The operations during the time period t3 to t4 are shown.

[0110] refer to Figure 7B , Figure 5 The step S150 shown may include: step S151 of applying a ground voltage VSS to the common source line CSL, step S153 of applying a programming pass voltage to the drain-side dummy word line and normal word line, and step S155 of applying a programming pulse to the source-side dummy word line.

[0111] refer to Figure 6 During the time period t3 to t4, the ground voltage VSS is applied to the common source line CSL (S151), the ground voltage VSS is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 as well as the normal word lines WL1 to WLn (S153), and the programming pulse VPGM is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 (S155).

[0112] During periods t5 to t6, the erase disable voltage Vinh can be applied to the dummy word lines DDWL1, DDWL2, SDWL1, and SDWL2, and the ground voltage VSS can be applied to the normal word lines WL1 to WLn. Furthermore, during periods t5 to t6, the erase voltage VERS can be applied to the common source line CSL.

[0113] refer to Figure 8 , Figure 5Step S170 may include: step S171 of applying an erase enable voltage to a normal word line and an erase disable voltage to a dummy word line, and step S173 of applying an erase voltage to a common source line. The erase enable voltage is a voltage applied during the erase operation to a word line connected to a memory cell selected as the erase target, and may be ground voltage VSS. The erase disable voltage is a voltage applied during the erase operation to a word line connected to a memory cell not corresponding to the erase target, and may be a voltage higher than the erase enable voltage. Figure 6 The diagram illustrates that the erase inhibit voltage Vinh is a voltage higher than the ground voltage VSS. In some embodiments, the erase inhibit voltage is applied to the dummy word line, but the dummy word line can be floating. Although the erase voltage VERS is applied to the common source line CSL, the voltage of the floating dummy word line is increased, and therefore, the dummy memory cells may not be erased.

[0114] According to the reference Figures 5 to 8 The embodiments of this disclosure described herein allow pre-programming operations to be performed on dummy memory cells prior to an erase operation on a selected memory block. Only a programming pulse is applied to the dummy memory cell, without any erase verification operation, enabling the pre-programming operation to be performed. Accordingly, the time required to perform the pre-programming operation can be reduced.

[0115] Furthermore, according to embodiments of this disclosure, the time periods t1 to t2 during which the drain-side dummy memory cells are programmed and the time periods t3 to t4 during which the source-side dummy memory cells are programmed can be separated from each other. The drain-side dummy memory cells and the source-side dummy memory cells are pre-programmed separately in different time periods, thereby improving the stability of the pre-programming operation.

[0116] exist Figure 6 The illustration shows an embodiment in which a programming pulse VPGM is first applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, and then applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2. However, this disclosure is not limited thereto. That is, in some embodiments, the programming pulse VPGS may be first applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, and then applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2.

[0117] Figure 9 This is a timing diagram illustrating an operation method of a semiconductor memory device according to another embodiment of the present disclosure.

[0118] refer to Figure 9The operation of a semiconductor memory device can be divided into a pre-programming step and an erasure step. The pre-programming step can be performed during time periods t7 to t10, and the erasure step can be performed during time periods t11 to t12.

[0119] During time intervals t7 and t8, a programming pulse VPGM can be applied to the first dummy word line among the dummy word lines connected to the selected memory block. Specifically, the first dummy word line can be the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2. Accordingly, during time intervals t7 and t8, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 connected to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 can be increased. Simultaneously with the application of the programming pulse VPGM to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the programming pulse VPGM is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the programming pass voltage Vpass can be applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. (Reference) Figure 6 While the programming pulse VPGM is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the ground voltage VSS is applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. However, in Figure 9 In the illustrated embodiment, a programming pass voltage Vpass higher than the ground voltage VSS is applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. The programming pass voltage Vpass can be a voltage lower than the programming pulse VPGM.

[0120] Accordingly, during the period from t7 to t8, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2, as well as the normal memory cells MC1 to MCn, do not need to be increased. Figure 5 The step S130 shown can correspond to Figure 9 The operations during the time period t7 to t8 are shown.

[0121] Figure 7A The "programming pass voltage" in step S133 shown is the voltage applied to the word line, and can be a voltage that does not change the threshold voltage of the memory cell. Figure 9 In the example shown, the programming is illustrated by a voltage Vpass that is higher than the ground voltage VSS.

[0122] Similarly, during time periods t9 to t10, the programming pass voltage Vpass can be applied to the first drain-side dummy word line DDWL1, the second drain-side dummy word line DDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t9 to t10, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2, and the normal memory cells MC1 to MCn, may not increase. Figure 5 The step S150 shown can correspond to Figure 9 The operations shown are for the period t9 to t10.

[0123] During time periods t11 to t12, the operation of the semiconductor memory device 100 can be synchronized with... Figure 6 The operations for time periods t5 to t6 are the same. Accordingly, repeated descriptions will be omitted.

[0124] Figure 10 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure. Figure 11A It is a diagram. Figure 5 A flowchart of another embodiment of step S130 shown. Figure 11B It is a diagram. Figure 5 A flowchart of another embodiment of step S150 is shown. Referring hereafter, it will be noted together with the above. Figure 10 , Figure 11A and Figure 11B To describe a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0125] refer to Figure 10 The operation of a semiconductor memory device can be divided into a pre-programming step and an erasure step. The pre-programming step can be performed in time periods t13 to t16, and the erasure step can be performed in time periods t17 to t18.

[0126] During time periods t13 and t14, a first programming pulse VPGM1 can be applied to a first dummy word line among the dummy word lines connected to the selected memory block. Specifically, the first dummy word line can be a first drain-side dummy word line DDWL1 and a second drain-side dummy word line DDWL2. Accordingly, during time periods t13 and t14, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 connected to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 can be increased. Simultaneously with the application of the first programming pulse VPGM1 to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the first programming pulse VPGM1 is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the programming pass voltage Vpass can be applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t13 to t14, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2 and the normal memory cells MC1 to MCn may not increase. Figure 5 The step S130 shown can correspond to Figure 10 The operations during the time period t13 to t14 are shown.

[0127] refer to Figure 11A , Figure 5 The step S130 shown may include: step S132 of applying a ground voltage VSS to the common source line CSL, step S134 of applying a programming pass voltage to the source-side dummy word line and normal word line, and step S136 of applying a first programming pulse to the drain-side dummy word line.

[0128] refer to Figure 10 During the time period t13 to t14, the ground voltage VSS is applied to the common source line CSL (S132), the programming pass voltage Vpass is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 as well as the normal word lines WL1 to WLn (S134), and the first programming pulse VPGM1 is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 (S136).

[0129] During time periods t15 and t16, a second programming pulse VPGM2 can be applied to a second dummy word line among the dummy word lines connected to the selected memory block. Specifically, the second dummy word line can be a first source-side dummy word line SDWL1 and a second source-side dummy word line SDWL2. Accordingly, during time periods t15 and t16, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2 connected to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 can be increased. Simultaneously with the application of the second programming pulse VPGM2 to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, as the second programming pulse VPGM2 is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, the programming pass voltage Vpass can be applied to the first drain-side dummy word line DDWL1, the second drain-side dummy word line DDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t15 to t16, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 and the normal memory cells MC1 to MCn may not increase. Figure 5 The step S150 shown can correspond to Figure 10 The operations during the time period t15 to t16 are shown.

[0130] refer to Figure 11B , Figure 5 The step S150 shown may include: step S152 applying a ground voltage VSS to the common source line CSL, step S154 applying a programming pass voltage to the drain-side dummy word line and normal word line, and step S156 applying a second programming pulse different from the first programming pulse to the source-side dummy word line.

[0131] refer to Figure 10 During the time period t15 to t16, the ground voltage VSS is applied to the common source line CSL (S152), the ground voltage VSS is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 as well as the normal word lines WL1 to WLn (S154), and the second programming pulse VPGM2 is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 (S156).

[0132] The programming operation characteristics of drain-side dummy memory cells DDC1 and DDC2 and source-side dummy memory cells SDC1 and SDC2 can be different from each other. Therefore, when the same programming pulse is used in the pre-programming operations of drain-side dummy memory cells DDC1 and DDC2 and the pre-programming operations of source-side dummy memory cells SDC1 and SDC2, the threshold voltage distribution characteristics of dummy memory cells DDC1, DDC2, SDC1, and SDC2 may degrade. Therefore, according to the semiconductor memory device and its operation method according to embodiments of the present disclosure, different programming pulses can be used in the pre-programming operations of drain-side dummy memory cells DDC1 and DDC2 and the pre-programming operations of source-side dummy memory cells SDC1 and SDC2.

[0133] During time periods t17 to t18, the operation of semiconductor memory device 100 can be synchronized with... Figure 6 The operation or during the time period t5 to t6 shown Figure 9 The operations for t11 to t12 shown are the same. Accordingly, repeated descriptions will be omitted.

[0134] According to the reference Figure 10 , Figure 11A and Figure 11B The embodiments of this disclosure described herein allow pre-programming operations to be performed on dummy memory cells prior to an erase operation on a selected memory block. Only a programming pulse is applied to the dummy memory cell, without any erase verification operation, enabling the pre-programming operation to be performed. Accordingly, the time required to perform the pre-programming operation can be reduced.

[0135] Furthermore, according to embodiments of this disclosure, the time periods t13 to t14 during which the drain-side dummy memory cells are programmed and t15 to t16 during which the source-side dummy memory cells are programmed can be separated from each other. The drain-side dummy memory cells and the source-side dummy memory cells are pre-programmed separately in different time periods, thereby improving the stability of pre-programming.

[0136] Furthermore, according to embodiments of this disclosure, a first programming pulse VPGM1 is used to pre-program the drain-side dummy memory cells DDC1 and DDC2, and a second programming pulse VPGM2, different from the first programming pulse VPGM1, is used to pre-program the source-side dummy memory cells SDC1 and SDC2.

[0137] exist Figure 10The illustration shows an embodiment in which a first programming pulse VPGM1 applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 is higher than a second programming pulse VPGM2 applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2. However, this disclosure is not limited thereto. That is, in some embodiments, the first programming pulse VPGM1 applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 may be lower than a second programming pulse VPGM2 applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2.

[0138] Figure 12 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0139] refer to Figure 12 The operation method of a semiconductor memory device according to another embodiment of the present disclosure can be divided into a pre-programming step and an erasing step. The pre-programming step can be performed in time periods t19 to t24, and the erasing step can be performed in time periods t25 to t26.

[0140] During time intervals t19 and t20, a first programming pulse VPGM1 can be applied to the first drain-side dummy word line DDL1, which is connected to the selected memory block. Correspondingly, during time intervals t19 and t20, the threshold voltage of the first drain-side dummy memory cell DDC1 connected to the first drain-side dummy word line DDWL1 can be increased. Simultaneously with the application of the first programming pulse VPGM1 to the first drain-side dummy word line DDWL1, a ground voltage VSS can be applied to the common source line CSL. Simultaneously with the application of the first programming pulse VPGM1 to the first drain-side dummy word line DDWL1, a programming pass voltage Vpass can be applied to the second drain-side dummy word line DDWL2, the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during the period from t19 to t20, the threshold voltages of the second drain-side dummy memory cell DDC2, the source-side dummy memory cells SDC1 and SDC2, and the normal memory cells MC1 to MCn do not need to be increased.

[0141] During time periods t20 to t21, a first programming pulse VPGM1 can be applied to the second drain-side dummy word line DDWL2, which is connected to the selected memory block. Correspondingly, during time periods t20 to t21, the threshold voltage of the second drain-side dummy memory cell DDC2 connected to the second drain-side dummy word line DDWL2 can be increased. Simultaneously with the application of the first programming pulse VPGM1 to the second drain-side dummy word line DDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously with the application of the first programming pulse VPGM1 to the second drain-side dummy word line DDWL2, a programming pass voltage Vpass can be applied to the first drain-side dummy word line DDWL1, the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during the period from t20 to t21, the threshold voltages of the first drain-side dummy memory cell DDC1, the source-side dummy memory cells SDC1 and SDC2, and the normal memory cells MC1 to MCn do not need to be increased.

[0142] During time periods t22 and t23, a second programming pulse VPGM2 can be applied to the first source-side dummy word line SDWL1, which is connected to the selected memory block. Correspondingly, during time periods t22 and t23, the threshold voltage of the first source-side dummy memory cell SDC1 connected to the first source-side dummy word line SDWL1 can be increased. Simultaneously with the application of the second programming pulse VPGM2 to the first source-side dummy word line SDWL1, a ground voltage VSS can be applied to the common source line CSL. Simultaneously with the application of the second programming pulse VPGM2 to the first source-side dummy word line SDWL1, a programming pass voltage Vpass can be applied to the first drain-side word line DDWL1, the second drain-side word line DDWL2, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during the period from t22 to t23, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2, the second source-side dummy memory cell SDC2, and the normal memory cells MC1 to MCn do not need to be increased.

[0143] During time periods t23 and t24, a second programming pulse VPGM2 can be applied to the second source-side dummy word line SDWL2, which is connected to the selected memory block. Correspondingly, during time periods t23 and t24, the threshold voltage of the second source-side dummy memory cell SDC2 connected to the second source-side dummy word line SDWL2 can be increased. Simultaneously with the application of the second programming pulse VPGM2 to the second source-side dummy word line SDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously with the application of the second programming pulse VPGM2 to the second source-side dummy word line SDWL2, a programming pass voltage Vpass can be applied to the first drain-side dummy word line DDWL1, the second drain-side dummy word line DDWL2, the first source-side dummy word line SDWL1, and the normal word lines WL1 to WLn. Accordingly, during the period from t23 to t24, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2, the first source-side dummy memory cell SDC1, and the normal memory cells MC1 to MCn do not need to be increased.

[0144] The operation of the semiconductor memory device 100 during time period t25 to t26 can be related to Figure 6 The operations for time periods t5 to t6 are the same. Accordingly, repeated descriptions will be omitted.

[0145] according to Figure 6 , Figure 9 and Figure 10 The illustrated embodiment shows an example in which a first drain-side dummy memory cell DDC1 and a second drain-side dummy memory cell DDC2 are simultaneously pre-programmed, and a first source-side dummy memory cell SDC1 and a second source-side dummy memory cell SDC2 are simultaneously pre-programmed. However, this is merely illustrative, and the present disclosure is not limited thereto. Figure 12 As shown, the first drain-side dummy memory cell DDC1 and the second drain-side dummy memory cell DDC2 can be pre-programmed during different time periods, and the first source-side dummy memory cell SDC1 and the second source-side dummy memory cell SDC2 can be pre-programmed during different time periods.

[0146] Figure 13 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure. Figure 14A It is a diagram. Figure 5 A flowchart of another embodiment of step S130 shown. Figure 14B It is a diagram. Figure 5 A flowchart of another embodiment of step S150 is shown. Referring hereafter, it will be noted together with the following text. Figure 13 , Figure 14A and Figure 14BTo describe a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0147] refer to Figure 13 The operation of a semiconductor memory device can be divided into a pre-programming step and an erasure step. The pre-programming step can be performed during time periods t27 to t30, and the erasure step can be performed during time periods t31 to t32.

[0148] During time periods t27 and t28, a programming pulse can be applied to a first dummy word line among the dummy word lines connected to the selected memory block. Specifically, the first dummy word line can be a first drain-side dummy word line DDWL1 and a first source-side dummy word line SDWL1. Accordingly, during time periods t27 and t28, the threshold voltages of the first drain-side dummy memory cell DDC1 and the first source-side dummy memory cell SDC1 connected to the first drain-side dummy word line DDWL1 and the first source-side dummy word line SDWL1 can be increased. In one embodiment, a first programming pulse VPGM1 can be applied to the first drain-side dummy word line DDWL1, and a second programming pulse VPGM2 can be applied to the first source-side dummy word line SDWL1. Simultaneously with the programming pulses applied to the first drain-side dummy word line DDWL1 and the first source-side dummy word line SDWL1, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the programming pulse is applied to the first drain-side dummy word line DDWL1 and the first source-side dummy word line SDWL1, the programming pass voltage Vpass can be applied to the second drain-side dummy word line DDWL2, the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during the period t27 to t28, the threshold voltages of the second drain-side dummy memory cell DDC2, the second source-side dummy memory cell SDC2, and the normal memory cells MC1 to MCn may not increase. Figure 5 The step S130 shown can correspond to Figure 13 The operations shown are for the period t27 to t28.

[0149] refer to Figure 14A , Figure 5 The step S130 shown may include: step S137 of applying a ground voltage VSS to the common source line CSL, step S138 of applying a programming pass voltage to the second source-side dummy word line, the second drain-side dummy word line and the normal word line, and step S139 of applying a programming pulse to the first source-side dummy word line and the first drain-side dummy word line.

[0150] refer to Figure 13During the time period t27 to t28, the ground voltage VSS is applied to the common source line CSL (S137), the programming pass voltage Vpass is applied to the second source-side dummy word line SDWL2, the second drain-side dummy word line DDWL2, and the normal word lines WL1 to WLn (S138), and programming pulses are applied to the first source-side dummy word line SDWL1 and the first drain-side dummy word line DDWL1 (S139). In step S139, the first programming pulse VPGM1 can be applied to the first drain-side dummy word line DDWL1, and the second programming pulse VPGM2 can be applied to the first source-side dummy word line SDWL1.

[0151] During time periods t29 to t30, a programming pulse can be applied to a second dummy word line among the dummy word lines connected to the selected memory block. Specifically, the second dummy word line can be the second drain-side dummy word line DDWL2 and the second source-side dummy word line SDWL2. Accordingly, during time periods t29 to t30, the threshold voltages of the second drain-side dummy memory cell DDC2 and the second source-side dummy memory cell SDC2 connected to the second drain-side dummy word line DDWL2 and the second source-side dummy word line SDWL2 can be increased. In one embodiment, a first programming pulse VPGM1 can be applied to the second drain-side dummy word line DDWL2, and a second programming pulse VPGM2 can be applied to the second source-side dummy word line SDWL2. Simultaneously with the programming pulses being applied to the second drain-side dummy word line DDWL2 and the second source-side dummy word line SDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the programming pulse is applied to the second drain-side dummy word line DDWL2 and the second source-side dummy word line SDWL2, the programming pass voltage Vpass can be applied to the first drain-side dummy word line DDWL1, the first source-side dummy word line SDWL1, and the normal word lines WL1 to WLn. Accordingly, during the period t29 to t30, the threshold voltages of the first drain-side dummy memory cell DDC1, the first source-side dummy memory cell SDC1, and the normal memory cells MC1 to MCn may not increase. Figure 5 The step S150 shown can correspond to Figure 13 The operations during the time period t29 to t30 are shown.

[0152] refer to Figure 14B , Figure 5 The step S150 shown may include: step S157 of applying a ground voltage VSS to the common source line CSL, step S158 of applying a programming pass voltage to the first source-side dummy word line, the first drain-side dummy word line and the normal word line, and step S159 of applying a programming pulse to the second source-side dummy word line and the second drain-side dummy word line.

[0153] refer to Figure 13 During the time period t29 to t30, the ground voltage VSS is applied to the common source line CSL (S157), the programming pass voltage Vpass is applied to the first source-side dummy word line SDWL1, the first drain-side dummy word line DDWL1, and the normal word lines WL1 to WLn (S158), and programming pulses are applied to the second source-side dummy word line SDWL2 and the second drain-side dummy word line DDWL2 (S159). In step S159, the first programming pulse VPGM1 can be applied to the second drain-side dummy word line DDWL2, and the second programming pulse VPGM2 can be applied to the second source-side dummy word line SDWL2.

[0154] The operation of the semiconductor memory device 100 during time period t31 to t32 can be related to Figure 6 The operation or during the time period t5 to t6 shown Figure 9 The operations for t11 to t12 shown are the same. Accordingly, repeated descriptions will be omitted.

[0155] Figure 15 It is a diagram. Figure 2 The circuit diagram of another embodiment of memory block BLK1, one of the memory blocks BLK1 to BLKz shown.

[0156] refer to Figure 15 The first memory block BLK1” includes multiple cell strings CS11” to CS1m” and CS21” to CS2m”. Each of the multiple cell strings CS11” to CS1m” and CS21” to CS2m” extends along the +Z direction. Each of the multiple cell strings CS11” to CS1m” and CS21” to CS2m” includes, stacked on a substrate (not shown) below the memory block BLK1”: at least one source selection transistor SST, at least one source-side dummy memory cell SDC1 and SDC2, first normal memory cell MC1 to nth normal memory cell MCn, at least one drain-side dummy memory cell DDC1 and DDC2, at least one intermediate dummy memory cell CDC1 and CDC2, and at least one drain selection transistor DST.

[0157] Intermediate dummy memory cells CDC1 and CDC2 in each cell string are connected in series between the i-th normal memory cell MCI and the j-th normal memory cell MCj. Intermediate dummy memory cells at the same height are connected to the same intermediate dummy word line. The gates of the first intermediate dummy memory cell CDC1 and the second intermediate dummy memory cell CDC2 can be connected to the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, respectively.

[0158] In one embodiment, the number of first normal memory cells MC1 to i-th normal memory cells MCI located between the second source-side dummy memory cell SDC2 and the first intermediate dummy memory cell CDC1 and the number of j-th normal memory cells MCj to n-th normal memory cells MCn located between the second intermediate dummy memory cell CDC2 and the first drain-side dummy memory cell DDC1 can be the same.

[0159] In another embodiment, the number of first normal memory cells MC1 to i-th normal memory cells MCI located between the second source-side dummy memory cell SDC2 and the first intermediate dummy memory cell CDC1 and the number of j-th normal memory cells MCj to n-th normal memory cells MCn located between the second intermediate dummy memory cell CDC2 and the first drain-side dummy memory cell DDC1 can be different from each other.

[0160] Figure 15 The memory block BLKl shown is Figure 4 The memory block BLK1' shown is identical, except that memory block BLK1" also includes intermediate dummy memory units CDC1 and CDC2 located between the i-th normal memory unit MCi and the j-th normal memory unit MCj. Therefore, repeated descriptions of other components besides the intermediate dummy memory units CDC1 and CDC2 will be omitted.

[0161] Figure 16 This is a flowchart illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure.

[0162] refer to Figure 16 An operation method of a semiconductor memory device according to another embodiment of the present disclosure includes: a step S210 of receiving an erase command; a step S230 of pre-programming a first dummy memory cell among the dummy memory cells included in a selected memory block; a step S250 of pre-programming a second dummy memory cell among the dummy memory cells included in the selected memory block; a step S260 of pre-programming a third dummy memory cell among the dummy memory cells included in the selected memory block; and a step S270 of erasing normal memory cells included in the selected memory block.

[0163] In step S210, the semiconductor memory device 100 may receive an erase command from an external source. More specifically, the semiconductor memory device 100 may receive an erase command from a controller. The semiconductor memory device 100 may receive the address of the memory block selected as the erase target along with the erase command.

[0164] In step S230, a first dummy memory cell among the dummy memory cells included in the memory block selected as the erasure target can be pre-programmed. That is, in step S230, a pre-programming operation can be performed on some of the dummy memory cells among the plurality of dummy memory cells included in the memory block selected as the erasure target. For this purpose, the semiconductor memory device 100 can apply a programming pulse to a dummy word line connected to the first dummy memory cell within a word line connected to the selected memory block. In one embodiment, a verification operation can be performed on the first dummy memory cell. In another embodiment, a verification operation can be omitted for the first dummy memory cell. In step S230, the programming pulse applied to the dummy word line connected to the first dummy memory cell can have a voltage level that sets a threshold voltage of the first dummy memory cell to a target threshold voltage.

[0165] In step S250, a second dummy memory cell among the dummy memory cells included in the memory block selected as the erasure target can be pre-programmed. The second dummy memory cell may be a different dummy memory cell from the first dummy memory cell. For this purpose, the semiconductor memory device 100 can apply a programming pulse to a dummy word line connected to the second dummy memory cell within a word line connected to the selected memory block. In one embodiment, a verification operation can be performed on the second dummy memory cell. In another embodiment, a verification operation may not be performed on the second dummy memory cell. In step S250, the programming pulse applied to the dummy word line connected to the second dummy memory cell can have a voltage level that sets a threshold voltage of the second dummy memory cell to a target threshold voltage.

[0166] In step S260, a third dummy memory cell among the dummy memory cells included in the memory block selected as the erasure target can be pre-programmed. The third dummy memory cell can be a different dummy memory cell from the first and second dummy memory cells. For this purpose, the semiconductor memory device 100 can apply a programming pulse to a dummy word line connected to the third dummy memory cell within a word line connected to the selected memory block. In one embodiment, a verification operation can be performed on the third dummy memory cell. In another embodiment, a verification operation can be omitted. In step S260, the programming pulse applied to the dummy word line connected to the third dummy memory cell can have a voltage level that sets the threshold voltage of the third dummy memory cell to a target threshold voltage.

[0167] In step S270, normal memory cells included in the selected memory block can be erased. For this purpose, the semiconductor memory device 100 can apply an erase voltage VERS to the common source line CSL. The source select transistor SST and drain select transistor DST can be controlled to be in a floating state. Furthermore, the semiconductor memory device 100 can apply an erase enable voltage (e.g., ground voltage) to the normal word lines connected to the selected memory block. Also, the semiconductor memory device 100 can apply an erase disable voltage to the dummy word lines connected to the selected memory block. Subsequently, the potential level of the channel can be increased according to the potential level of the common source line CSL, and according to the potential level of the channel, the potential levels of the source select line and drain select line, which are connected to multiple source select transistors and multiple drain select transistors in a floating state, can be increased due to coupling.

[0168] Data stored in normal memory cells is erased by increasing the potential level of the channel. That is, due to FN tunneling, electrons stored in the charge storage layer of normal memory cells are decapitated by the potential level of the channel. This will be described in more detail. Depending on the difference between the increased potential level of the channel and the potential level of the local word line with a ground level, electrons stored in the charge storage layer of the memory cell escape and are then decapitated, or hot holes generated in the channel are introduced into the charge storage layer of the memory cell, causing electrons stored in the charge storage layer to be decapitated.

[0169] After erasing the data of a normal memory cell via an erase operation, the erase voltage VERS applied to the common source line CSL is blocked, and the potential of the common source line CSL is discharged. When an erase voltage VERS with a high voltage level is applied to the common source line CSL during the erase operation, the source selection transistor is in a floating state. Therefore, a gate-introduced drain leakage (GIDL) current is generated due to the voltage difference with the source side, and hot holes are generated and then introduced in the channel direction. As a result, the channel potential can increase.

[0170] Figure 17A It is a diagram. Figure 16 A flowchart of one embodiment of step S230 is shown. Figure 17B It is a diagram. Figure 16 A flowchart of one embodiment of step S250 is shown. Figure 17C It is a diagram. Figure 16 A flowchart of one embodiment of step S260 is shown. Meanwhile, Figure 18 This is a timing diagram illustrating an operation method of a semiconductor memory device according to yet another embodiment of the present disclosure. It will be referred to together with the following text. Figure 17A , Figure 17B and Figure 17C To describe a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0171] refer to Figure 18 The operation of a semiconductor memory device can be divided into a pre-programming step and an erasure step. The pre-programming step can be performed in time periods t33 to t38, and the erasure step can be performed in time periods t39 to t40.

[0172] During time periods t33 and t34, a first programming pulse VPGM1 can be applied to a first dummy word line among the dummy word lines connected to the selected memory block. Specifically, the first dummy word line can be a first drain-side dummy word line DDWL1 and a second drain-side dummy word line DDWL2. Accordingly, during time periods t33 and t34, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2 connected to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 can be increased. Simultaneously with the application of the first programming pulse VPGM1 to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, a ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the first programming pulse VPGM1 is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the ground voltage VSS can be applied to the first source-side dummy word line SDWL1, the second source-side dummy word line SDWL2, the intermediate dummy word lines CDWL1 and CDWL2, and the normal word lines WL1 to WLn. Accordingly, during time periods t33 to t34, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2, the intermediate dummy memory cells CDC1 and CDC2, and the normal memory cells MC1 to MCn may not increase. Figure 16 The step S230 shown can correspond to Figure 18 The operations during the time period t33 to t34 are shown.

[0173] refer to Figure 17A , Figure 16 The step S230 shown may include: step S231 of applying a ground voltage VSS to the common source line CSL, step S233 of applying a programming pass voltage to the source-side dummy word line, intermediate dummy word line and normal word line, and step S235 of applying a programming pulse to the drain-side dummy word line.

[0174] refer to Figure 18During the time periods t33 to t34, a ground voltage VSS is applied to the common source line (S231). The ground voltage VSS is also applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, and the normal word lines WL1 to WLn (S233). Furthermore, a first programming pulse VPGM1 is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2 (S235). The "programming pass voltage" in step S233 is the voltage applied to the word lines and can be a voltage that does not change the threshold voltage of the memory cell. Figure 18 In the example shown, the programming is illustrated through the ground voltage VSS.

[0175] During time intervals t35 and t36, a second programming pulse VPGM2 may be applied to a second dummy word line connected to the selected memory block. In one embodiment, the second programming pulse VPGM2 may have the same value as the first programming pulse VPGM1. In another embodiment, the second programming pulse VPGM2 may have a different value than the first programming pulse VPGM1.

[0176] The second dummy word line can be the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2. Correspondingly, during time period t35 to t36, the threshold voltages of the intermediate dummy memory cells CDC1 and CDC2 connected to the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2 can be increased. Simultaneously with the second programming pulse VPGM2 applied to the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, the ground voltage VSS can be applied to the common source line. Simultaneously with the second programming pulse VPGM2 applied to the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, the ground voltage VSS can be applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn. Accordingly, during the period from t35 to t36, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2, the source-side dummy memory cells SDC1 and SDC2, and the normal memory cells MC1 to MCn do not need to be increased. Figure 16 The step S250 shown can correspond to Figure 18 The operations during the time period t35 to t36 are shown.

[0177] refer to Figure 17B , Figure 16The step S250 shown may include: step S251 of applying a ground voltage VSS to the common source line CSL, step S253 of applying a programming pass voltage to the drain-side dummy word line, the source-side dummy word line and the normal word line, and step S255 of applying a programming pulse to the intermediate dummy word line.

[0178] refer to Figure 18 During the time period t35 to t36, the ground voltage VSS is applied to the common source line (S251), the ground voltage VSS is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, and the normal word lines WL1 to WLn (S253), and the second programming pulse VPGM2 is applied to the intermediate dummy word lines CDWL1 and CDWL2 (S255).

[0179] During time intervals t37 and t38, a third programming pulse VPGM3 may be applied to a third dummy word line connected to the selected memory block. In one embodiment, the third programming pulse VPGM3 may have the same value as at least one of the first programming pulse VPGM1 and the second programming pulse VPGM2. In another embodiment, the third programming pulse VPGM3 may have a value different from at least one of the first programming pulse VPGM1 and the second programming pulse VPGM2.

[0180] Specifically, the third dummy word line can be the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2. Correspondingly, during time period t37 to t38, the threshold voltages of the source-side dummy memory cells SDC1 and SDC2 connected to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 can be increased. Simultaneously with the application of the third programming pulse VPGM3 to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, the ground voltage VSS can be applied to the common source line CSL. Simultaneously, while the third programming pulse VPGM3 is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2, the ground voltage VSS can be applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, and the normal word lines WL1 to WLn. Accordingly, during time period t37 to t38, the threshold voltages of the drain-side dummy memory cells DDC1 and DDC2, the intermediate dummy memory cells CDC1 and CDC2, and the normal memory cells MC1 to MCn may not increase. Figure 16 The step S260 shown can correspond to Figure 18The operations during the time period t37 to t38 are shown.

[0181] refer to Figure 17C , Figure 16 The step S260 shown may include: step S261 of applying a ground voltage VSS to the common source line CSL, step S263 of applying a programming pass voltage to the drain-side dummy word line, intermediate dummy word line and normal word line, and step S265 of applying a programming pulse to the source-side dummy word line.

[0182] refer to Figure 18 During the time period t37 to t38, the ground voltage VSS is applied to the common source line CSL (S261), the ground voltage VSS is applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, the first intermediate dummy word line CDWL1 and the second intermediate dummy word line CDWL2, and the normal word lines WL1 to WLn (S263), and the third programming pulse VPGM3 is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2 (S265).

[0183] At the same time, Figure 18 During the time periods t39 to t40, the erase disable voltage Vinh can be applied to the dummy word lines DDWL1, DDWL2, CDWL1, CDWL2, SDWL1, and SDWL2, and the ground voltage VSS can be applied to the normal word lines WL1 to WLn. Furthermore, during the time periods t39 to t40, the erase voltage VERS can be applied to the common source line CSL.

[0184] According to the reference Figures 15 to 18 The embodiments of this disclosure described herein allow pre-programming operations to be performed on three sets of dummy memory cells prior to an erase operation on the selected memory block. Only a programming pulse is applied to the dummy memory cells, without any erase verification operation, enabling the pre-programming operation to be performed. Accordingly, the time required to perform the pre-programming operation can be reduced.

[0185] Furthermore, according to embodiments of this disclosure, the time periods t33 to t34 during which the drain-side dummy memory cells are programmed, t35 to t36 during which the intermediate dummy memory cells are programmed, and t37 to t38 during which the source-side dummy memory cells are programmed can be separated from each other. The drain-side dummy memory cells, intermediate dummy memory cells, and source-side dummy memory cells are pre-programmed individually in different time periods, thereby improving the stability of the pre-programming operation.

[0186] exist Figure 18The illustration shows an embodiment in which a first programming pulse VPGM1 is first applied to the first drain-side dummy word line DDWL1 and the second drain-side dummy word line DDWL2, then a second programming pulse VPGM2 is applied to the intermediate dummy word lines CDWL1 and CDWL2, and finally, a third programming pulse VPGM3 is applied to the first source-side dummy word line SDWL1 and the second source-side dummy word line SDWL2. However, this disclosure is not limited thereto. That is, the order in which the drain-side dummy memory cells DDC1 and DDC2, the intermediate dummy memory cells CDC1 and CDC2, and the source-side dummy memory cells SDC1 and SDC2 are programmed can be varied if necessary.

[0187] Figure 19 This is a block diagram of a memory system 1000, which includes... Figure 1 The semiconductor memory device 100 shown.

[0188] refer to Figure 19 The memory system 1000 includes a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 The semiconductor memory device described. Repeated descriptions will be omitted in the following text.

[0189] Memory controller 1100 is coupled to a host computer and semiconductor memory device 100. Memory controller 1100 accesses semiconductor memory device 100 in response to requests from the host computer. For example, memory controller 1100 controls read, write, erase, and background operations on semiconductor memory device 100. Memory controller 1100 provides an interface between semiconductor memory device 100 and the host computer. Memory controller 1100 drives firmware for controlling semiconductor memory device 100.

[0190] The memory controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: working memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the memory controller 1100. Additionally, during write operations, the memory controller 1100 can temporarily store programming data provided by the host.

[0191] The host interface 1130 includes protocols for exchanging data between the host and the memory controller 1100. In one embodiment, the memory controller 1100 communicates with the host via at least one of a variety of interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0192] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface 1140 may include a NAND interface or a NOR interface.

[0193] Error correction block 1150 uses error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. In one embodiment, error correction block 1150 may be provided as a component of memory controller 1100.

[0194] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), or universal flash storage (UFS).

[0195] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive SSD includes a storage device configured to store data in semiconductor memory. If the memory system 1000 is used as a semiconductor drive SSD, the operating speed of the host coupled to the memory system 1000 can be significantly improved.

[0196] As another example, the memory system 1000 can be provided as one of a variety of components of an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, web tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), portable game console, navigation system, black box, digital camera, 3D TV, digital recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, device capable of transmitting / receiving information in a wireless environment, one of a variety of electronic devices constituting a home network, one of a variety of electronic devices constituting a computer network, one of a variety of electronic devices constituting a telematics network, RFID device, or one of a variety of components constituting a computing system.

[0197] In one embodiment, the semiconductor memory device 100 or memory system 1000 may be packaged in various forms. For example, the semiconductor memory device 100 or memory system 1000 may be packaged in ways such as: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processed stacked package (WSP).

[0198] Figure 20 It is a diagram. Figure 19 A block diagram of an application example of the memory system 1000 shown.

[0199] refer to Figure 20 The memory system 2000 includes a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0200] exist Figure 20 The diagram illustrates multiple groups communicating with the memory controller 2200 via channels CH1 to CHk. Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is configured and operated in the same manner.

[0201] Each group communicates with the memory controller 2200 via a shared channel. The memory controller 2200 and the reference... Figure 19 The memory controller 1100 described is configured similarly. The memory controller 2200 controls multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0202] Figure 21 This is a block diagram of a computing system 3000, which includes a reference... Figure 20 The memory system described is 2000.

[0203] refer to Figure 21 The computing system 3000 includes a central processing unit 3100, RAM 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0204] The memory system 2000 is electrically coupled to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via system bus 3500. Data supplied through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0205] exist Figure 21 The diagram illustrates a configuration where the semiconductor memory device 2100 is coupled to the system bus 3500 via the memory controller 2200. However, the semiconductor memory device 2100 can be directly coupled to the system bus 3500. The functions of the memory controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

[0206] exist Figure 21 The image shows one of the references. Figure 20 The memory system 2000 described is provided. However, the memory system 2000 can be replaced by the referenced... Figure 19 The memory system 1000 is described. In one embodiment, the computing system 3000 may include a reference... Figure 19 and Figure 20 The memory systems described are 1000 and 2000.

[0207] According to one embodiment of this disclosure, the semiconductor memory device and the method of operating the semiconductor memory device provide improved reliability.

[0208] While this disclosure has been shown and described with reference to certain embodiments, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0209] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0210] Furthermore, embodiments of this disclosure have been illustrated in the accompanying drawings and described in the specification. While specific terms are used herein, those terms are for the purpose of explaining the embodiments of this disclosure only. Therefore, this disclosure is not limited to the above embodiments, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made beyond the embodiments disclosed herein, building upon the technical scope of this disclosure.

Claims

1. A semiconductor memory device, comprising: A memory block includes virtual memory cells connected to virtual word lines and normal memory cells connected to normal word lines; The peripheral circuitry is configured to perform an erase operation on the memory block; as well as Control logic is configured to control the operation of the peripheral circuitry, wherein the control logic is configured to control the peripheral circuitry: In response to an erase command for the memory block, a preprogramming operation is performed on first virtual memory cells connected to a plurality of first virtual word lines among the virtual word lines, wherein the first virtual memory cells are simultaneously preprogrammed. After the preprogramming operation on the first dummy memory cell, a preprogramming operation is performed on the second dummy memory cell connected to the second dummy word line in the dummy word line; as well as An erase operation is performed on the normal memory cell.

2. The semiconductor memory device of claim 1, wherein the memory block comprises: The drain-select transistor is connected to the bit line; as well as The source selection transistor is connected to the common source line. The first dummy memory cell is located between the normal memory cell and the drain-select transistor, and The second dummy memory cell is located between the normal memory cell and the source selection transistor.

3. The semiconductor memory device of claim 2, wherein during the pre-programming operation on the first dummy memory cell, the control logic controls the peripheral circuitry: Apply a ground voltage to the common source line; Apply a programming pass voltage to the second dummy word line and the normal word line; as well as A first programming pulse is applied to the plurality of first dummy word lines.

4. The semiconductor memory device of claim 3, wherein during the pre-programming operation on the second dummy memory cell, the control logic controls the peripheral circuitry: Apply a ground voltage to the common source line; A programming pass voltage is applied to the plurality of first dummy word lines and the normal word lines; as well as A second programming pulse is applied to the second dummy word line.

5. The semiconductor memory device of claim 4, wherein the first programming pulse has the same voltage amplitude as the second programming pulse.

6. The semiconductor memory device of claim 4, wherein the first programming pulse has a voltage higher than that of the second programming pulse.

7. The semiconductor memory device of claim 4, wherein the first programming pulse has a voltage lower than that of the second programming pulse.

8. The semiconductor memory device of claim 1, wherein during the erase operation on the normal memory cell, the control logic controls the peripheral circuitry: An erase inhibit voltage is applied to the plurality of first dummy word lines and second dummy word lines; Apply an erase-permit voltage to the normal word line; as well as Apply an erase voltage to the common source line.

9. The semiconductor memory device of claim 1, wherein during the erase operation on the normal memory cell, the control logic controls the peripheral circuitry: Make the plurality of first dummy word lines and second dummy word lines float; Apply an erase-permit voltage to the normal word line; as well as Apply an erase voltage to the common source line.

10. The semiconductor memory device of claim 1, wherein after the pre-programming operation is performed on the second dummy memory cell, the control logic controls the peripheral circuitry to perform a pre-programming operation on a third dummy memory cell connected to a third dummy word line in the dummy word line.

11. The semiconductor memory device of claim 10, wherein the memory block comprises: The drain-select transistor is connected to the bit line; as well as The source selection transistor is connected to the common source line. The first dummy memory cell is located between the normal memory cell and the drain-select transistor. The second dummy memory cell is located between the normal memory cells, and The third dummy memory cell is located between the normal memory cell and the source selection transistor.

12. A method for operating a semiconductor memory device, the semiconductor memory device comprising a plurality of memory blocks, each memory block comprising first dummy memory cells connected to a plurality of first dummy word lines, second dummy memory cells connected to second dummy word lines, and normal memory cells connected to normal word lines, the method comprising: Receive erase command; The first dummy memory cell included in the selected memory block corresponding to the erase command among the plurality of memory blocks is preprogrammed, wherein the first dummy memory cell included in the selected memory block is simultaneously preprogrammed. After preprogramming the first dummy memory cell in the selected memory block, the second dummy memory cell included in the selected memory block is preprogrammed. as well as The normal memory cells included in the selected memory block are erased.

13. The method of claim 12, wherein preprogramming the first dummy memory cell included in the selected memory block comprises: Apply a ground voltage to the common source line connected to the selected memory block; A programming pass voltage is applied to the second dummy word line and the normal word line connected to the selected memory block; as well as A first programming pulse is applied to the plurality of first dummy word lines connected to the selected memory block.

14. The method of claim 13, wherein pre-programming the second dummy memory cells included in the selected memory block comprises: Apply a ground voltage to the common source line connected to the selected memory block; A programming pass voltage is applied to the plurality of first dummy word lines and the normal word lines connected to the selected memory block; as well as A second programming pulse is applied to the second dummy word line connected to the selected memory block.

15. The method of claim 14, wherein: The first dummy memory cell is a drain-side dummy memory cell; and The second dummy memory cell is a source-side dummy memory cell.

16. The method of claim 14, wherein: The first dummy memory cell is a source-side dummy memory cell; and The second dummy memory cell is a drain-side dummy memory cell.

17. The method of claim 12, wherein the erasure of the normal memory cells included in the selected memory block comprises: An erase enable voltage is applied to the normal word lines connected to the selected memory block, and an erase disable voltage is applied to the plurality of first dummy word lines and second dummy word lines connected to the selected memory block. as well as Apply an erase voltage to the common source line.

18. The method of claim 12, wherein erasing the normal memory cells included in the selected memory block comprises: An erase enable voltage is applied to the normal word lines connected to the selected memory block, and the plurality of first dummy word lines and second dummy word lines connected to the selected memory block are floated; as well as Apply an erase voltage to the common source line.

19. The method of claim 12, wherein the selected memory block further comprises a third dummy memory cell connected to a third dummy word line, and The method further includes: The third dummy memory cell is preprogrammed after the second dummy memory cell included in the selected memory block is preprogrammed and before the normal memory cell included in the selected memory block is erased.

20. The method of claim 19, wherein: The first dummy memory cell is a drain-side dummy memory cell; The second dummy memory cell is a dummy memory cell located between the normal memory cells; and The third virtual memory unit is a source-side virtual memory unit.

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