Method for manufacturing a chip and chip

Abstract

The application relates to a chip preparation method and a chip. The chip preparation method comprises the following steps: providing a wafer, the wafer comprising a scribe lane area and a die area, the scribe lane area at least surrounding part of the die area; obtaining a first size required by the scribe lane area; determining a second size required by the die area according to the first size required by the scribe lane area; determining the size of at least one structure distributed in the die area according to the second size required by the die area; and the ratio of the first size to the second size ranges from 1:24 to 1:18. According to the application, at least one structure in the original die area is expanded to the position of the scribe lane area without changing the size of the chip, so that over-etching occurs when the metal field plate is etched, space for the scribe knife to enter the scribe lane area is reserved, the space occupied by the structure of the die area is improved, and therefore the performance of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a chip preparation method and a chip. BACKGROUND

[0002] At present, the scribe blade commonly used by semiconductor chips is 25 um, and the scribe blade mark is about 30 um. In order to ensure that the chips in the wafer are cut into independent dies and ensure that the die structure is not damaged, the scribe lane of the layout design is generally about 80 um.

[0003] After the metal field plate is etched by a wet method, there is about 1:1.2 lateral corrosion (according to the thickness of the metal field plate The single-side lateral corrosion is about 6 um), which causes the metal field plate to shrink. In this way, the actual wafer scribe lane size will increase from 80 um in the layout to about 92 um, causing great waste of the die area. Since the width of the doped region, the metal field plate and the active area have a great influence on the reverse surge, VR and VF parameters, under the condition that the size of a single chip is fixed, in order to achieve the required reliability results and various parameters, the width of the doped region, the size of the metal field plate and the active area cannot be sacrificed to protect other sizes, and therefore, the wet etching over-etching will also cause product electrical parameter defects, so that the product performance is not outstanding, and the market competitiveness is not strong. SUMMARY

[0004] The present application aims to provide a chip preparation method and a chip, and aims to improve the space occupied by the die area structure, thereby improving the performance of the chip.

[0005] In a first aspect, an embodiment of the present application provides a chip preparation method, including the following steps: providing a wafer, the wafer including a scribe lane region and a die region, the scribe lane region at least surrounding part of the die region;

[0006] Obtaining a first size required by the scribe lane region;

[0007] According to the first size required by the scribe lane region, determining a second size required by the die region;

[0008] According to the second size required by the die region, determining the size of at least one structure distributed in the die region;

[0009] The ratio of the first size to the second size ranges from 1:24 to 1:18.

[0010] In the step of determining the size of at least one structure distributed in the die region according to the second size required by the die region, the step includes:

[0011] Obtaining real-time performance parameters of each structure in the die area, and comparing the real-time performance parameters of each structure with preset performance parameters of each structure to obtain parameter difference values of each structure;

[0012] According to the size of each parameter difference value, the size of the structure corresponding to each parameter difference value is changed in proportion; or,

[0013] According to the size of each parameter difference value, the maximum parameter difference value is obtained, and the size of the structure corresponding to the maximum parameter difference value is changed; or,

[0014] According to the size of each parameter difference value, the size of the structure corresponding to the maximum parameter difference value is changed in proportion, and the size of the structure corresponding to other parameter difference values is changed in average.

[0015] Before the step of obtaining the first size required by the scribe lane area, further comprising: according to the thickness of the metal field plate and the lateral etching depth of the metal field plate, obtaining the first size required by the scribe lane area.

[0016] When the thickness of the metal field plate is 6-10 μm, and the lateral etching depth of the metal field plate is 7-12 μm, the first size is 25-35 μm.

[0017] In an embodiment of the present application, the die area includes an active region, a doped region, and a metal field plate.

[0018] In the step of determining the size of at least one structure distributed in the die area according to the second size required by the die area, specifically: the size of the active region is changed, and the changed size of the active region is 540-560 μm.

[0019] In the step of determining the size of at least one structure distributed in the die area according to the second size required by the die area, specifically: the size of the doped region is changed, and the changed size of the doped region is 20-30 μm.

[0020] In the step of determining the size of at least one structure distributed in the die area according to the second size required by the die area, specifically: the size of the metal field plate is changed, and the changed size of the metal field plate is 600-640 μm.

[0021] In an embodiment of the present application, the scribe lane area includes a plurality of first scribe lanes and a plurality of second scribe lanes, the plurality of first scribe lanes are arranged along a first direction, the plurality of second scribe lanes are arranged along a second direction, and the plurality of first scribe lanes and the plurality of second scribe lanes intersect to form a plurality of die areas.

[0022] In a second aspect, the embodiments of the present application further provide a chip, which is manufactured by the above-mentioned method for manufacturing a chip, and the chip comprises: a die region; and a scribe lane region surrounding at least part of the die region.

[0023] According to the method for manufacturing a chip and the chip provided by the embodiments of the present application, by providing a wafer, the wafer comprises a scribe lane region and a die region, the scribe lane region surrounds at least part of the die region; and the first size required by the scribe lane region is obtained; the second size required by the die region is determined according to the first size required by the scribe lane region; the size of at least one structure distributed in the die region is determined according to the second size required by the die region; and the ratio of the first size to the second size ranges from 1:24 to 1:18. Without changing the size of the chip, at least one structure in the original die region is expanded to the position of the scribe lane region, so that over-etching occurs when the metal field plate is etched, a space for the scribe knife to enter the scribe lane region is reserved, and the space occupied by the structure of the die region is increased, thereby improving the performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0024] The features, advantages, and technical effects of the exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals. The drawings are not drawn to scale, but are used only to illustrate the relative positional relationship, and the layer thickness of some parts is exaggerated in the drawings for better understanding. The layer thickness in the drawings does not represent the actual ratio of the layer thickness.

[0025] Figure 1 is a plan view of the chip of the prior art;

[0026] Figure 2 is a sectional view based on Figure 1 ;

[0027] Figure 3 is a flowchart of the method of the present application;

[0028] Figure 4 is a flowchart of the specific way of size distribution of the present application;

[0029] Figure 5 is a plan view of Example 1 of the first embodiment of the present application;

[0030] Figure 6 is a sectional view of Example 1 of the first embodiment of the present application;

[0031] Figure 7 is a sectional view of Example 2 of the first embodiment of the present application;

[0032] Figure 8 is a sectional view of Example 3 of the first embodiment of the present application;

[0033] Figure 9 is a sectional view of a second embodiment of the present application;

[0034] Figure 10 is a sectional view of a third embodiment of the present application.

[0035] Explanation of Reference Numerals:

[0036] 1, die area; 11, doped region; 12, metal field plate; 13, active region; 14, epitaxial layer;

[0037] 2, scribe lane area. DETAILED DESCRIPTION

[0038] Features and exemplary embodiments of various aspects of the present application will be described below in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application can be practiced without some or all of these specific details. The description of the embodiments is merely illustrative of the present application and is not intended to limit the present application, as is apparent to one of ordinary skill in the art. In the drawings and description below, well-known structures and techniques have not been shown or described in detail in order not to obscure the application. Also, the size of the regions shown in the figures can be exaggerated, and the dimensions and the relative dimensions do not necessarily bear a relationship of scale to one another. Furthermore, features, structures or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0039] The orientation terms appearing in the following description are the directions shown in the drawings and are not intended to limit the specific structure of the present application. In the description of the present application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection" should be understood broadly, for example, can be fixed connection, or detachable connection, or integrally connected; can be directly connected, or indirectly connected. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] Semiconductor, refers to the normal temperature under the electrical performance between conductor (conductor) and insulator (insulator) between the material, which refers to a kind of electrical conductivity can be controlled, range can be from insulator to conductor between the material. Common semiconductor materials are silicon, germanium, gallium arsenide, etc., and silicon is one of the most influential semiconductor materials in commercial applications.

[0041] A Schottky diode is named after its inventor Dr. Schottky. A Schottky barrier diode (SBD) is not made by using the principle of forming a PN junction by the contact between a P-type semiconductor and an N-type semiconductor, but is made by using the principle of forming a metal-semiconductor junction by the contact between a metal and a semiconductor. Therefore, the SBD is also called a metal-semiconductor (contact) diode or a surface barrier diode, and it is a kind of hot carrier diode.

[0042] Referring to Figures 1-2 Fig. 1, an existing Schottky product is taken as an example. The existing Schottky product is a chip, which includes a die area and a scribe lane area. The die area includes an epitaxial layer, a doped region is formed in the epitaxial layer, an active region is formed on a side of the epitaxial layer close to the doped region, and a metal field plate is formed on a side of the active region away from the epitaxial layer.

[0043] At present, the width of a scribe knife used in a chip is generally 25 um, so that the scribe knife mark is 30 um. In order to ensure that the chip in the wafer is cut into an independent die and ensure that the die area is not damaged, the total width of the scribe lane area in the layout design is generally 80 um.

[0044] Since the metal field plate will have a 1:1.2 lateral etching (according to the thickness of the metal field plate The single-side lateral etching is about 6 um) after wet etching, the metal field plate is retracted, so that the total size of the scribe lane area on the actual wafer is increased from 80 um in the layout to about 92 um, causing great area waste. This waste also reduces the area occupied by the die area. The area of the die area directly affects the performance of the chip. The width of the doped region affects the reverse surge, the width of the metal field plate affects the reverse breakdown voltage (VR), and the width of the active region affects the forward voltage drop (VF). In the case of a fixed size of a single chip, in order to achieve the required reliability results and various parameters, the sizes of the doped region, the metal field plate and the active region cannot be sacrificed to protect other sizes. Wet etching over-etching will also cause poor product electrical parameters, so that the product performance is not outstanding and the market competitiveness is not strong.

[0045] Based on the above problems, the preparation method of a chip is described below taking a Schottky product as an example.

[0046] First embodiment

[0047] As shown in Figure 3 Fig. 1, a preparation method of a chip is provided, which includes the following steps:

[0048] S001, providing a wafer, the wafer including a scribe lane area and a die area 1, the scribe lane area at least surrounding part of the die area 1;

[0049] S002. Obtain the first dimension required for the scribbling area;

[0050] S003. Determine the second dimension required for the core region 1 based on the first dimension required for the dicing area;

[0051] S004. Determine the dimensions of at least one structure allocated to the core region 1 based on the second dimension required for the core region 1;

[0052] S005. The ratio of the first dimension to the second dimension is in the range of 1:24 to 1:18.

[0053] According to an embodiment of this application, a chip fabrication method is provided in which at least one structure in the original die region 1 is expanded to the dicing channel region without changing the chip size. This allows over-corrosion to occur when the metal field plate 12 is etched, reserving space for the dicing blade to enter the dicing channel region and increasing the space occupied by the structure in the die region 1, thereby improving the chip performance.

[0054] The die region 1 includes an epitaxial layer 14, in which a doped region 11 (which can be a doped region 11 in this embodiment) is formed. An active region 13 is formed on the side of the epitaxial layer 14 near the doped region 11, and a metal field plate 12 is formed on the side of the active region 13 away from the epitaxial layer 14.

[0055] Before step S002, the method further includes: obtaining the first dimension required for the scribe line area based on the thickness of the metal field plate 12 and the lateral etching depth of the metal field plate 12. Specifically, when the thickness of the metal field plate 12 is 6μm-10μm and the lateral etching depth of the metal field plate 12 is 7μm-12μm, the first dimension, originally 35μm-45μm, is reduced by 8μm-12μm, resulting in a final first dimension of 25μm-35μm. Correspondingly, the increased second dimension is 450μm-840μm.

[0056] In step S004, as follows Figure 4 As shown, considering that the excess size of the dicing area can be added to the doped region 11, metal field plate 12, or active region 13 within the die region 1, a single performance of reverse surge, VR, or VF can be made significantly outstanding, thereby improving chip performance. To ensure that the worst-performing structure is allocated, the specific method is as follows:

[0057] The real-time performance parameters of each structure in the die region 1 are obtained, and the real-time performance parameters of each structure are compared with the preset performance parameters of each structure to obtain the parameter difference of each structure.

[0058] According to the size of the parameter difference, the maximum parameter difference is obtained, and the size of the structure corresponding to the maximum parameter difference is changed.

[0059] In the acquisition of real-time performance parameters and preset performance parameters, the existing chip can be used for multiple experiments, and the obtained performance parameters are transmitted to the controller for comparison to obtain the difference.

[0060] According to the above method, first, the active region 13, the metal field plate 12 and the doped region 11 are respectively set with preset performance parameters, then the real-time performance parameters of the active region 13, the metal field plate 12 and the doped region 11 are obtained, and the difference of each parameter is obtained accordingly. According to the size of the difference, the structure corresponding to the maximum difference is obtained, and the size of the scribe lane region is reduced to the structure.

[0061] As shown in Figures 5-6 , as an example one, if the parameter difference of the forward voltage drop voltage VF is the largest, that is, the size of the active region 13 corresponding to the forward voltage drop voltage VF is smaller, so the size of the active region 13 needs to be changed, and the size of the scribe lane region reduced by 8-12 μm is increased to the active region 13, and finally the size of the active region 13 is 540-560 μm, so as to improve the forward voltage drop voltage VF of the chip, that is, the voltage corresponding to the rated current, and improve the electrical performance of the chip.

[0062] As shown in Figure 7 , as an example two, if the parameter difference of the reverse surge is the largest, that is, the size of the doped region 11 corresponding to the reverse surge is smaller, so the size of the doped region 11 needs to be changed, and the size of the scribe lane region reduced by 8-12 μm is increased to the size of the doped region 11. The size of the changed doped region 11 is 20-30 μm. By increasing the size of the doped region 11, the resistance of the reverse surge can be increased, so that the chip will not be broken down in the case that the battery is accidentally connected in the opposite polarity, thereby improving the electrical performance of the chip.

[0063] As shown in Figure 8 , as an example three, if the parameter difference of the reverse breakdown voltage VR is the largest, that is, the size of the metal field plate 12 corresponding to the reverse breakdown voltage VR is smaller, so the size of the metal field plate 12 needs to be changed, and the size of the scribe lane region reduced by 8-12 μm is increased to the metal field plate 12. The size of the changed metal field plate 12 is 600-640 μm. By increasing the size of the metal field plate 12, the high reliability of the reverse breakdown voltage VR is improved, so that the chip has high electrical performance.

[0064] It should be noted that in the embodiment, the size is preferentially allocated to the active layer to improve the forward voltage drop voltage VF of the chip, and example one is the most preferred embodiment, and the size is secondarily allocated to the metal field plate 12 and the doped region 11 to improve the reverse breakdown voltage VR and the reverse surge of the chip.

[0065] In an embodiment of the present application, the scribe lane region includes a plurality of first scribe lanes and a plurality of second scribe lanes, the plurality of first scribe lanes are arranged along a first direction, the plurality of second scribe lanes are arranged along a second direction, and the plurality of first scribe lanes and the plurality of second scribe lanes intersect to form a plurality of the die regions 1. Specifically, the first direction and the second direction are perpendicular to each other, so that an array of a plurality of die regions 1 is formed on each wafer.

[0066] Second embodiment

[0067] As shown in Figure 4 and Figure 9 The embodiment of the present application is basically the same as example one, and the difference is that in the step of allocating the size of at least one structure in the die region 1 according to the second size required by the die region 1, the embodiment includes:

[0068] Obtaining real-time performance parameters of each structure in the die region 1, and comparing the real-time performance parameters of each structure with preset performance parameters of each structure to obtain parameter difference values of each structure;

[0069] According to the size of each parameter difference value, the size of the structure corresponding to each parameter difference value is changed in proportion.

[0070] In the above manner, the sizes of the active region 13, the metal field plate 12 and the doped region 11 can be proportionally increased according to different performance conditions of the structure, so that the forward voltage drop voltage VF, the reverse surge and the reverse breakdown voltage VR of the chip are improved to different degrees, and the improvement of each performance is according to the parameter difference ratio, which is more in line with the needs, so that each electrical property of the chip can be reasonably improved.

[0071] Specifically, the active region 13, the metal field plate 12 and the doped region 11 are respectively allocated 4-5 μm, 2-4 μm and 2-3 μm, and the size of the allocated active region 13 is 534-555 μm, the size of the allocated metal field plate 12 is 592-634 μm, and the size of the allocated doped region 11 is 12-23 μm.

[0072] Third embodiment

[0073] As shown in Figure 10As shown, the embodiment of the present application is basically the same as the first embodiment, the difference is that in the step of distributing the size of at least one structure in the die area 1 according to the second size required by the die area 1, the embodiment comprises:

[0074] Obtaining the real-time performance parameters of each structure in the die area 1, and comparing the real-time performance parameters of each structure with the preset performance parameters of each structure to obtain the parameter difference of each structure;

[0075] According to the size of each parameter difference, the size of the structure corresponding to the largest parameter difference is changed in proportion, and the size of the structure corresponding to the other parameter difference is changed averagely.

[0076] In the above manner, the size of the structure corresponding to the largest parameter difference is preferentially distributed in proportion, for example, the size of the active region 13 is preferentially increased in proportion, and the remaining sizes are averagely distributed to the metal field plate 12 and the doped region 11, so that the forward voltage drop voltage VF of the chip is best improved, and the reverse surge and reverse breakdown voltage VR of the chip are improved to the same extent, so that the structure size of the chip which needs to be improved in performance can be effectively increased, and other structures are averagely distributed without the need for calculation and distribution, and other performances can also be improved, greatly saving the process.

[0077] Specifically, the active region 13, the metal field plate 12 and the doped region 11 are respectively distributed 4-5 μm, 2-3.5 μm and 2-3.5 μm, the size of the distributed active region 13 is 534-555 μm, the size of the distributed metal field plate 12 is 592-633.5 μm, and the size of the distributed doped region 11 is 12-23.5 μm.

[0078] It should be noted that the semiconductor device in the embodiment can also include other layer structures, such as substrates, positive and negative electrodes, etc., which will not be described here.

[0079] In addition, in the embodiment of the present application, since the scribe lane area intersects and surrounds the die area 1, and the die area 1 is surrounded by the scribe lane area, the first size and the second size of all the embodiments of the present application are 1 / 2 of the size of the scribe lane area and 1 / 2 of the size of the die area 1.

[0080] The technical solution of the present application can also be widely applied to the preparation of other various semiconductor devices, such as discrete device categories of fast recovery diodes (FRD), transient voltage suppressors (TVS), switch diodes, rectifier diodes, light source triodes, silicon controlled rectifier elements, and small signal triodes, all of which can be applicable to the above solutions.

[0081] It should be readily understood that "on", "over", and "above" in the present application should be interpreted in the broadest manner, such that "on" means not only "directly on", but also includes the meaning of "on" with intermediate features or layers therebetween, and "over" or "above" includes not only the meaning of "over" or "above", but also the meaning of "over" or "above" without intermediate features or layers therebetween (i.e., directly on).

[0082] The term "layer" as used herein can refer to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. Further, a layer can be a region of a continuous structure that is homogeneous or inhomogeneous and that has a thickness less than the thickness of the continuous structure. For example, a layer can be between or at any pair of lateral planes between a top surface and a bottom surface of the continuous structure. A layer can extend laterally, vertically, and / or along a tapered surface. A semiconductor device can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (within which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0083] Finally, it should be noted that the above-described embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the technical solutions of the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of producing a chip, characterized by, The chip comprises: providing a wafer, the wafer comprising a scribe lane region and a die region, the scribe lane region at least surrounding part of the die region; obtaining a first size required by the scribe lane region; determining a second size required by the die region according to the first size required by the scribe lane region; determining the size of at least one structure allocated into the die region according to the second size required by the die region, comprising: obtaining real-time performance parameters of each structure in the die region, and comparing the real-time performance parameters of each structure with preset performance parameters of each structure to obtain parameter differences of each structure; proportionally changing the size of the structure corresponding to each parameter difference according to the size of each parameter difference; or, obtaining the largest parameter difference according to the size of each parameter difference, and changing the size of the structure corresponding to the largest parameter difference; or, proportionally changing the size of the structure corresponding to the largest parameter difference, and averagely changing the size of the structure corresponding to other parameter differences according to the size of each parameter difference; the ratio of the first size to the second size ranges from 1:24 to 1:

18.

2. The method of claim 1, wherein the chip is prepared by a method comprising: Before the step of obtaining the first size required by the scribe lane region, the method further comprises: obtaining the first size required by the scribe lane region according to the thickness of the metal field plate and the lateral etching depth of the metal field plate.

3. The method of claim 2, wherein the chip is prepared by a method comprising: When the thickness of the metal field plate is 6 μm-10 μm, and the lateral etching depth of the metal field plate is 7 μm-12 μm, the first size is 25 μm-35 μm.

4. The method of claim 1, wherein the chip is prepared by a method comprising: The die region comprises an active region, a doped region, and a metal field plate.

5. The method of claim 4, wherein the chip is prepared by a method comprising: In the step of determining the size of at least one structure allocated into the die region according to the second size required by the die region, the size of the active region is changed, and the changed size of the active region is 540 μm-560 μm.

6. The method of claim 4, wherein the chip is prepared by a method comprising: In the step of determining the size of at least one structure allocated into the die region according to the second size required by the die region, the size of the doped region is changed, and the changed size of the doped region is 20 μm-30 μm.

7. The method of claim 4, wherein the chip is prepared by a method comprising: In the step of determining the size of at least one structure allocated into the die region according to the second size required by the die region, the size of the metal field plate is changed, and the changed size of the metal field plate is 600 μm-640 μm.

8. The method of claim 1, wherein the chip is a semiconductor chip. The scribe lane region comprises a plurality of first scribe lanes and a plurality of second scribe lanes, the plurality of first scribe lanes are arranged along a first direction, the plurality of second scribe lanes are arranged along a second direction, and the plurality of first scribe lanes and the plurality of second scribe lanes intersect to form a plurality of die regions.

9. A chip, characterized by The chip is prepared by the method of any one of claims 1-8, and the chip comprises: a die region; a scribe lane region at least surrounding part of the die region.

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