High-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation and its fabrication method

Abstract

This invention relates to a high-linearity Fin-HEMT device based on top-gate and side-wall gate decoupling modulation and its fabrication method, comprising: selecting a substrate layer; growing a buffer layer on the substrate layer; growing an i-GaN layer on the buffer layer; growing an AlGaN barrier layer on the i-GaN layer; depositing ohmic metal on the AlGaN barrier layer; implanting ions from the periphery of the AlGaN barrier layer into the i-GaN layer; fabricating a SiN layer on the AlGaN barrier layer; removing the SiN layer in the gate foot region; fabricating a top gate on the AlGaN barrier layer in the gate foot region; intermittently removing the top gate metal, AlGaN barrier layer, and part of the i-GaN layer in the side-wall gate region, such that the AlGaN barrier layer and the top gate metal on the AlGaN barrier layer are arranged discontinuously at predetermined intervals; fabricating an Al2O3 dielectric layer on the i-GaN layer and the top gate metal in the side-wall gate region; and fabricating a side-wall gate on the bottom and sidewall of the Al2O3 dielectric layer in the side-wall gate region. This invention improves the flatness of transconductance and the linearity of the device over a larger range of gate overdrive by applying different gate biases to the top gate and sidewall gate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation and its fabrication method. Background Technology

[0002] GaN-based high electron mobility transistors (HEMTs) have become candidates for next-generation high-power and high-speed devices due to their material advantages, such as large bandgap, high breakdown electric field, high saturation electron velocity, and high 2DEG (two-dimensional electron gas) density at the heterojunction caused by polarization. To improve the operating frequency of GaN-based HEMTs, reducing the gate length and increasing the channel carrier velocity are commonly used techniques.

[0003] However, when the gate length shrinks to the deep submicron range, undesirable short-channel effects (SCE) occur, which can be attributed to decreased gate control over the channel and the channel enhancement effect of the drain field. Since FinFET (Fin Field-Effect Transistor) structures improve gate controllability, especially for FinFET structures where the gate wraps around the nanochannel from three sides (including the top side and two sidewalls), providing stronger gate control for HEMTs, GaN-based HEMTs with nanochannels and FinFET structures have attracted considerable attention.

[0004] However, existing AlGaN / GaN HEMT technologies suffer from nonlinearity issues, leading to severe sidebanding, output power saturation at high input power, and signal distortion. Therefore, due to the surging demand for high data transmission rates and spectral efficiency in modern wireless communication technologies, improving the linearity of power amplifiers has become crucial. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation and its fabrication method.

[0006] One embodiment of the present invention provides a method for fabricating a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, the method comprising:

[0007] Select a substrate layer;

[0008] A buffer layer is grown on the substrate layer;

[0009] An i-GaN layer is grown on the buffer layer; an AlGaN barrier layer is grown on the i-GaN layer;

[0010] Ohmic metal is deposited on the AlGaN barrier layer to fabricate the source and drain electrodes;

[0011] Ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer to achieve device isolation;

[0012] A SiN layer is fabricated on the AlGaN barrier layer;

[0013] The SiN layer in the gate foot region is removed to expose the AlGaN barrier layer in the gate foot region;

[0014] Top gate metal is deposited on the AlGaN barrier layer in the gate foot region to fabricate the top gate;

[0015] The top gate metal, the AlGaN barrier layer, and part of the i-GaN layer in the sidewall gate region are removed at intervals so that the AlGaN barrier layer and the top gate metal on the AlGaN barrier layer are arranged in a discontinuous manner at a predetermined interval.

[0016] An Al2O3 dielectric layer is prepared on the i-GaN layer in the sidewall gate region and on the spaced-apart top gate metals;

[0017] Sidewall gate metal is deposited on the bottom and sidewalls of the Al2O3 dielectric layer in the sidewall gate region to prepare the sidewall gate.

[0018] In one embodiment of the present invention, the material of the buffer layer includes GaN.

[0019] In one embodiment of the present invention, an ohmic metal is deposited on the AlGaN barrier layer to fabricate the source and drain electrodes, comprising:

[0020] An ohmic metal is deposited on the AlGaN barrier layer using an electron beam evaporation method. The ohmic metal is an ohmic multilayer metal comprising Ti / Al / Ni / Au.

[0021] The device with the deposited ohmic metal is subjected to rapid thermal annealing in an N2 atmosphere to prepare the source and the drain.

[0022] In one embodiment of the present invention, ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer to achieve device isolation, including:

[0023] Boron ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer using an ion implantation method to achieve device isolation.

[0024] In one embodiment of the present invention, a SiN layer is fabricated on the AlGaN barrier layer, comprising:

[0025] SiN layers were deposited on the AlGaN barrier layer and the ohmic metal using the PECVD method;

[0026] The SiN layer on the ohmic metal is etched away using a dry etching method to expose the ohmic metal, while retaining the SiN layer on the AlGaN barrier layer.

[0027] In one embodiment of the present invention, removing the SiN layer in the gate pin region to expose the AlGaN barrier layer in the gate pin region includes:

[0028] The SiN layer in the gate pin region is removed using an F-based etching method to expose the AlGaN barrier layer in the gate pin region.

[0029] In one embodiment of the present invention, the top gate metal, the AlGaN barrier layer, and a portion of the i-GaN layer are removed at intervals from the sidewall gate region, including:

[0030] The top gate metal of the sidewall gate region is etched away using F-based etching.

[0031] The AlGaN barrier layer and part of the i-GaN layer in the sidewall gate region are etched away using Cl-based etchers to sever the channel.

[0032] In one embodiment of the present invention, after fabricating the sidewall gate, the method further includes:

[0033] Interconnect metal is deposited on the source, the drain, the top gate, and the sidewall gate.

[0034] In one embodiment of the invention, the top gate comprises a top gate tungsten, and the sidewall gate comprises Ni / Au.

[0035] One embodiment of the present invention provides a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, fabricated using the fabrication method described in any of the above embodiments, wherein the high linearity Fin-HEMT device comprises:

[0036] Substrate layer;

[0037] A buffer layer located on the substrate layer;

[0038] The i-GaN layer is located on the buffer layer;

[0039] AlGaN barrier layers are spaced apart in the gate foot region;

[0040] The source and drain are located on the AlGaN barrier layer;

[0041] The top gate is located on the AlGaN barrier layer in the gate foot region;

[0042] The i-GaN layer located between the two AlGaN barrier layers in the gate foot region and the Al2O3 dielectric layer on the top gate;

[0043] The sidewall gate is located at the bottom of the Al2O3 dielectric layer and on the sidewall of the sidewall gate region.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] This invention adjusts the gate bias of the sidewall gate by applying different gate biases to the top gate and sidewall gate regions, thereby enhancing the current contribution of the sidewall MIS channel to increase current drive capability, suppressing transconductance drop, and improving transconductance flatness. It has great potential in high linearity RF applications.

[0046] This invention improves the flatness of transconductance and the linearity of the device over a larger range of gate overdrive by applying different gate biases to the top gate and sidewall gate. Attached Figure Description

[0047] Figure 1 This is a schematic flowchart illustrating a method for fabricating a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, as provided in an embodiment of the present invention.

[0048] Figures 2a to 2e A schematic diagram illustrating the fabrication process of a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, provided in an embodiment of the present invention;

[0049] Figure 3 This is a top view of a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, provided for an embodiment of the present invention. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0051] It should be noted that, in this embodiment, "up," "down," "left," and "right" refer to the positional relationship of the Schottky diode structure when it is in the illustrated state, "length" refers to the lateral dimension of the Schottky diode when it is in the illustrated state, and "depth" refers to the longitudinal dimension of the Schottky diode when it is in the illustrated state.

[0052] Example 1

[0053] Please see Figure 1 , Figures 2a to 2e , Figure 3 , Figure 1 This is a schematic flowchart illustrating a method for fabricating a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, according to an embodiment of the present invention. Figures 2a to 2e This is a schematic diagram illustrating the fabrication process of a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, as provided in an embodiment of the present invention. Figure 3 This is a top view of a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, provided in an embodiment of the present invention. The embodiment of the present invention provides a method for fabricating a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, the method comprising:

[0054] Step 1: Select a substrate layer.

[0055] Preferably, the substrate is a SiC substrate.

[0056] Step 2: Grow a buffer layer on the substrate using MOCVD (Metal-organic Chemical Vapor Deposition).

[0057] Preferably, the material of the buffer layer includes GaN.

[0058] Step 3: Grow an i-GaN (unintentionally doped GaN) layer on the substrate.

[0059] Specifically, based on step 2, an i-GaN layer is grown on a buffer layer above the substrate using the MOCVD method.

[0060] Step 4: Grow an AlGaN barrier layer on the i-GaN layer.

[0061] Specifically, an AlGaN barrier layer is grown on the i-GaN layer using the MOCVD method.

[0062] Preferably, the AlGaN barrier layer is Al 0.25 GaN with a thickness of 20nm.

[0063] In this embodiment, an AlN layer can also be grown on the i-GaN layer before growing the AlGaN barrier layer. The AlN layer can be 1 nm in size.

[0064] Alternatively, a GaN cap layer can be grown on the AlGaN barrier layer, with a thickness of up to 2.5 nm.

[0065] In this embodiment, AlGaN / GaN heterojunction material was used.

[0066] Step 5: In this embodiment, the alignment mark can also be photolithographically etched. After the mark is made, each subsequent photolithographic overlay step can be compared with the mark to prevent misalignment.

[0067] Step 6: Deposit ohmic metal on the AlGaN barrier layer to prepare the source and drain.

[0068] Step 6.1: Deposit ohmic metal on the AlGaN barrier layer using electron beam evaporation. The ohmic metal is an ohmic multilayer metal, which includes Ti / Al / Ni / Au, i.e., Ti, Al, Ni, and Au from bottom to top.

[0069] Preferably, the thicknesses of Ti, Al, Ni, and Au are 20 nm, 160 nm, 55 nm, and 45 nm, respectively.

[0070] Step 6.2: Perform rapid thermal annealing on the device with deposited ohmic metal in an N2 atmosphere to prepare the source and drain electrodes.

[0071] Preferably, the rapid thermal annealing temperature is 860°C and the rapid thermal annealing time is 60 seconds.

[0072] Step 7: Implant ions from the periphery of the AlGaN barrier layer into the i-GaN layer to achieve device isolation.

[0073] Specifically, boron ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer using an ion implantation method to achieve device isolation.

[0074] Step 8: Prepare a SiN layer on the AlGaN barrier layer.

[0075] Step 8.1: Deposit SiN layers on the AlGaN barrier layer and ohmic metal using PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0076] Preferably, the thickness of the SiN layer is 120 nm.

[0077] Step 8.2: Use a dry etching method to etch away the SiN layer on the ohmic metal to expose the ohmic metal and retain the SiN layer on the AlGaN barrier layer.

[0078] Specifically, the opening is etched using a dry etching method with an ICP (inductively coupled plasma) etching device to remove the SiN layer on the ohmic metal.

[0079] Furthermore, the etching gas is CF4 / O2, with a flow rate of 25 / 5 sccm, a chamber pressure of 5 mTorr, an upper electrode power of 80 W, and a lower electrode power of 10 W.

[0080] The SiN layer can react with the dangling bonds on the barrier surface, reducing surface states and lowering current collapse.

[0081] Step 9: Remove the SiN layer in the gate foot region to expose the AlGaN barrier layer in the gate foot region, wherein the gate foot region is located between the source and drain.

[0082] Specifically, the SiN layer in the gate region is removed using an ICP etching device and an F-based etching method to expose the AlGaN barrier layer in the gate region.

[0083] Furthermore, the etching gas is CF4 / O2, with a flow rate of 25 / 5 sccm, a chamber pressure of 5 mTorr, an upper electrode power of 80 W, a lower electrode power of 10 W, and a bias voltage of 46 V.

[0084] Step 10, please refer to Figure 2a The top gate is fabricated by depositing top gate metal on the AlGaN barrier layer in the gate foot region.

[0085] Specifically, the top gate metal is deposited on the AlGaN barrier layer in the gate foot region using an electron beam evaporation method to fabricate the top gate.

[0086] Preferably, the top gate comprises a top gate tungsten. Because tungsten can be etched using dry etching, the top gate metal etching and barrier layer etching can be performed in a single photolithography step, reducing the number of process steps.

[0087] Step 11: Remove the top gate metal, AlGaN barrier layer and part of i-GaN layer from the sidewall gate region at intervals, so that the AlGaN barrier layer and the top gate metal on the AlGaN barrier layer are arranged in a discontinuous manner at a preset interval.

[0088] Step 11.1, please refer to Figure 2b First, electron beam lithography is used for photolithography. Then, F-based plasma is used to etch away the top gate metal in the sidewall gate region at intervals along the gate width. F-based plasma reacts with tungsten to generate WF6 gas, achieving dry etching of tungsten.

[0089] Step 11.2, please refer to Figure 2c The AlGaN barrier layer and part of the i-GaN layer in the sidewall gate region are etched away using Cl-based etching, so that the AlGaN barrier layer and the top gate metal on the AlGaN barrier layer are arranged in a discontinuous manner at predetermined intervals. In order to form a periodic nanochannel, the etching depth needs to reach the i-GaN layer.

[0090] Cl-based plasma reacts with GaN-based materials to generate gases GaCl3 and N2, enabling dry etching of AlGaN and GaN.

[0091] Step 12, please refer to Figure 2d An Al2O3 dielectric layer was prepared on the i-GaN layer in the sidewall gate region and on the spaced-apart top gate metal.

[0092] Specifically, an Al2O3 dielectric layer is fabricated on the i-GaN layer in the sidewall gate region and on the spaced-apart top gate metal layers using the ALD (Atomic Layer Deposition) method. The Al2O3 dielectric layer is used to achieve electrical isolation between the top gate and the sidewall gate. This is because both the top gate and the sidewall gate are metals, and they must be led out separately to apply different gate voltages. If the top gate and the sidewall gate were to come into contact, a short circuit would occur.

[0093] Step 13, please refer to Figure 2e Sidewall gate metal is deposited on the bottom and sidewalls of the Al2O3 dielectric layer in the sidewall gate region to prepare a sidewall gate of MIS (Metal-oxide-Semiconductor) structure.

[0094] Specifically, sidewall gate metal is deposited on the bottom and sidewalls of the Al2O3 dielectric layer in the sidewall gate region using an electron beam evaporation method.

[0095] Preferably, the sidewall gate comprises Ni / Au, i.e., Ni and Au arranged sequentially from bottom to top. The sidewall gate uses Ni / Au and is selectively deposited after photolithography.

[0096] Step 14: Deposit interconnect metal on the source, drain, top gate, and sidewall gate.

[0097] Specifically, deposition is performed using an electron beam evaporation device. Interconnected metal.

[0098] For planar HEMTs, increasing the gate bias to obtain more charge increases the charge surface density and decreases the saturation rate, thus reducing transconductance. For Fin-HEMTs, as the gate voltage increases, the current contribution from the sidewall MOS channel benefits the current drive capability, which can suppress transconductance roll-off. Building on this, separating the top-gate and sidewall gate control, and applying a different bias voltage to the sidewall gate than the top-gate to modulate the channel transport, improves transconductance flatness and device linearity.

[0099] This invention applies different gate biases to the top gate and side gate regions, thereby adjusting the side gate bias to enhance current contribution, suppress transconductance drop, and improve transconductance flatness, which has great potential in high linearity RF applications.

[0100] This invention improves the flatness of transconductance and the linearity of the device over a larger range of gate overdrive by applying different gate biases to the top gate and sidewall gate.

[0101] Example 2

[0102] Please see Figures 2a to 2e , Figure 3 Based on Embodiment 1, this invention also provides a high linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation. This high linearity Fin-HEMT device is fabricated using the fabrication method described in Embodiment 1. The high linearity Fin-HEMT device includes:

[0103] Substrate layer;

[0104] A buffer layer located on the substrate layer;

[0105] The i-GaN layer is located on the buffer layer;

[0106] AlGaN barrier layers are spaced apart in the gate foot region;

[0107] Source and drain located on the AlGaN barrier layer;

[0108] Top gate located on the AlGaN barrier layer in the gate foot region;

[0109] The i-GaN layer located between the two AlGaN barrier layers in the gate foot region and the Al2O3 dielectric layer on the top gate;

[0110] The sidewall gate is located at the bottom of the Al2O3 dielectric layer and on the sidewall of the sidewall gate region.

[0111] This invention applies different gate biases to the top gate and side gate regions, thereby adjusting the side gate bias to enhance current contribution, suppress transconductance drop, and improve transconductance flatness, which has great potential in high linearity RF applications.

[0112] This invention improves the flatness of transconductance and the linearity of the device over a larger range of gate overdrive by applying different gate biases to the top gate and sidewall gate.

[0113] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0114] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0115] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, characterized in that, The fabrication method of the high linearity Fin-HEMT device includes: Select a substrate layer; A buffer layer is grown on the substrate layer; An i-GaN layer is grown on the buffer layer; An AlGaN barrier layer is grown on the i-GaN layer; Ohmic metal is deposited on the AlGaN barrier layer to fabricate the source and drain electrodes; Ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer to achieve device isolation; A SiN layer is fabricated on the AlGaN barrier layer; The SiN layer in the gate foot region is removed to expose the AlGaN barrier layer in the gate foot region; Top gate metal is deposited on the AlGaN barrier layer in the gate foot region to fabricate the top gate; The top gate metal, the AlGaN barrier layer, and part of the i-GaN layer in the sidewall gate region are removed at intervals so that the AlGaN barrier layer and the top gate metal on the AlGaN barrier layer are arranged in a discontinuous manner at a predetermined interval. An Al2O3 dielectric layer is prepared on the i-GaN layer in the sidewall gate region and on the spaced-apart top gate metals; Sidewall gate metal is deposited on the bottom and sidewalls of the Al2O3 dielectric layer in the sidewall gate region to prepare the sidewall gate.

2. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, The material of the buffer layer includes GaN.

3. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, Depositing ohmic metal on the AlGaN barrier layer to fabricate the source and drain electrodes includes: An ohmic metal is deposited on the AlGaN barrier layer using an electron beam evaporation method. The ohmic metal is an ohmic multilayer metal comprising Ti / Al / Ni / Au. The device with the deposited ohmic metal is subjected to rapid thermal annealing in an N2 atmosphere to prepare the source and the drain.

4. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, Ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer to achieve device isolation, including: Boron ions are implanted from the periphery of the AlGaN barrier layer into the i-GaN layer using an ion implantation method to achieve device isolation.

5. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, Fabricating a SiN layer on the AlGaN barrier layer includes: SiN layers were deposited on the AlGaN barrier layer and the ohmic metal using the PECVD method; The SiN layer on the ohmic metal is etched away using a dry etching method to expose the ohmic metal, while retaining the SiN layer on the AlGaN barrier layer.

6. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, Removing the SiN layer in the gate pin region to expose the AlGaN barrier layer in the gate pin region includes: The SiN layer in the gate pin region is removed using an F-based etching method to expose the AlGaN barrier layer in the gate pin region.

7. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, The process of removing the top gate metal, the AlGaN barrier layer, and a portion of the i-GaN layer from the sidewall gate region at intervals includes: The top gate metal of the sidewall gate region is etched away using F-based etching. The AlGaN barrier layer and part of the i-GaN layer in the sidewall gate region are etched away using Cl-based etchers to sever the channel.

8. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, After fabricating the sidewall gate, the following steps are also included: Interconnect metal is deposited on the source, the drain, the top gate, and the sidewall gate.

9. The method for fabricating a high-linearity Fin-HEMT device according to claim 1, characterized in that, The top gate comprises a top gate tungsten, and the sidewall gate comprises Ni / Au.

10. A high-linearity Fin-HEMT device based on top-gate sidewall gate decoupling modulation, characterized in that, The high-linearity Fin-HEMT device, fabricated using the method according to any one of claims 1 to 9, comprises: Substrate layer; A buffer layer located on the substrate layer; The i-GaN layer is located on the buffer layer; AlGaN barrier layers are spaced apart in the gate foot region; The source and drain are located on the AlGaN barrier layer; The top gate is located on the AlGaN barrier layer in the gate foot region; The i-GaN layer located between the two AlGaN barrier layers in the gate foot region and the Al2O3 dielectric layer on the top gate; The sidewall gate is located at the bottom of the Al2O3 dielectric layer and on the sidewall of the sidewall gate region.

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