Method for manufacturing embedded component package substrate

Abstract

The application discloses a manufacturing method of an embedded component packaging substrate, comprising: (a) manufacturing a semi-finished product substrate, wherein the semi-finished product substrate comprises a first dielectric layer and a first circuit layer on the upper surface of the first dielectric layer; (b) manufacturing an embedded component layer, wherein the embedded component layer comprises a packaging layer and a component embedded in the packaging layer, and the back surface of the component is flush with the lower surface of the packaging layer; (c) laminating the semi-finished product substrate and the embedded component layer through an adhesive layer; (d) forming an interlayer conductive copper column layer penetrating through the packaging layer and the adhesive layer in the height direction in the packaging layer and the adhesive layer, forming a conductive hole in the packaging layer and in communication with the terminal of the component, and forming an outer circuit layer on the upper surface of the packaging layer, wherein the outer circuit layer is conductively connected with the first circuit layer through the interlayer conductive copper column layer, and the outer circuit layer is in communication with the terminal of the component through the conductive hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, in particular to a method for manufacturing a package substrate with embedded components. BACKGROUND

[0002] With the continuous development of the electronic industry, multifunction and miniaturization of electronic products have become a development trend. In the field of packaging substrates, embedding components into the interior of the substrate can help electronic products achieve the needs of high integration, multifunction and miniaturization.

[0003] In existing embedding technologies for packaging substrates, there are cavity technologies and cavity-free technologies. The cavity technology requires first making a cavity on the substrate, then placing the components into the cavity, and finally packaging and building up layers. The cavity-free technology directly mounts the components on the surface of the substrate or carrier board, and then packages and builds up layers.

[0004] In the cavity technology, the size and position accuracy of the cavity are limited by equipment and process methods, and the cost is relatively high. In existing cavity-free technologies, the common manufacturing method is to first manufacture a substrate, then single-sidedly attach components on the surface of the substrate, and finally compress the resin medium for packaging and manufacture the circuit. Or, first package the components on a carrier board, and then build up layers one by one on the surface thereof.

[0005] Both the cavity technology and the cavity-free technology are asymmetric in structure, and are asymmetrically manufactured. Due to the difference in CTE (coefficient of thermal expansion) between materials, especially when the resin medium is cured, stress imbalance occurs, resulting in substrate warping.

[0006] In addition, both the cavity technology and the cavity-free technology build up layers after packaging, and the scrap generated in the post-process directly leads to the loss of embedded components. The more the number of layers and the denser the circuit, the higher the yield loss, and the greater the loss of components. SUMMARY

[0007] Therefore, the purpose of the present application is to provide a method for manufacturing a package substrate with embedded components.

[0008] To achieve the above purpose, the present application provides, in a first aspect, a method for manufacturing a package substrate with embedded components, comprising the following steps:

[0009] (a) manufacturing a semi-finished substrate, wherein the semi-finished substrate comprises a first medium layer and a first circuit layer on the upper surface of the first medium layer;

[0010] (b) preparing an embedded component layer, wherein the embedded component layer comprises a packaging layer and a component embedded in the packaging layer, and the back surface of the component is flush with the lower surface of the packaging layer;

[0011] (c) compressing the semi-finished substrate and the embedded component layer through an adhesive layer.

[0012] (d) forming an interlayer conductive copper pillar layer penetrating through the encapsulation layer and the adhesive layer in the height direction within the encapsulation layer and the adhesive layer, forming a conductive via in the encapsulation layer in communication with the terminal of the device, forming an outer circuit layer on the upper surface of the encapsulation layer, the outer circuit layer being conductively connected with the first circuit layer through the interlayer conductive copper pillar layer, and the outer circuit layer being in communication with the terminal of the device through the conductive via.

[0013] In some embodiments, step (b) comprises:

[0014] (b1) preparing a temporary carrier plate, the temporary carrier plate comprising a copper-clad plate with double-layer copper foil on at least one side, wherein the copper-clad plate comprises a core layer, a first copper layer on the surface of the core layer, and a second copper layer on the first copper layer, wherein the first copper layer and the second copper layer are attached together by physical compression;

[0015] (b2) applying a die adhesive layer on the upper surface of the second copper layer;

[0016] (b3) attaching the back surface of the device on the die adhesive layer;

[0017] (b4) forming an encapsulation layer embedding the device on the die adhesive layer, and forming a copper foil layer on the upper surface of the encapsulation layer;

[0018] (b5) physically separating the first copper layer and the second copper layer to remove the core layer and the first copper layer;

[0019] (b6) etching the second copper layer and the copper foil layer.

[0020] In some embodiments, step (a) further comprises: forming a first rivet hole penetrating through the semi-finished substrate in the height direction.

[0021] In some embodiments, step (b5) further comprises: after removing the core layer and the first copper layer, forming a second rivet hole penetrating through the second copper layer, the encapsulation layer, and the copper foil layer in the height direction, and the first rivet hole and the second rivet hole can longitudinally coincide.

[0022] In some embodiments, step (c) further comprises: riveting the compressed semi-finished substrate and the embedded device layer by a rivet through the first rivet hole and the second rivet hole, and curing the riveted semi-finished substrate and the embedded device layer, and then removing the rivet.

[0023] In some embodiments, the core layer is selected from PP, metal, or glass.

[0024] In some embodiments, the thickness of the copper foil layer and the thickness of the second copper layer are the same or similar.

[0025] In some embodiments, step (b2) comprises applying a die attach layer on the upper surface of the temporary carrier by means of dispensing or taping a DAF.

[0026] In some embodiments, the encapsulation layer is selected from the group consisting of one or more of PP, ABF and PID.

[0027] In some embodiments, the adhesive layer is selected from the group consisting of PP, ABF, PID or pure glue die attach film.

[0028] In some embodiments, step (d) comprises:

[0029] (d1) forming a through blind via within the encapsulation layer and within the adhesive layer, the through blind via exposing a terminal of the first circuit layer or the device;

[0030] (d2) forming a first metal seed layer on the bottom and sidewall of the through blind via and on the upper surface of the encapsulation layer;

[0031] (d3) electroplating the through blind via to form an interlayer through copper pillar layer penetrating through the encapsulation layer and the adhesive layer in the height direction, and a through hole in communication with the terminal of the device, and electroplating to form an outer copper layer on the upper surface of the encapsulation layer;

[0032] (d4) applying a first photoresist layer on the outer copper layer, exposing and developing the first photoresist layer to form a first feature pattern;

[0033] (d5) etching the exposed outer copper layer and the first metal seed layer in the first feature pattern;

[0034] (d6) removing the first photoresist layer.

[0035] For the same purpose, the second aspect of the present application provides a method for manufacturing an embedded device package substrate, comprising the following steps:

[0036] (a) manufacturing a semi-finished product substrate, the semi-finished product substrate comprising a first dielectric layer and a first circuit layer on the upper surface of the first dielectric layer;

[0037] (b) preparing an embedded device layer, the embedded device layer comprising an encapsulation layer and a device embedded in the encapsulation layer, the terminal surface of the device being flush with the first surface of the encapsulation layer;

[0038] (c) laminating the semi-finished product substrate and the embedded device layer through an adhesive layer, wherein the second surface of the encapsulation layer is attached to the adhesive layer;

[0039] (d) forming an interlayer conductive copper pillar layer penetrating through the embedded device layer and the adhesive layer in the height direction within the encapsulation layer, forming an outer circuit layer on the upper surface of the encapsulation layer, the outer circuit layer being conductively connected with the first circuit layer through the interlayer conductive copper pillar layer, and the outer circuit layer being in communication with the terminals of the device.

[0040] In some embodiments, step (b) comprises:

[0041] (b1) preparing a sacrificial substrate;

[0042] (b2) laminating a thermalized release adhesive layer on the upper surface of the sacrificial substrate;

[0043] (b3) attaching the terminal surface of the device on the thermalized release adhesive layer;

[0044] (b4) forming an encapsulation layer embedding the device on the thermalized release adhesive layer, and the terminal surface of the device and the first surface of the encapsulation layer being flush;

[0045] (b5) separating the thermalized release adhesive layer and removing the sacrificial substrate.

[0046] In some embodiments, step (a) further comprises: forming a first rivet hole penetrating through the semi-finished substrate in the height direction.

[0047] In some embodiments, step (b) further comprises:

[0048] (b6) after step (b5), forming a second rivet hole penetrating through the encapsulation layer in the height direction, and the first rivet hole and the second rivet hole being longitudinally coincident.

[0049] In some embodiments, step (c) further comprises: riveting the laminated semi-finished substrate and the embedded device layer by a rivet penetrating through the first rivet hole and the second rivet hole, and curing the riveted semi-finished substrate and the embedded device layer, and then removing the rivet.

[0050] In some embodiments, the sacrificial substrate is selected from metal or glass.

[0051] In some embodiments, step (b5) comprises separating the thermalized release adhesive layer by heating.

[0052] In some embodiments, the encapsulation layer is selected from a combination of one or more of PP, ABF, and PID.

[0053] In some embodiments, the adhesive layer is selected from PP, ABF, PID, or pure adhesive bonding sheet.

[0054] In some embodiments, the adhesive layer is selected from PP, ABF or PID.

[0055] As can be seen from the above, the manufacturing method of the embedded component packaging substrate provided by the present application, when manufacturing the packaging substrate, the semi-finished substrate and the embedded component layer are prepared respectively, and then the semi-finished substrate and the embedded component layer are laminated through the adhesive layer. The symmetric manufacturing of the semi-finished substrate and the embedded component layer can avoid the warping of the substrate due to the stress imbalance when the curing resin medium is cured. Moreover, the circuit build-up and the component packaging are performed respectively, which avoids the loss of the components caused by the circuit build-up and reduces the loss of the component yield. BRIEF DESCRIPTION OF DRAWINGS

[0056] For a better understanding of the present application and to show how the same can be carried into effect, there will now be described by way of example, purely by way of non-restrictive example, and with reference to the accompanying drawings.

[0057] With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present application only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the application as used in its

[0058] Figures 1(a)-1(u) Fig. 1 shows a cross-sectional schematic view of the intermediate structure of each step of the manufacturing method of the embedded component packaging substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] With reference to Figures 1(a)-1(u) Fig. 1 shows a cross-sectional schematic view of the intermediate structure of each step of the manufacturing method of the embedded component packaging substrate according to an embodiment of the present application.

[0060] The manufacturing method comprises the following steps: manufacturing a semi-finished substrate and forming a first rivet hole penetrating the semi-finished substrate in the height direction - step a, as shown in Fig. 1(a). The semi-finished substrate comprises a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103 arranged in sequence in the longitudinal direction. The first rivet hole penetrates the first dielectric layer 101, the second dielectric layer 102 and the third dielectric layer 103 in the height direction, which can be drilled by a CCD drilling target machine or an X-Ray drilling target machine.

[0061] It should be noted that since the rivet hole itself is not part of the product, it only plays a role in fixing and positioning the substrate during the processing, and the rivet hole is arranged on the waste edge, so it is not shown in the drawings.

[0062] The first dielectric layer 101 includes a second circuit layer 1011 located in the lower surface of the first dielectric layer 101, a first conductive copper pillar layer 1012 located on the second circuit layer 1011, and a first circuit layer 1013 provided on the upper surface of the first dielectric layer 101, wherein the first circuit layer 1013 and the second circuit layer 1011 are conductively connected through the first conductive copper pillar layer 1012.

[0063] The second dielectric layer 102 includes a second conductive copper pillar layer 1022 penetrating the second dielectric layer 102 in the height direction.

[0064] The third dielectric layer 103 includes a third circuit layer 1031 located in the upper surface of the third dielectric layer 103, a third conductive copper pillar layer 1032 located on the third circuit layer 1031, and a fourth circuit layer 1033 provided on the lower surface of the third dielectric layer 103, wherein the second circuit layer 1011 and the third circuit layer 1031 are conductively connected through the second conductive copper pillar layer 1022, and the third circuit layer 1031 and the fourth circuit layer 1033 are conductively connected through the third conductive copper pillar layer 1032.

[0065] Generally, the end of the conductive copper pillar layer can be higher than the dielectric layer or flush with the dielectric layer.

[0066] The substrate mentioned in the present embodiment can be a coreless semi-finished substrate or a core semi-finished substrate, which can be selected as needed. The number of dielectric layers included in the semi-finished substrate is not limited to three layers, and the subsequent process is only demonstrated with a semi-finished substrate including three dielectric layers.

[0067] Optionally, the semi-finished substrate can be made by tenting process, MSAP process or SAP process, and the multi-layer dielectric layer can be prepared by Coreless technology or conventional CCL lamination technology, and the interlayer conductive mode can be copper pillar conductive, laser hole conductive or mechanical hole conductive, etc., which is not limited.

[0068] Next, a temporary support plate is prepared - step b, as shown in FIG. 1(b).

[0069] Optionally, the temporary support plate in the present embodiment can be a copper-clad plate with at least one double-layer copper foil, wherein the copper-clad plate includes a core layer 1041, a first copper layer 1042 on the surface of the core layer 1041, and a second copper layer 1043 on the first copper layer 1042, wherein the first copper layer 1042 and the second copper layer 1043 are attached together by physical pressing, the copper-clad plate can be removed by simply separating the first copper layer 1042 and the second copper layer 1043, and the second copper layer 1043 can be removed by etching. Preferably, the thickness of the first copper layer 1042 is 18 μm, and the thickness of the second copper layer 1043 is 3 μm.

[0070] Optionally, the core layer 1041 can be selected from PP, metal or glass. Preferably, the core layer 1041 is a PP dielectric layer with a thickness greater than or equal to 200 μm. Thick PP dielectric layer, metal and glass can resist stress warpage caused by subsequent encapsulation layer curing process.

[0071] Then, a die attach layer 1044 is applied on the upper surface of the second copper layer 1043—step c, as shown in Fig. 1(c). Typically, the die attach layer 1044 has a thickness of 10-40 μm, and can be applied on the upper surface of the second copper layer 1043 by dispensing or by attaching a DAF.

[0072] Next, the back surface of the device 105 is attached on the die attach layer 1044—step d, as shown in Fig. 1(d). Typically, the back surface of the device 105 can be attached on the die attach layer 1044 using a pick-and-place machine.

[0073] Then, an encapsulation layer 106 embedding the device 105 is formed on the die attach layer 1044, and a copper foil layer 1061 is formed on the upper surface of the encapsulation layer 106—step e, as shown in Fig. 1(e).

[0074] Typically, the encapsulation layer 106 can be selected from one or more combinations of PP (prepreg), ABF and PID (photoimageable dielectric).

[0075] The thickness of the copper foil layer 1061 is the same as or similar to the thickness of the second copper layer 1043, and preferably the thickness of the copper foil layer 1061 is 3 μm. By forming the copper foil layer 1061 on the upper surface of the encapsulation layer 106, a symmetrical embedded device layer structure can be obtained when the first copper layer 1042 and the second copper layer 1043 are physically separated to remove the temporary carrier, and the stress caused by the resin shrinkage of the encapsulation layer 106 is balanced. If the copper foil layer 1061 is not formed on the upper surface of the encapsulation layer 106, the encapsulation layer 106 will be severely rolled after the first copper layer 1042 and the second copper layer 1043 are physically separated, which is not conducive to subsequent processing.

[0076] Typically, after the encapsulation layer 106 and the copper foil layer 1061 are formed, they can be pressed and cured on a press.

[0077] Next, the core layer 1041 and the first copper layer 1042 are removed by physically separating the first copper layer 1042 and the second copper layer 1043, and a second rivet hole is formed through the second copper layer 1043, the encapsulation layer 106 and the copper foil layer 1061 in the height direction, and the first rivet hole and the second rivet hole can be vertically coincident—step f, as shown in Fig. 1(f).

[0078] It can be understood that after the first copper layer 1042 and the second copper layer 1043 are physically separated, the upper and lower surfaces of the embedded device layer are respectively attached with the copper foil layer 1061 and the second copper layer 1043 having the same thickness, the structure is symmetrical, the stress is balanced, and there is no obvious curling.

[0079] Generally, the second rivet hole can be drilled by using a CCD drill target machine or an X-Ray drill target machine, and the first rivet hole and the second rivet hole can be longitudinally coincided, which is beneficial to the riveting alignment of the semi-finished substrate and the embedded device layer in subsequent processes.

[0080] Then, the second copper layer 1043 and the copper foil layer 1061 are etched to form the embedded device layer—step g, as shown in FIG. 1(g).

[0081] Subsequently, the semi-finished substrate and the embedded device layer are laminated through the adhesive layer 107, and a rivet is passed through the first rivet hole and the second rivet hole to rivet and fix the laminated semi-finished substrate and embedded device layer, and then the riveted and fixed semi-finished substrate and embedded device layer are cured, and the rivet is removed—step h, as shown in FIG. 1(h).

[0082] Optionally, the adhesive layer 107 can be selected from PP, ABF, PID or pure glue bonding sheet. Generally, the embedded device layer and the semi-finished substrate can be accurately riveted and aligned, fixed according to the riveting alignment hole, and the embedded device layer and the semi-finished substrate after riveting and alignment can be laminated and cured on a laminator.

[0083] Then, a through blind hole 1062 exposing the terminal of the first circuit layer 1013 or the device 105 is formed in the packaging layer 106 and the adhesive layer 107—step i, as shown in FIG. 1(i).

[0084] Generally, the through blind hole can be formed by laser.

[0085] Subsequently, a first metal seed layer 1063 is formed on the bottom and sidewall of the through blind hole 1062 and the upper surface of the packaging layer 106—step j, as shown in FIG. 1(j).

[0086] Generally, the metal seed layer can be formed by electroless plating or sputtering, and the metal seed layer can include titanium, copper, titanium-tungsten alloy or a combination thereof; preferably, the metal seed layer is made of sputtered titanium and copper.

[0087] Then, the through blind hole 1062 is electroplated to form an interlayer through copper pillar layer 1064 penetrating the packaging layer 106 and the adhesive layer 107 in the height direction, a through hole 1065 in communication with the terminal of the device 105, and an outer copper layer 1066 formed on the upper surface of the packaging layer 106—step k, as shown in FIG. 1(k).

[0088] Generally, the conductive copper pillar layer can include at least one conductive copper pillar, and preferably the conductive copper pillar layer includes conductive copper pillars of different sizes; the conductive copper pillars can have the same or different sizes in the vertical direction.

[0089] Next, a first photoresist layer is applied on the outer copper layer 1066, the first photoresist layer is exposed and developed to form a first feature pattern, and the exposed outer copper layer 1066 and the first metal seed layer are etched to form an outer circuit layer 1067, the outer circuit layer 1067 is connected to the first circuit layer 1013 through the interlayer conductive copper pillar layer 1064, and the outer circuit layer 1067 is connected to the terminals of the device 105 through the conductive hole 1065; the first photoresist layer is removed to form the packaging substrate 100—step l, as shown in FIG. 1(l).

[0090] After step a, the sacrificial substrate 104 is prepared, and the thermal release adhesive layer 1045 is laminated on the upper surface of the sacrificial substrate 104—step m, as shown in FIG. 1(m).

[0091] Optionally, the sacrificial substrate 104 can be a glass substrate or a metal substrate, such as a copper plate, an aluminum plate, a stainless steel plate, or an aluminum alloy plate, etc.

[0092] Next, the terminal surface of the device 105 is attached to the thermal release adhesive layer 1045—step n, as shown in FIG. 1(n).

[0093] Then, the packaging layer 106 embedding the device 105 is formed on the thermal release adhesive layer 1045, and the terminal surface of the device 105 and the first surface of the packaging layer 106 are flush—step o, as shown in FIG. 1(o).

[0094] Generally, the packaging layer 106 can be selected from one or a combination of PP, ABF, and PID.

[0095] After the packaging layer 106 is formed, the packaging layer 106 can be heated and cured. Then, a CCD drill target machine or an X-Ray drill target machine is used to drill a riveting alignment hole in the subsequent process, so as to facilitate the alignment of the semi-finished substrate and the embedded device layer.

[0096] When the packaging layer 106 is heated and cured, the thermal release adhesive layer 1045 will also become low-adhesion due to heating, and the peeling between the thermal release adhesive layer 1045 and the packaging layer 106 can be easily achieved.

[0097] Next, the thermal release adhesive layer 1045 is separated and the sacrificial substrate 104 is removed, and then a second rivet hole is formed through the semi-finished substrate in the height direction, and the first rivet hole and the second rivet hole can be vertically overlapped to obtain an embedded device layer—step p, as shown in FIG. 1(p).

[0098] Generally, the second rivet hole can be drilled by using a CCD drill or an X-Ray drill, and the first rivet hole and the second rivet hole can be longitudinally coincided, which is beneficial for riveting alignment of the semi-finished substrate and the embedded device layer in subsequent processes.

[0099] Then, the semi-finished substrate and the embedded device layer are laminated by the adhesive layer 107, and a rivet is passed through the first rivet hole and the second rivet hole to rivet and fix the laminated semi-finished substrate and embedded device layer, and then the rivet-fixed semi-finished substrate and embedded device layer are cured, and the rivet is removed, wherein the second surface of the packaging layer 106 is attached to the adhesive layer 107—step q, as shown in FIG. 1(q).

[0100] Optionally, the adhesive layer 107 can be selected from PP, ABF, PID or pure glue bonding sheet. Generally, the embedded device layer and the semi-finished substrate can be accurately riveted and aligned, fixed according to the riveting alignment hole, and the riveting and aligned embedded device layer and semi-finished substrate can be laminated and cured on a laminator.

[0101] Next, a through blind hole 1062 exposing the first circuit layer 1013 is formed in the packaging layer 106 and the adhesive layer 107—step r, as shown in FIG. 1(r).

[0102] Then, a first metal seed layer 1063 is formed on the bottom and sidewall of the through blind hole 1062 and the upper surface of the packaging layer 106—step s, as shown in FIG. 1(s).

[0103] Next, the through blind hole 1062 is electroplated to form an interlayer through copper pillar layer 1064 penetrating the packaging layer 106 and the adhesive layer 107 in the height direction, and an outer copper layer 1066 is electroplated on the upper surface of the packaging layer 106—step t, as shown in FIG. 1(t).

[0104] Then, a first photoresist layer is applied on the outer copper layer 1066, the first photoresist layer is exposed and developed to form a first feature pattern, the exposed outer copper layer 1066 and the first metal seed layer are etched in the first feature pattern to form an outer circuit layer 1067, the outer circuit layer 1067 is connected to the first circuit layer 1013 through the interlayer through copper pillar layer 1064, and the outer circuit layer 1067 is in communication with the terminals of the device 105; the first photoresist layer is removed to form a packaging substrate 200—step u, as shown in FIG. 1(u).

[0105] Those skilled in the art will appreciate that the present application is not limited to what is specifically illustrated and described herein. Rather, the scope of the present application includes both combinations and sub-combinations of the various features and modifications as set forth above, as well as variations and modifications thereof that can be apparent to those skilled in the art upon reading the foregoing description.

[0106] In the claims, the term "include" and its variants are meant to be construed to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises elements not recited in the claim is nonetheless within the scope of such claim.

Claims

1. A method for fabricating a substrate for embedded components, comprising the following steps: (a) Fabricating a semi-finished substrate, the semi-finished substrate comprising a first dielectric layer and a first circuit layer located on the upper surface of the first dielectric layer; (b) Fabricating an embedded device layer, the embedded device layer comprising an encapsulation layer and a device embedded in the encapsulation layer, the back side of the device being flush with the lower surface of the encapsulation layer; (c) The semi-finished substrate and the embedded device are laminated together using an adhesive layer; (d) An interlayer conductive copper pillar layer is formed in the encapsulation layer and the adhesive layer, penetrating the encapsulation layer and the adhesive layer in the height direction. A via is formed in the encapsulation layer that communicates with the terminals of the device. An external circuit layer is formed on the upper surface of the encapsulation layer. The external circuit layer is conductively connected to the first circuit layer through the interlayer conductive copper pillar layer. The external circuit layer is connected to the terminals of the device through the via.

2. The manufacturing method according to claim 1, wherein step (b) comprises: (b1) Prepare a temporary support board, the temporary support board comprising a copper-clad laminate with at least one side covered with double copper foil, wherein the copper-clad laminate comprises a core layer, a first copper layer on the surface of the core layer and a second copper layer on the first copper layer, wherein the first copper layer and the second copper layer are attached together by physical pressing. (b2) Apply a chip bonding layer to the upper surface of the second copper layer; (b3) Attach the back side of the device to the chip adhesive layer; (b4) An encapsulation layer for embedding the device is formed on the chip bonding layer, and a copper foil layer is formed on the upper surface of the encapsulation layer; (b5) Physically separate the first copper layer and the second copper layer to remove the core layer and the first copper layer; (b6) Etch the second copper layer and the copper foil layer.

3. The manufacturing method according to claim 2, wherein step (a) further includes: A first rivet hole is formed that penetrates the semi-finished substrate along the height direction.

4. The manufacturing method according to claim 3, wherein step (b5) further includes: After removing the core layer and the first copper layer, a second rivet hole is formed that penetrates the second copper layer, the encapsulation layer and the copper foil layer along the height direction, and the first rivet hole and the second rivet hole can overlap longitudinally.

5. The manufacturing method according to claim 4, wherein step (c) further comprises: The semi-finished substrate and the embedded device layer are riveted and fixed by passing rivets through the first rivet hole and the second rivet hole, and the riveted and fixed semi-finished substrate and the embedded device layer are cured, and then the rivets are removed.

6. The manufacturing method according to claim 2, wherein the core layer is selected from PP, metal or glass.

7. The manufacturing method according to claim 2, wherein the thickness of the copper foil layer is the same as or similar to the thickness of the second copper layer.

8. The manufacturing method according to claim 2, wherein step (b2) includes applying a chip bonding layer to the upper surface of the temporary carrier board by dispensing glue or applying DAF.

9. The manufacturing method according to claim 2, wherein the encapsulation layer is selected from one or more combinations of PP, ABF and PID.

10. The manufacturing method according to claim 1, wherein the adhesive layer is selected from PP, ABF, PID or pure adhesive sheet.

11. The manufacturing method according to claim 1, wherein step (d) comprises: (d1) A through-hole is formed within the encapsulation layer and the adhesive layer to expose the terminals of the first circuit layer or the device; (d2) A first metal seed layer is formed on the bottom and sidewalls of the through-hole and on the upper surface of the encapsulation layer; (d3) Electroplating the through-holes to form an interlayer conductive copper pillar layer that penetrates the encapsulation layer and the adhesive layer along the height direction, and a through-hole communicating with the terminals of the device, and electroplating an outer copper layer on the upper surface of the encapsulation layer; (d4) A first photoresist layer is applied to the outer copper layer, and the first photoresist layer is exposed and developed to form a first feature pattern; (d5) Etch the exposed outer copper layer and the first metal seed layer in the first feature pattern; (d6) Remove the first photoresist layer.

12. A method for fabricating a substrate for embedded components, comprising the following steps: (a) Fabricating a semi-finished substrate, the semi-finished substrate comprising a first dielectric layer and a first circuit layer located on the upper surface of the first dielectric layer; (b) Fabricating an embedded device layer, the embedded device layer comprising an encapsulation layer and a device embedded in the encapsulation layer, wherein the terminal facet of the device is flush with a first surface of the encapsulation layer; (c) The semi-finished substrate and the embedded device are laminated together by an adhesive layer, wherein the second surface of the encapsulation layer is bonded to the adhesive layer; (d) An interlayer conductive copper pillar layer is formed within the encapsulation layer and the adhesive layer, penetrating the embedded device layer and the adhesive layer in the height direction. An external circuit layer is formed on the upper surface of the encapsulation layer. The external circuit layer is conductively connected to the first circuit layer through the interlayer conductive copper pillar layer. The external circuit layer is connected to the terminals of the device.

13. The manufacturing method according to claim 12, wherein step (b) comprises: (b1) Prepare the sacrificial substrate; (b2) A thermally cured release adhesive layer is pressed onto the upper surface of the sacrificial substrate; (b3) The terminal surface of the device is attached to the heat-cured release adhesive layer; (b4) An encapsulation layer for embedding the device is formed on the thermally released adhesive layer, and the terminal surface of the device is flush with the first surface of the encapsulation layer; (b5) Separate the thermal release adhesive layer and remove the sacrificial substrate.

14. The manufacturing method according to claim 13, wherein step (a) further comprises: A first rivet hole is formed that penetrates the semi-finished substrate along the height direction.

15. The manufacturing method according to claim 14, wherein step (b) further comprises: (b6) After step (b5), a second rivet hole is formed that penetrates the encapsulation layer along the height direction, and the first rivet hole and the second rivet hole can overlap longitudinally.

16. The manufacturing method according to claim 15, wherein step (c) further comprises: The semi-finished substrate and the embedded device layer are riveted and fixed by passing rivets through the first rivet hole and the second rivet hole, and the riveted and fixed semi-finished substrate and the embedded device layer are cured, and then the rivets are removed.

17. The manufacturing method according to claim 13, wherein the sacrificial substrate is selected from metal or glass.

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