A GaO-based x Fabrication method of PMOS / GaN-NMOS CMOS inverter

Abstract

This invention discloses a method based on GaO x Fabrication method of PMOS / GaN-NMOS CMOS inverter: A carbon-doped or silicon-doped GaN buffer layer is grown on a single-crystal Si substrate or GaN substrate. Photoresist is used to block one side of the carbon-doped GaN buffer layer, and Mg-doped GaN is epitaxially grown on the other side to form an n-MOS channel layer. The photoresist on one side is removed, blocking the surface of the n-MOS channel layer, and GaO is epitaxially grown on the surface where the photoresist has been removed. x A p-MOS channel layer is formed; vertical photolithography is performed at the critical position between the n-MOS channel layer and the p-MOS channel layer, and a high thermal conductivity material is grown in the formed isolation region to form a barrier layer; using photoresist barrier, Si is implanted at both ends of the n-MOS channel layer surface to form an n region, and Mg is implanted at both ends of the p-MOS channel layer surface to form a p region; partial insulating layers are etched at both ends of the n-MOS channel layer and the p-MOS channel layer, and in the barrier layer region, and metal films are deposited, stripped, and annealed to obtain the source and drain, respectively; the insulating layers in the n-MOS channel layer and p-MOS channel layer regions are stripped and annealed to form the gate.

Description

Technical Field

[0001] This invention relates to the field of materials technology, and in particular to a method for fabricating a CMOS inverter based on GaOx-PMOS / GaN-NMOS. Background Technology

[0002] In recent years, GaN and Ga2O3 have been identified as among the most important semiconductors for power applications. Both possess relatively large band gaps and breakdown electric fields, enabling high-voltage, high-current, and stable device operation. Inverters with GaN / AlGaN heterojunctions have attracted significant attention and widespread application due to their excellent performance. The main characteristics of these inverters are: high switching speed, low parasitic inductance, and suitability for high-frequency and high-voltage applications.

[0003] However, existing inverters have high power consumption, complex manufacturing processes and circuits, poor heat dissipation, and the maximum on-current density is limited to tens of mA / mm. The devices are also relatively large, and the manufacturing process usually requires plasma etching, which has a significant impact on device performance. Summary of the Invention

[0004] This invention provides a GaO-based x The fabrication method of PMOS / GaN-NMOS CMOS inverters includes:

[0005] A carbon-doped GaN buffer layer is grown on a single-crystal Si substrate. A region on one side of the carbon-doped GaN buffer layer is blocked using photoresist, and an n-MOS channel layer is epitaxially grown on the other side using Mg-doped GaN. The photoresist on one side is then removed to block the surface of the n-MOS channel layer, and GaO is epitaxially grown on the surface where the photoresist has been removed. x Forming a p-MOS channel layer;

[0006] Vertical photolithography is performed at the critical position between the n-MOS channel layer and the p-MOS channel layer, and diamond is grown in the formed isolation region to form a barrier layer;

[0007] Using photoresist blocking, Si is ion-implanted at both ends of the n-MOS channel layer surface to form an n region, and Mg is ion-implanted at both ends of the p-MOS channel layer surface to form a p region;

[0008] A gate dielectric layer is deposited on the device surface, stripped, and annealed. Part of the insulating layer is etched in the end regions of the n-MOS channel layer and p-MOS channel layer, and a metal film is deposited. The source is obtained by stripping and annealing. Part of the insulating layer is etched in the barrier layer region, a metal film is deposited, stripped, and annealed to obtain the drain. The gate is formed by stripping and annealing the insulating layer in the n-MOS channel layer and p-MOS channel layer regions.

[0009] Furthermore, the thickness of the carbon- or silicon-doped GaN buffer layer is 3-5 μm.

[0010] Furthermore, the concentration of carbon or silicon doping is 1–3 × 10⁻⁶. 18 cm -3 .

[0011] Furthermore, the thickness of the n-MOS channel layer is 150-250 nm.

[0012] Furthermore, the thickness of the p-MOS channel layer is 150-250 nm.

[0013] Furthermore, the length of the high thermal conductivity material is 4–10 μm.

[0014] Furthermore, Al2O3 is used as the gate dielectric layer, with a thickness of 20–30 nm.

[0015] Furthermore, the Al2O3 is silicon-doped, with a silicon doping concentration of 2 × 10⁻⁶. 18 cm -3 .

[0016] Furthermore, the drain and source metal films are made of Ti, Al, Ni, or Au, and are annealed at 650°C in an N2 environment.

[0017] Furthermore, the gate metal film uses Ni or Au.

[0018] This invention proposes a method based on GaO x -PMOS / GaN-NMOS CMOS inverter, due to GaO x The high bandgap and support for higher frequencies of GaO can improve the performance of inverters, thus making them better suited for power devices in high-voltage, high-temperature, and high-power applications; furthermore, the structure is simpler, and GaO... x Because the self-compensation exhibits an n-type shape, a doping step is eliminated; and high thermal conductivity materials are used for isolation, resulting in good heat dissipation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A GaO-based embodiment of the present invention is provided. x - Fabrication method of PMOS / GaN-NMOS CMOS inverter;

[0021] Figure 2 Another GaO-based embodiment of the present invention is provided. x - Fabrication method of PMOS / GaN-NMOS CMOS inverter;

[0022] Figure 3 Another GaO-based embodiment provided by the present invention x - Fabrication method of PMOS / GaN-NMOS CMOS inverter;

[0023] Figure 4 The GaO-based materials prepared for embodiments of the present invention x -Schematic diagram of a PMOS / GaN-NMOS CMOS inverter;

[0024] Figure 5 The GaO-based materials prepared for embodiments of the present invention x -Circuit diagram of a PMOS / GaN-NMOS CMOS inverter. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0026] One embodiment of the present invention provides a GaO-based x The fabrication method of a PMOS / GaN-NMOS CMOS inverter includes the following steps:

[0027] Step 1: Grow a carbon-doped or silicon-doped GaN buffer layer on a single-crystal Si or GaN substrate. Use photoresist to block the area on one side of the carbon-doped GaN buffer layer, and epitaxially grow Mg-doped GaN on the other side to form an n-MOS channel layer. Remove the photoresist on one side to block the surface of the n-MOS channel layer, and epitaxially grow GaO on the surface where the photoresist has been removed. x Forming a p-MOS channel layer;

[0028] In this embodiment, as Figure 1 As shown, a 3-5 μm carbon-doped or silicon-doped GaN buffer layer is grown on a Si substrate by organic chemical vapor deposition (MOCVD). Preferably, a 4 μm carbon-doped or silicon-doped GaN buffer layer is grown on the Si substrate. Using photoresist as a barrier, a 150-250 nm thick, preferably 200 nm thick, Mg-doped GaN layer is grown on one side of the buffer layer as an n-MOS channel layer by MOCVD. After removing the photoresist, a 150-250 nm thick, preferably 200 nm thick GaO layer is grown on the other side. x As a p-MOS channel layer.

[0029] Preferably, the concentration of carbon or silicon doping is 1 to 3 × 10⁻⁶. 18 cm -3 Preferably 2×10 18 cm -3 The thickness of the substrate is 1 to 1.5 mm, preferably 1.15 mm.

[0030] Step 2: Perform vertical photolithography at the critical position between the n-MOS channel layer and the p-MOS channel layer, and grow a high thermal conductivity material in the formed isolation region to form a barrier layer;

[0031] Embodiments of the present invention, such as Figure 2 As shown, a highly thermally conductive material, such as diamond or aluminum nitride ceramic, is vertically grown in a buffer layer of the intermediate isolation region using metal-organic chemical vapor deposition (MOCVD). The length of the diamond or aluminum nitride ceramic is 4–10 μm, preferably 5 μm.

[0032] Step 3: Using photoresist blocking, Si is implanted at both ends of the n-MOS channel layer to form the n-region, and Mg is implanted at both ends of the p-MOS channel layer to form the p-region. A gate dielectric layer is deposited on the device surface, stripped, and annealed. Part of the insulating layer is etched at both ends of the n-MOS and p-MOS channel layers, and a metal film is deposited. The source is obtained by stripping and annealing. Part of the insulating layer is etched in the blocking layer region, and a metal film is deposited. The drain is obtained by stripping and annealing. The gate is formed by stripping and annealing the insulating layer in the n-MOS and p-MOS channel layer regions.

[0033] Embodiments of the present invention, such as Figure 3 As shown, in the fabrication of the drain and source electrodes: metal films (such as Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm)) are deposited using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation. After forming the electrodes using a lift-off process, they are annealed at 650℃ in an N2 environment. In the fabrication of the gate electrode, methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation are used to deposit metal films on GaO. x and Mg-GaO x A metal film (such as Ni (25nm) / Au (25nm)) is deposited on the layer, and after forming electrodes using a lift-off process, it is annealed at 650°C in an N2 environment.

[0034] In this embodiment of the invention, Al2O3 is used as the gate dielectric layer with a thickness of 20–30 nm, and silicon is used as the dopant with a doping concentration of 1–3 × 10⁻⁶. 18 cm -3 Preferably 2×10 18 cm -3 .

[0035] like Figure 4 To prepare the GaO-based x -A schematic diagram of the structure of a GaN CMOS inverter, where 1 is a silicon single crystal substrate, 2 is a GaN buffer layer, 3 is an n-MOS channel layer, 4 and 8 are sources, 5 and 7 are gates, 6 is a drain, 9 is an Al2O3 gate dielectric layer, 10 is a diamond layer, and 11 is a p-MOS channel layer. Figure 5 As shown, this is a GaO-based material prepared according to an embodiment of the present invention. x -Circuit diagram of a PMOS / GaN-NMOS CMOS inverter.

[0036] This invention proposes a CMOS inverter based on GaOx-PMOS / GaN-NMOS, because GaO... x The high bandgap and support for higher frequencies of GaO can improve the performance of inverters, thus making them better suited for power devices in high-voltage, high-temperature, and high-power applications; furthermore, the structure is simpler, and GaO... x Because the self-compensation exhibits an n-type shape, a doping step is eliminated; and high thermal conductivity materials are used for isolation, resulting in good heat dissipation.

[0037] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0038] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A GaO-based x A method for fabricating a PMOS / GaN-NMOS CMOS inverter, characterized in that... include: A carbon-doped GaN buffer layer is grown on a single-crystal Si or GaN substrate. A region on one side of the carbon-doped GaN buffer layer is blocked using photoresist, and Mg-doped GaN is epitaxially grown on the other side to form an n-MOS channel layer. The photoresist on one side is removed, blocking the surface of the n-MOS channel layer, and GaO is epitaxially grown on the surface where the photoresist has been removed. x Forming a p-MOS channel layer; Vertical photolithography is performed at the critical position between the n-MOS channel layer and the p-MOS channel layer, and a high thermal conductivity material is grown in the formed isolation region to form a barrier layer; Using photoresist blocking, Si is ion-implanted at both ends of the n-MOS channel layer surface to form an n region, and Mg is ion-implanted at both ends of the p-MOS channel layer surface to form a p region; A gate dielectric layer is deposited on the device surface, stripped, and annealed. Part of the insulating layer is etched in the end regions of the n-MOS channel layer and p-MOS channel layer, and a metal film is deposited. The source is obtained by stripping and annealing. Part of the insulating layer is etched in the barrier layer region, a metal film is deposited, stripped, and annealed to obtain the drain. The gate is formed by stripping and annealing the insulating layer in the n-MOS channel layer and p-MOS channel layer regions.

2. The preparation method according to claim 1, characterized in that, The thickness of the carbon-doped or silicon-doped GaN buffer layer is 3-5 μm.

3. The preparation method according to claim 2, characterized in that, The concentration of carbon or silicon doping is 1~3×10⁻⁶. 18 cm -3 .

4. The preparation method according to claim 1, characterized in that, The thickness of the n-MOS channel layer is 150-250 nm.

5. The preparation method according to claim 1, characterized in that, The thickness of the p-MOS channel layer is 150-250 nm.

6. The preparation method according to claim 1, characterized in that, The length of materials with high thermal conductivity is 4~10 μm.

7. The preparation method according to claim 1, characterized in that, Al2O3 is used as the gate dielectric layer, and the thickness of Al2O3 is 20~30nm.

8. The preparation method according to claim 7, characterized in that, Al₂O₃ is silicon-doped, with a silicon doping concentration of 1~3×10⁻⁶. 18 cm -3 .

9. The preparation method according to claim 1, characterized in that, The drain and source metal films are made of Ti, Al, Ni or Au, and are annealed at 650°C in an N2 environment.

10. The preparation method according to claim 1, characterized in that, The gate metal film uses Ni or Au.

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