A GaO-based x Fabrication method of NMOS / GaN-PMOS CMOS inverter

Abstract

This invention discloses GaO x Fabrication method of NMOS / GaN-PMOS CMOS inverter: A carbon-doped GaN buffer layer is grown on a Si substrate. One side of the carbon-doped GaN buffer layer is blocked with photoresist, and Si-doped GaN is epitaxially grown on the other side to form a p-MOS channel layer. The photoresist on the other side is removed, blocking the surface of the p-MOS channel layer. A portion of the n-MOS channel layer is etched down to the carbon-doped GaN buffer layer. Using SiO2 as a growth mask, GaN is grown on the etched carbon-doped GaN buffer layer to form the p-MOS channel layer. Finally, the photoresist is removed from the surface... GaOx is epitaxially grown to form an n-MOS channel layer; vertical photolithography is performed at the critical position between the n-MOS and p-MOS channel layers, and diamond is grown in the formed isolation region to form a barrier layer; photoresist is used as a barrier, and Si and Mg are implanted on the surfaces of the n-MOS and p-MOS channel layers to form n and p regions, respectively; a metal film and a dielectric layer are deposited on the device surface, stripped, and annealed, and the drain and source are obtained at both ends of the n-MOS and p-MOS channel layers in the barrier layer region, and the gate is formed on the n-MOS and p-MOS channel layers.

Description

Technical Field

[0001] This invention relates to the field of materials technology, and in particular to a GaO-based... x Fabrication method of CMOS inverters of -NMOS / GaN-PMOS. Background Technology

[0002] In recent years, GaN and Ga2O3 have been identified as among the most important semiconductors for power applications. Both possess relatively large band gaps and breakdown electric fields, enabling high-voltage, high-current, and stable device operation. Inverters with GaN / AlGaN heterojunctions have attracted significant attention and widespread application due to their excellent performance. The main characteristics of these inverters are: high switching speed, low parasitic inductance, and suitability for high-frequency and high-voltage applications.

[0003] However, existing inverters have high power consumption, complex manufacturing processes and circuits, poor heat dissipation, and the maximum on-current density is limited to tens of mA / mm. The devices are also relatively large, and the manufacturing process usually requires plasma etching, which has a significant impact on device performance. Summary of the Invention

[0004] This invention provides a GaO-based x The fabrication method of -NMOS / GaN-PMOS CMOS inverters includes:

[0005] A carbon-doped GaN buffer layer is grown on a single-crystal Si substrate. A region on one side of the carbon-doped GaN buffer layer is blocked using photoresist. Si-doped GaN is epitaxially grown on the surface of the carbon-doped GaN buffer layer to form a p-MOS channel layer. A portion of the p-MOS channel layer surface is etched down to the carbon-doped GaN buffer layer. Using SiO2 as a growth mask, Mg-doped GaN is epitaxially grown on the exposed carbon-doped GaN buffer layer after etching. x Forming an n-MOS channel layer;

[0006] Using photoresist blocking, Si is ion-implanted at both ends of the n-MOS channel layer surface to form an n region, and Mg is ion-implanted at both ends of the p-MOS channel layer surface to form a p region;

[0007] Vertical photolithography is performed at the critical position between the n-MOS channel layer and the p-MOS channel layer, and diamond is grown in the formed isolation region to form a barrier layer;

[0008] A metal film and dielectric layer are deposited on the device surface, stripped, and annealed to obtain a set of adjacent drains and sources in the barrier layer region. Another set of drains and sources is obtained at both ends of the n-MOS channel layer and the p-MOS channel layer. A metal film and dielectric layer are deposited on the surface of the n-MOS channel layer and the p-MOS channel layer, stripped, and annealed to form the gate, wherein the gate is located between the drain and the source.

[0009] Furthermore, the thickness of the carbon-doped GaN buffer layer is 6-10 μm.

[0010] Furthermore, the carbon doping concentration is 1~3×10 18 cm -3 .

[0011] Furthermore, the thickness of the n-MOS channel layer is 150-250 nm.

[0012] Furthermore, the thickness of the p-MOS channel layer is 150-250 nm.

[0013] Furthermore, the length of the diamond is 4~10 μm.

[0014] Furthermore, Al2O3 is used as the gate dielectric layer, with a thickness of 20~30nm.

[0015] Furthermore, the Al2O3 is silicon-doped, with a silicon doping concentration of 2 × 10⁻⁶. 18 cm -3 .

[0016] Furthermore, the drain and source metal films are made of Ti, Al, Ni, or Au, and are annealed at 650°C in an N2 environment.

[0017] Furthermore, the gate metal film uses Ni or Au.

[0018] This invention proposes a method based on GaO x - NMOS / GaN-PMOS CMOS inverters can improve inverter performance due to the high bandgap and support for higher frequencies of GaO, thus making them better suited for power devices with high voltage, high temperature and high power requirements. In addition, the structure is simpler, and GaO exhibits an n-type shape due to self-compensation, eliminating the need for a doping step. Diamond isolation is used for good heat dissipation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A GaO-based embodiment of the present invention is provided. x Fabrication method of -NMOS / GaN-PMOS CMOS inverter;

[0021] Figure 2 Another GaO-based embodiment of the present invention is provided. x Fabrication method of -NMOS / GaN-PMOS CMOS inverter;

[0022] Figure 3 The GaO-based materials prepared for embodiments of the present invention x A schematic diagram of the structure of a CMOS inverter of type NMOS / GaN-PMOS. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0024] One embodiment of the present invention provides a GaO-based x The fabrication method of a CMOS inverter for NMOS / GaN-PMOS includes the following steps:

[0025] Step 1: Grow a carbon-doped GaN buffer layer on a single-crystal Si substrate. Use photoresist to block the area on one side of the carbon-doped GaN buffer layer, and epitaxially grow Si-doped GaN on the surface of the carbon-doped GaN buffer layer to form a p-MOS channel layer. Etch a portion of the surface of the p-MOS channel layer down to the carbon-doped GaN buffer layer. Use SiO2 as a growth mask to epitaxially grow Mg-doped GaO on the exposed carbon-doped GaN buffer layer after etching. x Forming an n-MOS channel layer;

[0026] In this embodiment, as Figure 1As shown, a 6-10 μm carbon-doped GaN buffer layer is grown on a Si substrate using organic chemical vapor deposition (MOCVD). Preferably, an 8 μm carbon-doped GaN buffer layer is grown on the Si substrate. By changing the temperature conditions, a 150-250 nm (preferably 200 nm) GaN layer is grown on the substrate above the buffer layer using MOCVD as the p-MOS channel layer; that is, Mg-GaN is doped on one side using photoresist as the p-MOS channel layer. After removing the photoresist, the structure is etched down to the GaN buffer layer using plasma etching. Then, using SiO2 as a growth mask, selective MOCVD is used to grow a 150-250 nm (preferably 200 nm) GaO layer as the n-MOS channel layer; that is, Si-GaO is doped on the other side. x As an n-MOS channel layer.

[0027] Preferably, the concentration of carbon or silicon doping is 1~3×10⁻⁶. 18 cm -3 Preferably 2×10 18 cm -3 The thickness of the substrate is 1~1.5mm, preferably 1.15mm.

[0028] Step 2: Perform vertical photolithography at the critical position between the n-MOS channel layer and the p-MOS channel layer, and grow diamond in the formed isolation region to form a barrier layer;

[0029] Embodiments of the present invention, such as Figure 2 As shown, diamond is vertically grown in a buffer layer in the intermediate isolation region using metal-organic chemical vapor deposition (MOCVD). The length of the diamond is 4~10 μm, preferably 5 μm.

[0030] Step 3: Using photoresist blocking, Si is ion-implanted at both ends of the n-MOS channel layer to form an n-region, and Mg is ion-implanted at both ends of the p-MOS channel layer to form a p-region. A metal film and dielectric layer are deposited on the device surface, stripped, and annealed to obtain a set of adjacent drains and sources in the blocking layer region. Another set of drains and sources is obtained at both ends of the n-MOS and p-MOS channel layers. A metal film and dielectric layer are deposited on the n-MOS and p-MOS channel layers, stripped, and annealed to form a gate, wherein the gate is located between the drain and source.

[0031] Embodiments of the present invention, such as Figure 2As shown, in the fabrication of the drain and source electrodes: metal films (such as Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm)) are deposited using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation. After forming the electrodes using a lift-off process, they are annealed at 650℃ in an N2 environment. In the fabrication of the gate electrode, methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation are used to deposit metal films on GaO. x and Mg-GaO x Metal films (such as Ni (25nm) / Au (25nm)) are deposited on the layer, and electrodes are formed using a stripping process and then annealed at 650°C in an N2 environment.

[0032] In this embodiment of the invention, Al2O3 is used as the gate dielectric layer with a thickness of 20-30 nm, and silicon is used as the dopant with a doping concentration of 1-3 × 10⁻⁶. 18 cm -3 Preferably 2×10 18 cm -3 .

[0033] like Figure 3 To prepare the GaO-based x - A schematic diagram of the structure of a GaN CMOS inverter, where 1 is a silicon single crystal substrate, 2 is an n-MOS channel layer, 3 and 6 are sources, 4 and 7 are gates, 5 and 8 are drains, 9 is a p-MOS channel layer, 10 is a GaN buffer layer, and 11 is a diamond layer.

[0034] This invention proposes a method based on GaO x - NMOS / GaN-PMOS CMOS inverters can improve inverter performance due to the high bandgap and support for higher frequencies of GaO, thus making them better suited for power devices with high voltage, high temperature and high power requirements. In addition, the structure is simpler, and GaO exhibits an n-type shape due to self-compensation, eliminating the need for a doping step. Diamond isolation is used for good heat dissipation.

[0035] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0036] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A GaO-based x The method for fabricating a CMOS inverter of NMOS / GaN-PMOS is characterized by... include: A carbon-doped GaN buffer layer is grown on a single-crystal Si substrate. A region on one side of the carbon-doped GaN buffer layer is blocked using photoresist. Si-doped GaN is epitaxially grown on the surface of the carbon-doped GaN buffer layer to form a p-MOS channel layer. A portion of the p-MOS channel layer surface is etched down to the carbon-doped GaN buffer layer. Using SiO2 as a growth mask, Mg-doped GaN is epitaxially grown on the exposed carbon-doped GaN buffer layer after etching. x Forming an n-MOS channel layer; Vertical photolithography is performed at the critical position between the n-MOS channel layer and the p-MOS channel layer, and diamond is grown in the formed isolation region to form a barrier layer; Using photoresist blocking, Si is ion-implanted at both ends of the n-MOS channel layer surface to form an n region, and Mg is ion-implanted at both ends of the p-MOS channel layer surface to form a p region; A metal film and dielectric layer are deposited on the device surface, stripped, and annealed to obtain a set of adjacent drains and sources in the barrier layer region. Another set of drains and sources is obtained at both ends of the n-MOS channel layer and the p-MOS channel layer. A metal film and dielectric layer are deposited on the surface of the n-MOS channel layer and the p-MOS channel layer, stripped, and annealed to form the gate, wherein the gate is located between the drain and the source.

2. The preparation method according to claim 1, characterized in that, The thickness of the carbon-doped GaN buffer layer is 6-10 μm.

3. The preparation method according to claim 2, characterized in that, The carbon doping concentration is 1~3×10 18 cm -3 .

4. The preparation method according to claim 1, characterized in that, The thickness of the n-MOS channel layer is 150-250 nm.

5. The preparation method according to claim 1, characterized in that, The thickness of the p-MOS channel layer is 150-250 nm.

6. The preparation method according to claim 1, characterized in that, Diamonds are 4 to 10 μm in length.

7. The preparation method according to claim 1, characterized in that, Al2O3 is used as the gate dielectric layer, and the thickness of Al2O3 is 20~30nm.

8. The preparation method according to claim 7, characterized in that, Al₂O₃ is silicon-doped, with a silicon doping concentration of 1~3×10⁻⁶. 18 cm -3 .

9. The preparation method according to claim 1, characterized in that, The drain and source metal films are made of Ti, Al, Ni or Au, and are annealed at 650°C in an N2 environment.

10. The preparation method according to claim 1, characterized in that, The gate metal film uses Ni or Au.

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