Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame includes a carrier and a plurality of pins. Each pin has a top surface and a first bottom surface, an inner end and an outer end. The inner end faces the carrier, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface with a flat side wall and an arc-shaped recess surface. The chip is arranged on the carrier and electrically connected to the pins. The packaging colloid covers the lead frame and the chip. The packaging colloid has a lower surface and a side surface. The lower surface exposes and is flush with the first bottom surface of the pin. The side surface is flush with the flat side wall of the pin and exposes the arc-shaped recess surface. The conductive material layer is arranged on the first bottom surface of the pin and on the arc-shaped recess surface. The semiconductor packaging structure and the manufacturing method thereof of the present invention have better bonding strength.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, the pursuit of miniaturized packaging has led to the emergence of Dual Flat No-Lead (DFN) and Quad Flat No-Lead (QFN) packages, both of which offer smaller footprints and superior heat dissipation, quality stability, and electrical performance, making them widely used in various packaging structures.

[0003] Generally speaking, double-sided flat no-lead packages and four-sided flat no-lead packages only use the bottom surface with the pins exposed as the external electrical connection point. In this case, the limited wettable area often cannot provide sufficient bonding strength between the package structure and external components (such as a printed circuit board), which in turn leads to electrical abnormalities or failures. Therefore, the technology of exposing the side walls of the pins and forming wettable flanks with a stepped structure has begun to be applied to increase the wettable area of ​​the pins and improve the bonding strength of the package structure electrically connected to the printed circuit board. However, the above-mentioned stepped wettable flanks are still limited by the area exposed in the package structure and cannot significantly improve the bonding strength of the pins electrically connected to the printed circuit board. Summary of the Invention

[0004] The present invention is directed to a semiconductor packaging structure and a manufacturing method thereof, wherein the pins of the semiconductor packaging structure have better bonding strength.

[0005] According to an embodiment of the present invention, a semiconductor packaging structure includes a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame includes a carrier and a plurality of pins surrounding the carrier. Each pin has a top surface and a first bottom surface, an inner end and an outer end opposite to each other. The inner end faces the carrier, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface with a flat side wall and an arc-shaped recess surface. The chip is arranged on the carrier and electrically connected to the pins. The packaging colloid covers the lead frame and the chip. The packaging colloid has a lower surface and a side surface. The lower surface exposes and is cut flush with the first bottom surface of each pin, and the side surface is cut flush with the flat side wall of each pin and exposes the arc-shaped recess surface. The conductive material layer is arranged on the first bottom surface of each pin and on the arc-shaped recess surface.

[0006] In the semiconductor package structure according to the embodiment of the present invention, the surface of the arc-shaped recess is a rough surface.

[0007] In the semiconductor package structure according to an embodiment of the present invention, the inner end of each pin has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface via the first sidewall, the second bottom surface, and the second sidewall. The recess is filled with encapsulant.

[0008] In the semiconductor package structure according to the embodiment of the present invention, the conductive material layer is made of lead-free solder.

[0009] According to an embodiment of the present invention, a method for manufacturing a semiconductor packaging structure includes the following steps. A semi-finished package is provided. The semi-finished package includes a lead frame bar, a plurality of chips, and an encapsulation resin. The lead frame bar has a plurality of lead frame units and a plurality of connecting bars connecting the lead frame units. Each lead frame unit includes a support seat and a plurality of pins surrounding the support seat. The outer end of each pin is connected to one of the adjacent connecting bars. The pins of two adjacent lead frame units are arranged opposite each other in pairs and form a plurality of connecting portions on one of the corresponding connected connecting bars. The bottom of the connecting portion has a groove. The chips are respectively arranged on the support seats of the lead frame units and electrically connected to the pins. The encapsulation resin covers the lead frame bar and the chip, wherein the encapsulation resin fills the groove of the connecting portion, and the lower surface of the encapsulation resin is exposed and cut flush with the first bottom surface of each pin. The semi-finished package is subjected to an etching process to form a recess in the portion of the first bottom surface of each pin adjacent to the recess. The encapsulation resin in each recess separates the recess of the two oppositely arranged pins, and the recess has an arc-shaped recess surface. The encapsulation colloid in the groove is removed to connect the recesses of the two oppositely arranged pins and expose the inner surface of the connecting portion. A conductive material layer is formed on the first bottom surface of the pin and the surface of the arc-shaped recess. A singulation process is performed to cut the encapsulation colloid and the connecting portion to form independent semiconductor packaging structures. The semiconductor packaging structure includes a lead frame having a support seat and pins surrounding the support seat, a chip, an encapsulation colloid and a conductive material layer. The pin has a top surface and a first bottom surface, an inner end and an outer end opposite to each other. The inner end faces the support seat, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface covered with the conductive material layer with a flat side wall and the arc-shaped recess surface covered with the conductive material layer. The side surface of the encapsulation colloid is cut flush with the flat side wall of each pin and the arc-shaped recess surface is exposed.

[0010] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the step of performing an etching process on the semi-finished package product includes providing a mask layer to cover a portion of the first bottom surface of the pin; and using the mask layer as an etching mask to form a recess on the first bottom surface of each pin.

[0011] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, before removing the encapsulation adhesive in the groove, the mask layer is removed to expose the first bottom surface of the lead.

[0012] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the surface of the arc-shaped recess is a rough surface.

[0013] In a method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the inner end of each pin has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface via the first sidewall, the second bottom surface, and the second sidewall. The recess is filled with encapsulant.

[0014] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the conductive material layer is made of lead-free solder.

[0015] Based on the above, the method for manufacturing a semiconductor package structure of the present invention further forms a recess on the portion of the first bottom surface of the pin adjacent to the groove of the connecting portion (i.e., at the outer end). Specifically, an inwardly recessed recess is formed at the bottom of the outer end of the pin. After the encapsulation gel in the recess is subsequently removed, the recesses of the two oppositely disposed pins and the corresponding grooves are interconnected to form a large recessed cavity. Next, a conductive material layer is disposed at least on the arc-shaped recessed surfaces formed by the recesses of the pins and on the first bottom surface. Therefore, the pins having the aforementioned arc-shaped recessed surfaces can increase the bonding area of ​​the conductive material layer, thereby increasing the area of ​​the conductive material layer on the pins exposed to the semiconductor package structure, thereby enhancing the bonding strength of the electrical connection of the semiconductor package structure. Furthermore, the arc-shaped recessed surfaces of the pins can be roughened. This roughened arc-shaped recessed surface allows for better adhesion of the conductive material layer to the arc-shaped recessed surface and reduces the formation of metal burrs during the singulation process, thereby enhancing the structural reliability of the semiconductor package structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1G FIG. 4 is a cross-sectional diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present invention.

[0017] Description of Reference Numerals

[0018] 10: Encapsulate semi-finished products;

[0019] 20: semiconductor packaging structure;

[0020] 100: lead frame unit;

[0021] 100': conductor rack;

[0022] 110: bearing seat;

[0023] 110b: bottom surface;

[0024] 120: pin;

[0025] 120a: top surface;

[0026] 120b: first bottom surface;

[0027] 122: medial end;

[0028] 122a: first side wall;

[0029] 122b: second bottom surface;

[0030] 122c: second side wall;

[0031] 124: lateral end;

[0032] 124c: flat sidewall;

[0033] 128: Depression;

[0034] 200: chip;

[0035] 210: welding wire;

[0036] 220: adhesive;

[0037] 300: Encapsulation colloid;

[0038] 300b: lower surface;

[0039] 300c: side surface;

[0040] 400: conductive material layer;

[0041] 500: connecting strip;

[0042] 510: connecting portion;

[0043] 512: inner surface;

[0044] LF: lead frame strip;

[0045] C: concave;

[0046] G: groove;

[0047] M: mask layer;

[0048] S: arc-shaped concave surface. DETAILED DESCRIPTION

[0049] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0050] The following fully describes exemplary embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be implemented in many different ways and should not be construed as limited to the embodiments described herein. In the accompanying drawings, for the sake of clarity, the sizes and thicknesses of various regions, parts, and layers may not be drawn to scale. For ease of understanding, identical elements will be designated by the same reference numerals throughout the following description.

[0051] Figures 1A to 1G 1 is a cross-sectional view of a method for manufacturing a semiconductor package structure according to an embodiment of the present invention. Figure 1A , providing a semi-finished package product 10, wherein the semi-finished package product 10 includes a lead frame strip LF, a plurality of chips 200, and an encapsulant 300. The lead frame strip LF has a plurality of lead frame units 100 and a plurality of connecting bars 500 connecting the lead frame units 100. The lead frame units 100 of the lead frame strip LF are, for example, arranged in a matrix and separated by connecting bars 500, and each lead frame unit 100 includes a carrier 110 and a plurality of pins 120 surrounding the carrier 110. The outer end 124 of each pin 120 is connected to an adjacent connecting bar 500, and the pins 120 of two adjacent lead frame units 100 are arranged opposite each other in pairs and form a plurality of connecting portions 510 on the corresponding connected connecting bars 500.

[0052] Next, please also refer to Figure 1A and Figure 1B Each connecting portion 510 has a groove G at its bottom. In this embodiment, the grooves G of each connecting portion 510 are interconnected to form a single elongated groove extending along the connecting strip 500. However, in other embodiments not shown, the grooves G of each connecting portion 510 may be separate grooves, so that a plurality of separate grooves are formed on the connecting strip 500. The present invention does not limit the form and number of the grooves. Furthermore, the chips 200 of this embodiment are respectively disposed on the carrier 110 of the lead frame unit 100 and electrically connected to the pins 120. The chip 200 and the carrier 110 can be fixed with an adhesive 220, wherein the adhesive 220 is, for example, a commonly used epoxy resin, silver glue, or die attach film (DAF). Here, the chip 200 is electrically connected to the pins 120 via bonding wires 210, but this electrical connection method is not limited to this method. The material of the bonding wires 210 is, for example, gold, copper, or other suitable conductive materials, which are not limited here.

[0053] Next, please refer to Figure 1A and Figure 1BThe encapsulant 300 covers the lead frame LF and the chip 200. In this embodiment, the inner end 122 of each pin 120 has a recess 128 at the first bottom surface 120b. The encapsulant 300 fills the recess 128 of the pin 120 and the groove G of the connecting portion 510. The lower surface 300b of the encapsulant 300 is exposed and flush with the first bottom surface 120b of the pin 120. The encapsulant 300 is made of, for example, epoxy resin or other suitable polymer materials, which can prevent the intrusion of moisture or contaminants. By filling the recess 128 of the pin 120 with the encapsulant 300, the pin 120 can be locked in the encapsulant 300, preventing the pin 120 from falling out of the encapsulant 300. Furthermore, in this embodiment, the lower surface 300 b of the encapsulant 300 also exposes the bottom surface 110 b of the carrier 110 . However, in other embodiments not shown, the bottom surface 110 b of the carrier 110 may be covered by the encapsulant 300 and not exposed.

[0054] Next, please refer to Figure 1C The semi-finished package 10 is subjected to an etching process. First, a mask layer M is provided to partially cover the first bottom surface 120b of the lead 120. In this embodiment, the mask layer M also covers the bottom surface 110b of the carrier 110. The mask layer M can be made of, for example, an insulating photoresist material or a metal material. Metal materials such as gold, palladium, or other selectively etchable metals can exhibit better etching selectivity.

[0055] Next, please also refer to Figure 1C and Figure 1D The entire semi-finished package product 10 is placed in a metal etching solution, such as a copper etching solution, using the mask layer M as an etching mask. The portions of the lead 120 not shielded by the mask layer M are etched, thereby forming a cavity C in the portion of the first bottom surface 120b of the lead 120 adjacent to the groove G. The encapsulant 300 in the groove G separates the cavities C of the two oppositely disposed leads 120, and each cavity C has an arcuate cavity surface S. Here, the arcuate cavity surface S is embodied as a rough surface, that is, a sawtooth-like structure at a microscopic level, but the present invention is not limited to this.

[0056] Next, please also refer to Figure 1D and Figure 1E, remove the mask layer M to expose the first bottom surface 120b of the pin 120. Next, remove the packaging colloid 300 in the groove G, and connect the recesses C of the two oppositely arranged pins 120, and expose the inner surface 512 of the connecting portion 510. Here, the method of removing the packaging colloid 300 in the groove G is preferably by laser ablation, but is not limited to this. Then, form a conductive material layer 400 on the first bottom surface 120b of the pin 120 and the arc-shaped recess surface S. Further, the conductive material layer 400 can be selectively formed on the inner surface 512 of the connecting portion 510 and the bottom surface 110b of the support seat 110. Here, the conductive material layer 400 is formed by, for example, electroplating or printing, and the material of the conductive material layer 400 is, for example, lead-free solder, but is not limited to this. At this point, by etching the lead 120, a cavity C is formed in the portion of the first bottom surface 120b of the lead 120 adjacent to the groove G (i.e., at the outer end 124). In other words, an inwardly recessed cavity C is formed at the bottom of the outer end 124 of the lead 120. After the encapsulant 300 in the groove G is subsequently removed, the cavities C of the two oppositely disposed leads 120 and the corresponding groove G are interconnected, forming a large cavity. Next, the conductive material layer 400 can be formed on the surface of the large cavity. This configuration increases the bonding area between the conductive material layer 400 and the lead 120. Furthermore, the roughened arcuate cavity surface S allows the conductive material layer 400 to adhere better to the arcuate cavity surface S and reduces the generation of metal burrs during the subsequent singulation process.

[0057] Afterwards, please also refer to Figure 1F and Figure 1G , a singulation process is performed to cut the encapsulation body 300 and the connection portion 510 so that the side surface 300c of the encapsulation body 300 is aligned with the plane side wall 124c of each lead 120 and the conductive material layer 400 on the arc-shaped recess surface S of the outer end 124 is exposed, thereby forming each independent semiconductor package structure (at Figure 1G Schematically showing a semiconductor package structure 20). At this point, the fabrication of the semiconductor package structure 20 has been completed.

[0058] Regarding the structure, please refer to Figure 1GThe semiconductor package structure 20 of this embodiment includes a lead frame 100', a chip 200, an encapsulant 300, and a conductive material layer 400. The lead frame 100' includes a carrier 110 and pins 120 surrounding the carrier 110. Each pin 120 has a top surface 120a and a first bottom surface 120b facing each other, an inner end 122, and an outer end 124. The inner end 122 faces the carrier 110, and the inner end 122 of each pin 120 has a recess 128 at the first bottom surface 120b, so that the inner end 122 connects the top surface 120a and the first bottom surface 120b through a first sidewall 122a, a second bottom surface 122b, and a second sidewall 122c. The outer end 124 defines a cavity C on the first bottom surface 120b, connecting the top surface 120a and the first bottom surface 120b via the planar sidewalls 124c and the arcuate cavity surface S. The chip 200 is disposed on the carrier 110 and electrically connected to the lead 120 using, for example, wirebonds 210. The chip 200 is secured to the carrier 110 via an adhesive 220. The encapsulant 300 covers the lead frame 100' and the chip 200 and fills the cavity 128. The encapsulant 300 has a lower surface 300b and a side surface 300c. The lower surface 300b is exposed and flush with the first bottom surface 120b of the lead 120, while the side surface 300c is flush with the planar sidewalls 124c of the lead 120 and exposes the arcuate cavity surface S. A conductive material layer 400 is disposed on the first bottom surface 120b and the arcuate cavity surface S of each lead 120. Compared to conventional pins with a stepped structure, the pins 120 of this embodiment with an arc-shaped concave surface S can increase the bonding area with the conductive material layer 400 (i.e., increase the wettable area of ​​the pins 120), thereby improving the bonding yield of the semiconductor package structure 20 and the external terminals.

[0059] In summary, through the manufacturing method of the semiconductor package structure of the present invention, a recess is further formed on the portion of the first bottom surface of the pin adjacent to the groove of the connecting portion (i.e., at the outer end). Specifically, an inwardly recessed recess is formed at the bottom of the outer end of the pin. After the encapsulation gel in the recess is subsequently removed, the recesses of the two oppositely arranged pins and the corresponding grooves are interconnected to form a large recessed hole. Next, a conductive material layer is disposed at least on the arc-shaped recessed surface formed by the recess of the pin and the first bottom surface. Therefore, the pin having the aforementioned arc-shaped recessed surface can increase the bonding area of ​​the conductive material layer, thereby increasing the area of ​​the conductive material layer on the pin exposed to the semiconductor package structure, thereby improving the bonding strength of the electrical connection of the semiconductor package structure. In addition, the arc-shaped recessed surface of the pin can be roughened. The rough arc-shaped recessed surface allows the conductive material layer to adhere better to the arc-shaped recessed surface and reduces the formation of metal burrs during the singulation process, thus providing the semiconductor package structure of the present invention with better structural reliability.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor packaging structure, characterized in that: include: A semi-finished package is provided, the semi-finished package comprising a lead frame strip, a plurality of chips, and an encapsulation resin, the lead frame strip having a plurality of lead frame units and a plurality of connecting bars connecting the plurality of lead frame units, each of the plurality of lead frame units comprising a carrier and a plurality of pins surrounding the carrier, an outer end of each of the plurality of pins being connected to one of the adjacent plurality of connecting bars, the plurality of pins of two adjacent plurality of lead frame units being arranged opposite to each other in pairs and forming a plurality of connecting portions on one of the correspondingly connected plurality of connecting bars, the bottom of each of the plurality of connecting portions having a groove, the plurality of chips being respectively arranged on the carrier of each of the plurality of lead frame units and electrically connected to the plurality of pins, the encapsulation resin covering the lead frame strip and the plurality of chips, wherein the encapsulation resin fills the groove of each of the plurality of connecting portions, and a lower surface of the encapsulation resin is exposed and flush with a first bottom surface of each of the plurality of pins; performing an etching process on the semi-finished package product to form a cavity on a portion of the first bottom surface of each of the plurality of leads adjacent to the groove, wherein the encapsulant in the groove separates the cavity of two oppositely disposed leads, and the cavity has an arc-shaped cavity surface; Removing the encapsulant in the groove to connect the two oppositely disposed recesses of the plurality of pins and expose the inner surfaces of the plurality of connecting portions; forming a conductive material layer on the first bottom surface of each of the plurality of pins and on the surface of the arc-shaped recess; A singulation process is performed to cut the encapsulation body and the plurality of connecting portions to form a plurality of independent semiconductor package structures, wherein each of the plurality of semiconductor package structures includes a lead frame having the carrier and the plurality of pins surrounding the carrier, one of the plurality of chips, the encapsulation body, and the conductive material layer, wherein each of the plurality of pins has a top surface and the first bottom surface opposite to each other, an inner end, and an outer end, the inner end facing the carrier, and the outer end having the recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface covered with the conductive material layer with a planar sidewall and the arc-shaped recess surface covered with the conductive material layer, and a side surface of the encapsulation body is cut flush with the planar sidewall of each of the plurality of pins and exposes the arc-shaped recess surface.

2. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The step of performing the etching process on the semi-finished package product comprises: providing a mask layer to cover a portion of the first bottom surface of each of the plurality of pins; and The mask layer is used as an etching mask to form the cavity on the first bottom surface of each of the plurality of pins.

3. The method for manufacturing a semiconductor package structure according to claim 2, wherein: Before removing the encapsulant in the groove, the mask layer is removed to expose the first bottom surface of each of the plurality of pins.

4. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The surface of the arc-shaped recess is a rough surface.

5. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The inner end of each of the plurality of pins has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface through the first side wall, the second bottom surface and the second side wall, and the encapsulation glue fills the recess.

6. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The conductive material layer is made of lead-free solder.

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