Embedded fan-out package structure and method of manufacturing the same

Abstract

The application discloses an embedded fan-out packaging structure and a manufacturing method thereof. The structure comprises an FCBGA substrate and an embedded fan-out package. The fan-out package is internally packaged with a Si interposer chip and a redistribution layer. Surface contacts of the redistribution layer form first metal bumps. The substrate comprises a core layer and a plurality of stacked build-up boards on the surface of the core layer. The build-up boards are electrically connected through laser drilling and metal plating. When the fan-out package is embedded in the substrate, the first metal bumps on the surface of the fan-out package and the plated metal on the surface of the substrate are exposed on the surface of the build-up board. The medium-density wiring is moved from the Si interposer chip to the fan-out package. The fan-out package can be designed with medium-density wiring and has a lower cost. The size of the Si interposer chip is reduced. The fan-out package is embedded in the FCBGA substrate, which can reduce the cost, and the packaging process is relatively simple, and the packaging cost is relatively low.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor packaging, and particularly relates to an embedded fan-out packaging structure and a manufacturing method thereof. BACKGROUND

[0002] With the need of higher memory bandwidth for various applications such as artificial intelligence (AI), data center, high performance computing (HPC), network and graphics acceleration cards, advanced packaging becomes an increasingly important factor to support high bandwidth memory (HBM) wide I / O. Currently, there are three advanced packaging technologies used in the industry, TSMC's CoWoS (Chip on Wafer on Substrate), Intel's EMIB (Embedded Multi-Die Interconnect Bridge) and Samsung's H-Cube.

[0003] TSMC's CoWoS: Typical 2.5D packaging, the chips of Processor, Logic and HBM are mounted on a Si interposer, and there are multiple layers of redistribution layers (RDL) on the Si interposer. The line width and pitch of the redistribution layer wiring is less than 1.2 microns (um). Such fine wiring can provide high and medium density signal connections between chips, which cannot be provided by FCBGA substrates (or called carrier boards), as well as medium and low density signal connections. The Si interposer is mounted on the FCBGA substrate, and the Si interposer has TSVs (through silicon vias) to guide the signals from the upper layer to the lower layer, and then make signal conduction with the FCBGA substrate. The fabrication of the Si interposer wafer is completed by the wafer factory. Due to the limitations of reticle and exposure process equipment, it is difficult to make the Si interposer large enough to place many chips, and the high cost is the main criticism of CoWoS.

[0004] Intel's EMIB: Intel's approach is to reduce the size of the expensive Si interposer. The Si interposer does not have TSVs (through silicon vias) to guide the signals from the upper layer to the lower layer, because the signals are only transmitted in the RDL on the surface of the Si interposer, and there is a potential to reduce the performance of the chip.

[0005] Single or multiple Si interposer embedded in FCBGA substrate, high and medium density signal connection routing design on Si interposer, low density signal connection routing design on FCBGA substrate, although the size of Si interposer is reduced to reduce the cost, but the FCBGA substrate cannot design medium density signal connection routing (line width and line spacing between 8um to 1.5um), ABF material has silica filler, blind via hole cannot be opened by etching, and laser drilling is used to open blind via hole, size is limited, too small hole cannot be drilled, so the size and pitch of the junction of the substrate and the chip cannot be reduced, the size of the Si interposer and the chip cannot be further reduced, and the cost cannot be reduced.

[0006] The pitch of the junction between the chip and the Si interposer is 55um, and the pitch of the junction between the chip and the FCBGA substrate is 130um.

[0007] Samsung's H-Cube: basically similar to TSMC's CoWoS, the chip is mounted on a large Si interposer, the Si interposer is mounted on a fine pitch substrate, and the fine pitch substrate is mounted on a high density interconnect (HDI) substrate. Because a large Si interposer and two substrates are used, the problem faced is the same as CoWoS, the Si interposer is difficult to make large enough and the cost is very high.

[0008] Therefore, the existing method not only has a large size of Si interposer (because all high, medium and low density routing is on it) and needs TSV (through silicon via), resulting in high cost. Even if the size of the Si interposer is reduced, high and medium density routing is on it, and the FCBGA substrate can only design low density (line width and line spacing greater than 8um) routing, the size of the Si interposer cannot be further reduced, and even when more chips are placed, the size of the Si interposer must be increased, and the cost cannot be further reduced. SUMMARY

[0009] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides an embedded fan-out packaging structure and a manufacturing method thereof, which has low cost and high input / output density, and greatly helps to integrate more HBM and Processor to improve the operation efficiency.

[0010] The technical scheme adopted by the present application is:

[0011] An embedded fan-out package structure, comprising a FCBGA substrate and a fan-out package embedded in the FCBGA substrate; the fan-out package encapsulates a Si interposer chip and a redistribution layer electrically connected therein, the redistribution layer is routed on the surface of the Si interposer chip, and the surface contacts of the redistribution layer form first metal bumps; the FCBGA substrate comprises a core layer and at least two layers of build-up boards stacked on the surface of the core layer, and each layer of the build-up boards is electrically connected through laser drilling and hole filling with electroplated metal.

[0012] When the fan-out package is embedded in the FCBGA substrate, the first metal bumps on the surface of the fan-out package and the electroplated metal on the surface of the FCBGA substrate are exposed on the surface of the build-up board.

[0013] Optionally, the contacts on the upper surface of the Si interposer chip form second metal bumps, and multiple layers of the redistribution layer are routed on the upper surface of the Si interposer chip and electrically connected with the second metal bumps.

[0014] Optionally, the line width and line spacing of the redistribution layer are between 30 μm and 1.5 μm.

[0015] Optionally, the upper surface and the lower surface of the core layer are respectively laminated with multiple layers of the build-up board, and each layer of the build-up board comprises an ABF build-up film and a circuit formed on the surface of the ABF build-up film.

[0016] Optionally, the build-up board on the upper surface of the FCBGA substrate corresponds to the fan-out package to form a cavity, and the gap between the fan-out package and the cavity is filled with resin.

[0017] Optionally, the bottom of the build-up board on the lower surface of the FCBGA substrate forms a tin ball pad.

[0018] Optionally, the core layer is provided with a through hole, and the upper surface and the lower surface of the core layer respectively form a circuit and are conductive through the through hole.

[0019] Optionally, the upper surface of the FCBGA substrate is provided with a tin-copper bump for electrically connecting a memory chip, a processor chip or a logic chip.

[0020] Optionally, the gap between the upper surface of the FCBGA substrate and the memory chip, the processor chip or the logic chip to be mounted is provided with an underfill and is attached with a heat sink.

[0021] A manufacturing method for manufacturing the embedded fan-out package structure as described above, the manufacturing method comprising:

[0022] Fabricating a fan-out package, the fan-out package encapsulating a Si interposer chip and a redistribution layer electrically connected, the redistribution layer routing on the surface of the Si interposer chip, the surface contacts of the redistribution layer forming first metal bumps;

[0023] Fabricating a FCBGA substrate, laminating multilayer build-up boards on the top and bottom surfaces of the core layer of the FCBGA substrate, the build-up boards of each layer being electrically connected through laser drilling and filling the holes with electroplated metal;

[0024] Drilling cavities on the build-up boards on the top surface of the FCBGA substrate, placing the fan-out package in the cavities, the first metal bumps facing upward;

[0025] Continuing to fabricate build-up boards on the top surface of the fan-out package and the FCBGA substrate for encapsulation, exposing the first metal bumps and the electroplated metal in the build-up boards;

[0026] Fabricating tin ball pads on the bottom of the build-up boards on the bottom surface of the FCBGA substrate.

[0027] Optionally, the steps of fabricating a fan-out package include:

[0028] Attaching a Si interposer chip to a carrier, setting second metal bumps on the surface contacts of the Si interposer chip;

[0029] Continuing to encapsulate by molding resin on the Si interposer chip, and grinding the resin to expose the second metal bumps;

[0030] Routing a redistribution layer on the top surface of the resin, the redistribution layer being electrically connected with the second metal bumps;

[0031] Setting first metal bumps on the surface contacts of the redistribution layer;

[0032] Removing the carrier and cutting into single fan-out packages.

[0033] Optionally, the core layer of the FCBGA substrate is fabricated by the following steps, including:

[0034] Using glass fiber and resin as the intermediate layer of the core layer, combining the top and bottom surfaces of the intermediate layer with copper foil respectively;

[0035] Drilling holes on the core layer and plating copper in the holes;

[0036] Etching to remove the copper foil except the circuit part, forming a circuit on the top and bottom surfaces of the core layer and conducting through the holes.

[0037] Optionally, the step of pressing the multi-layer build-up circuit board on the upper and lower surfaces of the core layer of the FCBGA substrate comprises:

[0038] ABF build-up film is pressed on the upper and lower surfaces of the core layer, circuit patterns are exposed on the surface of the ABF build-up film, and the ABF build-up film is etched and plated with copper to form circuits;

[0039] The process of pressing the ABF build-up film and plating copper to form circuits is repeated multiple times to stack the build-up layers, and the copper conductors of each layer of circuits are electrically connected through blind holes filled with electroplated copper.

[0040] Optionally, after the step of manufacturing tin ball pads on the bottom of the build-up circuit board on the lower surface of the FCBGA substrate, the method further comprises the step of cutting the FCBGA substrate into single pieces.

[0041] The technical scheme has the following beneficial effects:

[0042] The embedded fan-out packaging structure has high-density RDL wiring on the surface of the Si interposer chip, the Si interposer chip is packaged in the fan-out packaging, the fan-out packaging has multiple layers of RDL to provide medium-density wiring, the RDL line width and line spacing can be as small as 1.5 microns, the fan-out packaging is completed by a packaging factory, the fan-out packaging is sent to a substrate factory, and is embedded in a low-density wiring FCBGA substrate. After the process is completed, the fan-out packaging is delivered to the packaging factory for subsequent FCBGA process. Thus, the medium-density wiring is removed from the Si interposer chip and placed in the fan-out packaging, the fan-out packaging can be designed with medium-density wiring (the RDL line width and line spacing are between 30 microns and 1.5 microns), and the cost is relatively low. The size of the Si interposer chip is reduced and is packaged in the fan-out packaging, the fan-out packaging is embedded in the FCBGA substrate, the cost is reduced, the packaging process is relatively simple, and the packaging cost is relatively low. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0044] Figures 1-5 The structure schematic diagram presented by each step of the packaging method of the fan-out packaging provided by the embodiments of the present application.

[0045] Figures 6-11 The structure schematic diagram presented by each step of the packaging method of the FCBGA substrate provided by the embodiments of the present application. DETAILED DESCRIPTION

[0046] The specific embodiments of the present application will be further described with reference to the drawings. It is to be noted that the description of these embodiments is intended for the purpose of illustration only and is not intended to limit the present application in any way. Furthermore, the features of the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0047] First, the technical terms appearing in the text are explained as follows:

[0048] RDL: Redistribution Layer, redistribution layer, contains copper connection lines or tracks, used to realize the electrical connection between the various parts of the package, it is a layer of metal or polymer dielectric material, the die can be stacked in the package, thereby reducing the I / O pitch of the chip set; RDL has become an indispensable part of 2.5D and 3D packaging solutions, so that the chips on it can communicate with each other through the interposer;

[0049] DAF: Die Attach Film, die attach film, the purpose is that when laser cutting, the die can be cut and separated together, peeled off, so that the cut die can still be attached to the film and will not be scattered due to cutting;

[0050] FCBGA (Flip Chip Ball Grid Array): Flip Chip Ball Grid Array packaging format, which is also the most important packaging format for graphics acceleration chips and central processing units;

[0051] Build-up: a processing technology for forming a thin film on the surface of a wafer;

[0052] ABF: ABF material is a material developed by Intel, used for the production of Flip Chip and other high-level carriers. Compared with BT substrate, ABF material can make the circuit finer, suitable for high-pin high-transmission ICs, and is mainly used for CPU, GPU and chipsets and other large high-end chips. ABF as a build-up material, copper foil substrate directly attached with ABF can be used for circuit, and does not require a hot pressing process;

[0053] HBM: High Bandwidth Memory, high bandwidth memory chip;

[0054] PI: Polyimide, polyimide, refers to the main chain containing imide ring (-CO-N-CO-) of a class of polymers, is one of the best comprehensive performance of organic polymer materials. Its high temperature resistance up to 400 ℃ or more, long-term use temperature range -200~300 ℃, some no obvious melting point, high insulation performance, 103 hertz under the dielectric constant 4.0, dielectric loss only 0.004~0.007, F to H level insulation.

[0055] Specifically refer to Figure 5 And Figure 11 , Figure 5 The fan-out package provided by the embodiment of the application is a schematic diagram of the overall structure after the package is completed, Figure 11 The embedded fan-out package structure provided by the embodiment of the application is a schematic diagram of the overall structure after the package is completed.

[0056] The embedded fan-out package structure mainly uses the interposer of different materials to show different line widths and pitches to support the interconnection of signals between high input / output (I / O: Input / Output) density chips. The present application provides an embedded fan-out package structure and a manufacturing method thereof to achieve the above-mentioned purpose.

[0057] The embedded fan-out package structure mainly includes an FCBGA substrate 1 and a fan-out package 2 embedded in the FCBGA substrate 1; the fan-out package 2 internally encapsulates an electrically connected Si interposer chip 21 and a redistribution layer 22, the redistribution layer 22 is wired on the surface of the Si interposer chip 21, the surface contacts of the redistribution layer 22 form a plurality of first metal bumps 23, and the first metal bumps 23 can adopt copper bumps or copper columns; the FCBGA substrate 1 includes a core layer 11 and at least two layers of build-up circuit boards 12 stacked on the surface of the core layer 11, the layers of build-up circuit boards 12 are electrically connected through laser drilling blind holes 131 and filling of electroplated metal 13 in the blind holes, and the electroplated metal 13 can adopt electroplated copper.

[0058] The fan-out package 2 is embedded in the build-up circuit board 12 on the upper surface of the FCBGA substrate 1, the first metal bumps 23 on the upper surface of the fan-out package 2 face upward, and the build-up circuit board 12 on the upper surface of the FCBGA substrate 1 is provided with a cavity corresponding to the position of the fan-out package 2. At this time, the first metal bumps 23 on the surface of the fan-out package 2 and the electroplated metal 13 in the blind hole are exposed on the surface of the build-up circuit board 12 of the FCBGA substrate 1, preferably, the first metal bumps 23, the electroplated metal 13 in the blind hole and the surface of the build-up circuit board 12 are at the same height and reach the design flatness. Copper tin is electroplated on the exposed first metal bumps 23 and the electroplated metal 13 in the blind hole, and the height is consistent, and a tin ball pad 14 is arranged on the lower surface of the FCBGA substrate 1.

[0059] Further cooperation Figure 5The fan-out package 2 is embedded in the FCBGA 1. The fan-out package 2 has two Si interposer chips 21 arranged side by side. The upper surface of the Si interposer chips 21 has second metal bumps 211, which can be copper pillars or copper bumps. A plurality of redistribution layers (RDLs) 22 are arranged on the upper surface of the Si interposer chips 21 and are electrically connected to the second metal bumps 211. The Si interposer chips 21 can provide high RDL wiring density. The fan-out package 2 can have a line width and line spacing of 1.5 micrometers, which is suitable for medium-density wiring (line width and line spacing of 30-1.5 micrometers). Therefore, the fan-out package 2 can be used to manufacture medium-density interposers.

[0060] The Si interposer embedded in the FCBGA can reduce cost and has a relatively simple packaging process and low packaging cost. However, the size of the Si interposer cannot be further reduced because high-density and medium-density wiring are arranged on the Si interposer. When more chips are arranged, the size of the Si interposer has to be increased.

[0061] The present application removes the medium-density wiring from the Si interposer and arranges the medium-density wiring in the fan-out package. The fan-out package can have medium-density wiring (line width and line spacing of 30-1.5 micrometers) and low cost. The Si interposer embedded in the fan-out package can reduce cost, has a relatively simple packaging process, and has low packaging cost.

[0062] Throughout the electronic and semiconductor supply chain, the wafer foundry process mainly handles line width and line spacing of 1 micrometer (um) to 3 nanometers (nm). The printed circuit board process handles line width and line spacing of several millimeters (mm) or more. The packaging factory process handles line width and line spacing of several millimeters (mm) to several micrometers (um). The substrate used in the packaging factory has a process that handles line width and line spacing of 8 micrometers (um) to several hundred micrometers. The bump of the packaging factory has a fan-in / fan-out packaging process that handles line width and line spacing of tens of micrometers to 1 micrometer. Based on this, the bottleneck encountered by current advanced packaging is solved.

[0063] The difference between the fan-in wafer level package (FI-WLP) and the fan-out wafer level package (FO-WLP) is that the tin balls of the fan-in package are within the range of the chip, and the tin balls of the fan-out package are outside the range of the chip.

[0064] Fan-out wafer level packaging (FOWLP) is a process in which the semiconductor die is connected to a redistribution layer (RDL) from the die's pads, and then the die is encapsulated. Therefore, no substrate is needed, and no wire or bump is needed, which reduces the production cost and makes the chip and package thinner. In order to form the RDL, the front-end process must be introduced to the packaging, which greatly improves the process capability of the packaging factory, from several millimeters to several microns.

[0065] Wafer level packaging is mainly based on wafer level process, and the process is processed in units of one or more wafers.

[0066] FOWLP processes are divided into two categories:

[0067] Chip-first FO: The qualified dies (KGD, known good die) are placed on the wafer level carrier, selected from the original device wafer, and covered with a re-constitution wafer by molding resin, and then further processed into RDL on the wafer, ball planting, carrier removal, and singulation.

[0068] RDL-first FO: The wafer level carrier establishes the RDL layer and temporarily bonds, places the KGD on the top, and then molds the resin, grinds, removes the carrier, plants the ball, and singulates.

[0069] Under these two process architectures, various changes can be derived according to different customer needs, such as die facing up bonding, die facing down bonding, RDL fine line first, and RDL thick line first. The RDL line width and spacing capability of FOWLP can be as small as 1.5 microns.

[0070] FOWLP is more suitable for chips smaller than 5mm 2 If the chip is very large, the wafer level is circular, which will waste a lot of wafer space. The solution is to use fan-out packaging FOPLP (fan-out panel level package) to save space and increase unit output, which greatly reduces the cost.

[0071] The process capability of the panel level can be the same as the wafer level. If the working area of the wafer level equipment is enlarged, of course, this must be developed with the material and equipment suppliers to develop suitable materials and process equipment to achieve the same process capability. The RDL line width and spacing capability can be as small as 1.5 microns.

[0072] With the newly developed materials and equipment, the line width and space capability of the RDL process of the fan-out panel level package can be as small as 1.5 microns, which just meets the requirement of the medium density wiring (the line width and space capability of the RDL is between 30-1.5 microns), so the medium wiring density interposer can be made by the process of the fan-out panel level package.

[0073] The Si interposer provides high RDL wiring density, the interposer of the fan-out panel level package provides medium density RDL wiring, and the substrate of the FCBGA provides low density wiring, so if the advanced package uses these three different wiring density media at the same time, the Processor, logic and HBM multi-chip integration in the advanced package can be provided, and the HBM can be put into the package from 1 to 6, and the more the number of HBM, the better the operation efficiency of the Processor.

[0074] The scheme provided by the application is to arrange high density RDL wiring on the surface of the Si interposer chip, and then package the Si interposer chip in the fan-out package, the fan-out package has multiple layers of RDL to provide medium density wiring, the line width and space capability of the RDL is as small as 1.5 microns, the fan-out package is completed by the packaging factory, the fan-out package is sent to the substrate factory, and then embedded in the FCBGA substrate with low density wiring, and after the process is completed, the product is sold to the packaging factory for subsequent FCBGA process.

[0075] Cooperation Figures 1-5 As shown in the structure schematic diagram provided by the packaging method of the fan-out package 2 of the embodiment of the application.

[0076] The process of the fan-out package 2 is as follows:

[0077] Step 1: The packaging factory receives the Si interposer wafer completed by the wafer factory, and then a second metal bump 211 (copper column) is made on the contact point of the Si interposer wafer, and then the wafer is cut into chips;

[0078] Step 2: Next is the wafer level or panel level fan-out process, the cut Si interposer chip 21 is adhered to the carrier 30 by the adhesive 31, as shown in the figure; Figure 1

[0079] Step 3: The Si interposer chip 21 is molded and filled with resin 32 for packaging, as shown in the figure; the upper surface of the mold is ground until the copper column is exposed and stops at the designed height, as shown in the figure; Figure 2 Figure 3

[0080] Step 4: Then a plurality of redistribution layers 22 (RDL) are made on the upper surface of the resin 32, the line width and space capability of the RDL can be as small as 1.5 microns (medium density wiring), as shown in the figure; Figure 4

[0081] ​​​​Step 5: Finally, make the first metal bump 23 (copper column) at the upper surface contact point of the uppermost RDL, as shown in Figure 4 ;

[0082] Step 6: Dissolve the adhesive 31, remove the carrier 30, cut into single fan-out package, and send to the substrate factory.

[0083] Further in combination Figures 6-11 , the structure schematic diagram presented by each step of the packaging method of the FCBGA substrate provided by the embodiment of the present application is shown.

[0084] As shown in Figure 6 , the core layer 11 of the FCBGA substrate 1 has several layers, and the main three layers are the middle layer 111 of glass fiber and resin material, and the upper and lower layers of the middle layer 111 are copper foil 112. The through hole 113 is opened on the core layer 11 substrate, the through hole 113 is plated with copper, and the copper foil outside the circuit part is removed by etching to form a circuit and the upper and lower two layers of the circuit are connected through the through hole 113.

[0085] As shown in Figure 7 , the upper surface and the lower surface of the core layer 11 are respectively pressed with a plurality of build-up boards 12, and each build-up board 12 includes an ABF build-up film 121 and a circuit 122 (copper wire) formed on the surface of the ABF build-up film 121. Specifically, the ABF (Ajinomoto Build-up Film) or the same material is pressed on both surfaces of the core layer 11 by using the laminate process (or build-up process), the circuit pattern is exposed, and the circuit 122 (copper wire) is directly formed by developing etching and copper plating treatment. The laminate process is repeated several times to stack the build-up (lamination), and there are blind holes 131 between the copper wires of each layer for electrical connection. The blind hole 131 is drilled by laser, and the size is limited. Too small holes cannot be drilled. The blind hole 131 is filled with electroplated metal 13 (electroplated copper). The laminate process is repeated several times to the required number of layers, as shown in Figure 8 and Figure 9 .

[0086] As shown in Figure 10 , the position where the fan-out package 1 is placed in the build-up board 12 on the upper surface of the FCBGA substrate 1 is excavated or a cavity 15 is opened by laser. The face of the fan-out package 2 with the first metal bump 23 is upward, and the bottom of the package without the first metal bump 23 is fixed in the cavity 15. Preferably, DAF glue 151 can be used for fixation, as shown in Figure 11The gap between the fan-out package 2 and the cavity 15 is filled with resin. Then, the ABF build-up board 12 is pressed to cover the fan-out package 2 and the copper wires on the FCBGA substrate. The surface of the ABF build-up board 12 is polished to expose the copper pillars and the electroplated copper in the blind holes. The copper pillars, the electroplated copper and the ABF build-up board 12 are at the same height and reach the design flatness. The exposed copper pillars and the electroplated copper in the blind holes are electroplated with tin-copper bumps 16, which are at the same height. The lower surface of the FCBGA substrate is provided with tin ball pads 14.

[0087] The process of the FCBGA substrate 1 is as follows:

[0088] Step 1: The core layer 11 of the FCBGA substrate 1 is made. The core layer 11 has several layers, and the main three layers are the middle layer made of glass fiber and resin material. The upper and lower layers of the middle layer are copper foils 112. Through holes 113 are opened on the core layer 11 substrate. The through holes 113 are electroplated with copper. The copper foils outside the circuit part are removed by etching to form a circuit. The upper and lower layers of the circuit are connected through the through holes 113. The core layer process is completed, as shown in Figure 6 .

[0089] Step 2: The next step is the lamination process (or build-up process). ABF (Ajinomoto Build-up Film) or equivalent material is pressed on both sides of the core layer 11. The circuit pattern is exposed and directly formed by developing, etching and electroplating copper treatment. The process is repeated multiple times to stack and build up (laminate). There are blind holes between the copper wires of each layer for electrical connection. The blind holes are drilled by laser, and the size is limited. Too small holes cannot be drilled. The blind holes are filled with electroplated copper. The lamination process is repeated several times to the required number of layers, as shown in Figures 7-9 .

[0090] Step 3: A cavity 15 is dug on the upper surface of the FCBGA substrate 1 where the fan-out package is to be placed. The contacts of the fan-out package 2 have copper bumps or copper pillars facing upwards. The bottom of the package without copper bumps or copper pillars is fixed in the cavity 15. The gap between the fan-out package 2 and the cavity 15 is filled with resin. Then, the ABF build-up board 12 is pressed to cover the fan-out package 2 and the copper wires on the FCBGA substrate 1. The surface of the ABF build-up board 12 is polished to expose the copper pillars and the electroplated copper in the blind holes. The copper pillars, the electroplated copper and the ABF build-up board 12 are at the same height and reach the design flatness. The exposed copper pillars and the electroplated copper in the blind holes are electroplated with tin-copper bumps 16, which are at the same height. The lower surface of the FCBGA substrate is provided with tin ball pads 14.

[0091] Step 4: After the build-up process, the outer layer process is performed. The FCBGA substrate is cleaned, cut into single pieces, and checked for appearance and electrical properties. Part of the FCBGA substrate manufacturing process is completed.

[0092] Step 5. The FCBGA substrate is sent to a packaging factory, and a processor 33, logic, and 1-6 high bandwidth memory (HBM) chips 34 are inverted on the upper surface of the FCBGA substrate 1. The contacts of the plurality of tin-copper bumps on the memory chip 34 are welded to the contacts of the plurality of tin-copper bumps 16 on the upper surface of the FCBGA substrate to make electrical conduction. The tin-copper bumps 16 are filled with polyimide (PI) 36. The gap between the memory chip 34 and the FCBGA substrate 1 is filled with underfill 35. A heat sink is attached, and the heat sink and the back surface of the memory chip 34 have thermal interface material (TIM) to assist heat conduction. Finally, a plurality of tin balls are planted on the ball pads on the lower surface of the FCBGA substrate 1, and the heat sink is covered with a lid. The appearance and electrical properties are checked, and the process of the FCBGA substrate is completed.

[0093] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connected", "connection" should be interpreted broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be directly connected, or indirectly connected through an intermediate medium; can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0094] In the description of the present application, it should be understood that the terms "upper", "lower", "vertical", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0095] The terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features.

[0096] The embodiments of the present application are described in detail above with reference to the drawings, but the present application is not limited to the described embodiments. For those skilled in the art, various changes, modifications, replacements and variations of the embodiments can be made without departing from the principles and spirits of the present application, and still fall within the protection scope of the present application.

Claims

1. An embedded fan-out package structure, characterized by: The application relates to a fan-out package embedded in an FCBGA substrate, wherein a Si interposer chip and a redistribution layer are electrically connected and embedded in the fan-out package, the redistribution layer is arranged on the surface of the Si interposer chip, and surface contacts of the redistribution layer form first metal bumps; the FCBGA substrate comprises a core layer and at least two layers of build-up boards stacked on the surface of the core layer, and the build-up boards are electrically connected through laser drilling and filling of electroplated metal in holes. When the fan-out package is embedded in the FCBGA substrate, the first metal bumps on the surface of the fan-out package and the electroplated metal on the surface of the FCBGA substrate are exposed on the surface of the build-up board. The upper surface and the lower surface of the core layer are respectively laminated with a plurality of layers of build-up boards, and each layer of the build-up board comprises an ABF build-up film and a circuit formed on the surface of the ABF build-up film. The build-up board on the upper surface of the FCBGA substrate corresponds to the fan-out package to form a cavity, and a gap between the fan-out package and the cavity is filled with resin. The fan-out package is designed with high-density wiring, and the line width and line spacing of the RDL are between 30 microns and 1.5 microns.

2. The embedded fan-out package structure of claim 1, wherein: Second metal bumps are formed on the surface contacts of the Si interposer chip, and a plurality of layers of the redistribution layer are arranged on the upper surface of the Si interposer chip and are electrically connected with the second metal bumps.

3. The embedded fan-out package structure of claim 2, wherein: The line width and line spacing of the redistribution layer are between 30 microns and 1.5 microns.

4. The embedded fan-out package structure of claim 1, wherein: The bottom of the build-up board on the lower surface of the FCBGA substrate is provided with tin ball pads.

5. The embedded fan-out package structure of claim 1, wherein: The core layer is provided with a through hole, and the upper surface and the lower surface of the core layer form a circuit and are conductive through the through hole.

6. The embedded fan-out package structure of claim 1, wherein: The upper surface of the FCBGA substrate is provided with tin-copper bumps for electrically connecting memory chips, processor chips or logic chips.

7. The flip-chip fan-out package structure of claim 6, wherein: The gap between the upper surface of the FCBGA substrate and the memory chips, the processor chips or the logic chips to be mounted is filled with underfill and is provided with a heat sink.

8. A manufacturing method for manufacturing the embedded fan-out package structure according to any one of claims 1 to 7, characterized by, The manufacturing method comprises the following steps: A fan-out package is manufactured, the fan-out package is electrically connected and embedded with a Si interposer chip and a redistribution layer, the redistribution layer is arranged on the surface of the Si interposer chip, and surface contacts of the redistribution layer form first metal bumps. An FCBGA substrate is manufactured, a plurality of layers of build-up boards are laminated on the upper surface and the lower surface of the core layer of the FCBGA substrate, and the build-up boards are electrically connected through laser drilling and filling of electroplated metal in holes. A cavity is formed in the build-up board on the upper surface of the FCBGA substrate, the fan-out package is placed in the cavity by using a chip mounter, and the first metal bumps face upwards. The build-up board is continuously manufactured on the upper surface of the fan-out package and the FCBGA substrate to form a package, and the first metal bumps and the electroplated metal in the build-up board are exposed. Tin ball pads are manufactured on the bottom of the build-up board on the lower surface of the FCBGA substrate.

9. The production method according to claim 8, wherein The steps of manufacturing the fan-out package comprise the following steps: A Si interposer chip is adhered to a carrier, and second metal bumps are arranged on the surface contacts of the Si interposer chip. Mold resin on the Si interposer chip to continue packaging, grind resin to expose the second metal bump; On the resin surface, wire redistribution layer, the redistribution layer is electrically connected with the second metal bump; On the upper surface of the redistribution layer, set the first metal bump; Remove the carrier, cut into a single fan-out package.

10. The manufacturing method according to claim 8, wherein The core layer of the FCBGA substrate is made by the following steps, including: Take glass fiber and resin as the intermediate layer of the core layer, combine the upper and lower surfaces of the intermediate layer with copper foil respectively; Open a via on the core layer and plate copper in the via; Etch to remove the copper foil outside the circuit part, form a circuit on the upper and lower surfaces of the core layer and conduct through the via.

11. The manufacturing method according to claim 8, wherein The steps of pressing the multilayer build-up board on the upper and lower surfaces of the core layer of the FCBGA substrate include: Press ABF build-up film on the upper and lower surfaces of the core layer respectively, expose the circuit pattern on the surface of the ABF build-up film and form a circuit by developing etching and copper plating treatment; Repeat the process of pressing ABF build-up film and forming circuit by copper plating for multiple times to stack the build-up, use the blind hole filled with electroplated copper to electrically connect the copper wires of each layer of circuit, and use laser drilling to form the blind hole.

12. The manufacturing method according to claim 8, wherein After the step of making tin ball pads on the bottom of the build-up board on the lower surface of the FCBGA substrate, it further includes the step of cutting into a single FCBGA substrate.

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