Semiconductor structure

Abstract

A semiconductor structure includes a substrate including wiring structures, first and second semiconductor dies disposed above the substrate, and a multi-terminal capacitor structure embedded in the substrate. The multi-terminal capacitor structure includes first positive and ground terminals electrically coupled to the first semiconductor die through the wiring structures, and second positive and ground terminals electrically coupled to the second semiconductor die through the wiring structures. The semiconductor structure employs a multi-terminal capacitor structure including multiple capacitors and multiple terminals, and the multi-terminal capacitor structure is embedded in the substrate. Accordingly, the semiconductor structure can reduce the space occupied by the capacitors, and can increase the conductive structures remaining on the substrate. Thus, the semiconductor structure can increase design flexibility, and can be designed more easily. The semiconductor structure can also provide an improvement in semiconductor package performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] Power system design is becoming increasingly challenging because high-performance integrated circuits need to deliver large currents at relatively low supply voltages at high frequencies. Decoupling capacitors can be used as temporary charge reservoirs to prevent momentary fluctuations in the supply voltage. Decoupling capacitors are becoming increasingly important for reducing power supply noise during the operation of digital circuits, such as those with many transistors alternating between on and off states.

[0003] While existing semiconductor structures are generally sufficient, they are not satisfactory in every respect. For example, integrating decoupling capacitors is challenging because multiple capacitors must be used for different power domains of different semiconductor components. For instance, a central processing unit (CPU) might require one decoupling capacitor, while a high-performance system-on-chip (SoC) chip might need five to ten. Therefore, further improvements to semiconductor structures are needed to provide design flexibility. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor structure to solve the problems or deficiencies of the prior art.

[0005] According to a first aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0006] Substrate, including wiring structure;

[0007] A first semiconductor die and a second semiconductor die are disposed above the substrate; and

[0008] A multi-terminal capacitor structure is embedded in the substrate, and the multi-terminal capacitor structure includes:

[0009] The first positive terminal and the first ground terminal are electrically coupled to the first semiconductor die through the wiring structure; and

[0010] The second positive terminal and the second ground terminal are electrically coupled to the second semiconductor die through the wiring structure.

[0011] According to a second aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0012] substrate;

[0013] A packaging structure is disposed above the substrate and includes a first semiconductor die having a first power domain and a second semiconductor die having a second power domain, the second power domain being different from the first power domain; and

[0014] A multi-terminal capacitor structure is embedded in the substrate, and the multi-terminal capacitor structure includes:

[0015] A first multi-terminal capacitor includes a first positive terminal electrically coupled to the first power domain and a first ground terminal; and

[0016] The second multi-terminal capacitor includes a second positive terminal and a second ground terminal electrically coupled to the second power supply domain.

[0017] The semiconductor structure of the present invention includes: a substrate with a wiring structure; a first semiconductor die and a second semiconductor die disposed above the substrate; and a multi-terminal capacitor structure embedded in the substrate. The multi-terminal capacitor structure includes: a first positive terminal and a first ground terminal electrically coupled to the first semiconductor die via the wiring structure; and a second positive terminal and a second ground terminal electrically coupled to the second semiconductor die via the wiring structure. Compared to using separate capacitors for different voltage domains of different semiconductors, the present invention employs a multi-terminal capacitor structure including multiple capacitors and multiple terminals, with the multi-terminal capacitor structure embedded in the substrate. Therefore, the present invention can reduce the space occupied by the capacitors and increase the conductive structure retained on the substrate. Thus, the present invention can increase design flexibility and is easier to design. The present invention can also provide improved semiconductor packaging performance. Attached Figure Description

[0018] Figure 1 This is a cross-sectional view of an exemplary semiconductor structure according to some embodiments;

[0019] Figure 2 This is a cross-sectional view of an exemplary semiconductor structure according to some embodiments;

[0020] Figure 3 This is a cross-sectional view of an exemplary semiconductor structure according to some embodiments;

[0021] Figure 4A and 4B This is a top view of a multi-terminal capacitor structure based on an exemplary semiconductor structure according to some embodiments;

[0022] Figure 5A , 5B 5C is a conceptual diagram of the terminals of a multi-terminal capacitor structure according to some embodiments of an exemplary semiconductor structure; and

[0023] Figure 6 This is a cross-sectional view of a multi-terminal capacitor structure based on an exemplary semiconductor structure according to some embodiments. Detailed Implementation

[0024] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0025] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0026] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0027] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0028] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0029] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0030] Semiconductor structures are described according to some embodiments of the present invention. The semiconductor structures include multi-terminal capacitor structures having multiple terminals electrically coupled to different power domains to reduce footprint and improve design flexibility. Furthermore, the multi-terminal capacitor structure is embedded within a substrate, which can further reduce footprint.

[0031] Figure 1 This is a cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. Additional features may be added to the semiconductor structure 100. For different embodiments, some features described below may be replaced or eliminated. For simplicity, only a portion of the semiconductor structure 100 is shown.

[0032] like Figure 1As shown, according to some embodiments, the semiconductor structure 100 includes a substrate 102. The substrate 102 may have a wiring structure therein. In some embodiments, the wiring structure in the substrate 102 includes a conductive layer, conductive vias, conductive pillars, or combinations thereof. The wiring structure in the substrate 102 may be formed of a metal, such as copper, tungsten, or combinations thereof.

[0033] The wiring structure in substrate 102 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer is formed of an organic material such as a polymer substrate, an organic material such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. Substrate 102 may have a first surface and a second surface opposite to the first surface. It should be noted that the configuration of substrate 102 shown in the figures is merely exemplary and is not intended to limit the invention. Any desired semiconductor element can be formed in and on substrate 102. However, for the sake of simplicity, only a flat substrate 102 is shown.

[0034] like Figure 1 As shown, according to some embodiments, the semiconductor structure 100 includes a plurality of conductive structures 104. The conductive structures 104 may be disposed on a first surface of the substrate 102 and electrically coupled to a wiring structure of the substrate 102. In some embodiments, the conductive structures 104 are formed of a metal, such as copper, tungsten, or combinations thereof. The conductive structures 104 may be microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof.

[0035] According to some embodiments, the semiconductor structure 100 includes a package structure 110, which includes a first semiconductor die 110a, a second semiconductor die 110b, and a third semiconductor die 110c. The package structure 110 may be disposed on a second surface of the substrate 102. The first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may be electrically coupled to the wiring structure of the substrate 102.

[0036] Although the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c are arranged in one package structure as shown in the figure, the present invention is not limited thereto. For example, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c can be arranged in different package structures.

[0037] According to some embodiments, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c each independently include a SoC die, a logic device, a memory device, a radio frequency (RF) device, or any combination thereof. For example, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may each independently include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) chip, a global positioning system (GPS) device, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (I / O) chip, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high-bandwidth memory (HBM), or any combination thereof.

[0038] According to some other embodiments, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c can be different functional circuits or different cores in the die, and they can use different power domains.

[0039] The first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may have different power domains (or power supply domains). According to some embodiments, the semiconductor structure 100 includes a first capacitor 106a, a second capacitor 106b, and a third capacitor 106c for the semiconductor dies 110a, 110b, and 110c, respectively, to reduce the system current resistance (IR) drop.

[0040] According to some embodiments, the semiconductor structure 100 includes a plurality of interconnects 108 that electrically couple a first capacitor 106a to a first semiconductor die 110a, a second capacitor 106b to a second semiconductor die 110b, and a third capacitor 106c to a third semiconductor die 110c. The interconnects 108 may include bump structures, wiring structures of the substrate 102, or other suitable interconnects.

[0041] The first capacitor 106a, the second capacitor 106b, and the third capacitor 106c each occupy space. For example... Figure 1 As shown, the first capacitor 106a and the third capacitor 106c can be disposed on the die side, while the second capacitor 106b can be disposed on the pad side. The die-side capacitors (DSCs) 106a and 106c can increase the thickness of the semiconductor structure 100 and can occupy areas that would otherwise be used for active circuitry. The land-side capacitor (LSC) 106b can occupy the area of ​​the conductive structure 104. With the increasing demand for more functionality and smaller devices, this presents challenges for integrating different capacitors for different semiconductor components. Therefore, the present invention provides another embodiment to address the aforementioned problems.

[0042] Figure 2 This is a cross-sectional view of a semiconductor structure 200 according to some other embodiments of the present invention. It should be noted that the semiconductor structure 200 may include... Figure 1 Components identical or similar to the semiconductor structure 100 shown are not described further for simplicity. Figure 1 Compared to the embodiments in which the semiconductor structure 100 includes a plurality of capacitors disposed on the die side and / or the pad side, the following embodiments will... Figure 1 These capacitors are replaced with multi-terminal capacitor structures in the substrate to reduce the space occupied.

[0043] like Figure 2 As shown, according to some embodiments, semiconductor structure 200 includes a multi-terminal capacitor structure 206. Multi-terminal capacitor structure 206 may be a system-on-a-chip (SoC) capacitor, a silicon capacitor, or any suitable capacitor. Multi-terminal capacitor structure 206 may include positive terminals and a ground terminal for a first semiconductor die 110a, a second semiconductor die 110b, and a third semiconductor die 110c. According to some embodiments, semiconductor structure 200 includes a plurality of interconnects 108 electrically coupling the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c to multi-terminal capacitor structure 206.

[0044] Different power domains of the semiconductor die can share a single multi-terminal capacitor structure 206. Therefore, it is not necessary to use a separate capacitor for each different voltage design. Furthermore, since the multi-terminal capacitor structure 206 is embedded within the substrate 102, the footprint and height of the semiconductor structure 200 can be reduced, and more conductive structure 104 can be retained. As a result, design flexibility is provided.

[0045] like Figure 2 As shown, the multi-terminal capacitor structure 206 can partially overlap the package structure 110 in a direction substantially perpendicular to the first surface of the substrate 102. Figure 2 As shown, although three semiconductor chips (first semiconductor chip 110a, second semiconductor chip 110b, and third semiconductor chip 110c) share a single multi-terminal capacitor structure 206, the present invention is not limited thereto. For example, two semiconductor chips may share the multi-terminal capacitor structure 206. Alternatively, two or more multi-terminal capacitor structures may be used for multiple semiconductor chips.

[0046] According to some embodiments, the semiconductor structure 200 also includes one or more passive components (not shown), such as resistors, capacitors, inductors, etc., or combinations thereof. For example, passive elements may be included in the package structure 110 and / or disposed on a first surface (the upper surface in the figure) of the substrate 102.

[0047] Figure 3 This is a cross-sectional view of a semiconductor structure 300 according to some embodiments of the present invention. It should be noted that the semiconductor structure 300 may include... Figure 2 The semiconductor structure 200 shown contains the same or similar elements, which will not be described again for simplicity. In the following embodiments, a substrate having an embedded multi-terminal capacitor structure will be further described.

[0048] like Figure 3 As shown, according to some embodiments, the semiconductor structure 30 includes a printed circuit board (PCB) 302 and a substrate 102 disposed above the PCB 302. The PCB 302 may have wiring structures (not shown) therein, which may include conductive layers, conductive vias, conductive pillars, or combinations thereof. The wiring structures in the PCB 302 may be formed of metal, such as copper, tungsten, or combinations thereof.

[0049] The wiring structure in PCB 302 can be disposed in an IMD layer (not shown). In some embodiments, the IMD layer is formed of organic materials such as polymer substrates, inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., or combinations thereof. Any desired semiconductor element can be formed in and on PCB 302. However, for the sake of simplicity, only a flat PCB 302 is shown.

[0050] The wiring structure in substrate 102 can be electrically coupled to the wiring structure in PCB 302 through multiple conductive structures 104. The wiring structure in substrate 102 may include conductive layers, conductive vias, conductive pillars, or combinations thereof. In some embodiments, the wiring structure in substrate 102 includes a first conductive layer 305 and a second conductive layer 307, and multiple conductive vias 306 electrically connect the conductive structures 104 to the first conductive layer 305 and electrically connect the first conductive layer 305 and the second conductive layer 307. In one embodiment, the first conductive layer 305 and the second conductive layer 307 may not be electrically connected to the multi-terminal capacitor structure 206. In another embodiment, the multi-terminal capacitor structure 206 may be electrically connected to the first conductive layer 305 and the second conductive layer 307, for example, the ground terminal in the multi-terminal capacitor structure 206 may be electrically connected to a ground terminal through the first conductive layer 305 and the second conductive layer 307.

[0051] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a multi-terminal capacitor structure 206 disposed in the substrate 102. The multi-terminal capacitor structure 206 may be substantially aligned with the first conductive layer 305, for example, the upper surface of the multi-terminal capacitor structure 206 may be flush with the upper surface of the first conductive layer 305, or the lower surface of the multi-terminal capacitor structure 206 may be flush with the lower surface of the first conductive layer 305. A second conductive layer 307 may extend above the multi-terminal capacitor structure 206 and the first conductive layer 305. The second conductive layer 307 may be electrically coupled to the multi-terminal capacitor structure 206 through a conductive via 306. Wiring structures in the substrate 102 may also have conductive layers (not shown) extending below the multi-terminal capacitor structure 206 and the first conductive layer 305.

[0052] In some embodiments, the substrate 102 includes an insulating core (not shown), such as a glass fiber reinforced resin core, to prevent warping of the substrate 102. In embodiments where the substrate 102 includes a core (insulating core or core), the multi-terminal capacitor structure 206 can be disposed in the core (or core) of the substrate 102, i.e., placed in the core position. This can both enhance the mechanical strength of the substrate and further protect the multi-terminal capacitor structure, thereby achieving all-round protection while enhancing the strength of the substrate. Alternatively, the multi-terminal capacitor structure 206 can be disposed above the core (or core) and substantially aligned with one of the conductive layers.

[0053] like Figure 3 As shown, according to some embodiments, the multi-terminal capacitor structure 206 and the wiring structure in the substrate 102 are disposed in the IMD layer 304. In some embodiments, the IMD layer 304 is formed of organic materials (e.g., polymer substrates), inorganic materials (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.), or combinations thereof.

[0054] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a packaging structure 310 disposed above the substrate 102. The packaging structure 310 may be similar to... Figure 2 The encapsulation structure 110 shown will not be described in detail here. The encapsulation structure 310 may partially overlap the multi-terminal capacitor structure 206, the second conductive layer 307, and the conductive via 306 in a direction substantially perpendicular to the first surface of the substrate 102.

[0055] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a plurality of conductive structures 308 disposed between the package structure 310 and the substrate 102. The conductive structures 308 can electrically couple the package structure 310 to the wiring structure of the substrate 102. In some embodiments, the conductive structures 308 are formed of metal, such as copper, tungsten, or combinations thereof. The conductive structures 308 can be microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof.

[0056] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a first semiconductor die 110a, a second semiconductor die 110b, and a third semiconductor die 110c in a package structure 310. The first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c can be similar to Figure 2The first semiconductor die 110a, the second semiconductor die 110b, and / or the third semiconductor die 110c shown are not repeated. According to some embodiments, the package structure 310 also includes one or more passive elements (not shown), such as resistors, capacitors, inductors, etc., or combinations thereof.

[0057] The first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c can be electrically coupled to the wiring structure of the substrate 102 through the conductive structure 308, and are electrically coupled to the multi-terminal capacitor structure 206 through the wiring structure of the substrate 102 and the conductive structure 308. Specifically, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c can be electrically coupled to the multi-terminal capacitor structure 206 through the second conductive layer 307, the conductive via 306, and the conductive structure 308. Specifically, the first semiconductor die 110a can be electrically connected to the multi-terminal capacitor structure 206 through the first conductive structure in the conductive structure 308 and the first wiring structure in the wiring structure of the substrate 102 (e.g., including a first conductive via, a conductive layer, etc.). The second semiconductor die 110b can be electrically connected to the multi-terminal capacitor structure 206 through the second conductive structure in the conductive structure 308 and the second wiring structure in the wiring structure of the substrate 102 (e.g., including a second conductive via). The third semiconductor die 110c can be electrically connected to the multi-terminal capacitor structure 206 through the third conductive structure in the conductive structure 308 and the third wiring structure in the wiring structure of the substrate 102 (e.g., including a third conductive via). The first conductive structure, the second conductive structure, and the third conductive structure can be independent of each other, and the first wiring structure, the second wiring structure, and the third wiring structure can be independent of each other. One or more of the first wiring structure, the second wiring structure, and the third wiring structure may include structures such as a first conductive layer 305, a conductive via 306 (or other conductive vias, etc.), and a second conductive layer 307, etc., within the substrate 102.

[0058] The multi-terminal capacitor structure 206 may include positive terminals and a ground terminal for the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c to reduce the equivalent series resistor (ESR) and equivalent series inductance (ESL) to reduce the system IR voltage drop. Each of the multi-terminal capacitors for the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may include one positive terminal and one ground terminal.

[0059] The first semiconductor die 110a can be electrically coupled to the first positive terminal V1 and the first ground terminal G1. The second semiconductor die 110b can be electrically coupled to the second positive terminal V2 and the second ground terminal G2. The third semiconductor die 110c can be electrically coupled to the third positive terminal V3 and the third ground terminal G3. In one embodiment, the multi-terminal capacitor structure 206 may include a plurality of multi-terminal capacitors (not shown) for the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c, which may be referred to as the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor, respectively. Specifically, for example, the first semiconductor die 110a can be electrically coupled to the first multi-terminal capacitor through the first positive terminal V1 and the first ground terminal G1, the first set of conductive structures 308, and the first set of wiring structures in the substrate 102. The second semiconductor die 110b can be electrically coupled to the second multi-terminal capacitor through the second positive terminal V2 and the second ground terminal G2, the second set of conductive structures 308, and the second set of wiring structures in the substrate 102. The third semiconductor die 110c can be electrically coupled to the third multi-terminal capacitor via the third positive terminal V3, the third ground terminal G3, the third set of conductive structures 308, and the third set of wiring structures in the substrate 102. The first, second, and third sets of wiring structures are independent of each other and are not electrically connected (e.g., electrically isolated). Similarly, the first, second, and third sets of conductive structures are independent of each other and are not electrically connected (e.g., electrically isolated). Thus, each semiconductor die is independently connected to an independent multi-terminal capacitor (e.g., the first multi-terminal capacitor, the second multi-terminal capacitor, etc.) and operates independently. Of course, if required, the various multi-terminal capacitors can also be electrically connected (e.g., two multi-terminal capacitors connected to a common voltage terminal or a common ground terminal, etc., which can be achieved through the interconnection between wiring structures, the interconnection between conductive structures 114, or the interconnection between terminals), depending on specific needs, and this invention does not impose any limitations. Furthermore, the number of multi-terminal capacitors can be freely increased or decreased as needed. The above are just examples; the quantity of each component can be freely increased or decreased according to embodiments of the present invention. Figure 3In this embodiment, the multi-terminal capacitor structure 206 has three capacitors, which are electrically connected to the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c, respectively, providing different voltage domains. The three capacitors in the multi-terminal capacitor structure 206 may not be electrically connected to each other, or each may have a terminal connected to a common ground or a terminal connected to the same voltage. The three capacitors operate independently and are integrated in the multi-terminal capacitor structure 206. Of course, the multi-terminal capacitor structure 206 can have more capacitors, all of which can operate independently to meet different capacitance requirements. Furthermore, in this embodiment, the number of semiconductor dies can be four, five, or more, and the number of multi-terminal capacitors in the multi-terminal capacitor structure can be four, five, or more; the number of semiconductor dies and the number of multi-terminal capacitors need not be the same, for example, there can be more semiconductor dies or more multi-terminal capacitors.

[0060] like Figure 3 As shown, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c are arranged in a row or a line, which is shown for illustrative purposes only. For example, the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may be stacked vertically. Similarly, the first positive terminal V1, the first ground terminal G1, the second positive terminal V2, the second ground terminal G2, the third positive terminal V3, and the third ground terminal G3 are also shown for illustrative purposes only. Some exemplary configurations are described in the following paragraphs.

[0061] Figure 4A This is a top view of a multi-terminal capacitor structure 400a according to some embodiments. It is worth noting that the multi-terminal capacitor structure 400a may include... Figure 3 The components of the multi-terminal capacitor structure 206 of the semiconductor structure 300 shown are the same or similar, and for simplicity, these components will not be discussed in detail.

[0062] In some embodiments, the first multi-terminal capacitor 401 includes a first positive terminal V1 and a first ground terminal G1, the second multi-terminal capacitor 402 includes a second positive terminal V2 and a second ground terminal G2, and the third multi-terminal capacitor 403 includes a third positive terminal V3 and a third ground terminal G3. The multi-terminal capacitor structure 206 also includes some other terminals shown for illustrative purposes only. Two adjacent multi-terminal capacitors 401, 402, 403 and their terminals may be arranged side-by-side.

[0063] like Figure 4AAs shown, the first positive terminal V1, the second grounding terminal G2, and the third positive terminal V3 can be arranged along the first line, and the third grounding terminal G3 can be arranged along the second line. The first line can be substantially parallel to the second line. Figure 4A In this embodiment, the two electrodes of each multi-terminal capacitor are connected to different locations to accommodate different needs. Alternatively, at least two of the multi-terminal capacitors may have their two electrodes connected to the same voltage terminal, depending on design requirements.

[0064] According to some embodiments, Figure 5A A conceptual diagram of a multi-terminal capacitor structure 400a is shown. A first multi-terminal capacitor (including a first positive terminal V1 and a first ground terminal G1), a second multi-terminal capacitor (including a second positive terminal V2 and a second ground terminal G2), and a third multi-terminal capacitor (including a third positive terminal V3 and a third ground terminal G3) can be separate. The first positive terminal V1, the second positive terminal V2, and the third positive terminal V3 can be electrically isolated from each other (electrically isolated or electrically insulated). The first ground terminal G1, the second ground terminal G2, and the third ground terminal G3 can be electrically isolated from each other. Specifically, the first, second, and third multi-terminal capacitors can be electrically isolated from each other.

[0065] Figure 4B This is a top view of a multi-terminal capacitor structure 400b according to some embodiments. It should be noted that the multi-terminal capacitor structure 400b may include... Figure 4B The components shown in the multi-terminal capacitor structure 400a are the same as or similar to those in the multi-terminal capacitor structure 400a. For simplicity, these components will not be discussed in detail.

[0066] In some embodiments, the first, second, third, and fourth positive terminals are equal (equal voltage), and can be referred to as voltage V4. In some embodiments, the first, second, third, and fourth ground terminals are equal (equal voltage), and can be referred to as voltage G4. Adjacent terminals can be arranged side by side. Adjacent two terminals in a multi-terminal capacitor including these terminals can also be arranged side by side.

[0067] like Figure 4B As shown, the first positive terminal, the second positive terminal, the third positive terminal, and the fourth positive terminal V4 can be arranged along the first line, and the first ground terminal, the second ground terminal, the third ground terminal, and the fourth ground terminal G4 can be arranged along the second line. The first line can be substantially parallel to the second line. Figure 4BIn one embodiment, one of the two electrodes of a plurality of multi-terminal capacitors is connected to the same reference voltage, while the other electrode is connected to another identical reference voltage. For example, one electrode is connected to voltage V4, and the other electrode is connected to voltage G4. Alternatively, the two electrodes of at least one multi-terminal capacitor may be connected differently from the two electrodes of the other multi-terminal capacitors (e.g., using...). Figure 4A Implementation examples and Figure 4B (The embodiments may be used in combination or in part, depending on the design requirements.) Figures 4A-4B Examples of different connections between the two electrodes (or terminals) of each capacitor in a multi-terminal capacitor structure 206 are shown. The two electrodes (or terminals) of each capacitor can also have other connection methods, and are not limited to these. Figures 4A-4B As shown, in the multi-terminal capacitor structure 206, the two electrodes (or terminals) of each capacitor can be freely electrically connected according to different needs.

[0068] According to some embodiments, in Figure 5B The diagram shows a conceptual diagram of the six terminals of a multi-terminal capacitor structure 400b. The first positive terminal, the second positive terminal, and the third positive terminal V4 can be electrically coupled to each other. The first ground terminal, the second ground terminal, and the third ground terminal G4 can also be electrically coupled to each other. That is, the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor can be electrically coupled to each other.

[0069] Figure 5C This is a conceptual diagram of a multi-terminal capacitor structure according to some embodiments. In some embodiments, the first terminal includes a first positive terminal V1 and a first ground terminal, the second terminal includes a second positive terminal V2 and a second ground terminal, and the third terminal includes a third positive terminal V3 and a third ground terminal. The first ground terminal, the second ground terminal, and the third ground terminal can be electrically coupled to a common ground terminal G5. Figures 5A-5C Examples of different connections between the two electrodes (or terminals) of each capacitor in a multi-terminal capacitor structure 100 are shown. The two electrodes (or terminals) of each capacitor may also have other connection methods, and are not limited to these. Figures 5A-5C As shown, in the multi-terminal capacitor structure 206, the two electrodes (or terminals) of each capacitor can be freely electrically connected according to different needs. Figures 5A-5C There is no electrical connection between the two electrodes of each of the three capacitors shown, so each capacitor operates independently.

[0070] Figure 6 This is a cross-sectional view of a multi-terminal capacitor structure 600 according to some embodiments of a semiconductor structure. It should be noted that the multi-terminal capacitor structure 600 may include, with... Figure 3 The components shown in the multi-terminal capacitor structure 206 are the same as or similar to those in the multi-terminal capacitor structure 206. For simplicity, these components will not be discussed in detail.

[0071] like Figure 6 As shown, according to some embodiments, the multi-terminal capacitor structure 600 includes a semiconductor substrate (substrate) 602. The semiconductor substrate 602 may be formed of silicon, silicon-germanium, germanium, other suitable semiconductors, or combinations thereof. It should be noted that the configuration of the semiconductor substrate 602 shown in the figures is merely exemplary and is not intended to limit the invention. Any desired semiconductor element can be formed in and on the semiconductor substrate 602. However, for the sake of simplicity, only a flat semiconductor substrate 602 is shown.

[0072] like Figure 6 As shown, according to some embodiments, the multi-terminal capacitor structure 600 includes an insulating layer 604 disposed above a semiconductor substrate 602. The insulating layer 604 may cover the top surface of the semiconductor substrate 602. The insulating layer 604 may be formed of silicon oxide, silicon nitride, silicon oxynitride, other suitable insulating materials, or combinations thereof.

[0073] like Figure 6 As shown, the multi-terminal capacitor structure 600 includes a first multi-terminal capacitor 610a and a second multi-terminal capacitor 610b disposed above an insulating layer 604. The insulating layer 604 electrically isolates the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b. The multi-terminal capacitors 610a and 610b are separated from the substrate 102. Therefore, multiple multi-terminal capacitors can be grouped to form a single capacitor (i.e., the multi-terminal capacitor structure 600), which provides decoupling capacitance for different voltage domains, thereby reducing the space occupied by the capacitors. Furthermore, design flexibility can be improved, and performance enhancement can also be provided. The first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b are disposed above the insulating layer 604 and are electrically isolated from the semiconductor substrate 602.

[0074] like Figure 6As shown, according to some embodiments, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b includes conductive layers 606, 608, and 616. The conductive layers 606, 608, and 616 may be formed of metal, such as copper, tungsten, or combinations thereof. According to some embodiments, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b includes a capacitor unit 612 between conductive layers 606 and 608, and includes a plurality of conductive vias 614 between conductive layers 606 and 616 and between conductive layers 608. The conductive vias 614 may be formed of metal, such as copper, tungsten, or combinations thereof. Specifically, the capacitor unit 612 in this invention is configured such that conductive layers 606 and 608 can be two electrodes of the capacitor unit, and an insulating layer 630 (e.g., a high-k material) is present between conductive layers 606 and 608. Conductive layers 606 and 608 may include tungsten or other metals, and conductive materials 631 (e.g., polycrystalline silicon) and 632 (e.g., polycrystalline silicon) are further present between conductive layers 606 and 608. Conductive layer 608 is electrically connected to conductive material 631, and conductive layer 606 is electrically connected to conductive material 632. Insulating layer 630 surrounds conductive materials 631 and 632, and spacees conductive material 631 from conductive layer 606 and conductive material 632 from conductive layer 608, thereby forming a capacitor unit. In this invention, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b may have multiple capacitors or capacitor units. Figure 6 The examples shown are merely illustrative and not intended to limit the invention (e.g., limitations on quantity). Furthermore, the multi-terminal capacitor structure 600 of the present invention may include more multi-terminal capacitors in addition to the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b. Figure 6 The examples shown are merely illustrative and are not intended to limit the invention (e.g., limitations on quantity, etc.).

[0075] like Figure 6 As shown, according to some embodiments, the multi-terminal capacitor structure 600 includes a dielectric layer 618 disposed above an insulating layer 604 and surrounding a first multi-terminal capacitor 610a and a second multi-terminal capacitor 610b. The dielectric layer 618 may be formed of an organic material (e.g., a polymer substrate), an organic material (e.g., silicon nitride, silicon oxide, silicon oxynitride), or a combination thereof.

[0076] like Figure 6As shown, according to some embodiments, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b includes a terminal 620 disposed above and electrically coupled to the conductive layer 616. The terminal 620 may be exposed by the dielectric layer 618. The terminal 620 may be formed of a metal, such as copper, tungsten, or a combination thereof.

[0077] The terminals 620 of the first multi-terminal capacitor 610a may include a positive terminal and a ground terminal, and the capacitor unit 612 may be electrically coupled to a semiconductor die (e.g., Figure 2 The first semiconductor die 110a shown. Terminals 620 of the second multi-terminal capacitor 610b may include a positive terminal and a ground terminal, and may electrically couple capacitor cell 612 to another semiconductor die (e.g., ...). Figure 2 The second semiconductor die 110b shown. The two terminals 620 of each multi-terminal capacitor (e.g., the first multi-terminal capacitor 610a) can be the two electrodes of the capacitor. The multi-terminal capacitors (e.g., the first multi-terminal capacitor 610a, the first multi-terminal capacitor 610b, etc.) in the multi-terminal capacitor structure 600 can be arranged side by side or in an array, etc., to achieve the integration of multiple capacitors in the multi-terminal capacitor structure and meet different application requirements.

[0078] In summary, this invention employs a multi-terminal capacitor structure within a substrate. This multi-terminal capacitor structure may include positive terminals and a ground terminal for different power domains of different semiconductor dies. Compared to using individual capacitors disposed on the die side and / or pad side, this invention reduces the area and thickness occupied by the capacitor. Therefore, design flexibility is increased, and the design is easier, allowing for more conductive structures (e.g., conductive structure 104) retained on the substrate. This invention also provides improved semiconductor packaging performance. Furthermore, this invention reduces equivalent series resistance (ESR) and equivalent series inductance (ESL), thereby reducing system IR voltage drop.

[0079] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, including wiring structure; A first semiconductor die and a second semiconductor die are disposed above the substrate; as well as A multi-terminal capacitor structure is embedded in the substrate, and the multi-terminal capacitor structure includes: The first positive terminal and the first ground terminal are electrically coupled to the first semiconductor die through the wiring structure; and The second positive terminal and the second ground terminal are electrically coupled to the second semiconductor die through the wiring structure; The multi-terminal capacitor structure includes: a first multi-terminal capacitor, including the first positive terminal and the first ground terminal; and a second multi-terminal capacitor, including the second positive terminal and the second ground terminal; The first positive terminal and the second positive terminal are electrically isolated from each other, and the first positive terminal and the second positive terminal are electrically coupled to different power domains; The first semiconductor die and the second semiconductor die use different power domains, and both the first semiconductor die and the second semiconductor die are connected to the same multi-terminal capacitor structure. The multi-terminal capacitor structure further includes: a semiconductor substrate; and a first insulating layer disposed on the semiconductor substrate, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are disposed on the first insulating layer and electrically isolated from the semiconductor substrate; The first multi-terminal capacitor includes a first conductive layer disposed on the first insulating layer and a second conductive layer disposed on the first conductive layer, as well as a first conductive material, a second insulating layer and a second conductive material disposed between the first conductive layer and the second conductive layer, wherein the first conductive material is connected to the first conductive layer, the second conductive material is connected to the second conductive layer, the second insulating layer surrounds the first conductive material and the second conductive material, and the second insulating layer separates the second conductive material from the first conductive layer and also separates the first conductive material from the second conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The multi-terminal capacitor structure is disposed in the core of the substrate.

3. The semiconductor structure as described in claim 1, characterized in that, The wiring structure includes a first conductive layer and a conductive via, wherein the multi-terminal capacitor structure is substantially aligned with the first conductive layer and electrically coupled to the first semiconductor die and / or the second semiconductor die through the conductive via.

4. The semiconductor structure as described in claim 3, characterized in that, The wiring structure also includes a second conductive layer disposed on the multi-terminal capacitor structure, which electrically couples the multi-terminal capacitor structure to the first semiconductor die and / or the second semiconductor die.

5. The semiconductor structure as described in claim 1, characterized in that, The first positive terminal and the second positive terminal are arranged along a first line, and the first ground terminal and the second ground terminal are arranged along a second line, wherein the first line is substantially parallel to the second line; or, wherein the first positive terminal and the second ground terminal are arranged along a first line, and the first ground terminal and the second positive terminal are arranged along a second line, wherein the first line is substantially parallel to the second line.

6. The semiconductor structure as described in claim 1, characterized in that, The first grounding terminal and the second grounding terminal are electrically coupled to a common grounding terminal.

7. The semiconductor structure as described in claim 1, characterized in that, The first grounding terminal is electrically coupled to the second grounding terminal.

8. A semiconductor structure, characterized in that, include: substrate; A packaging structure is disposed above the substrate and includes a first semiconductor die having a first power domain and a second semiconductor die having a second power domain, the second power domain being different from the first power domain. as well as A multi-terminal capacitor structure is embedded in the substrate, and the multi-terminal capacitor structure includes: A first multi-terminal capacitor includes a first positive terminal electrically coupled to the first power domain and a first ground terminal; and The second multi-terminal capacitor includes a second positive terminal and a second ground terminal electrically coupled to the second power domain. The multi-terminal capacitor structure includes: a first multi-terminal capacitor, including the first positive terminal and the first ground terminal; and a second multi-terminal capacitor, including the second positive terminal and the second ground terminal; The first positive terminal and the second positive terminal are electrically isolated from each other, and the first positive terminal and the second positive terminal are electrically coupled to different power domains; The first semiconductor die and the second semiconductor die use different power domains, and both the first semiconductor die and the second semiconductor die are connected to the same multi-terminal capacitor structure. The multi-terminal capacitor structure further includes: a semiconductor substrate; and a first insulating layer disposed on the semiconductor substrate, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are disposed on the first insulating layer and electrically isolated from the semiconductor substrate; The first multi-terminal capacitor includes a first conductive layer disposed on the first insulating layer and a second conductive layer disposed on the first conductive layer, as well as a first conductive material, a second insulating layer and a second conductive material disposed between the first conductive layer and the second conductive layer, wherein the first conductive material is connected to the first conductive layer, the second conductive material is connected to the second conductive layer, the second insulating layer surrounds the first conductive material and the second conductive material, and the second insulating layer separates the second conductive material from the first conductive layer and also separates the first conductive material from the second conductive layer.

9. The semiconductor structure as described in claim 8, characterized in that, The multi-terminal capacitor structure also includes a third multi-terminal capacitor, which includes a third positive terminal and a third ground terminal. The first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor are electrically isolated from each other.

10. The semiconductor structure as described in claim 9, characterized in that, The first positive terminal, the second positive terminal, and the third positive terminal are arranged along a first line, and the first grounding terminal, the second grounding terminal, and the third grounding terminal are arranged along a second line; or, the first positive terminal, the second grounding terminal, and the third positive terminal are arranged along a first line, and the first grounding terminal, the second positive terminal, and the third grounding terminal are arranged along a second line.

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