Layout pattern of static random access memory and forming method thereof

Abstract

The present invention discloses a layout pattern of a static random access memory and a method for forming the same, wherein the layout pattern of the static random access memory includes at least a substrate, a plurality of fin structures located on the substrate, a plurality of gate structures located on the substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read transistor (RPD) and a second read transistor (RPG), and an additional fin structure, wherein the additional fin structure is located between the fin structure of the first access transistor (PG1) and the fin structure of the second read transistor (RPG).

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a layout pattern of the SRAM capable of reducing current variation. Background Art

[0002] An embedded static random access memory (SRAM) contains a logic circuit and an SRAM connected to the logic circuit. SRAM itself is a volatile memory cell, meaning that when the power to the SRAM is lost, the stored data is erased. SRAM stores data by utilizing the conductive state of transistors within the memory cell. SRAM is based on mutually coupled transistors, eliminating the capacitor discharge issue and requiring constant charging to maintain data. This is different from dynamic random access memory (DRAM), which is also a volatile memory and uses the charged state of capacitors to store data. SRAM has a very fast access speed, making it suitable for use as cache memory in computer systems. Summary of the Invention

[0003] A layout pattern of a static random access memory includes at least a substrate, multiple fin structures located on the substrate, multiple gate structures located on the substrate and spanning the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structure, wherein the multiple transistors include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2 and a second pull-down transistor PD2, which together form a latch circuit, a first access transistor PG1 and a second access transistor PG2 connected to the latch circuit, and a first read transistor RPD and a second read transistor RPG connected in series, wherein the gate structure included in the first read transistor RPD is connected to the gate structure of the first pull-down transistor PD1, and an additional fin structure, wherein the additional fin structure is located between the fin structure of the first access transistor PG1 and the fin structure of the second read transistor RPG.

[0004] A method for forming a layout pattern of a static random access memory includes providing a substrate, forming multiple fin structures on the substrate, forming multiple gate structures located on the substrate and spanning the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structure, wherein the multiple transistors include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2 and a second pull-down transistor PD2, which together form a latch circuit, a first access transistor PG1 and a second access transistor PG2 connected to the latch circuit, and a first read transistor RPD and a second read transistor RPG connected in series, wherein the gate structure included in the first read transistor RPD is connected to the gate structure of the first pull-down transistor PD1, and an additional fin structure is formed, wherein the additional fin structure is located between the fin structure of the first access transistor PG1 and the fin structure of the second read transistor RPG.

[0005] A layout pattern of a static random access memory includes at least a substrate, multiple fin structures located on the substrate, and multiple gate structures located on the substrate and spanning the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structure, wherein the multiple transistors include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, and a second pull-down transistor PD2, which together form a latch circuit, and a first access transistor PG1A, a second access transistor PG1B, a third access transistor PG2A, and a fourth access transistor PG2B are connected to the latch circuit, wherein the fin structure included in the first pull-down transistor PD1 includes at least one extended fin structure, wherein the distance from the fin structure of the first access transistor PG1A to the extended fin structure is equal to the distance from the fin structure of the second access transistor PG1B to the extended fin structure.

[0006] A feature of the present invention is that by forming additional or extended fin structures, the problem of excessive insulation area around specific transistors (i.e., surrounding voids) is reduced, which in turn causes increased stress. The method provided by the present invention improves device symmetry, effectively reducing the current disparity between different transistors, thereby improving SRAM quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A circuit diagram of a group of static random access memory storage cells in a static random access memory according to a first embodiment of the present invention;

[0008] Figure 2 A layout diagram of a static random access memory according to a first preferred embodiment of the present invention;

[0009] Figure 3 A layout diagram of a static random access memory according to a second preferred embodiment of the present invention;

[0010] Figure 4 A circuit diagram of a group of eight-transistor dual-port SRAM (8TDP-SRAM) memory cells in the static random access memory of the present invention;

[0011] Figure 5 A layout diagram of a static random access memory according to a third preferred embodiment of the present invention;

[0012] Figure 6 FIG. 4 is a layout diagram of a static random access memory according to a fourth preferred embodiment of the present invention.

[0013] Description of main component symbols

[0014] 10:8TRF-SRAM memory cell

[0015] 12:8TDP-SRAM memory cells

[0016] 22: Latch circuit

[0017] 24: Storage Node

[0018] 26: Storage Node

[0019] 28: Series circuit

[0020] 30: Series circuit

[0021] 52: Base

[0022] 53: Insulation layer

[0023] 54: Fin structure

[0024] 56: Gate structure

[0025] 56A: first gate structure

[0026] 56B: Second gate structure

[0027] 56C: Third gate structure

[0028] 56D: Fourth gate structure

[0029] 56E: Fifth gate structure

[0030] 56F: Sixth gate structure

[0031] 57: Connection structure

[0032] 58: Connection structure

[0033] 59: Contact

[0034] 60A: First area connection layer

[0035] 60B: Second area connection layer

[0036] 62: Contact column

[0037] 63: Contact layer

[0038] 70: Add fin structure

[0039] 72: Extended fin structure

[0040] PU1: first pull-up transistor

[0041] PU2: Second pull-up transistor

[0042] PD1: first pull-down transistor

[0043] PD2: Second pull-down transistor

[0044] PG1: first access transistor

[0045] PG2: Second access transistor

[0046] PG1A: First access transistor

[0047] PG1B: Second access transistor

[0048] PG2A: Third access transistor

[0049] PG2B: fourth access transistor

[0050] RPG: Read Transistor

[0051] RPD: Read Transistor

[0052] ID1: Current value

[0053] ID2: Current value

[0054] WL1: Character Line

[0055] WL2: Character Line

[0056] RWL: Read word line

[0057] RBL: Read bit line

[0058] BL1: First line

[0059] BL2: Second bit line

[0060] BL3: third bit line

[0061] BL4: fourth bit line

[0062] Vcc: voltage source

[0063] Vss: voltage source

[0064] X1: distance

[0065] X1': distance

[0066] X2: Distance

[0067] X2': distance DETAILED DESCRIPTION

[0068] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0069] For ease of explanation, the drawings of this invention are merely illustrative to facilitate understanding of the present invention. The detailed scales may be adjusted based on design requirements. The vertical relationships of relative components depicted in the drawings herein are understood by those skilled in the art to refer to the relative positions of the objects. Therefore, the same components can be reversed to present the same components, and this is fully understood within the scope of this specification. This is further clarified.

[0070] Please refer to Figure 1 and Figure 2 , Figure 1 FIG. 1 is a circuit diagram of a group of static random access memory storage cells in a static random access memory according to a first embodiment of the present invention. Figure 2 FIG. 1 is a layout diagram of a static random access memory according to the first preferred embodiment of the present invention.

[0071] In this embodiment, at least one 8TRF-SRAM memory cell 10 is included. The 8TRF-SRAM memory cell 10 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1, a second access transistor PG2, and two read transistors RPG and RPD connected in series. The first pull-up transistor PU1, the second pull-up transistor PU2, and the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit 22, which latches data at a storage node. In this embodiment, a source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0072] The gates of the first access transistor PG1 and the second access transistor PG2 are coupled to a word line WL1, while the sources S of the first access transistor PG1 and the second access transistor PG2 are coupled to corresponding first bit line BL1 and second bit line BL2, respectively. Furthermore, the gate of the read transistor RPG is connected to a read word line RWL, the source of the read transistor RPG is connected to a read bit line RBL, the gate of the read transistor RPD is connected to the latch circuit 22, and the drain of the read transistor RPD is connected to the voltage source Vss.

[0073] In this embodiment, if Figure 2 As shown, the 8TRF-SRAM memory cell 10 is provided on a substrate 52, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 52 can be a planar structure or provided with a plurality of fin structures 54, and a plurality of gate structures 56 are located on the substrate 52. In other embodiments of the present invention, it can also be applied to a planar SRAM, which means that there is no need to form a fin structure on the substrate, but to form a doped region in the substrate, which also falls within the scope of the present invention. In addition, it also includes a plurality of connection structures 57 and 58 located on the substrate 52, and a plurality of contacts 59, which are electrically connected to the connection structures 57 and 58 respectively. The remaining structures and operating principles of the 8TRF-SRAM belong to the known technology in the art and will not be elaborated here.

[0074] In the layout pattern of the present invention, a three-dimensional SRAM is taken as an example (ie, a fin-shaped structure 54 is formed to replace the planar doped region). Figure 2As shown, in addition to the positions where the fin structure 54, the gate structure 56, the connection structure 57, the connection structure 58 and the contact 59 are formed on the substrate 52, the rest of the substrate 52 is covered with an insulating layer 53, such as a shallow trench isolation structure (STI), to isolate the electronic components (such as transistors) to avoid short circuits. In addition, each gate structure 56 spans across a portion of the fin structure 54 to form a transistor (such as the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, the second access transistor PG2, the read transistor RPG and the read transistor RPD-). For the clarity of the drawings, the positions of the above-mentioned transistors are directly marked on Figure 2 , particularly the junction between the gate structure 56 and the fin structure 54 .

[0075] The applicant has discovered that during SRAM operation, due to differences in layout design or other factors such as energy loss, a problem may arise: the current through the first access transistor PG1 (i.e., the current flowing from source to drain, labeled ID1) and the current through the second access transistor PG2 (i.e., the current flowing from source to drain, labeled ID2) may be inconsistent. Using a 28nm 8TDP-SRAM as an example, according to the applicant's experimental results, the current ID1 through the first access transistor PG1 is approximately 7% to 13% smaller than the current ID2 through the second access transistor PG2.

[0076] One of the reasons for the above-mentioned current inconsistency is that each transistor is surrounded by an insulating layer 53, and the insulating layer 53 itself has a certain amount of stress. The applicant has found that if a transistor is surrounded by a relatively empty area, that is, there are fewer components around it, the transistor will also be subjected to more stress due to the larger area of the surrounding insulating layer 53. Figure 2Taking the embodiment of FIG1 as an example, since the read transistor RPD- needs to be connected below the first pull-down transistor PD1 (in the negative Y direction), the open area around it is larger (especially the area near the negative Y direction) to reserve sufficient area for component formation. Since the gate structure 56 is connected between the first pull-down transistor PD1 and the read transistor RPD-, there is a component, so that the insulating layer 53 does not cause significant stress on the first pull-down transistor PD1 and the read transistor RPD. However, the first access transistor PG1, which is parallel to the first pull-down transistor PD1 in the X direction, has a larger open area around it because its gate structure 56 is not connected to the gate structure 56 of the read transistor RPG. In other words, the area of the first access transistor PG1 surrounded by the insulating layer 53 is larger than the area of the second access transistor PG2 surrounded by the insulating layer 53. This results in different stresses on the first access transistor PG1 and the second access transistor PG2, which in turn affects the current value passing through and may cause current inconsistency in the SRAM device.

[0077] In order to solve the above problem, the present invention proposes an improved solution, which uses an additional fin structure to prevent the insulating layer around a specific transistor from being too large and causing more stress. Figure 3 , Figure 3 FIG2 is a layout diagram of a static random access memory according to a second preferred embodiment of the present invention. Figure 2 The layout shown differs in that an additional fin structure 70 is formed between the first access transistor PG1 and the read transistor RPG. Unlike the aforementioned fin structure 54, which is continuous (i.e., not clearly cut off from the diagram), the additional fin structure 70 is segmented. The additional fin structure 70, positioned around the first access transistor PG1, partially blocks the stress imparted by the insulating layer 53, thereby aligning the open area around the first access transistor PG1 with the open area around the second access transistor PG2.

[0078] In this embodiment, the fin structure 54 included in the first access transistor PG1 and the fin structure 54 included in the read transistor RPG are both continuous structures, while the additional fin structure 70 is a segmented structure. The additional fin structure 70 and each fin structure 54 are arranged parallel to each other (eg, along the X-axis).

[0079] Furthermore, in this embodiment, the additional fin structure 70 partially overlaps with the gate structure 56 included in the first access transistor PG1 , but the additional fin structure 70 does not overlap with the gate structure of the read transistor RPG.

[0080] In this embodiment, a plurality of patterned metal layers (ie, connection structures 57 , connection structures 58 , and contacts 59 ) are included, spanning across each of the fin structures 54 .

[0081] In this embodiment, by forming an additional fin structure, the insulating layer area (i.e., the surrounding open area) around a specific transistor is reduced, thereby reducing the stress on the transistor. The method provided by the present invention can improve the symmetry of the device and effectively reduce the current difference between different transistors, thereby improving the quality of SRAM.

[0082] The following describes various embodiments of the SRAM layout pattern and its fabrication method according to the present invention. For simplicity, the following description focuses on the differences between the embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated by identical reference numerals to facilitate comparison between the various embodiments.

[0083] The concepts proposed in the present invention can also be applied to the layout patterns of other SRAM shapes, such as an eight-transistor dual-port SRAM (8TDP-SRAM), as shown below:

[0084] Please refer to Figure 4 and Figure 5 , Figure 4 The present invention is a circuit diagram of a group of eight-transistor dual-port static random access memory (8TDP-SRAM) memory cells in the static random access memory. Figure 5 FIG. 4 is a layout diagram of a static random access memory according to the third preferred embodiment of the present invention.

[0085] like Figure 4 and Figure 5 As shown, the SRAM of the present invention preferably includes at least one group of SRAM cells, wherein each SRAM cell includes an 8-transistor dual-port SRAM cell 12 .

[0086] Please refer to Figure 4In this embodiment, each 8TDP-SRAM memory cell 12 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1A, a second access transistor PG1B, a third access transistor PG2A, and a fourth access transistor PG2B forming a flip-flop. The first and second pull-up transistors PU1 and PU2, and the first and second pull-down transistors PD1 and PD2 form a latch circuit, allowing data to be latched at the storage node 24 or 26. Furthermore, the first and second pull-up transistors PU1 and PU2 serve as active loads and can alternatively be replaced by conventional resistors as pull-up transistors. In this case, the result is a four-transistor static random access memory (4T-SRAM). In addition, in this embodiment, a source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0087] In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the 8TDP-SRAM memory cell 12 are formed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, and the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, and the fourth access transistor PG2B are formed of N-type metal oxide semiconductor (NMOS) transistors, but the present invention is not limited thereto. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the two constitute a series circuit 28, the two terminals of which are respectively coupled to a voltage source Vcc and a voltage source Vss. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 constitute another inverter, and the two constitute a series circuit 30, the two terminals of which are also respectively coupled to the voltage source Vcc and the voltage source Vss. Each of the access transistors (including the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, and the fourth access transistor PG2B) is connected to the output terminals of the two mutually coupled inverters. Each of the pull-up transistors, each of the pull-down transistors, and each of the access transistors includes a gate structure that spans at least one fin structure to form a fin transistor (FinFET).

[0088] In addition, at the storage node 24, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, as well as the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, the first access transistor PG1A, and the second access transistor PG1B are electrically connected respectively; similarly, at the storage node 26, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, as well as the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, the third access transistor PG2A, and the fourth access transistor PG2B are also electrically connected respectively. The gates of the first access transistor PG1A and the third access transistor PG2A are respectively coupled to a word line WL1, and the gates of the second access transistor PG1B and the fourth access transistor PG2B are respectively coupled to a word line WL2. The source of the first access transistor PG1A is coupled to the corresponding bit line BL1, the source of the second access transistor PG1B is coupled to the corresponding bit line BL2, the source of the third access transistor PG2A is coupled to the corresponding bit line BL3, and the source of the fourth access transistor PG2B is coupled to the corresponding bit line BL4.

[0089] Please refer to Figure 5 In this embodiment, the 8TDP-SRAM memory cell 12 is disposed on a substrate 52, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. A plurality of fin structures 54 arranged parallel to each other are disposed on the substrate 52, and shallow trench isolation (not shown) is disposed around each fin structure 54.

[0090] In addition, the substrate 52 includes a plurality of gate structures 56. Each of the aforementioned transistors (including the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, and the fourth access transistor PG2B) includes a gate structure 56 that spans over at least one fin structure 54 and constitutes each transistor.

[0091] like Figure 5 As shown, to clearly define the positions of the gate structures 56, the gate structures 56 are divided into a first gate structure 56A, a second gate structure 56B, a third gate structure 56C, a fourth gate structure 56D, a fifth gate structure 56E, and a sixth gate structure 56F. The first gate structure 56A spans the fin structure 54 to form a first access transistor PG1A; the second gate structure 56B spans the fin structure 54 to form a second access transistor PG1B; the third gate structure 56C spans the fin structure 54 to form a third access transistor PG2A; the fourth gate structure 56D spans the fin structure 54 to form a fourth access transistor PG2B; the fifth gate structure 56E spans at least two different fin structures 54 to form a second pull-up transistor PU2 and a second pull-down transistor PD2; and the sixth gate structure 56F spans at least two different fin structures 54 to form a first pull-up transistor PU1 and a first pull-down transistor PD1. It is understandable that the first to sixth gate structures 56A to 56F all belong to the gate structure 56 .

[0092] In the present invention, each gate structure 56 is arranged along a first direction (eg, X-axis), and each fin structure 54 is arranged along a second direction (eg, Y-axis). Preferably, the first direction and the second direction are perpendicular to each other.

[0093] The present invention further includes a first-region connection layer 60A and a second-region connection layer 60B, both arranged along a first direction. The first-region connection layer 60A spans over the fin structures 54 included in the first pull-up transistor PU1, the first pull-down transistor PD1, the first access transistor PG1A, and the second access transistor PG1B. The second-region connection layer 60B spans over the fin structures 54 included in the second pull-up transistor PU2, the second pull-down transistor PD2, the third access transistor PG2A, and the fourth access transistor PG2B.

[0094] In addition, the substrate 52 includes a plurality of contact pillars 62 and a contact layer 63, which connect different transistors (for example, connecting the gate of the second pull-up transistor PU2 to the drain of the first pull-up transistor PU1), or connecting each transistor to other components (for example, connecting the source of the first pull-up transistor PU1 to the voltage source Vcc). Figure 5 The components corresponding to each contact structure (such as the voltage source Vcc, the voltage source Vss, the first word line WL1, the second word line WL2, the first bit line BL1, the second bit line BL, the third bit line BL3 and the fourth bit line BL4) are directly marked on each contact column 62 or the contact layer 63 to clearly express the corresponding components of each contact column 62 and the contact layer 63.

[0095] In this embodiment, a first pull-down transistor PD1 is formed next to the second access transistor PG1B (on the right side, in the positive X direction), but no transistor is formed on the right side of the first access transistor PG1A. As a result, the fin structure 54 included in the second access transistor PG1B is connected to another adjacent fin structure ( Figure 5 The distance X1 in the figure is the distance between the fin structure 54 included in the first access transistor PG1A and the adjacent fin structure ( Figure 5 The distances (the distances in the figure x2) are different, which causes the problem of uneven stress on the transistor.

[0096] Therefore, the above improvement solution can be applied to this embodiment, please refer to Figure 6 , Figure 6 FIG4 is a layout diagram of a static random access memory according to a fourth preferred embodiment of the present invention. In this embodiment, part of the fin structure can be extended, that is, a part of the fin structure 54 included in the original first pull-down transistor PD1 is replaced with an extended fin structure 72. Therefore, the fin structure 54 included in the second access transistor PG1B is connected to the adjacent extended fin structure 72 ( Figure 6 The distance X1′) is the distance between the fin structure 54 included in the first access transistor PG1A and the adjacent extended fin structure 72 ( Figure 6 The distance X2′ in the transistors is the same, which can avoid the problem of uneven stress on the transistors and improve the quality of the SRAM.

[0097] It is worth noting that Figure 6 As shown, the fin structure of the original second pull-down transistor PD2 can also be replaced by an extended fin structure 72, so that the current passing through the third access transistor PG2A and the current passing through the fourth access transistor PG2B are close to each other. The concept is the same as above and will not be repeated here.

[0098] It is worth noting that in the layout pattern of this embodiment, for a single transistor (e.g., the first pull-down transistor PD1 or the second pull-down transistor PD2), two fin structures with different lengths are included, namely, a fin structure 54 and an extended fin structure 72, and the length of the extended fin structure 72 is greater than the length of the fin structure 54.

[0099] In summary, one feature of the present invention is that by forming an additional or extended fin structure, the problem of excessive insulation area around a particular transistor (i.e., surrounding voids) is reduced, which in turn causes increased stress. The method provided by the present invention improves device symmetry, effectively reducing the current disparity between different transistors, thereby improving SRAM quality.

[0100] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A layout pattern of a static random access memory, characterized in that: At least: substrate; a plurality of fin-like structures located on the substrate; A plurality of gate structures are located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structure, wherein the plurality of transistors include: A first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) together form a latch circuit; A first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit; as well as a first read transistor (RPD) and a second read transistor (RPG) connected in series, wherein the gate structure included in the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1); as well as An additional fin structure is provided, wherein the additional fin structure is located between the fin structure of the first access transistor (PG1) and the fin structure of the second read transistor (RPG), and the length of the additional fin structure is less than the length of the plurality of fin structures.

2. The layout pattern of claim 1, wherein the fin structure of the first access transistor (PG1) and the fin structure of the second read transistor (RPG) are both continuous structures. 3 . The layout pattern as claimed in claim 2 , wherein the additional fin structure is a segmented structure. 4 . The layout pattern as claimed in claim 1 , wherein the additional fin structure and each of the fin structures are arranged parallel to each other. 5 . The layout pattern of claim 1 , wherein the gate structure included in the second read transistor (RPG) is not connected to the gate structure of the first access transistor (PG1 ). 6 . The layout pattern of claim 1 , wherein the additional fin structure partially overlaps the gate structure of the first access transistor ( PG1 ), and the additional fin structure does not overlap the gate structure of the second read transistor (RPG). 7 . The layout pattern as claimed in claim 1 , further comprising a plurality of patterned metal layers spanning across each of the fin structures.

8. A method for forming a layout pattern of a static random access memory, comprising: providing a substrate; forming a plurality of fin-shaped structures on the substrate; A plurality of gate structures are formed on the substrate and across the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structure, wherein the plurality of transistors include: A first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) together form a latch circuit; A first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit; as well as a first read transistor (RPD) and a second read transistor (RPG) connected in series, wherein the gate structure included in the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1); as well as An additional fin structure is formed, wherein the additional fin structure is located between the fin structure of the first access transistor (PG1) and the fin structure of the second read transistor (RPG), and the length of the additional fin structure is shorter than the length of the plurality of fin structures. 9 . The method of claim 8 , wherein the fin structure of the first access transistor ( PG1 ) and the fin structure of the second read transistor (RPG) are both continuous structures. 10 . The forming method according to claim 9 , wherein the added fin-shaped structure is a segmented structure. The forming method according to claim 8 , wherein the additional fin-shaped structure and each of the fin-shaped structures are arranged parallel to each other. 12 . The method of claim 8 , wherein the gate structure included in the second read transistor (RPG) is not connected to the gate structure of the first access transistor (PG1 ). 13 . The method of claim 8 , wherein the additional fin structure partially overlaps the gate structure of the first access transistor ( PG1 ), and the additional fin structure does not overlap the gate structure of the second read transistor (RPG). 14 . The forming method according to claim 8 , further comprising a plurality of patterned metal layers spanning across each of the fin structures.

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