SRAM (Static Random Access Memory) verification method, system and equipment

Abstract

The invention discloses an SRAM (Static Random Access Memory) verification method, system and equipment, relates to the technical field of integrated circuits, and is used for solving the problems of low code reuse rate, long verification period and difficulty in defect positioning in the existing SRAM verification method. The method comprises the following steps: setting a unified virtual shell program module for a to-be-verified SRAM memory module, and packaging key attribute information of the to-be-verified SRAM memory module through macro definition parameters; distributing a serial number for the SRAM type of each SRAM memory module to be verified, and establishing a mapping relation between the serial number and the interface module; calling a corresponding excitation signal from an excitation signal library according to the serial number, and determining a corresponding target interface module through a mapping relation; and connecting a virtual shell program module of the SRAM module to be verified through the target interface module, sending an excitation signal, and triggering function verification. According to the technical scheme provided by the invention, high efficiency, compatibility and expansibility of verification can be realized, and the accuracy of a verification result is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an SRAM memory verification method, system, and device. Background Technology

[0002] In the field of integrated circuit design, functional verification of SRAM memory is a crucial step in ensuring the correctness of chip design. Currently, SRAM memory verification typically relies on verification environments customized for specific memory types. This approach has significant limitations: First, due to differences in interface protocols, storage capacity, and functional characteristics among different SRAM memories, verification engineers need to rewrite verification code for each type, resulting in extremely low code reuse and development efficiency. Second, the lack of a unified generation mechanism for functionally similar stimulus signals necessitates repetitive design, causing the verification cycle to increase linearly with the number of SRAM types. Furthermore, the analysis of verification results heavily relies on manual comparison of waveform signals, making it difficult to quickly and accurately locate design defects. These technical shortcomings collectively lead to inefficiency, poor compatibility, and complex management issues in the SRAM memory verification process.

[0003] Therefore, there is an urgent need to provide a more reliable SRAM memory verification scheme. Summary of the Invention

[0004] The purpose of this invention is to provide an SRAM memory verification method, system, and device to solve the problems of low code reuse rate, long verification cycle, and difficulty in defect location in existing SRAM memory verification methods.

[0005] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides an SRAM memory verification method, the method being applied to an SRAM memory verification system, wherein the SRAM memory verification system includes at least an SRAM memory module to be verified configured with a virtual shell program module; the method includes: A unified virtual shell program module is set up for the SRAM memory module to be verified, and the key attribute information of the SRAM memory module to be verified is encapsulated through macro definition parameters; the key attribute information includes at least the SRAM type. Assign a serial number to each SRAM type of the SRAM memory module to be verified, and establish a mapping relationship between the serial number and the interface module; Based on the serial number corresponding to the SRAM memory module to be verified, the corresponding excitation signal is retrieved from the excitation signal library, and the corresponding target interface module is determined through the mapping relationship. The virtual shell program module of the SRAM memory module to be verified is connected through the target interface module, and the excitation signal is sent to trigger the functional verification.

[0006] Optionally, the step of retrieving the corresponding excitation signal from the excitation signal library based on the serial number corresponding to the SRAM memory module to be verified, and determining the corresponding target interface module through the mapping relationship, further includes: The verification module receives information packets from all SRAM memory modules to be verified. The information packet is used to generate excitation signals for each SRAM type and store them in the excitation signal library.

[0007] Optionally, the step of sending the stimulus signal to trigger functional verification via the virtual shell program module connected to the SRAM memory module to be verified through the target interface module includes: The interface module connects to the virtual shell program module of the SRAM memory module to be verified, and preprocesses the port module integrated in the virtual shell program module; each SRAM type corresponds to one interface module. The preprocessed port module sends an excitation signal to the SRAM program module inside the SRAM memory to trigger functional verification.

[0008] Optionally, the virtual shell program module connected to the SRAM memory module to be verified through the interface module, and the preprocessing of the port module integrated in the virtual shell program module, includes: If there are idle input ports in the port module, the idle input ports will be left floating or combined for calculation. If there is an idle output port in the port module, the idle output port is set to the default state; the idle output port includes the idle output port of the unverified SRAM memory module without error correction function; the default state includes setting the idle output port to 0 or 1.

[0009] Optionally, the step of sending the stimulus signal to trigger functional verification via the virtual shell program module connected to the SRAM memory module to be verified through the target interface module includes: For read / write function verification, the virtual shell program module sends write and read commands to the SRAM program module, checks whether the returned data is consistent with the written data, and completes the verification. For SRAM memory with error correction function, a stimulus signal containing erroneous data is sent to the SRAM program module, and the verification is completed by verifying whether the SRAM memory can correctly correct and return the correct data.

[0010] Compared with existing technologies, this invention provides an SRAM memory verification method applicable to an SRAM memory verification system that includes at least one SRAM memory module configured with a virtual shell program module. The method involves setting a unified virtual shell program module for each SRAM memory module to be verified and encapsulating key attribute information of the SRAM memory module through macro-defined parameters. A serial number is assigned to each SRAM type of the SRAM memory module to be verified, and a mapping relationship is established between the serial number and the interface module. Based on the serial number of the SRAM memory module to be verified, the corresponding stimulus signal is retrieved from the stimulus signal library, and the corresponding target interface module is determined through the mapping relationship. Then, the virtual shell program module of the SRAM memory module to be verified is connected through the target interface module to send the stimulus signal and trigger functional verification. Using the solution in this invention, the external interface form of different types of SRAM memory modules is unified by the virtual shell program module, supporting the verification of multiple SRAM memories, avoiding the repetitive work of building the verification environment, and greatly improving verification efficiency. Furthermore, the entire process, from stimulus signal generation, interface module matching, port preprocessing to verification result judgment, is highly automated, reducing manual intervention and the possibility of human error. When new types of SRAM memories emerge, only the macro definition parameters of the virtual shell program module need to be modified, without requiring a large-scale reconstruction of the entire verification system. This results in high code reusability and excellent compatibility and scalability. Furthermore, effective preprocessing of idle ports avoids the introduction of interference signals, further improving the accuracy and reliability of the verification results.

[0011] In a second aspect, the present invention provides an SRAM memory verification system, wherein the system employs the SRAM memory verification method provided in the first aspect above for verification, and the system includes: Verification module, interface module, and SRAM memory module to be verified; The SRAM memory module to be verified is configured with a virtual shell program module, which encapsulates the key attribute information of the SRAM memory module to be verified through macro definition parameters; the key attribute information includes at least the SRAM type. The verification module establishes a connection with the virtual shell program module of the SRAM memory module to be verified through the interface module, and sends an excitation signal to trigger the functional verification.

[0012] Optionally, the verification module is used to generate excitation signals, manage sequence numbers, schedule interface modules and analyze responses, and adapt to different SRAM types through parameter configuration; The verification module is also used to establish and maintain the mapping relationship between the serial number and the interface module; the serial number also corresponds to the SRAM type of the SRAM memory module to be verified and the excitation signal in the excitation signal library.

[0013] Optionally, the number of interface modules is equal to the number of SRAM types; and each interface module corresponds to an SRAM interface protocol, through which the signal interaction between the verification module and the SRAM memory module to be verified is realized.

[0014] Optionally, each type of SRAM memory module to be verified encapsulates a unified virtual shell program module; the virtual shell program module integrates the SRAM's storage parameters, port modules, and functional information; The port module includes multiple input ports and multiple output ports; the input ports include at least a read / write clock port, a read / write address port, a write data port, and a control signal port; the output ports include at least a read data port and a data valid flag port. The control signal port includes at least one of the following: chip select signal port, write enable signal port, check enable signal port, and low power enable signal port; the output port includes at least one of the following: check result port, power status port, port status port, error flag port, clock synchronization signal port, and temperature monitoring signal port.

[0015] Compared with existing technologies, this invention provides an SRAM memory verification system. It includes a verification module, an interface module, and an SRAM memory module to be verified. The SRAM memory module to be verified is configured with a virtual shell program module, which encapsulates key attribute information of the SRAM memory module through macro-defined parameters. The verification module establishes a connection with the virtual shell program module of the SRAM memory module to be verified through the interface module and sends a stimulus signal to trigger functional verification. This invention unifies the external interface form of different types of SRAM memories through the virtual shell program module, enabling a single verification system to support the verification of multiple SRAM memories, avoiding the repetitive work of building verification environments, and significantly improving verification efficiency. The verification module integrates stimulus generation, serial number management, and interface scheduling functions, combined with the mapping mechanism between serial numbers and interface modules, to achieve full automation from stimulus signal generation to interface matching, reducing manual intervention and human error. When a new type of SRAM memory appears, the system can be expanded simply by modifying the macro-defined parameters of the virtual shell program module, without large-scale reconstruction of the verification environment. This results in high code reusability and demonstrates good compatibility and scalability. Furthermore, by effectively preprocessing the idle ports, the introduction of interference signals is avoided, further improving the accuracy and reliability of the verification results.

[0016] Thirdly, the present invention provides an SRAM memory verification device, the device comprising: The system includes a memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be executed by the processor; when the processor runs the computer program, it performs the SRAM memory verification method described above. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of an SRAM memory verification method provided by the present invention; Figure 2 This is a schematic diagram illustrating the complete verification process of the SRAM memory provided by the present invention; Figure 3 This invention provides a schematic diagram of an SRAM memory verification system structure. Figure 4 A schematic diagram of the virtual shell program module provided by the present invention; Figure 5 This is a schematic diagram of an SRAM memory verification device provided by the present invention. Detailed Implementation

[0018] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0019] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0020] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0021] SRAM (Static Random Access Memory) is a type of volatile memory whose basic cell structure stores data using a bistable trigger circuit composed of six transistors. SRAM memory mainly includes a storage array, a sensitive amplifier, timing control circuitry, decoding circuitry, and input / output driver modules.

[0022] The SRAM memory array is the core carrier of data storage, consisting of a large number of memory cells arranged in a row-column matrix. Each cell can store one bit of data (0 or 1), and data access and transmission are achieved through intersecting word lines (WL) and bit lines (BL / BLB). The sensitive amplifier is a key module for improving SRAM read performance. Its core function is to amplify the weak differential voltage signal (typically only tens of millivolts) read from the memory cell into a full-swing logic level to ensure reliable data identification. The timing control circuit is the "commander" of the SRAM's internal timing coordination, responsible for generating and synchronizing key signals such as clock (CLK), chip select (CS), write enable (WE), and output enable (OE), ensuring that the memory array, sensitive amplifier, and other modules work together according to strict timing logic. The decoding circuit is responsible for converting address signals to control signals and is divided into row decoders and column decoders. The row decoder converts the input row address into word line control signals, activating all memory cells in the corresponding row. The column decoder converts the column address into column select signals, selecting the path between the bit lines and the input / output driver module, thereby determining the specific location for data reading and writing. The input / output driver module acts as a "bridge" between the SRAM and external circuits, responsible for bidirectional data transmission and signal conditioning.

[0023] Traditional SRAM memory verification schemes are primarily based on a categorized, independent verification model. For different types, configurations, or functions of SRAM memory, functional verification is performed by manually building separate, cumbersome verification environments for each module. The specific methods are as follows: Setting up the verification environment involves writing dedicated verification code for specific SRAM types, including a test platform, stimulus generation module, and response checking module, and configuring interface protocols adapted to its clock, address, data, and control signal timing logic. A typical verification environment includes components such as a stimulus generator, interface driver, reference model, monitor, and assertion checker. The stimulus generator generates read and write instructions and data, the interface driver adapts to the timing requirements of the SRAM memory, the reference model calculates the expected response, the monitor captures the SRAM memory output signals, and the assertion checker compares the actual response with the expected result.

[0024] Excitation signal design: Verification personnel need to manually design the excitation signal sequence based on the functional characteristics of the SRAM memory, covering scenarios such as basic read / write operations, boundary address access, and error injection testing. The design of the excitation signals must be closely related to the specific functions of the SRAM memory, ensuring coverage of various signal interaction scenarios for its normal operation.

[0025] Port and Timing Handling: For SRAM memory input / output ports, such as clock ports, chip select signals, and write enable signals, individual timing constraints must be applied based on their type. Single-clock SRAM memories only need to handle the timing logic of a single clock domain, while dual-clock SRAM memories require synchronous coordination of read and write operations across both clock domains. Unused idle ports are typically handled with fixed levels, such as grounding or connecting to a power supply, to ensure the stability of port states in the verification environment.

[0026] The verification process is implemented in stages according to functional modules. First, basic read and write function verification is performed to ensure the correctness of data access in normal scenarios. After the basic function verification is passed, advanced function verification is then carried out.

[0027] In the process of verifying SRAM memory using the aforementioned traditional methods, the applicant discovered the following technical defects in the prior art: (1) Each type of SRAM memory requires rewriting the verification code, resulting in extremely low reuse rate; (2) Excitation signals with similar functions need to be designed repeatedly, and there is a lack of a unified excitation generation mechanism, which leads to the verification cycle increasing linearly with the increase of SRAM type; (3) The analysis of verification results relies on manual comparison of waveforms, making it difficult to quickly locate defects.

[0028] To address the shortcomings of the prior art, this invention proposes an SRAM memory verification method, system, and device. The solutions provided in the embodiments of this specification will now be described in conjunction with the accompanying drawings: like Figure 1 As shown, the present invention provides an SRAM memory verification method, which may include the following steps: Step 110: Set up a unified virtual shell program module for the SRAM memory module to be verified, and encapsulate the key attribute information of the SRAM memory module to be verified through macro definition parameters.

[0029] The key attribute information includes at least the SRAM type, and may also include the storage depth, data width, and functional information of the SRAM memory module to be verified; the functional information includes at least the error correction function.

[0030] When setting up a unified virtual shell module, a consistent virtual shell module can be configured for each type of SRAM memory module. Detailed information about the SRAM memory is precisely recorded through macro-defined parameters. For example, for a 1KB capacity, single-clock, error-correction-free SRAM memory, the macro definition of the virtual shell module is marked as "Type=Single Clock, Depth=1024, Width=8, Error Correction=None"; for a 2KB capacity, dual-clock, error-correction-free SRAM memory, it is marked as "Type=Dual Clock, Depth=2048, Width=16, Error Correction=Yes". This unified packaging method masks the internal differences between different SRAM memories, providing a foundation for subsequent general verification.

[0031] Step 110 unifies the external interface of different types of SRAM memory through the virtual shell program module, enabling a single verification system to support the verification of multiple SRAM memory types, avoiding the need to repeatedly build verification environments, and significantly improving verification efficiency.

[0032] Step 120: Assign a serial number to each SRAM type of the SRAM memory module to be verified, and establish a mapping relationship between the serial number and the interface module.

[0033] The serial number corresponds to the SRAM type, the interface module, and the excitation signal. Therefore, when assigning serial numbers and establishing interface mappings, a unique serial number can be assigned to each SRAM type of the SRAM memory module to be verified. For example, the serial number of a single-clock SRAM memory is 1, and the serial number of a dual-clock SRAM memory is 2.

[0034] Additionally, a mapping between "serial number → interface module" can be established. For example, serial number 1 corresponds to interface module A, and serial number 2 corresponds to interface module B. This allows the verification module to quickly locate the corresponding communication interface based on the serial number in the SRAM memory.

[0035] Step 130: Based on the serial number corresponding to the SRAM memory module to be verified, retrieve the corresponding excitation signal from the excitation signal library, and determine the corresponding target interface module through the mapping relationship.

[0036] In this step, the excitation signals are stored in an excitation signal library. When a specific SRAM memory needs to be verified, the verification module can retrieve the corresponding excitation signal from the library based on the SRAM memory's serial number. Simultaneously, the corresponding interface module is determined through the "serial number → interface mapping table." For example, to verify a single-clock SRAM memory with serial number 1, the verification module retrieves the single-clock read / write excitation signal from the excitation signal library and selects interface module A for connection.

[0037] Step 140: Connect the virtual shell program module of the SRAM memory module to be verified through the target interface module, send the excitation signal, and trigger the functional verification.

[0038] The verification module establishes a connection with the virtual shell program module of the SRAM memory module to be verified through the interface module, sends an excitation signal to trigger the functional verification, receives the response signal returned by the SRAM program module, and compares it with the expected result to draw a verification conclusion.

[0039] Figure 1 The method described herein is applied to an SRAM memory verification system that includes at least one SRAM memory module to be verified, configured with a virtual shell program module. It involves setting a unified virtual shell program module for each SRAM memory module to be verified and encapsulating key attribute information of the SRAM memory module through macro-defined parameters; assigning serial numbers to each SRAM type of the SRAM memory module to be verified and establishing a mapping relationship between serial numbers and interface modules; retrieving the corresponding stimulus signal from the stimulus signal library based on the serial number of the SRAM memory module to be verified, and determining the corresponding target interface module through the mapping relationship; then connecting the virtual shell program module of the SRAM memory module to be verified through the target interface module, sending the stimulus signal, and triggering functional verification. Using the scheme in this invention, the external interface form of different types of SRAM memory modules is unified by the virtual shell program module, supporting the verification of multiple SRAM memories, avoiding the repetitive work of building the verification environment, and greatly improving verification efficiency. Furthermore, the entire process, from stimulus signal generation, interface module matching, port preprocessing to verification result judgment, is highly automated, reducing manual intervention and the possibility of human error. When new types of SRAM memories emerge, only the macro definition parameters of the virtual shell program module need to be modified, without requiring a large-scale reconstruction of the entire verification system. This results in high code reusability and excellent compatibility and scalability. Furthermore, effective preprocessing of idle ports avoids the introduction of interference signals, further improving the accuracy and reliability of the verification results.

[0040] based on Figure 1In addition to the method described herein, this specification also provides some specific implementation methods of this method, which will be described below.

[0041] First, such as Figure 2 As shown, the complete verification process for SRAM memory mainly consists of two parts. The first part involves setting up a unified environment by configuring a virtual shell program module, and the second part involves automated signal interaction and verification. In the first part, setting up the unified environment, the virtual shell program module is configured first, then serial numbers are assigned and interface mappings are established, followed by the generation of an excitation signal library. In the second part, automated signal interaction and verification, excitation signals and matching interfaces are first acquired, then the SRAM memory module and port preprocessing are connected, excitation signals and functional verification are sent, and finally, response signals are used for judgment and verification conclusions.

[0042] Next, combined Figure 2 The complete process is described in detail, with each step explained in detail: The configuration of the virtual shell program module, the allocation of serial numbers, and the establishment of interface mapping have been explained in the above descriptions of steps 110 and 120, and will not be repeated here.

[0043] Based on the serial number corresponding to the SRAM memory module to be verified, the corresponding excitation signal is retrieved from the excitation signal library, and the corresponding target interface module is determined through the mapping relationship. The process may also include generating the excitation signal library beforehand.

[0044] Specifically, the verification module can receive information packets from all SRAM memory modules to be verified; then, it generates stimulus signals for each SRAM type based on the information packets and stores them in the stimulus signal library. For example, for a single-clock SRAM memory, it generates single-clock read / write stimulus signals, such as single-clock read / write stimulus signals including basic operation sequences such as address increment write and address decrement read. For SRAM memories with error correction capabilities, in addition to the basic read and write stimulus signals, stimulus signals are also generated for testing the error correction function. For example, for SRAM memories with error correction capabilities, in addition to the basic read and write stimulus signals, dedicated stimulus signals for testing the error correction function, such as single-bit flip and double-bit error injection, are also generated. These generated stimulus signals are categorized and stored in a stimulus signal library, which can preferably be implemented in the form of a database or file system.

[0045] The acquisition of the excitation signal and matching interface in Part 2 has already been discussed in the explanation of step 130 above. More specifically, the verification module can retrieve the corresponding excitation signal (single-clock read / write excitation signal) from the excitation signal library based on the serial number of the target SRAM memory (e.g., serial number 1), and simultaneously determine the corresponding interface module (interface module A) by querying the mapping table. Subsequently, the steps of connecting the SRAM memory module and port preprocessing are performed: the virtual shell program module of the target SRAM memory is connected through the selected interface module A. After establishing the connection, the port modules of the virtual shell are preprocessed: if there is an idle input port (e.g., the ECC_EN port of an SRAM without error correction function), it is left floating, i.e., not connected to any signal source, or fixed at a certain level by pull-up / pull-down resistors; if there is an idle output port (e.g., the ECC_RESULT port of an SRAM without error correction function), it is set to the default state, such as setting its output register to 0 or 1 through the initialization program. The specific parameters of port preprocessing, such as the resistance values ​​of pull-up and pull-down resistors, can be set according to the actual application.

[0046] After acquiring the excitation signal and matching interface, it is necessary to connect the SRAM memory module and port preprocessing. Specifically, the virtual shell program module of the SRAM memory module to be verified is connected through the interface module, and the port module integrated in the virtual shell program module is preprocessed, which may include: If there are idle input ports in the port module, the idle input ports will be left floating or combined for calculation. If there is an idle output port in the port module, the idle output port is set to the default state; the idle output port includes the idle output port of the unverified SRAM memory module without error correction function; the default state includes setting the idle output port to 0 or 1.

[0047] Therefore, in the connection of the SRAM memory module and port preprocessing, after connection, the port module of the virtual shell is first verified and processed. If there is an idle input port, it is left floating, that is, not connected to any signal source, or combined calculation is performed. This can avoid invalid signals interfering with the verification.

[0048] However, if there are idle output ports such as the error correction flag of an SRAM memory without error correction function, they can be set to the default state, such as 0 or 1. This setting can ensure that the port state will not affect the verification result.

[0049] The above scheme, through effective preprocessing of idle ports, avoids the introduction of interference signals, further improving the accuracy and reliability of verification results.

[0050] When sending excitation signals and performing functional verification, the following may be included: The interface module connects to the virtual shell program module of the SRAM memory module to be verified, and preprocesses the port module integrated in the virtual shell program module; each SRAM type corresponds to one interface module. The preprocessed port module sends an excitation signal to the SRAM program module inside the SRAM memory to trigger functional verification.

[0051] Furthermore, for the verification of read and write functions, the virtual shell program module sends write and read commands to the SRAM program module, checks whether the returned data is consistent with the written data, and completes the verification. For SRAM memory with error correction function, a stimulus signal containing erroneous data is sent to the SRAM program module, and the verification is completed by verifying whether the SRAM memory can correctly correct and return the correct data.

[0052] In practical applications, the process of sending the stimulus signal and verifying the function described above can be achieved by sending the first stimulus signal to the SRAM program module inside the SRAM memory through the preprocessed port, triggering the SRAM memory's functional verification. For example, for read / write function verification, an instruction to "write address 0, data 100" is sent, followed by an instruction to "read data from address 0," and the returned data is checked to see if it is 100. For SRAM memories with error correction capabilities, incorrect data is intentionally written to verify whether the SRAM memory can correctly correct and return the correct data.

[0053] Next, let's illustrate with another example: For read / write function verification, first, a command to "write to address 0x000, data 0x55AA" is sent. After waiting for at least one clock cycle, a command to "read data from address 0x000" is sent. The response analysis unit checks whether the returned data is 0x55AA. For SRAM memory with error correction, the verification module intentionally writes erroneous data to a specific address (e.g., by flipping the 3rd bit of the data), and then verifies whether the SRAM memory can correctly detect and correct the error through its error correction circuit, returning the correct data.

[0054] Finally, when judging and verifying the response signal, the response signal returned by the SRAM program module can be received and compared with the expected result. If the data read and write are consistent, the timing constraints are not violated (such as setup time and hold time meeting preset requirements), and the functional characteristics are activated normally, then the SRAM program module is determined to have passed the verification. If data misalignment, timing conflict, or functional failure occurs, an error log is recorded and the defect is located. The error log may include information such as error type, occurrence time, relevant signal waveforms, and suggested troubleshooting directions.

[0055] Based on the same approach, this invention also provides an SRAM memory verification system, which employs the SRAM memory verification method described in the foregoing embodiments. By constructing a unified verification framework and an automated verification process, it solves the bottleneck problems of low efficiency, poor compatibility, and complex management in existing SRAM memory verification methods. Figure 3 As shown, the system may include: Verification module 310, interface module 320, and SRAM memory module to be verified 330; The SRAM memory module 330 to be verified is configured with a virtual shell program module, which encapsulates the key attribute information of the SRAM memory module 330 to be verified through macro definition parameters; the key attribute information includes at least the SRAM type. The verification module 310 establishes a connection with the virtual shell program module of the SRAM memory module 330 to be verified through the interface module 320, and sends an excitation signal to trigger the functional verification.

[0056] More specifically, there is a close relationship between the verification module 310, the interface module 320, and the SRAM memory module to be verified 330, which can be summarized as a "control-adaptation-verification" mode.

[0057] The verification module 310, as the system control core, integrates stimulus generation, serial number management, interface scheduling, and response analysis functions. It supports adapting to different SRAM types of SRAM memory modules 330 to be verified through parameter configuration and acts as the coordinator of the entire verification process. The integrated stimulus generation, serial number management, and interface scheduling functions of the verification module, combined with the mapping mechanism between serial numbers and interface modules, achieve full automation from stimulus signal generation to interface matching, reducing manual intervention and minimizing human error.

[0058] Interface module 320: Serves as a bridge between verification module 310 and SRAM memory module 330 to be verified. The number of interface modules is consistent with the number of SRAM types to be verified. Each interface module corresponds to an SRAM interface protocol (such as single-clock interface, dual-clock interface, verification interface, etc.) and is used to realize signal interaction between verification module and SRAM memory module 330 to be verified, so that verification module 310 can communicate effectively with SRAM memory modules 330 to be verified with different protocols.

[0059] The SRAM memory module 330 to be verified is the object of verification. The verification module 310 establishes a connection with the SRAM memory module 330 through an interface module and sends corresponding stimulus signals to the program module in the SRAM memory to verify the SRAM memory module 330. Each SRAM memory module 330 to be verified is configured with a virtual shell program module. This module encapsulates key information such as the type of SRAM memory, storage depth, data width, and whether it has special functions through macro-defined parameters, providing a standardized interactive interface for the verification module, enabling the verification process to proceed smoothly. When a new type of SRAM memory appears, the system can be expanded simply by modifying the macro-defined parameters of the virtual shell program module, without the need for a large-scale reconstruction of the verification environment, demonstrating good compatibility and scalability.

[0060] based on Figure 3 The system may also include specific implementation units: First, we combine the virtual shell program module configured for each SRAM memory module 330 to be verified with... Figure 4 Explanation: like Figure 4 As shown, the virtual shell program module includes an SRAM program module; The virtual shell program module integrates SRAM storage parameters, port modules, and functional information; Figure 4 The numbers “1, 2, 3, 4” represent serial numbers.

[0061] The port module includes multiple input ports and multiple output ports; the input ports include at least a read / write clock port, a read / write address port, a write data port, and a control signal port; the output ports include at least a read data port and a data valid flag port. The control signal port includes at least one of the following: chip select signal port, write enable signal port, check enable signal port, and low power enable signal port; the output port includes at least one of the following: check result port, power status port, port status port, error flag port, clock synchronization signal port, and temperature monitoring signal port.

[0062] As an optional embodiment, the port module may include 12 input ports: read / write clock (CLK_R / CLK_W), read / write address (ADDR_R / ADDR_W), write data (DATA_W), control signals (chip select CS, write enable WE, parity enable ECC_EN, low power enable LP_EN), and configuration parameters (depth selection DEP_SEL, width selection WID_SEL). The port module can also include 8 output ports: read data (DATA_R), data valid flag (DATA_VAL), verification result (ECC_RESULT), power consumption status (PWR_STATE), port status (PORT_STATUS), error flag (ERR_FLAG), clock synchronization signal (CLK_SYNC), and temperature monitoring signal (TEMP_MON). (The number of ports can be adjusted according to the type of SRAM to be tested.)

[0063] As an optional embodiment, the verification module 310 can be implemented using a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and can internally integrate a stimulus generation unit, a sequence number management unit, an interface scheduling unit, and a response analysis unit. The stimulus generation unit is configured to generate test vectors according to a predefined algorithm; the sequence number management unit is used to assign and maintain unique identifiers for each SRAM memory type; the interface scheduling unit is responsible for coordinating the timing of different interface modules; and the response analysis unit collects and performs preliminary processing on the response signals returned by the SRAM.

[0064] As an optional embodiment, each interface module 320 can be specifically implemented as a combination of physical level conversion circuit and protocol parsing logic to adapt to different SRAM interface protocols, such as single-clock synchronous interface, dual-clock synchronous interface or asynchronous interface with verification function.

[0065] For the SRAM memory module 330 to be verified, the virtual shell program module can be implemented using a hardware description language (such as Verilog or VHDL). Internally, it encapsulates key parameters of the SRAM memory using `define macro definition statements, including but not limited to memory type (TYPE), memory depth (DEPTH), data width (WIDTH), and special function identifiers (such as ECC_EN indicating error correction enabled). It is understood that the virtual shell program module can be physically integrated onto the same chip as the SRAM core module to be verified, or it can exist as an independent simulation model.

[0066] Through the above embodiments, the SRAM memory verification method and system provided by the present invention have at least the following technical effects: (1) By adopting the solution in this invention, the external interface form of different types of SRAM memory is unified by using the virtual shell program module, so that a verification system can support the verification of multiple SRAM memory, avoiding the work of repeatedly building the verification environment and greatly improving the verification efficiency.

[0067] (2) By adopting the solution in this invention, the entire process from the generation of excitation signals, the matching of interface modules, the preprocessing of ports to the judgment of verification results is highly automated, reducing manual intervention and the possibility of human error.

[0068] (3) When a new type of SRAM memory appears, only the macro definition parameters of the virtual shell program module need to be modified, without the need for large-scale reconstruction of the entire verification system. It has good compatibility and scalability.

[0069] (4) By adopting the solution in this invention, the introduction of interference signals is avoided through effective processing of idle ports, thereby improving the accuracy and reliability of the verification results.

[0070] Based on the same approach, embodiments of this specification also provide an SRAM memory verification device. For example... Figure 5 As shown, the device includes: The system includes a memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be executed by the processor; when the processor runs the computer program, it performs the aforementioned SRAM memory verification method.

[0071] like Figure 5 As shown, the processor described above can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. The communication interface described above can be one or more. The communication interface can use any transceiver-like system for communicating with other devices or communication networks.

[0072] like Figure 5 As shown, the terminal device described above may also include a communication line. The communication line may include a path for transmitting information between the components described above.

[0073] Optional, such as Figure 5 As shown, the terminal device may further include a memory. The memory stores a computer program that can be executed by the processor; when the processor executes the computer program, it implements the method provided in the embodiments of the present invention.

[0074] like Figure 5As shown, the memory can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via communication lines. The memory can also be integrated with the processor.

[0075] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0076] In a specific implementation, as one example, such as Figure 5 As shown, a processor may include one or more CPUs, such as Figure 5 CPU0 and CPU1 in the CPU.

[0077] In a specific implementation, as one example, such as Figure 5 As shown, the terminal device may include multiple processors, such as Figure 5 The processors in the system. Each of these processors can be a single-core processor or a multi-core processor.

[0078] The foregoing mainly describes the solutions provided by the embodiments of the present invention from the perspective of the interaction between various modules. It is understood that each module, in order to achieve the above functions, includes corresponding hardware structures and / or software units for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0079] The embodiments of the present invention can divide functional modules according to the above method examples. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in the embodiments of the present invention is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0080] The processor described in this specification may also function as a memory. The memory stores computer execution instructions for carrying out the present invention, and its execution is controlled by the processor. The processor executes the computer execution instructions stored in the memory, thereby implementing the method provided in the embodiments of the present invention.

[0081] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results. The invention has been described in conjunction with specific features and embodiments; it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Obviously, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if these modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include these modifications and modifications.

Claims

1. A method for verifying SRAM memory, characterized in that, The method is applied to an SRAM memory verification system, which includes at least an SRAM memory module to be verified configured with a virtual shell program module; the method includes: A unified virtual shell program module is set up for the SRAM memory module to be verified, and the key attribute information of the SRAM memory module to be verified is encapsulated through macro definition parameters; the key attribute information includes at least the SRAM type. Assign a serial number to each SRAM type of the SRAM memory module to be verified, and establish a mapping relationship between the serial number and the interface module; Based on the serial number corresponding to the SRAM memory module to be verified, the corresponding excitation signal is retrieved from the excitation signal library, and the corresponding target interface module is determined through the mapping relationship. The virtual shell program module of the SRAM memory module to be verified is connected through the target interface module, and the excitation signal is sent to trigger the functional verification.

2. The method according to claim 1, characterized in that, The step of retrieving the corresponding excitation signal from the excitation signal library based on the serial number corresponding to the SRAM memory module to be verified, and determining the corresponding target interface module through the mapping relationship, further includes: The verification module receives information packets from all SRAM memory modules to be verified. The information packet is used to generate excitation signals for each SRAM type and store them in the excitation signal library.

3. The method according to claim 1, characterized in that, The virtual shell program module, which connects to the SRAM memory module to be verified through the target interface module, sends the stimulus signal to trigger functional verification, including: The interface module connects to the virtual shell program module of the SRAM memory module to be verified, and preprocesses the port module integrated in the virtual shell program module; each SRAM type corresponds to one interface module. The preprocessed port module sends an excitation signal to the SRAM program module inside the SRAM memory to trigger functional verification.

4. The method according to claim 3, characterized in that, The virtual shell program module, which connects to the SRAM memory module to be verified through the interface module, and the port module integrated in the virtual shell program module, are preprocessed, including: If there are idle input ports in the port module, the idle input ports will be left floating or combined for calculation. If there is an idle output port in the port module, the idle output port is set to the default state; the idle output port includes the idle output port of the unverified SRAM memory module without error correction function; the default state includes setting the idle output port to 0 or 1.

5. The SRAM memory verification method according to claim 3, characterized in that, The virtual shell program module, which connects to the SRAM memory module to be verified through the target interface module, sends the stimulus signal to trigger functional verification, including: For read / write function verification, the virtual shell program module sends write and read commands to the SRAM program module, checks whether the returned data is consistent with the written data, and completes the verification. For SRAM memory with error correction function, a stimulus signal containing erroneous data is sent to the SRAM program module, and the verification is completed by verifying whether the SRAM memory can correctly correct and return the correct data.

6. An SRAM memory verification system, characterized in that, The system employs the SRAM memory verification method according to any one of claims 1-5 for verification, the system comprising: Verification module, interface module, and SRAM memory module to be verified; The SRAM memory module to be verified is configured with a virtual shell program module, which encapsulates the key attribute information of the SRAM memory module to be verified through macro definition parameters; the key attribute information includes at least the SRAM type. The verification module establishes a connection with the virtual shell program module of the SRAM memory module to be verified through the interface module, and sends an excitation signal to trigger the functional verification.

7. The system according to claim 6, characterized in that, The verification module is used to generate excitation signals, manage sequence numbers, schedule interface modules and analyze responses, and adapt to different SRAM types through parameter configuration. The verification module is also used to establish and maintain the mapping relationship between the serial number and the interface module; the serial number also corresponds to the SRAM type of the SRAM memory module to be verified and the excitation signal in the excitation signal library.

8. The system according to claim 6, characterized in that, The number of interface modules is equal to the number of SRAM types; and each interface module corresponds to an SRAM interface protocol, through which the signal interaction between the verification module and the SRAM memory module to be verified is realized.

9. The system according to claim 6, characterized in that, Each type of SRAM memory module to be verified encapsulates a unified virtual shell program module; the virtual shell program module integrates the SRAM's storage parameters, port modules, and functional information; The port module includes multiple input ports and multiple output ports; the input ports include at least a read / write clock port, a read / write address port, a write data port, and a control signal port; the output ports include at least a read data port and a data valid flag port. The control signal port includes at least one of the following: chip select signal port, write enable signal port, check enable signal port, and low power enable signal port; the output port includes at least one of the following: check result port, power status port, port status port, error flag port, clock synchronization signal port, and temperature monitoring signal port.

10. An SRAM memory verification device, characterized in that the device... include: Memory, processor, and communication interface coupled to the processor; The memory stores computer programs that can be executed by the processor; When the processor runs the computer program, it performs the SRAM memory verification method as described in any one of claims 1 to 5.

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