Light emitting device and method of fabricating the same
By employing a stepped structure and passivation layer design in LED devices, and optimizing the current spreading layer and electrode layout, the problems of poor lateral current transmission and current congestion are solved, thereby improving luminous efficiency and flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-11
- Publication Date
- 2026-03-27
AI Technical Summary
In existing LED electrode processes, the lateral current transmission capability is poor, the current congestion effect is significant, and the electrode size cannot be flexibly adjusted according to the mesa area, affecting current distribution and luminous efficiency.
A stepped structure and passivation layer design are adopted to form a flattened device mesa, and the current distribution is optimized through a special layout of the current spreading layer and electrodes, including the connection of the gate electrode, the first electrode and the second electrode.
It improves luminous efficiency, alleviates current congestion, allows for flexible adjustment of electrode size to adapt to LED devices with different mesa sizes, and reduces process complexity and cost.
Smart Images
Figure CN114725152B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a light-emitting device and a preparation method thereof. BACKGROUND
[0002] Since the first high-brightness GaN-based light-emitting diode (LED) was introduced in the early 1990s, GaN-based LEDs have developed rapidly in the following 40 years. GaN-based LEDs have the advantages of high efficiency, high reliability, low power consumption, long service life, etc., and are widely used in general lighting, biomedical, large-size display and other fields as an environmentally friendly and energy-saving green light source.
[0003] The existing LED electrode process generally makes electrodes on the LED mesa and designs certain electrode and grid line shapes, and then conducts current to the entire range of the mesa through the current conducting layer below the electrodes and grid lines. In the LED preparation process, the processes related to the electrodes include current spreading layer preparation and wet etching, passivation layer opening, and metal stripping process.
[0004] The disadvantage of preparing electrodes on the LED mesa is that the P-GaN has poor lateral current transmission capability, and the current crowding effect is significant; for vertical structure LEDs, the electrode size generally cannot be less than 60 μm x 60 μm regardless of the size of the LED mesa (because the gold wire pad diameter is generally 60 μm to 100 μm during wire packaging). When studying epitaxial materials, LED devices of different mesa sizes need to be prepared, but the method of preparing electrodes on the top of the mesa cannot reduce the electrodes in proportion to the area of the mesa, and cannot control the influence of electrode shading and current crowding effect on LEDs of different mesa sizes.
[0005] Therefore, in view of the above technical problems, it is necessary to provide a light-emitting device and a preparation method thereof. SUMMARY
[0006] In view of the above, the purpose of the present application is to provide a light-emitting device and a preparation method thereof.
[0007] To achieve the above-mentioned purpose, the technical solution provided by an embodiment of the present application is as follows:
[0008] A light-emitting device, comprising an epitaxial wafer, a passivation layer, a current spreading layer and an electrode, wherein:
[0009] The epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer in sequence, and a light-emitting unit and a step beside the light-emitting unit and etched to the N-type semiconductor layer are formed on the epitaxial wafer, and the step has an upwardly inclined side wall;
[0010] The passivation layer is located on the step, the passivation layer has a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface is flush with the top surface of the light emitting unit and constitutes a planarized device mesa, and an isolation groove is formed in the passivation layer and penetrates the second surface to the N-type semiconductor layer;
[0011] The current spreading layer is located above the device mesa and all or part of the second surface;
[0012] The electrode includes a gate line electrode, a first electrode and a second electrode, the gate line electrode is located on the current spreading layer in the area above the device mesa and is electrically connected with the P-type semiconductor layer, the first electrode is located in the area above the second surface of the passivation layer and is electrically connected with the gate line electrode, and the second electrode is located in the isolation groove and is electrically connected with the N-type semiconductor layer.
[0013] In an embodiment, the first surface of the passivation layer is located in the area above the step sidewall, and the second surface is located in the area above the step bottom wall.
[0014] In an embodiment, the horizontal height of the first surface is higher than the horizontal height of the second surface, the difference in horizontal height is less than or equal to 100 nm, and the passivation layer further has a third surface connecting the first surface and the second surface.
[0015] In an embodiment, the gate line electrode is located on the current spreading layer in the area above the top surface of the light emitting unit.
[0016] In an embodiment, the substrate is a silicon substrate, a GaN template substrate on sapphire or a GaN self-supporting substrate; and / or,
[0017] The material of the N-type semiconductor layer and / or the P-type semiconductor layer is a GaN-based material; and / or,
[0018] The material of the active layer is a GaN-based quantum well or a self-assembled quantum dot material; and / or,
[0019] The material of the passivation layer is SiO2 or Si3N4; and / or,
[0020] The transmittance of the current spreading layer in the light emitting wavelength band of the light emitting device is greater than or equal to 95%; and / or,
[0021] The current spreading layer is an ITO thin film with a thickness of 100 nm to 300 nm; and / or,
[0022] The gate line electrode, and / or the first electrode, and / or the second electrode is an ohmic contact electrode; and / or,
[0023] The gate line electrode, and / or the first electrode, and / or the second electrode is a Ti / Al / Ti / Au composite metal electrode.
[0024] Another embodiment of the present application provides the technical solutions as follows:
[0025] A preparation method of a light emitting device, the preparation method comprising:
[0026] S1, sequentially epitaxially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate to obtain an epitaxial wafer;
[0027] S2, forming photoresist on the light emitting unit on the epitaxial wafer by one-time photolithography alignment;
[0028] S3, etching the epitaxial wafer to the N-type semiconductor layer by a dry etching process to form a step on the side of the light emitting unit, the step having an upwardly inclined sidewall;
[0029] S4, depositing a passivation layer on the step and the photoresist;
[0030] S5, stripping the photoresist and the passivation layer thereon;
[0031] S6, planarizing the passivation layer by a wet etching process, the planarized passivation layer having a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface being flush with the top surface of the light emitting unit and constituting a planarized device mesa;
[0032] S7, opening the passivation layer to form an isolation groove penetrating through the second surface to the N-type semiconductor layer;
[0033] S8, preparing a current spreading layer above the device mesa and all or part of the second surface;
[0034] S9, preparing a gate line electrode on the current spreading layer in the area above the device mesa, preparing a first electrode electrically connected with the gate line electrode above the area of the second surface of the passivation layer, and preparing a second electrode electrically connected with the N-type semiconductor layer in the isolation groove.
[0035] In an embodiment, the etching depth of the N-type semiconductor layer in the step S3 is greater than the deposition thickness of the passivation layer in the step S4.
[0036] In an embodiment, after the step S6 of planarizing the passivation layer, the first surface of the passivation layer is located in the area above the sidewall of the step, and the second surface is located in the area above the bottom wall of the step; the horizontal height of the first surface is higher than that of the second surface, the difference in horizontal height is less than or equal to 100 nm, and the passivation layer further has a third surface connecting the first surface and the second surface.
[0037] In an embodiment, the N-type semiconductor layer, the active layer and the P-type semiconductor layer in the step S1 are epitaxially grown by a molecular beam epitaxy process; and / or,
[0038] The dry etching process in the step S3 is an inductively coupled plasma etching process, the etching gas is a mixed gas of Cl2 and BCl3, the gas flow ratio of Cl2 to BCl3 is 2-5:5-8, the total flow of the etching gas is 10-100sccm, the bottom radio frequency power is 10-300W, the top radio frequency power is 100-1000W, and the etching time is 1-60min; and / or,
[0039] The passivation layer in the step S4 is obtained by inductively coupled plasma chemical vapor deposition or plasma enhanced chemical vapor deposition, and the deposition temperature is not higher than 300℃; and / or,
[0040] The step S5 is specifically: using acetone solution for ultrasonic treatment for 10-100min to peel off the photoresist and the passivation layer thereon; and / or,
[0041] The step S6 is specifically: using BOE solution for wet etching for 1-30s to planarize the passivation layer; and / or,
[0042] The step S7 is performed by reactive ion etching; and / or,
[0043] The current spreading layer in the step S8 is prepared by film plating, photolithography and wet etching; and / or,
[0044] The electrode in the step S9 is prepared by a metal peeling method.
[0045] In an embodiment, the substrate is a silicon substrate, a GaN template substrate on sapphire or a GaN self-supporting substrate; and / or,
[0046] The material of the N-type semiconductor layer and / or the P-type semiconductor layer is a GaN-based material; and / or,
[0047] The material of the active layer is a GaN-based quantum well or a self-assembled quantum dot material; and / or,
[0048] The material of the passivation layer is SiO2 or Si3N4; and / or,
[0049] The transmittance of the current spreading layer in the light-emitting wavelength band of the light-emitting device is greater than or equal to 95%; and / or,
[0050] The current spreading layer is an ITO thin film with a thickness of 100-300nm; and / or,
[0051] The gate line electrode, and / or the first electrode, and / or the second electrode are ohmic contact electrodes; and / or,
[0052] The gate line electrode, the first electrode and / or the second electrode are Ti / Al / Ti / Au composite metal electrodes.
[0053] The present application has the following advantages:
[0054] The first electrode does not form a light shield for the device, which greatly improves the light emitting efficiency of the device. BRIEF DESCRIPTION OF DRAWINGS
[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.
[0056] Figure 1 A structure diagram of a light emitting device in a specific embodiment of the present application;
[0057] Figures 2a to 2i A process flow chart of a light emitting device preparation method in a specific embodiment of the present application;
[0058] Figure 3 A flow chart of a light emitting device preparation method in a specific embodiment of the present application. DETAILED DESCRIPTION
[0059] In order to make the person skilled in the art better understand the technical solutions in the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.
[0060] The present application discloses a light emitting device, comprising an epitaxial wafer, a passivation layer, a current spreading layer and an electrode, wherein:
[0061] The epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer in sequence, and the epitaxial wafer is formed with a light emitting unit and a step beside the light emitting unit and etched to the N-type semiconductor layer, the step has an upwardly inclined side wall;
[0062] The passivation layer is located on the step, the passivation layer has a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface is flush with the top surface of the light emitting unit and forms a planarized device mesa, and the passivation layer is formed with an isolation groove penetrating from the second surface to the N-type semiconductor layer;
[0063] The current spreading layer is located above the device mesa and all or part of the second surface;
[0064] The electrode includes a gate line electrode, a first electrode and a second electrode, the gate line electrode is located on the current spreading layer in the area above the device mesa and is electrically connected with the P-type semiconductor layer, the first electrode is located in the area above the second surface of the passivation layer and is electrically connected with the gate line electrode, and the second electrode is located in the isolation groove and is electrically connected with the N-type semiconductor layer.
[0065] The application further discloses a preparation method of the light emitting device, comprising:
[0066] S1, sequentially epitaxially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate to obtain an epitaxial wafer;
[0067] S2, forming photoresist on the light emitting unit on the epitaxial wafer by one-time photolithography alignment;
[0068] S3, etching the epitaxial wafer to the N-type semiconductor layer by a dry etching process to form a step on the side of the light emitting unit, the step has an upwardly inclined side wall;
[0069] S4, depositing a passivation layer on the step and the photoresist;
[0070] S5, stripping the photoresist and the passivation layer thereon;
[0071] S6, planarizing the passivation layer by a wet etching process, the planarized passivation layer has a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface is flush with the top surface of the light emitting unit and forms a planarized device mesa;
[0072] S7, opening the passivation layer to form an isolation groove penetrating from the second surface to the N-type semiconductor layer;
[0073] S8, preparing a current spreading layer above the device mesa and all or part of the second surface;
[0074] S9, preparing a gate line electrode on the current spreading layer in the area above the device mesa, a first electrode electrically connected with the gate line electrode in the area above the second surface of the passivation layer, and a second electrode electrically connected with the N-type semiconductor layer in the isolation groove.
[0075] The application will be further described in conjunction with specific embodiments.
[0076] Referring to Figure 1 In combination Figures 2a to 2i As shown in the embodiment, the light emitting device is an LED device, which comprises an LED epitaxial wafer 10, a passivation layer 20, a current spreading layer 30 and electrodes, wherein:
[0077] The LED epitaxial wafer 10 comprises a substrate 101, an N-type semiconductor layer 102, an active layer 103 and a P-type semiconductor layer 104 in sequence, and the LED epitaxial wafer 10 is formed with a light emitting unit 12 and a step 111 beside the light emitting unit 12 and etched to the N-type semiconductor layer, the step 111 having an upwardly inclined sidewall;
[0078] The passivation layer 20 is located on the step, the passivation layer 20 has a first surface 21 adjacent to the light emitting unit 12 and a second surface 22 away from the light emitting unit 12, the first surface 21 is flush with the top surface of the light emitting unit 12 and constitutes a planarized device mesa 200, and the passivation layer 20 is formed with an isolation groove 221 penetrating the second surface to the N-type semiconductor layer;
[0079] The current spreading layer 30 is located above the device mesa 200 and part of the second surface 22;
[0080] The electrodes comprise a gate line electrode 43, a first electrode 41 and a second electrode 42, the gate line electrode 43 is located on the current spreading layer 30 in the area above the device mesa and is electrically connected with the P-type semiconductor layer 104, the first electrode 41 is located on the second surface 22 of the passivation layer 20 and is electrically connected with the gate line electrode 43, and the second electrode 42 is located in the isolation groove 221 and is electrically connected with the N-type semiconductor layer 102.
[0081] Preferably, the first surface 21 of the passivation layer 20 in the embodiment is located in the area above the step sidewall, and the second surface 22 is located in the area above the step bottom wall. The horizontal height of the first surface 21 is higher than that of the second surface 22, and the passivation layer 20 further has a third surface 23 connecting the first surface 21 and the second surface 22. Further, the horizontal height difference between the first surface 21 and the second surface 22 is less than or equal to 100 nm.
[0082] In addition, the gate line electrode 43 is located on the current spreading layer 30 in the area above the top surface of the light emitting unit 12.
[0083] Preferably, the substrate is a silicon substrate, a GaN template substrate on sapphire or a GaN self-supporting substrate; the material of the N-type semiconductor layer and / or the P-type semiconductor layer is a GaN-based material; and the material of the active layer is a GaN-based quantum well or a self-assembled quantum dot material.
[0084] Among them, the passivation layer can be prepared by inductively coupled plasma chemical vapor deposition or plasma-enhanced chemical vapor deposition, the deposition temperature is not higher than 300 °C, and the material of the passivation layer can be silicon oxide (SiO2), silicon nitride (Si3N4), etc.
[0085] Among them, the current spreading layer is suitable for GaN materials, the thickness is matched with the emission wavelength of the LED device, the transmittance in the emission band of the LED device is greater than or equal to 95%, and it has good contact with the top material of the LED epitaxial wafer; preferably, the current spreading layer is an indium tin oxide (ITO) thin film with a thickness of 100 nm to 300 nm.
[0086] Among them, the gate line electrode, the first electrode, and the second electrode are ohmic contact electrodes, and good ohmic contacts can be formed between the first electrode / gate line electrode and the current spreading layer, and the second electrode and the N-type semiconductor layer. Preferably, when the semiconductor material is a GaN-based material and the current spreading layer is an ITO thin film, the gate line electrode, the first electrode, and the second electrode are Ti / Al / Ti / Au (25 nm / 200 nm / 25 nm / 200 nm) composite metal electrodes.
[0087] Refer Figure 3 And in combination with Figures 2a to 2i As shown, the manufacturing method of the LED device in this embodiment specifically includes the following steps:
[0088] S1, refer Figure 2a As shown, an N-type semiconductor layer 102, an active layer 103, and a P-type semiconductor layer 104 are sequentially epitaxially grown on a substrate 101 to obtain an LED epitaxial wafer 10.
[0089] Among them, the N-type semiconductor layer 102, the active layer 103, and the P-type semiconductor layer 104 are epitaxially grown by molecular beam epitaxy. The N-type semiconductor layer 102 and the P-type semiconductor layer 104 are an N-type GaN layer and a P-type GaN layer respectively, and the active layer 103 is a GaN-based quantum well active layer.
[0090] S2, refer Figure 2b As shown, through one-time photolithography alignment, a photoresist 50 is formed on the light-emitting unit 12 on the LED epitaxial wafer 10.
[0091] Through one-time photolithography alignment, the pattern on the mask plate is printed onto the surface of the LED epitaxial wafer through the exposure of light. After photolithography, a mesa-shaped photoresist pattern is left on the surface of the LED epitaxial wafer.
[0092] S3, continue to refer Figure 2b As shown, the LED epitaxial wafer 10 is etched to the N-type semiconductor layer 102 through a dry etching process, and a step 111 is formed under the etching mesa 11 (the mesa other than the light-emitting unit), and the step 111 is located beside the light-emitting unit 12.
[0093] The dry etching process is an inductively coupled plasma (ICP) etching process, and the step 111 is formed by controlling parameters in the etching process to have an upwardly inclined sidewall.
[0094] Specifically, in the ICP etching process, the etching gas is a mixture of Cl2 and BCl3, the gas flow ratio of Cl2 to BCl3 is 3:7, the total flow rate of the etching gas is 35 sccm, the bottom radio frequency power (RF Power) is 100 W, the top radio frequency power (ICP Power) is 300 W, the etching time is about 7-8 min, and the etching depth is about 700 nm.
[0095] S4, as shown in the figure, a passivation layer 20 is deposited on the step 111 and the photoresist 50. Figure 2c
[0096] The passivation layer is obtained by inductively coupled plasma chemical vapor deposition or plasma enhanced chemical vapor deposition, and the deposition temperature is not higher than 300°C.
[0097] In this embodiment, the material of the passivation layer is silicon oxide (SiO2), and the thickness is 700 nm.
[0098] S5, as shown in the figure, the photoresist 50 and the passivation layer 20 thereon are stripped. Figure 2d
[0099] In this embodiment, the photoresist 50 and the passivation layer thereon are stripped by using acetone solution for ultrasonic treatment for 10-100 min.
[0100] S6, as shown in the figure, the passivation layer 20 is planarized by a wet etching process. Figure 2e
[0101] In this embodiment, the wet etching process uses a BOE solution for wet etching for 30 s to planarize the passivation layer.
[0102] The planarized passivation layer 20 has a first surface 21 adjacent to the light emitting unit 12 and a second surface 22 away from the light emitting unit 12, the first surface 21 is flush with the top surface of the light emitting unit 12 and constitutes a planarized device mesa 200.
[0103] The first surface 21 of the passivation layer 20 is located in the area above the step sidewall, and the second surface 22 is located in the area above the step bottom wall. The horizontal height of the first surface 21 is higher than that of the second surface 22, and the passivation layer 20 further has a third surface 23 connecting the first surface 21 and the second surface 22.
[0104] Preferably, the height difference between the first surface 21 and the second surface 22 is less than or equal to 100 nm.
[0105] S7, referring to FIG. 7, the passivation layer 20 is opened to form an isolation groove 221 extending to the N-type semiconductor layer 102. Figure 2f
[0106] In this embodiment, the opening is performed by reactive ion etching (RIE), and the opening depth is equal to the thickness of the passivation layer, i.e. 700 nm, so that the N-type semiconductor layer 102 below is exposed.
[0107] S8, referring to FIG. 8, the current spreading layer 30 is prepared above the device mesa 200 and part of the second surface 22. Figure 2g
[0108] The ITO film is patterned by photolithography and wet etching process to form the current spreading layer 30.
[0109] In this embodiment, the current spreading layer 30 is an ITO film with a thickness of 100 nm, which is suitable for GaN material and matches the light-emitting wavelength of the LED device.
[0110] S9, referring to FIG. 9, the gate line electrode 43 is prepared on the current spreading layer 30 in the area above the device mesa 200, the first electrode 41 electrically connected to the gate line electrode 43 is prepared in the area above the second surface 22 of the passivation layer 20, and the second electrode 42 electrically connected to the N-type semiconductor layer 102 is prepared in the isolation groove 221. Figure 2h 2i The cross-sectional and top views of the final LED device are shown in FIGS. 10 and 11, respectively. Figure 2h 2i In this embodiment, the gate line electrode, the first electrode and the second electrode are prepared by metal stripping method, and all of them are Ti / Al / Ti / Au (25 nm / 200 nm / 25 nm / 200 nm) composite metal electrodes.
[0111] The passivation layer of the present application has first and second surfaces with different heights, the gate line electrode and the first electrode are prepared on the current spreading layer, the gate line electrode is located in the area above the planarized device mesa, and the first electrode is located in the area above the second surface of the passivation layer. The gate line electrode is the only electrode in the area above the device mesa, and the first electrode does not block the light, which greatly improves the light-emitting efficiency of the device.
[0112] The passivation layer of the present application has first and second surfaces with different heights, the gate line electrode and the first electrode are prepared on the current spreading layer, the gate line electrode is located in the area above the planarized device mesa, and the first electrode is located in the area above the second surface of the passivation layer. The gate line electrode is the only electrode in the area above the device mesa, and the first electrode does not block the light, which greatly improves the light-emitting efficiency of the device.
[0113] In the preparation of light emitting devices of different sizes, the width and length of the gate line electrode and the size of the first electrode can be controlled to realize the equal ratio reduction or enlargement of the gate line electrode and the first electrode, which is conducive to the research on material properties and can significantly alleviate the current crowding effect.
[0114] In addition, the present application adopts a passivation layer stripping process, without the need for secondary photolithography alignment of the device mesa, thereby reducing the photolithography alignment and exposure precision required for device preparation, reducing the process complexity and process cost, and enabling the preparation of small-size LED devices.
[0115] It should be understood that the light emitting device in the above embodiments is exemplified by an LED device, and in other embodiments, it can also be other light emitting devices, such as a Micro-LED device.
[0116] As can be seen from the above technical solutions, the present application has the following advantages:
[0117] The device mesa of the present application only has a gate line electrode in the upper region, and the first electrode does not form a light shielding for the device, greatly improving the light emitting efficiency of the device; the width and length of the gate line electrode and the size of the first electrode can be reduced or enlarged in equal ratio, which is conducive to the research on material properties and can significantly alleviate the current crowding effect.
[0118] It is apparent for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and scope of the equivalent elements of the claims. Any reference signs in the claims should not be regarded as limiting the claims involved.
[0119] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.
Claims
1. A light emitting device, characterized by, The light emitting device comprises an epitaxial wafer, a passivation layer, a current spreading layer and an electrode, wherein: The epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer in sequence, and a light emitting unit and a step beside the light emitting unit and etched to the N-type semiconductor layer are formed on the epitaxial wafer, the step has an upwardly inclined side wall; The passivation layer is located on the step, the passivation layer has a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface is flush with the top surface of the light emitting unit and constitutes a planarized device mesa, and an isolation groove is formed in the passivation layer and penetrates the second surface to the N-type semiconductor layer; The current spreading layer is located above the device mesa and all or part of the second surface; The electrode comprises a gate line electrode, a first electrode and a second electrode, the gate line electrode is located on the current spreading layer in the area above the device mesa and is electrically connected with the P-type semiconductor layer, the first electrode is located in the area above the second surface of the passivation layer and is electrically connected with the gate line electrode, and the second electrode is located in the isolation groove and is electrically connected with the N-type semiconductor layer; The first surface of the passivation layer is located in the area above the step side wall, the second surface is located in the area above the step bottom wall, and the passivation layer further has a third surface connecting the first surface and the second surface.
2. The light emitting device of claim 1, wherein, The horizontal height of the first surface is higher than that of the second surface, and the difference in horizontal height is less than or equal to 100 nm.
3. The light emitting device of claim 1, wherein, The gate line electrode is located on the current spreading layer in the area above the top surface of the light emitting unit.
4. The light emitting device of claim 1, wherein, The substrate is a silicon substrate, a GaN template substrate on sapphire or a GaN self-supporting substrate; and / or, The material of the N-type semiconductor layer and / or the P-type semiconductor layer is a GaN-based material; and / or, The material of the active layer is a GaN-based quantum well or a self-assembled quantum dot material; and / or, The material of the passivation layer is SiO2 or Si3N4; and / or, The transmittance of the current spreading layer in the light emitting band of the light emitting device is greater than or equal to 95%; and / or, The current spreading layer is an ITO thin film with a thickness of 100 nm to 300 nm; and / or, The gate line electrode, the first electrode and / or the second electrode are ohmic contact electrodes; and / or, The gate line electrode, the first electrode and / or the second electrode are Ti / Al / Ti / Au composite metal electrodes.
5. A method for manufacturing a light emitting device, characterized by: The preparation method comprises: S1, epitaxially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate in sequence to obtain an epitaxial wafer; S2, forming a photoresist on the light emitting unit on the epitaxial wafer by one-time photoetching alignment; S3, etching the epitaxial wafer to the N-type semiconductor layer by a dry etching process to form a step beside the light emitting unit, the step has an upwardly inclined side wall; S4, depositing a passivation layer on the step and the photoresist; S5, stripping the photoresist and the passivation layer thereon; S6, the passivation layer is planarized by a wet etching process, the planarized passivation layer has a first surface adjacent to the light emitting unit and a second surface away from the light emitting unit, the first surface is flush with the top surface of the light emitting unit and constitutes a planarized device mesa, the first surface of the passivation layer is located above the step sidewall region, the second surface is located above the step bottom wall region, and the passivation layer also has a third surface connecting the first surface and the second surface; S7, the passivation layer is opened to form an isolation groove penetrating through the second surface to the N-type semiconductor layer; S8, a current spreading layer is prepared above the device mesa and all or part of the second surface; S9, a gate line electrode is prepared on the current spreading layer in the area above the device mesa, a first electrode electrically connected with the gate line electrode is prepared in the area above the second surface of the passivation layer, and a second electrode electrically connected with the N-type semiconductor layer is prepared in the isolation groove.
6. The production method according to claim 5, wherein The etching depth of the N-type semiconductor layer in step S3 is greater than the deposition thickness of the passivation layer in step S4.
7. The preparation method according to claim 6, characterized in that, The horizontal height of the first surface is higher than the horizontal height of the second surface, and the difference in horizontal height is less than or equal to 100 nm.
8. The preparation method according to claim 5, characterized in that, The N-type semiconductor layer, the active layer and the P-type semiconductor layer in step S1 are obtained by molecular beam epitaxy process; and / or, The dry etching process in step S3 is inductively coupled plasma etching process, the etching gas is a mixed gas of Cl2 and BCl3, the gas flow ratio of Cl2 to BCl3 is 2-5:5-8, the total flow rate of the etching gas is 10-100sccm, the bottom radio frequency power is 10-300W, the top radio frequency power is 100-1000W, and the etching time is 1-60min; and / or, The passivation layer in step S4 is obtained by inductively coupled plasma chemical vapor deposition or plasma enhanced chemical vapor deposition, and the deposition temperature is not higher than 300 DEG C; and / or, The step S5 is specifically: using acetone solution ultrasonic treatment for 10-100min, stripping the photoresist and the passivation layer thereon; and / or, The step S6 is specifically: using BOE solution wet etching for 1-30s to planarize the passivation layer; and / or, The step S7 is opened by reactive ion etching; and / or, The current spreading layer in step S8 is prepared by plating, photolithography and wet etching; and / or, The electrode in step S9 is prepared by metal stripping method.
9. The preparation method according to claim 5, characterized in that, The substrate is a silicon substrate, a GaN template substrate on sapphire or a GaN self-supporting substrate; and / or, The material of the N-type semiconductor layer and / or the P-type semiconductor layer is GaN-based material; and / or, The material of the active layer is GaN-based quantum well or self-assembled quantum dot material; and / or, The material of the passivation layer is SiO2 or Si3N4; and / or, The transmittance of the current spreading layer in the light emitting wavelength band of the light emitting device is greater than or equal to 95%; and / or, The current spreading layer is ITO thin film with a thickness of 100-300nm; and / or, The gate line electrode, and / or the first electrode, and / or the second electrode is an ohmic contact electrode; and / or, The gate line electrode, and / or the first electrode, and / or the second electrode is a Ti / Al / Ti / Au composite metal electrode.
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