High efficiency charging integrated micro supercapacitor chip

Abstract

The present invention provides a high-efficiency charging integrated micro super capacitor group chip, which includes a power supply circuit, a voltage balancing circuit, a micro super capacitor group and a control circuit. The micro super capacitor group and the circuit are manufactured on a silicon base using a semiconductor manufacturing process, combined together by a silicon-based bonding technology, and then packaged; wherein the control circuit is respectively connected to the power supply circuit, the voltage balancing circuit and the micro super capacitor group; the output end of the power supply circuit is connected to the voltage balancing circuit and the micro super capacitor group to supply power to the voltage balancing circuit and the micro super capacitor group; the voltage balancing circuit is connected to the micro super capacitor group, and the voltage balancing between each capacitor in the micro super capacitor group is achieved through the voltage balancing circuit; the micro super capacitor group is composed of a plurality of micro super capacitors. The present invention combines a micro energy storage device with a circuit, uses a comparator and a resistor to form a Schmitt trigger for voltage detection, a buffer, and an inverter to realize a feedback channel, so as to respond quickly to the circuit to better protect the micro super capacitor.

Description

Technical Field

[0001] The present invention relates to circuit design and system integration in the field of microelectronics, and in particular to the integration of a micro energy storage device and a management circuit inside a high-efficiency charging integrated micro super capacitor chip. Background Art

[0002] On-chip micro supercapacitors have the advantages of high power density, small area, fast charge / discharge rate and long cycle life. In particular, they can be produced as micro energy storage devices through semiconductor manufacturing processes, which facilitates integration and can be mass-produced in the current micro device process. They can also be used as energy collectors to collect solar energy, electrostatic energy, etc. The collected energy can be used to power mobile wearable electronic devices, IoT devices and micro wireless sensors.

[0003] The existing technology mainly focuses on the management circuit of supercapacitors, and supercapacitors are generally used as energy storage for microgrids or cars, and their management circuits are made into chips separately. In addition, the current mainstream is to adopt energy consumption management solutions. In the management circuit of supercapacitors, the energy in the high-voltage monomer is consumed in the form of heat energy, which causes serious heating of the system and large energy loss. The present invention is aimed at the integration of micro energy storage devices and management circuits. Summary of the invention

[0004] In view of the above problems, the present invention provides a micro supercapacitor energy storage device and a charging circuit integrated chip.

[0005] A charging integrated micro super capacitor group chip comprises a power supply circuit, a voltage equalizing circuit, a super capacitor group and a control circuit, wherein the control circuit is respectively connected to the power supply circuit, the voltage equalizing circuit and the micro super capacitor group; the output end of the power supply circuit is connected to the voltage equalizing circuit and the micro super capacitor group to supply power to the voltage equalizing circuit and the micro super capacitor group; the voltage equalizing circuit is connected to the micro super capacitor group, and voltage equalization between each capacitor in the micro super capacitor group is achieved through the voltage equalizing circuit; the micro super capacitor group is composed of a plurality of micro super capacitors; the power supply circuit, the voltage equalizing circuit, the micro super capacitor group and the control circuit are all integrated on a silicon substrate, combined through silicon-based bonding technology, and then packaged together; wherein the control circuit is used to achieve voltage balance between each micro super capacitor by controlling the voltage equalizing circuit when it is detected that the voltage of any capacitor in the super capacitor group is unbalanced with the voltage of other capacitors.

[0006] Optionally, the voltage balancing circuit is used to make the capacitors in the supercapacitor group in a series state during the charging process. When the voltage value of any micro supercapacitor in the charging process is not balanced with the voltage values ​​of other micro supercapacitors and exceeds the protection voltage, the charging process ends and the voltage balancing process is started; during the voltage balancing process, the capacitors in the supercapacitor group change from a series state to a parallel state, and the voltage values ​​of each micro supercapacitor are in a balanced state through the parallel connection of the capacitors; the micro supercapacitor group includes four micro supercapacitors: a first micro supercapacitor SC1, a second micro supercapacitor SC2, a third micro supercapacitor SC3, and a fourth micro supercapacitor SC4; the power supply circuit includes a power supply Vin and a power switch M10, and the power switch M10 is turned on during the charging process and turned off during the voltage balancing process.

[0007] Furthermore, the voltage balancing circuit includes nine voltage balancing switch tubes, namely: a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9; wherein the positive electrode of the first micro super capacitor SC1 is connected to the drain of the power switch tube M10 and the drain of the fourth switch tube M4; the negative electrode of the first micro super capacitor SC1 is connected to the drain of the first switch tube M1 and the drain of the seventh switch tube M7; the positive electrode of the second micro super capacitor SC2 is connected to the source of the first switch tube M1, the source of the fourth switch tube M4, and the drain of the fifth switch tube M5; the second micro super capacitor SC2 is connected to the source of the first switch tube M1, the source of the fourth switch tube M4, and the drain of the fifth switch tube M5; the The negative electrode of the container SC2 is connected to the drain of the second switch tube M2, the source of the seventh switch tube M7, and the drain of the eighth switch tube M8; the positive electrode of the third micro super capacitor SC3 is connected to the source of the second switch tube M2, the source of the fifth switch tube M5, and the drain of the sixth switch tube M6; the negative electrode of the third micro super capacitor SC3 is connected to the drain of the third switch tube M3, the source of the eighth switch tube M8, and the drain of the ninth switch tube M9; the positive electrode of the fourth micro super capacitor SC4 is connected to the source of the third switch tube M3 and the source of the sixth switch tube M6; the negative electrode of the fourth micro super capacitor SC4 is connected to the source of the ninth switch tube M9, and is connected to the power supply circuit as a voltage input negative terminal.

[0008] The control circuit includes four voltage detection circuits corresponding to four micro super capacitors, the four voltage detection circuits are respectively used to detect the voltages across the four micro super capacitors, and the output ends of the four voltage detection circuits are connected to the input ends of the logic AND gate. The voltage detection circuit includes four voltage comparators and corresponding resistors: a first voltage comparator A1, a second voltage comparator A2, a third voltage comparator A3, and a fourth voltage comparator A4; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8; the positive and negative electrodes of the first micro super capacitor SC1 are connected in series through the first resistor R1 and the second resistor R2, wherein the middle of the first resistor R1 and the second resistor R2 is connected to the inverting end of the first voltage comparator A1, the in-phase end of the first voltage comparator is connected to the reference voltage Vref through the ninth resistor R9, and the output end of the first voltage comparator A1 is connected to the in-phase end of the first voltage comparator through the tenth resistor R10; the positive and negative electrodes of the second micro super capacitor SC2 are connected in series through the third resistor R3 and the fourth resistor R4, wherein the middle of the third resistor R3 and the fourth resistor R4 is connected to the inverting end of the second voltage comparator A2, The in-phase end of the second voltage comparator is connected to the reference voltage Vref through the eleventh resistor R11, and the output end of the second voltage comparator A2 is connected to the in-phase end of the second voltage comparator through the twelfth resistor R12; the positive and negative electrodes of the third micro super capacitor SC3 are connected in series through the fifth resistor R5 and the sixth resistor R6, wherein the middle of the fifth resistor R5 and the sixth resistor R6 is connected to the inverting end of the third voltage comparator A3, the in-phase end of the third voltage comparator is connected to the reference voltage Vref through the thirteenth resistor R13, and the output end of the third voltage comparator A3 is connected to the in-phase end of the third voltage comparator through the fourteenth resistor R14; the positive and negative electrodes of the fourth micro super capacitor SC4 are connected in series through the seventh resistor R7 and the eighth resistor R8, wherein the middle of the seventh resistor R7 and the eighth resistor R8 is connected to the inverting end of the fourth voltage comparator A4, The in-phase end of the fourth voltage comparator is connected to the reference voltage Vref through the fifteenth resistor R15, and the output end of the fourth voltage comparator A4 is connected to the in-phase end of the fourth voltage comparator through the sixteenth resistor R16; the output end of the first voltage comparator A1, the output end of the second voltage comparator A2, the output end of the third voltage comparator A3, and the output end of the fourth voltage comparator A4 are connected to the input end of the logic AND gate G1, the output end of the logic AND gate G1 is connected to the input end of the buffer G2, and the output end of the buffer G2 constitutes the first output end Φ1 of the voltage detection circuit. The first output end Φ1 is connected to the output end of the voltage detection circuit through the buffer G2, and the first output end Φ1 is connected to the second output end Φ2 through the inverter G2; the first output end Φ1 is used to control the charging process of the supercapacitor, and the second output end Φ2 is used to control the voltage equalization process of the supercapacitor.The first output end Φ1 is respectively connected to the gate of the first switch tube M1, the gate of the second switch tube M2, the gate of the third switch tube M3 and the gate of the power switch M10; the second output end Φ2 is respectively connected to the gate of the fourth switch tube M4, the gate of the fifth switch tube M5, the gate of the sixth switch tube M6, the gate of the seventh switch tube M7, the gate of the eighth switch tube M8 and the gate of the ninth switch tube M9.

[0009] The present invention also provides a micro super capacitor charging circuit, which integrates a power supply circuit, a voltage equalizing circuit, a micro super capacitor group and a control circuit into a chip.

[0010] The present invention integrates the on-chip micro supercapacitor and the charging voltage equalization management circuit on the silicon substrate, and then manufactures them by silicon-based bonding technology and 130nm CMOS process. It is proposed to integrate the power management circuit and the micro supercapacitor on the silicon substrate in the field of micro energy storage devices, and use the energy transfer type voltage equalization design scheme to make a chip, so as to achieve high efficiency, low loss and low cost of the integrated micro supercapacitor chip.

[0011] Since the single cell voltage of micro supercapacitors is relatively low, a structure of multiple micro supercapacitors connected in series is usually adopted when used in energy storage systems. The unbalanced voltage of each cell in the series micro supercapacitor group will reduce the efficiency of the energy storage system and shorten the service life of the system. In response to current needs, the present invention designs a voltage equalization circuit, which is composed only of micro supercapacitors and devices composed of CMOS, providing convenience for system integration. In order to ensure that the state of the micro supercapacitor can be monitored in real time, a feedback channel is realized in this design through a Schmitt trigger, a logic AND gate, a buffer, and an inverter, so as to respond quickly to the circuit to better protect the micro supercapacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the structure of a micro supercapacitor charging circuit;

[0013] Figure 2 Circuit diagram of the micro supercapacitor charging circuit;

[0014] Figure 3 Schematic diagram of the charging process;

[0015] Figure 4 It is a schematic diagram of the pressure equalization process;

[0016] Figure 5 This is a schematic diagram of the structure of micro supercapacitors and circuits on a silicon substrate;

[0017] Figure 6 This is a schematic diagram of the structure of the integrated chip of the micro supercapacitor group;. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, so that the above-mentioned and other objects, features and advantages of the present invention will be clearer. The same reference numerals in all the drawings indicate the same parts. The drawings are not deliberately drawn to scale, and the focus is on illustrating the subject matter of the present invention.

[0019] Example 1

[0020] The present invention is described in detail below with reference to the accompanying drawings. Figure 1 The micro-supercapacitor charging circuit of the present invention includes a power supply circuit, a voltage equalizing circuit, a micro-supercapacitor group and a control circuit, wherein the control circuit is connected to the power supply circuit, the voltage equalizing circuit and the micro-supercapacitor group respectively; the output end of the power supply circuit is connected to the voltage equalizing circuit and the micro-supercapacitor group to supply power to the voltage equalizing circuit and the micro-supercapacitor group; the voltage equalizing circuit is connected to the micro-supercapacitor group, and the voltage equalization between each capacitor in the micro-supercapacitor group is achieved through the voltage equalizing circuit; the micro-supercapacitor group is composed of a plurality of micro-supercapacitors. The control circuit is used to achieve the balance between the voltages of each capacitor by controlling the voltage equalizing circuit when it is detected that the voltage of any capacitor in the micro-supercapacitor group is unbalanced with the voltage of other capacitors.

[0021] Next, combine Figure 2 The various parts of the micro supercapacitor charging circuit are further introduced in detail.

[0022] Micro supercapacitor group

[0023] like Figure 2 As shown, the supercapacitor group includes four micro supercapacitors: a first micro supercapacitor SC1, a second micro supercapacitor SC2, a third micro supercapacitor SC3, and a fourth micro supercapacitor SC4. It should be noted that the present invention only introduces the composition of the supercapacitor group by taking four as an example, but those skilled in the art should understand that the number of a group of micro supercapacitors in the present invention is not limited to four, and can be, for example, 2, 3, 5, 6, etc., and a chip of the present invention can also integrate multiple micro supercapacitor groups.

[0024] Power Circuit

[0025] The power supply circuit includes a power supply Vin, a reference voltage source, and a power switch M10. The power switch M10 can be, for example, a MOS tube, a transistor, etc. The output of the power supply Vin can be controlled by the power switch M10. The reference voltage source is connected to the input end of the comparator and compared with the sampled voltage of the micro supercapacitor.

[0026] Voltage balancing circuit

[0027] Corresponding to the above four micro supercapacitors, the voltage balancing circuit includes nine voltage balancing switch tubes, namely: a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9. These switches can be MOS tubes.

[0028] The positive electrode of the first micro super capacitor SC1 is connected to the drain of the power switch tube M10 and the drain of the fourth switch tube M4; the negative electrode of the first micro super capacitor SC1 is connected to the drain of the first switch tube M1 and the drain of the seventh switch tube M7; the positive electrode of the second micro super capacitor SC2 is connected to the source of the first switch tube M1, the source of the fourth switch tube M4, and the drain of the fifth switch tube M5; the negative electrode of the second micro super capacitor SC2 is connected to the drain of the second switch tube M2, the source of the seventh switch tube M7, and the drain of the eighth switch tube M8.

[0029] By analogy, correspondingly, the positive electrode of the third micro super capacitor SC3 is connected to the source of the second switch tube M2, the source of the fifth switch tube M5, and the drain of the sixth switch tube M6; the negative electrode of the third micro super capacitor SC3 is connected to the drain of the third switch tube M3, the source of the eighth switch tube M8, and the drain of the ninth switch tube M9; the positive electrode of the fourth micro super capacitor SC4 is connected to the source of the third switch tube M3 and the source of the sixth switch tube M6; the negative electrode of the fourth micro super capacitor SC4 is connected to the source of the ninth switch tube M9, and is connected to the power supply circuit as a voltage input negative terminal.

[0030] Control Circuit

[0031] The control circuit includes four voltage detection circuits corresponding to the four micro supercapacitors, and the four voltage detection circuits are respectively used to detect the voltages at both ends of the four micro supercapacitors, and the voltage detection circuit includes four voltage comparators and corresponding resistors: a first voltage comparator A1, a second voltage comparator A2, a third voltage comparator A3, and a fourth voltage comparator A4; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 may have equal resistance values, thereby forming four voltage divider circuits.

[0032] The positive and negative electrodes of the first micro super capacitor SC1 are connected in series through the first resistor R1 and the second resistor R2, wherein the first resistor R1 and the second resistor R2 are connected to the inverting end of the first voltage comparator A1, and the first voltage comparator is connected to the reference voltage Vref in phase; the positive and negative electrodes of the second micro super capacitor SC2 are connected in series through the third resistor R3 and the fourth resistor R4, wherein the third resistor R3 and the fourth resistor R4 are connected to the inverting end of the second voltage comparator A2, and the second voltage comparator is connected to the reference voltage Vref in phase; the positive and negative electrodes of the third micro super capacitor SC3 are connected in series through the fifth resistor R5 and the sixth resistor R6, wherein the fifth resistor R5 and the sixth resistor R6 are connected to the inverting end of the third voltage comparator A3, and the third voltage comparator is connected to the reference voltage Vref in phase; the positive and negative electrodes of the fourth micro super capacitor SC4 are connected in series through the seventh resistor R7 and the eighth resistor R8, wherein the seventh resistor R7 and the eighth resistor R8 are connected to the inverting end of the third voltage comparator A3, and the third voltage comparator is connected to the reference voltage Vref in phase.

[0033] The output end of the first voltage comparator A1, the output end of the second voltage comparator A2, the output end of the third voltage comparator A3, and the output end of the fourth voltage comparator A4 are connected to the input end of the logic AND gate G1, the output end of the logic AND gate G1 is connected to the input end of the buffer G2, and the output end of the buffer G2 constitutes the first output end Φ1 of the voltage detection circuit.

[0034] The control circuit further includes a first output terminal Φ1 and a second output terminal Φ2. The first output terminal Φ1 is connected to the second output terminal Φ2 via an inverter G3.

[0035] The first output terminal Φ1 is used to control the charging process of the micro super capacitor, and the second output terminal Φ2 is used to control the voltage equalization process of the micro super capacitor.

[0036] Specifically, the first output terminal Φ1 is respectively connected to the gate of the first switch tube M1, the gate of the second switch tube M2, the gate of the third switch tube M3, and the gate of the power switch M10. The second output terminal Φ2 is respectively connected to the gate of the fourth switch tube M4, the gate of the fifth switch tube M5, the gate of the sixth switch tube M6, the gate of the seventh switch tube M7, the gate of the eighth switch tube M8, and the gate of the ninth switch tube M9.

[0037] Working process

[0038] Next, Figure 1 , Figure 2The working principle of the integrated micro supercapacitor group chip circuit shown in the figure is introduced. Generally speaking, under the control of the control circuit, the working process can be divided into a charging process and a voltage equalization process. During the charging process, the capacitors in the supercapacitor group are in a series state. When the voltage value of any micro supercapacitor is not balanced with the voltage values ​​of other micro supercapacitors during the charging process, the charging process ends and the voltage equalization process is started. During the voltage equalization process, the capacitors in the supercapacitor group change from a series state to a parallel state. Through the parallel connection of the capacitors, the capacitors at high voltage charge the capacitors at low voltage, and finally the voltage values ​​of each micro supercapacitor are in a balanced state.

[0039] Charging process: When the circuit starts working, the first output terminal Φ1 of the control circuit outputs a high-level signal, and the second output terminal Φ2 outputs a low-level signal. Under the control of the first output terminal Φ1, the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4 and the power switch M10 are turned on, and the four micro supercapacitors are connected in series. The power supply Vin charges the four micro supercapacitors through the power switch M10. At this time, the outputs of the Schmitt trigger composed of four comparators and resistors are all high-level, and at the same time, the four outputs are output as high-level through the logic AND gate G1. At this time, the buffer G2 outputs a high-level, and the inverter G3 outputs a low-level. The fourth switch tube M4, the fifth switch tube M5, the sixth switch tube M6, the seventh switch tube M7, the eighth switch tube M8, and the ninth switch tube M9 are in the off state. During the charging process, the micro supercapacitor connection structure is as shown in FIG. Figure 3 shown.

[0040] Voltage balancing process: When the voltage across any micro-supercapacitor after resistor voltage division is higher than the upper threshold voltage of the Schmitt trigger When the voltage is large, for example, taking the first micro super capacitor SC1 as an example, Vsc1 is the voltage across the first super capacitor, R1 and R2 are the resistance values ​​of the series voltage divider resistors across the first micro super capacitor, and R9 and R10 are the positive feedback resistors of the Schmitt trigger. When the following conditions are met:

[0041] hour,( is the output voltage of the Schmitt trigger, As the output terminal of the first voltage comparator A1, the output terminal of the second voltage comparator A2, the output terminal of the third voltage comparator A3, and the output terminal of the fourth voltage comparator A4 are connected through the logic AND gate G1, the output terminal of the voltage detection circuit outputs a low level, the first output terminal Φ1 of the control circuit becomes a low level, and the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4 and the power switch M10 are turned off.

[0042] At the same time, the second output terminal Φ2 becomes high level, and the fourth switch tube M4, the fifth switch tube M5, the sixth switch tube M6, the seventh switch tube M7, the eighth switch tube M8, and the ninth switch tube M9 are turned on. The four micro supercapacitors are in a parallel state due to the feedback effect of the circuit. Figure 4 In this way, energy is transferred from the micro supercapacitor with a high voltage to the micro supercapacitor with a low voltage, so that the voltage of each micro supercapacitor tends to be consistent.

[0043] During the voltage balancing process, when the voltage of the micro-supercapacitor meets

[0044] When the micro-supercapacitor is connected to a series connection, it returns to the state of series charging. This ensures that the micro-supercapacitor always works within the limited voltage range.

[0045] Example 2

[0046] In this embodiment, the present invention integrates the power circuit, voltage balancing circuit, micro supercapacitor group and control circuit on the silicon substrate. In the conventional technology, the supercapacitor group and its corresponding management circuit are separately arranged. This method is mainly suitable for large supercapacitors, which is not conducive to the miniaturization, low cost and convenience of use of micro devices. At the same time, it is inconvenient to use because the management circuit and supercapacitor group need to be separately arranged in practical applications.

[0047] In this embodiment of the present invention, the power supply circuit, voltage balancing circuit, micro super capacitor group and control circuit are integrated on the silicon substrate through semiconductor technology. Specifically, the on-chip micro super capacitor and charging voltage balancing management circuit are integrated on the silicon substrate, and then the two silicon substrates are combined through silicon-based bonding technology. The circuit part is manufactured using 130nm CMOS technology. The chip structure diagram is shown in FIG. Figure 5 , 6 shown.

[0048] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A charging integrated micro supercapacitor chip, characterized in that: It includes a power supply circuit, a voltage balancing circuit, a supercapacitor group and a control circuit, wherein the control circuit is connected to the power supply circuit, the voltage balancing circuit and the micro supercapacitor group respectively; the output end of the power supply circuit is connected to the voltage balancing circuit and the micro supercapacitor group to supply power to the voltage balancing circuit and the micro supercapacitor group; the voltage balancing circuit is connected to the micro supercapacitor group, and the voltage balancing between each capacitor in the micro supercapacitor group is achieved through the voltage balancing circuit; the micro supercapacitor group is composed of a plurality of micro supercapacitors; the power supply circuit, the voltage balancing circuit, the micro supercapacitor group and the control circuit are all integrated on a silicon substrate, combined by silicon-based bonding technology, and then packaged together; wherein the control circuit is used to achieve voltage balancing between each micro supercapacitor by controlling the voltage balancing circuit when it is detected that the voltage of any one capacitor in the supercapacitor group is unbalanced with the voltage of other capacitors; The voltage balancing circuit is used to make the capacitors in the supercapacitor group in series during the charging process. When the voltage value of any micro supercapacitor is not balanced with the voltage values ​​of other micro supercapacitors during the charging process, the charging process ends and the voltage balancing process is started; during the voltage balancing process, the capacitors in the micro supercapacitor group change from a series state to a parallel state, and the voltage values ​​of each micro supercapacitor are in a balanced state through the parallel connection of the micro capacitors; Wherein the micro supercapacitor group includes four micro supercapacitors: a first micro supercapacitor SC1, a second micro supercapacitor SC2, a third micro supercapacitor SC3, and a fourth micro supercapacitor SC4; The voltage balancing circuit includes nine voltage balancing switch tubes, namely: a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9; wherein the positive electrode of the first micro super capacitor SC1 is connected to the drain of the power switch tube M10 and the drain of the fourth switch tube M4; the negative electrode of the first micro super capacitor SC1 is connected to the drain of the first switch tube M1 and the drain of the seventh switch tube M7; the positive electrode of the second micro super capacitor SC2 is connected to the source of the first switch tube M1, the source of the fourth switch tube M4, and the drain of the fifth switch tube M5; the negative electrode of the second micro super capacitor SC2 is connected to the drain of the second switch tube M2, the source of the seventh switch tube M7, and the drain of the eighth switch tube M8; The positive electrode of the micro super capacitor SC3 is connected to the source of the second switch tube M2, the source of the fifth switch tube M5, and the drain of the sixth switch tube M6; the negative electrode of the third micro super capacitor SC3 is connected to the drain of the third switch tube M3, the source of the eighth switch tube M8, and the drain of the ninth switch tube M9; the positive electrode of the fourth micro super capacitor SC4 is connected to the source of the third switch tube M3 and the source of the sixth switch tube M6; the negative electrode of the fourth micro super capacitor SC4 is connected to the source of the ninth switch tube M9, and is connected to the power supply circuit as a voltage input negative terminal.

2. The supercapacitor chip according to claim 1, characterized in that: The power supply circuit includes a power input Vin, a reference voltage source and a power switch M10. The power switch M10 is turned on during the charging process and is turned off during the voltage equalization process.

3. The supercapacitor chip according to claim 1, characterized in that: The control circuit includes four voltage detection circuits corresponding to the four micro super capacitors, and the four voltage detection circuits are respectively used to detect the voltages across the four micro super capacitors.

4. The supercapacitor chip according to claim 3, characterized in that: The voltage detection circuit includes four Schmitt triggers and corresponding resistors: a first voltage comparator A1, a second voltage comparator A2, a third voltage comparator A3, and a fourth voltage comparator A4; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16; The positive and negative electrodes of the first micro super capacitor SC1 are connected in series through the first resistor R1 and the second resistor R2, wherein the first resistor R1 and the second resistor R2 are connected in the middle to the inverting end of the first voltage comparator A1, the in-phase end of the first voltage comparator A1 is connected to the reference voltage Vref through the ninth resistor R9, and the output end of the first voltage comparator A1 is connected to the in-phase end of the first voltage comparator A1 through the tenth resistor R10; the positive and negative electrodes of the second micro super capacitor SC2 are connected in series through the third resistor R3 and the fourth resistor R4, wherein the third resistor R3 and the fourth resistor R4 are connected in the middle to the inverting end of the second voltage comparator A2, the in-phase end of the second voltage comparator A2 is connected to the reference voltage Vref through the eleventh resistor R11, and the output end of the second voltage comparator A2 is connected to the in-phase end of the second voltage comparator A2 through the twelfth resistor R12; The positive and negative electrodes of the third micro supercapacitor SC3 are connected in series through the fifth resistor R5 and the sixth resistor R6, wherein the middle of the fifth resistor R5 and the sixth resistor R6 is connected to the inverting end of the third voltage comparator A3, the non-inverting end of the third voltage comparator A3 is connected to the reference voltage Vref through the thirteenth resistor R13, and the output end of the third voltage comparator A3 is connected to the non-inverting end of the third voltage comparator A3 through the fourteenth resistor R14; the positive and negative electrodes of the fourth micro supercapacitor SC4 are connected in series through the seventh resistor R7 and the eighth resistor R8, wherein the middle of the seventh resistor R7 and the eighth resistor R8 is connected to the inverting end of the fourth voltage comparator A4, the non-inverting end of the fourth voltage comparator A4 is connected to the reference voltage Vref through the fifteenth resistor R15, and the output end of the fourth voltage comparator A4 is connected to the non-inverting end of the fourth voltage comparator A4 through the sixteenth resistor R16.

5. The supercapacitor chip according to claim 4, characterized in that: The output end of the first voltage comparator A1, the output end of the second voltage comparator A2, the output end of the third voltage comparator A3, and the output end of the fourth voltage comparator A4 are connected to the input end of the logic AND gate G1, the output end of the logic AND gate G1 is connected to the input end of the buffer G2, and the output end of the buffer G2 constitutes the first output end Φ1 of the voltage detection circuit.

6. The supercapacitor chip according to claim 5, characterized in that: The first output terminal Φ1 is connected to the second output terminal Φ2 through an inverter G3; the first output terminal Φ1 is used to control the charging process of the micro supercapacitor, and the second output terminal Φ2 is used to control the voltage equalization process of the micro supercapacitor.

7. The supercapacitor chip according to claim 6, characterized in that: The first output end Φ1 is respectively connected to the gate of the first switch tube M1, the gate of the second switch tube M2, the gate of the third switch tube M3 and the gate of the power switch M10; the second output end Φ2 is respectively connected to the gate of the fourth switch tube M4, the gate of the fifth switch tube M5, the gate of the sixth switch tube M6, the gate of the seventh switch tube M7, the gate of the eighth switch tube M8 and the gate of the ninth switch tube M9.

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