Modulation Wave Superposition DC Bias Modulation Method for Asymmetric Split-Bus Four-Level Inverter

Abstract

The invention discloses a modulation wave superimposed DC bias modulation method for an asymmetric split bus four-level inverter. The DC bus of the asymmetric split bus four-level inverter includes four groups of voltage sources. The modulation wave superimposed DC bias modulation method includes an A-phase modulation wave superimposed DC bias module, an A-phase upper drive signal generation module, an A-phase lower drive signal generation module, and an A-phase drive signal switching module. The upper positive triangle carrier, the upper negative triangle carrier, the lower positive triangle carrier, and the lower negative triangle carrier are adjusted according to the four groups of power supplies of the DC bus. The magnitude of the modulation wave is compared with zero, and the upper drive signal and the lower drive signal are switched by selecting a switch, and finally a drive signal is generated for driving a power switch device. The modulation wave superimposed DC bias modulation method for an asymmetric split bus four-level inverter proposed by the invention can ensure the normal operation of the inverter when the amplitudes of the four groups of power supplies of the DC bus change, and the output current has high sinusoidality and low harmonics, and has good adaptability.

Description

Technical Field

[0001] The invention relates to the field of power conversion and designs a modulation technology for an inverter, and specifically refers to a modulation wave superimposed direct current bias modulation method for an asymmetric split-bus four-level inverter. Background Art

[0002] The inverter is the core and key component of new energy power generation systems such as wind power and photovoltaic power generation, and its performance determines the quality of output power. Researching and applying four-level inverters can effectively promote the advancement of new energy power generation technology. Compared with traditional two-level and three-level inverters, four-level inverters have obvious advantages. First, the switching stress of the four-level inverter is low, and power switching devices with lower withstand voltage can be used; second, when the output current harmonics are the same, the four-level inverter can use a lower switching frequency and a smaller filter inductor to reduce switching loss and inductor loss.

[0003] In traditional diode-clamped four-level inverters or flying capacitor four-level inverters, additional clamping diodes or flying capacitors are required to assist in outputting the four-level voltage, and it is very difficult to balance the voltage of the DC bus. Asymmetric split-bus four-level inverters put forward new requirements for modulation strategies. When the bus voltage is asymmetric, the traditional modulation strategy cannot meet the impulse equivalent principle, which will greatly increase the output current harmonics and seriously affect the output power quality. Summary of the invention

[0004] The purpose of the present invention is to solve the above technical problems and provide a modulation wave superimposed DC bias modulation method for an asymmetric split-bus four-level inverter, which can ensure the normal operation of the inverter when the amplitudes of the four groups of power supplies of the DC bus change, and has high sinusoidality of the output current, low harmonics and good adaptability.

[0005] The present invention is implemented by the following technical scheme: a modulation wave superimposed DC bias modulation method for an asymmetric split bus four-level inverter, characterized in that: the main circuit includes four groups of voltage sources V1, V2, V1', V2' of the asymmetric split bus, and the connection mode of the three phases A, B, and C is the same; taking the A phase main circuit as an example, the power switch device Q a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 , and the load inductance L a , load resistance R a ; V1 negative pole and V2 positive pole are connected to point O, V1' negative pole and V2' positive pole are connected to point O', V1 positive pole and V1' positive pole are connected to the DC bus positive pole point P, V2 negative pole and V2' negative pole are connected to the DC bus negative pole point N; Q a1One end is connected to the positive pole P of the DC bus, and the other end is connected to the positive pole P of the DC bus. a Dot and Q a6 Connect, and then through Q a6 Connect to the negative pole of the DC bus, point N; point O through Q a4 and Q a5 Connect to X a Point; O' point through Q a2 and Q a3 Connect to X a Point; X a Point and A phase load inductance L a and A phase load resistance R a Connect in sequence; the three-phase modulation methods of A, B, and C are the same, and the A-phase modulation is still taken as an example, including an A-phase modulation wave superimposed DC bias module, an A-phase upper drive signal generating module, an A-phase lower drive signal generating module, and an A-phase drive signal switching module.

[0006] Preferably, in the A-phase modulation wave superposition DC bias module, on the one hand, the voltage sources V1' and V2' of the asymmetric split bus are subtracted and multiplied by the proportional coefficient 0.5 to obtain the upper DC bias u dc_up , A phase modulation wave u a * with u dc_up After superposition, the bias modulation wave u on phase A is obtained a_up * On the other hand, the voltage sources V1 and V2 of the asymmetric split bus are subtracted and multiplied by the proportional coefficient 0.5 to obtain the lower DC bias u dc_down , A phase modulation wave u a * with u dc_down After superposition, the A phase down-bias modulation wave u is obtained a_down * .

[0007] Preferably, in the upper drive signal generating module, on the one hand, the A phase upper bias modulation wave u a_up * With the upper positive triangle carrier C up1 Compare, if u a_up * >C up1 , then the upper drive signal S a1 + =1, S a3 + =0, otherwise S a1 + =0, S a3 + =1; on the other hand, the bias modulation wave u on phase A a_up * With the negative triangle carrier C up2Compare, if u a_up * >C up2 , then the upper drive signal S a2 + =1, S a6 + =0, otherwise S a2 + =0, S a6 + =1; In addition, S a4 + and S a5 + Maintain the 0 state in this module.

[0008] Preferably, in the lower drive signal generating module, on the one hand, the A phase lower bias modulation wave u a_down * With the lower positive triangle carrier C down1 Compare, if u a_down * >C down1 , then the lower driving signal S a1 – =1, S a5 – =0, otherwise S a1 – =0, S a5 – =1; on the other hand, the A phase down-bias modulation wave u a_down * With the negative triangle carrier C down2 Compare, if u a_down * >C down2 , then the lower driving signal S a4 – =1, S a6 – =0, otherwise S a4 – =0, S a6 – =1; In addition, S a2 – and S a3 – Maintain the 0 state in this module.

[0009] Preferably, in the A-phase drive signal switching module, the A-phase modulation wave u is compared. a * With the size of 0, by selecting the switch Sel, the upper drive signal S a1 + , S a2 + , S a3+ , S a4 + , S a5 + , S a6 + and the lower drive signal S a1 – , S a2 – , S a3 – , S a4 – , S a5 – , S a6 – Switch between them and finally generate the driving signal S a1 , S a2 , S a3 , S a4 , S a5 , S a6 , respectively used to drive the A phase power switch device Q a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 .

[0010] The beneficial effects of the present invention compared with the prior art are:

[0011] 1) The modulation wave superimposed DC bias modulation method of the asymmetric split bus four-level inverter proposed in the present invention adjusts the upper positive triangle carrier, the upper negative triangle carrier, the lower positive triangle carrier, and the lower negative triangle carrier according to the four groups of power supplies of the DC bus, and the output current has high sinusoidality and low harmonics;

[0012] 2) The modulation wave superposition DC bias modulation method of the asymmetric split-bus four-level inverter proposed in the present invention can ensure the normal operation of the inverter when the amplitudes of the four groups of power supplies of the DC bus change, and has good adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Main circuit topology of asymmetric split-bus four-level inverter

[0014] Figure 2 Principle diagram of the A-phase modulation wave superimposed DC bias modulation method

[0015] Figure 3 A-phase modulation wave superimposed DC bias module

[0016] Figure 4 A phase upper drive signal generation module

[0017] Figure 5 A phase lower drive signal generation module

[0018] Figure 6 A phase drive signal switching module

[0019] Figure 7 Schematic diagram of the drive signal generated by superimposing the modulation wave on phase A with DC bias

[0020] Figure 8 Schematic diagram of driving signal generated by superimposing DC bias on modulation wave in phase A

[0021] Fig. 9 Output current waveform when the modulation wave is not superimposed with DC bias

[0022] Fig.10 Output current waveform when the modulation wave of the present invention is superimposed with DC bias DETAILED DESCRIPTION

[0023] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0024] See also Figure 1 In the main circuit topology diagram of the asymmetric split bus four-level inverter, V1, V2, V1', and V2' are four groups of voltage sources for the asymmetric split bus. a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 is the power switch device of phase A, Q b1 , Q b2 , Q b3 , Q b4 , Q b5 , Q b6 is the power switch device of phase B, Q c1 , Q c2 , Q c3 , Q c4 , Q c5 , Q c6 It is the power switch device of phase C. a , L b , L c is the three-phase load inductance, R a , R b , R c is the three-phase load resistance. a 、i b 、i c is the three-phase output current.

[0025] Continue to see Figure 1 , take the A-phase main circuit as an example to explain the connection method of the main circuit. Points P and N are the positive and negative poles of the DC bus respectively; the negative pole of V1 and the positive pole of V2 are connected to point O, the negative pole of V1' and the positive pole of V2' are connected to point O', the positive pole of V1 and the positive pole of V1' are connected to the positive pole of the DC bus P, and the negative pole of V2 and the negative pole of V2' are connected to the negative pole of the DC bus N. Q a1 One end is connected to the positive pole P of the DC bus, and the other end is connected to the positive pole P of the DC bus. a Dot and Q a6 Connect, and then through Q a6 Connect to the negative pole of the DC bus, point N. Point O is connected to the negative pole of the DC bus, point Q a4 and Q a5 Connect to X a Point; O' point through Q a2 and Q a3 Connect to X a Point. X a Point and A phase load inductance L a and A phase load resistance R a The connection method of the B-phase and C-phase main circuits is the same as that of the A-phase, so it will not be repeated here.

[0026] In the modulation wave superimposed DC bias modulation method proposed in the present invention, the modulation methods of the three phases A, B and C are the same, and the implementation principle of the modulation wave superimposed DC bias modulation method is still introduced by taking the A phase as an example.

[0027] See also Figure 2 In the principle block diagram of the A-phase modulation wave superimposed DC bias modulation method, it includes an A-phase modulation wave superimposed DC bias module, an A-phase upper drive signal generating module, an A-phase lower drive signal generating module, and an A-phase drive signal switching module. The implementation method of each module is introduced below.

[0028] See also Figure 3 , in the A-phase modulation wave superimposed DC bias module, u a * is the A phase modulation wave, u dc_up is the upper DC bias, u a_up * is the bias modulation wave on phase A, u dc_down is the lower DC bias, u a_down * is the A phase down bias modulation wave. On the one hand, V1' and V2' are subtracted and multiplied by the proportional coefficient 0.5 to obtain the upper DC bias u dc_up , A phase modulation wave u a * with u dc_up After superposition, the bias modulation wave u on phase A is obtained a_up *On the other hand, subtract V1 from V2 and multiply by the proportionality factor 0.5 to obtain the lower DC bias u dc_down , A phase modulation wave u a * with u dc_down After superposition, the A phase down-bias modulation wave u is obtained a_down * .

[0029] See also Figure 4 In the upper drive signal generation module, on the one hand, C1 is a positive triangle carrier with an amplitude between 0 and 1; V1' and C1 are multiplied to obtain the upper positive triangle carrier C up1 , whose amplitude is between 0 and V1'; the bias modulation wave u on phase A a_up * With C up1 Compare, if u a_up * >C up1 , then the upper drive signal S a1 + =1, S a3 + =0, otherwise S a1 + =0, S a3 + =1. On the other hand, C2 is a negative triangular carrier with an amplitude between –1 and 0; V2' and C2 are multiplied to obtain the upper negative triangular carrier C up2 , whose amplitude is between –V2' and 0; the bias modulation wave u on phase A a_up * With C up2 Compare, if u a_up * >C up2 , then the upper drive signal S a2 + =1, S a6 + =0, otherwise S a2 + =0, S a6 + =1. In addition, S a4 + and S a5 + Maintain the 0 state in this module.

[0030] See also Figure 5 In the lower driving signal generation module, on the one hand, V1 is multiplied by the positive triangle carrier C1 to obtain the lower positive triangle carrier C down1 , its amplitude is between 0 and V1; A phase down bias modulation wave u a_down * With C down1Compare, if u a_down * >C down1 , then the lower driving signal S a1 – =1, S a5 – =0, otherwise S a1 – =0, S a5 – = 1. On the other hand, V2 is multiplied by the negative triangular carrier C2 to obtain the negative triangular carrier C down2 , its amplitude is between –V2 and 0. A phase lower bias modulation wave u a_down * With C down2 Compare, if u a_down * >C down2 , then the lower driving signal S a4 – =1, S a6 – =0, otherwise S a4 – =0, S a6 – =1. In addition, S a2 – and S a3 – Maintain the 0 state in this module.

[0031] See also Figure 6 In the A-phase drive signal switching module, the drive signal is switched by selecting the switch Sel. The selection switch Sel includes 4 terminals, Input1 and Input2 are selected signal input terminals, Com is the comparison signal input terminal, and Out is the output terminal. When the signal of the comparison signal input terminal Com is greater than 0, the output terminal Out will be connected to the selection signal input terminal Input1; when the signal of the comparison signal input terminal Com is less than or equal to 0, the output terminal Out will be connected to the selection signal input terminal Input2.

[0032] Continue to see Figure 6 , to generate the driving signal S a1 For example, the A phase modulation wave u a * Connected to the comparison signal input terminal Com, the upper drive signal S a1 + Connected to Input1, the lower drive signal S a1 – Connected to Input2, driving signal S a1 Connected to Out. On the one hand, when u a* >0, the output terminal Out of the selection switch Sel will be connected to Input1 internally, so that S a1 =S a1 + On the other hand, when u a * ≤0, the output terminal Out of the selection switch Sel will be connected to Input2 internally, so that S a1 =S a1 – .

[0033] Continue to see Figure 6 , compare the A phase modulation wave u a * With the size of 0, by selecting the switch Sel, the upper drive signal S a1 + , S a2 + , S a3 + , S a4 + , S a5 + , S a6 + and the lower drive signal S a1 – , S a2 – , S a3 – , S a4 – , S a5 – , S a6 – Switch between them and finally generate the driving signal S a1 , S a2 , S a3 , S a4 , S a5 , S a6 , respectively used to drive the A phase power switch device Q a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 .

[0034] In order to more specifically demonstrate the principle of the modulation wave superposition DC bias modulation method of the asymmetric split-bus four-level inverter, the generation of the drive signal is divided into Figure 7 and Figure 8 The two cases shown are further explained.

[0035] See also Figure 7In the schematic diagram of the drive signal generated by superimposing the modulation wave on the A phase, the A phase modulation wave u a * Superimposed with DC bias u dc_up Generate A phase bias modulation wave u a_up * .u a_up * With the upper positive triangle carrier C up1 , upper negative triangular carrier C up2 The comparison generates an upper drive signal. a * >0 in the upper drive signal enable region, the upper drive signal will be output through the selection switch Sel; a * In the upper prohibited area of ​​the drive signal ≤0, the upper drive signal will not be output.

[0036] See also Figure 8 In the schematic diagram of the driving signal generated by superimposing the modulation wave of phase A with DC bias, the modulation wave of phase A u a * Superimposed with DC bias u dc_down Generate A phase down bias modulation wave u a_down * .u a_down * With the lower positive triangle carrier C up1 , lower negative triangle carrier C up2 The comparison generates the lower drive signal. a * >0 in the down drive signal prohibition area, the down drive signal will not be output; a * In the lower drive signal enable region of ≤0, the lower drive signal will be output through the selection switch Sel.

[0037] The above describes in detail the A phase drive signal S a1 ~S a6 The generation process of the B-phase and C-phase drive signals S b1 ~S b6 , S c1 ~S c6 The generation process is the same and will not be repeated here.

[0038] In order to verify the proposed asymmetric split-bus four-level inverter modulation wave superimposed DC bias modulation method, simulation verification is carried out in Matlab / Simulink. The four groups of voltage sources V1, V2, V1', and V2' of the DC bus of the asymmetric split-bus four-level inverter are set to 400V, 200V, 200V, and 400V respectively; the three-phase load inductance L a , L b , Lc All are 1.5mH, three-phase load resistance R a , R b , R c All are 35Ω; the switching frequency is set to 20kHz, the modulation index is set to 0.8, and the dead time is set to 2μs. First, the modulation method without DC bias is adopted. The output current waveform is as follows Fig. 9 As shown. It can be seen that the three-phase output current contains a large number of harmonics. Through Fourier analysis, the three-phase current THD is 9.7%. Then, by adopting the modulation wave superimposed DC bias modulation method proposed in the present invention, the sinusoidality is significantly improved, and the three-phase current THD is 4.3%. It can illustrate the effectiveness of the asymmetric split bus four-level inverter modulation wave superimposed DC bias modulation method proposed in the present invention.

[0039] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A modulation wave superimposed DC bias modulation method for an asymmetric split-bus four-level inverter, characterized in that: The main circuit includes four groups of voltage sources V1, V2, V1', V2' of asymmetrical split busbars. The connection method of phases A, B and C is the same. Taking the A phase main circuit as an example, it includes power switching device Q a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 , and the load inductance L a , load resistance R a ; V1 negative pole and V2 positive pole are connected to point O, V1' negative pole and V2' positive pole are connected to point O', V1 positive pole and V1' positive pole are connected to the DC bus positive pole point P, V2 negative pole and V2' negative pole are connected to the DC bus negative pole point N; Q a1 One end is connected to the positive pole P of the DC bus, and the other end is connected to the positive pole P of the DC bus. a Dot and Q a6 Connect, and then through Q a6 Connect to the negative pole of the DC bus, point N; point O through Q a4 and Q a5 Connect to X a Point; O' point through Q a2 and Q a3 Connect to X a Point; X a Point and A phase load inductance L a and A phase load resistance R a The three-phase modulation methods of A, B and C are the same. The A-phase modulation is still taken as an example, which includes an A-phase modulation wave superimposed DC bias module, an A-phase upper drive signal generating module, an A-phase lower drive signal generating module and an A-phase drive signal switching module. In the A-phase modulation wave superimposed DC bias module, on the one hand, the voltage sources V1' and V2' of the asymmetrically split bus are subtracted, and the upper DC bias u is obtained after multiplying by the proportional coefficient 0.

5. dc_up , A phase modulation wave u a * with u dc_up After superposition, the bias modulation wave u on phase A is obtained a_up * On the other hand, the voltage sources V1 and V2 of the asymmetric split bus are subtracted and multiplied by the proportional coefficient 0.5 to obtain the lower DC bias u dc_down , A phase modulation wave u a * with u dc_down After superposition, the A phase down-bias modulation wave u is obtained a_down * In the upper drive signal generating module, on the one hand, the A phase upper bias modulation wave u a_up * With the upper positive triangle carrier C up1 Compare, if u a_up * >C up1 , then the upper drive signal S a1 + =1, S a3 + =0, otherwise S a1 + =0, S a3 + =1; on the other hand, the bias modulation wave u on phase A a_up * With the negative triangle carrier C up2 Compare, if u a_up * >C up2 , then the upper drive signal S a2 + =1, S a6 + =0, otherwise S a2 + =0, S a6 + =1; In addition, S a4 + and S a5 + Keep the 0 state in this module; in the lower drive signal generation module, on the one hand, the A phase lower bias modulation wave u a_down * With the lower sine triangle carrier C down1 Compare, if u a_down * >C down1 , then the lower driving signal S a1 – =1, S a5 – =0, otherwise S a1 – =0, S a5 – =1; on the other hand, the A phase down-bias modulation wave u a_down * With the negative triangle carrier C down2 Compare, if u a_down * >C down2 , then the lower driving signal S a4 – =1, S a6 – =0, otherwise S a4 – =0, S a6 – =1; In addition, S a2 – and S a3 – Keep the 0 state in this module; in the A phase drive signal switching module, compare the A phase modulation wave u a * With the size of 0, by selecting the switch Sel, the upper drive signal S a1 + , S a2 + , S a3 + , S a4 + , S a5 + , S a6 + and the lower drive signal S a1 – , S a2 – , S a3 – , S a4 – , S a5 – , S a6 – Switch between them and finally generate the driving signal S a1 , S a2 , S a3 , S a4 , S a5 , S a6 , respectively used to drive the A phase power switch device Q a1 , Q a2 , Q a3 , Q a4 , Q a5 , Q a6 .

Images