Photovoltaic inverter topology circuit and control method thereof

Abstract

The invention discloses a photovoltaic inverter topology circuit and a control method thereof. The photovoltaic inverter topology circuit comprises a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors and a plurality of diodes, the in-phase end of an operational amplifier U1 in the operational amplifiers is connected with one end of a resistor R2, the source electrode of an MOS tube Q2, the anti-phase end of the operational amplifier U1 in the operational amplifiers is connected with one end of a resistor R3, the source electrode of an MOS tube Q1, and the output end of the operational amplifier U1 in the operational amplifiers is connected with the other end of the resistor R3; the in-phase end of the operational amplifier U5 is connected with the cathode of the diode D4, the anti-phase end is connected with the in-phase end of the operational amplifier U6, the cathode of the diode D2 and one end of the capacitor C1, and the output end is connected with the anode of the diode D2; the inverting end of the operational amplifier U6 is connected with the output end and one end of the resistor R1; the grid electrode of the MOS tube Q1 is connected with the grid electrode of the MOS tube Q2, and the drain electrode is connected with one end of the resistor R4 The drain electrode of the MOS tube Q2 is connected with the other end of the resistor R1; the anode of the diode D4 is connected with the P1 end of the connector; the other end of the resistor R4 is connected with the P2 end of the connector; the other end of the capacitor C1 and the other end of the resistor R2 are grounded.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a photovoltaic inverter topology circuit and a control method thereof. Background Art

[0002] Publication No. CN118100292A discloses a photovoltaic inverter topology circuit, identification method, control system and control method. By arranging multiple DC conversion modules on the input side of the inverter module, when the number of photovoltaic strings is greater than the number of DC conversion modules, the excess photovoltaic strings are connected in parallel, and the input currents of the multiple DC conversion modules are balanced through MPPT loop control. Although this method can enable the inverter input to obtain the required current and voltage, its cost and volume are too high overall, and the photovoltaic components will cause parameter deviation due to light and loss aging, which will lead to differences in output current / voltage between each photovoltaic component, increasing the workload of the entire circuit. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a photovoltaic inverter topology circuit, including a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors, and a plurality of diodes. The operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R2 and the source of the MOS tube Q2 in the same phase, connected to one end of the resistor R3 and the source of the MOS tube Q1 in the opposite phase, and connected to the other end of the resistor R3 at the output terminal; the operational amplifier U5 is connected to the cathode of the diode D4 in the same phase, connected to the cathode of the diode D2 and one end of the capacitor C1 in the opposite phase, and connected to the anode of the diode D2 at the output terminal; the operational amplifier U6 is connected to the output terminal and one end of the resistor R1 in the opposite phase; the gate of the MOS tube Q1 is connected to the gate of the MOS tube Q2, and the drain is connected to one end of the resistor R4; the drain of the MOS tube Q2 is connected to the other end of the resistor R1; the anode of the diode D4 is connected to the end of the connector P1; the other end of the resistor R4 is connected to the end of the connector P2; the other end of the capacitor C1 and the other end of the resistor R2 are grounded.

[0004] Furthermore, it also includes an AND gate, wherein the operational amplifier U9 among the plurality of operational amplifiers is connected to one end of the resistor R1 in phase, connected to one end of the resistor R16 and the resistor R17 in reverse phase, and its output end is connected to the first input end of the AND gate U2 and the other end of the resistor R16; the second input end of the AND gate U2 is connected to the connector P3 end, and its output end is connected to the gate of the MOS tube Q1; and the other end of the resistor R17 is grounded.

[0005] Furthermore, the source of the MOS tube Q7 among the plurality of MOS tubes is connected to one end of the resistor R11, the gate is connected to the gate of the MOS tube Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS tube Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS tube Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

[0006] Furthermore, the op amp U8 among the plurality of op amps is connected to the source of the MOS tube Q8 at the same phase terminal, connected to the resistor R9 and one end of the resistor R10 at the opposite phase terminal, and connected to the gate of the MOS tube Q3 at the output terminal; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19R19; the other end of the resistor R10 and the source of the MOS tube Q3 are grounded.

[0007] Furthermore, the op amp U3 among the plurality of op amps is connected to the output end of the op amp U1 at the same phase terminal, connected to the same phase terminal of the op amp U4, the cathode of the diode D1, one end of the capacitor C4, and the drain of the MOS tube Q3 at the opposite phase terminal, and connected to the anode of the diode D1 at the output end; the op amp U4 is connected to the output end and the anode of the diode D3 at the opposite phase terminal; the cathode of the diode D3 is connected to the cathode of the diode D4; and the other end of the capacitor C4 is grounded.

[0008] Furthermore, it also includes a triode, wherein the operational amplifier U7 among the plurality of operational amplifiers is connected to the drain of the MOS tube Q6 and one end of the resistor R8 in the same phase terminal, connected to the other end of the resistor R9 in the opposite phase terminal, and connected to the gate of the MOS tube Q4 at the output terminal; the drain of the MOS tube Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS tube Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS tube Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS tube Q4, the resistor R8, and the other end of the resistor R13 are grounded.

[0009] Furthermore, one end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

[0010] Furthermore, one end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

[0011] Furthermore, one end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4, and the other end is grounded.

[0012] Furthermore, a photovoltaic inverter control method comprises the following steps:

[0013] S1. Obtaining initial demand signals and matching signals based on transformer parameters and photovoltaic module parameters;

[0014] S2. Obtain a matching start signal, and calculate and memorize the remaining required matching signals;

[0015] S3. Obtain a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the remaining matching signal is recalculated and memorized based on the matching parameters of this time;

[0016] S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

[0017] The beneficial effects of the present invention compared with the prior art are:

[0018] The present invention can automatically match and assemble the photovoltaic units in the photovoltaic module based on the required current of the inverter input end and the output current of each photovoltaic component, and can automatically match and assemble the photovoltaic module based on the required voltage of the inverter input end and the output voltage of each photovoltaic unit after matching and assembling, so as to prevent the increase of the workload of the entire circuit due to the difference in output current / voltage between each photovoltaic component when the photovoltaic component causes parameter deviation due to light and loss aging. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a circuit structure diagram provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0022] The invention discloses a photovoltaic inverter topology circuit, comprising a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors and a plurality of diodes. An operational amplifier U1 in the plurality of operational amplifiers is connected to one end of a resistor R2 and a source of a MOS tube Q2 in the same phase, connected to one end of a resistor R3 and a source of a MOS tube Q1 in the opposite phase, and connected to the other end of the resistor R3 in the output end; an operational amplifier U5 is connected to the cathode of a diode D4 in the same phase, connected to the cathode of an operational amplifier U6 in the opposite phase, connected to the same phase end of a diode D2 and one end of a capacitor C1 in the opposite phase, and connected to the anode of a diode D2 in the output end; an operational amplifier U6 in the opposite phase is connected to the output end and one end of a resistor R1 in the opposite phase; a gate of a MOS tube Q1 is connected to a gate of a MOS tube Q2, and a drain is connected to one end of a resistor R4; a drain of a MOS tube Q2 is connected to the other end of the resistor R1; an anode of a diode D4 is connected to an end of a connector P1; the other end of the resistor R4 is connected to an end of a connector P2; the other end of the capacitor C1 and the other end of the resistor R2 are grounded.

[0023] Specifically, it also includes an AND gate, wherein the operational amplifier U9 among the plurality of operational amplifiers is connected to one end of the resistor R1 in phase, connected to one end of the resistor R16 and the resistor R17 in reverse phase, and its output is connected to the first input end of the AND gate U2 and the other end of the resistor R16; the second input end of the AND gate U2 is connected to the connector P3, and its output is connected to the gate of the MOS tube Q1; and the other end of the resistor R17 is grounded.

[0024] Specifically, the source of the MOS tube Q7 among the plurality of MOS tubes is connected to one end of the resistor R11, the gate is connected to the gate of the MOS tube Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS tube Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS tube Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

[0025] Specifically, the op amp U8 among the plurality of op amps is connected to the source of the MOS tube Q8 in the same phase, connected to the resistor R9 and one end of the resistor R10 in the opposite phase, and connected to the gate of the MOS tube Q3 at the output end; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19R19; the other end of the resistor R10 and the source of the MOS tube Q3 are grounded.

[0026] Specifically, the op amp U3 among the plurality of op amps is connected to the output end of the op amp U1 in the same phase terminal, connected to the same phase terminal of the op amp U4, the cathode of the diode D1, one end of the capacitor C4, and the drain of the MOS tube Q3 in the opposite phase terminal, and connected to the anode of the diode D1 in the output end; the op amp U4 is connected to the output end and the anode of the diode D3 in the opposite phase terminal; the cathode of the diode D3 is connected to the cathode of the diode D4; and the other end of the capacitor C4 is grounded.

[0027] Specifically, it also includes a triode, wherein the operational amplifier U7 among the plurality of operational amplifiers is connected to the drain of the MOS tube Q6 and one end of the resistor R8 in the same phase terminal, connected to the other end of the resistor R9 in the opposite phase terminal, and connected to the gate of the MOS tube Q4 at the output terminal; the drain of the MOS tube Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS tube Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS tube Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS tube Q4, the resistor R8, and the other end of the resistor R13 are grounded.

[0028] Specifically, one end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

[0029] Specifically, one end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

[0030] Specifically, one end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4 , and the other end is grounded.

[0031] Specifically, a photovoltaic inverter control method includes the following steps:

[0032] S1. Obtaining initial demand signals and matching signals based on transformer parameters and photovoltaic module parameters;

[0033] S2. Obtain a matching start signal, and calculate and memorize the remaining required matching signals;

[0034] S3. Obtain a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the remaining matching signal is recalculated and memorized based on the matching parameters of this time;

[0035] S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

[0036] The photovoltaic unit is composed of several photovoltaic components connected in parallel, and the number of parallel connections is determined by the output current of each photovoltaic component and the required input current of the inverter. The photovoltaic module is composed of several photovoltaic units connected in series, and the photovoltaic units in series are determined by the output voltage of each photovoltaic unit and the required input voltage of the inverter. Before the matching and assembly of the photovoltaic modules, the photovoltaic units are matched and assembled first. A matching module is set in the topological circuit. When the photovoltaic units / photovoltaic modules are initially matched and assembled, the matching module feeds back an initial demand signal to the connector P1 on the topological circuit based on the demand current / demand voltage at the input end of the inverter. The amplitude of the initial demand signal is the middle value of the allowable deviation range of the demand current / demand voltage at the input end of the inverter. Connector P1 on the topological circuit The demand signal is obtained, and the connector P2 obtains the matching signal. If the photovoltaic unit is formed, when the topology circuit obtains the signal feedback from the connector P1 end once, the first memory end on the topology circuit automatically memorizes the signal, and then the matching module selects the photovoltaic component with the largest output current among all photovoltaic components and feeds back the corresponding matching signal to the connector P2 on the topology circuit based on its output current. The signal is the initial matching current signal. If the photovoltaic module is formed, the signal obtained by the connector P1 end is the demand voltage signal of the inverter input end. When the topology circuit obtains the signal feedback from the connector P1 end once, the first memory end on the topology circuit automatically memorizes the signal, and then the matching module selects the photovoltaic unit with the largest output voltage among all photovoltaic units and feeds back the corresponding matching signal to the connector P2 on the topology circuit. Based on its output voltage, the corresponding matching signal is fed back to the connector P2 on the topology circuit. The matching signal is the initial matching voltage signal. After the connector P2 end obtains the feedback, the matching module feeds back the matching start signal to the connector P3 on the topology circuit. When the topology circuit obtains the matching start signal, the topology circuit calculates the remaining required matching signal based on the initial required memory signal amplitude and the initial matching signal amplitude. After the calculation is completed, the second memory end of the topology circuit automatically memorizes the signal. When the topology circuit loses the matching start signal, the topology circuit prioritizes clearing the first memory end signal, and after clearing it, it records the second memory end signal. After the first matching is completed, the matching module obtains the signal of the first memory end after the first matching is completed. Then the matching module compares the signal amplitude of the current / voltage output by the remaining photovoltaic components / photovoltaic units based on the amplitude of the first memory end signal. If there is no photovoltaic component / photovoltaic unit that can be directly matched, the photovoltaic component / photovoltaic unit with the largest output current / voltage is selected again and the corresponding matching signal is fed back to the connector P2 on the topology circuit based on its output current / voltage. When the matching module feeds back a new matching start signal again, the topology circuit clears the second memory end signal first. At the same time, the topology circuit calculates the difference between the remaining required matching signals based on the amplitude of the first memory end signal after the first matching and the amplitude of the matching signal fed back for the second time. After the calculation is completed, the second memory end of the topology circuit automatically memorizes the signal again.When the matching module finishes the feedback of the matching signal again, the first memory end signal is cleared and the second memory end signal is recorded. The successfully matched photovoltaic components are connected in parallel, and the successfully matched photovoltaic units are connected in series. In this way, the photovoltaic unit / photovoltaic module is formed by multiple matching. If the current / voltage amplitude output by the photovoltaic component / photovoltaic unit matched this time is consistent with the amplitude of the first memory end signal after the previous matching is completed, the topological circuit after the matching is completed automatically restores the initial state. If the output current / voltage of the photovoltaic unit / photovoltaic module is within the allowable deviation range of the required current / required voltage at the input end of the inverter after the last matching, the matching unit will feedback a signal amplitude higher than the first memory end signal amplitude at the last matching to reset the topological circuit. The photovoltaic modules are regularly re-matched to prevent the photovoltaic components from causing parameter deviation due to light and loss aging, and the increase in the workload of the entire circuit caused by the difference in output current / voltage between each photovoltaic component.

[0037] VCC is the power supply terminal, GND is the ground terminal, and the signal at the connector P1 end is fed back to the in-phase terminal of the operational amplifier U5 after passing through the diode D4. When the connector P1 end obtains the signal, the signal at the output end of the operational amplifier U5 causes the potential of the capacitor C1 to rise after passing through the diode D2. The signal at the capacitor C1 end rises to the same amplitude as the signal at the connector P1 end. When the connector P1 end loses the signal feedback, the diode D2 prevents reverse flow, and the signal at the capacitor C1 end is the first memory end signal. The signal at the capacitor C1 end is fed back to the in-phase terminal of the operational amplifier U6, and the operational amplifier U6 follows the output capacitor C1 end signal. At this time, the first memory end signal is the initial required voltage. The first memory signal is fed to the ground via resistor R1, the drain of MOS tube Q2, the source of MOS tube Q2, and resistor R2. The signal at the end of resistor R2 is fed back to the in-phase end of op amp U1. The initial matching current / voltage signal is fed back to the inverting end of op amp U1 via the drain of MOS tube Q1, the source of MOS tube Q1, and the output end of op amp U1 is negatively feedback connected to the inverting end of op amp U1 via resistor R3. At this time, op amp U1 outputs the remaining required matching current / voltage signal, which is the difference between the amplitude of the initial required current / voltage memory signal and the initial matching current / voltage signal.

[0038] The output signal of the operational amplifier U6 is fed back to the in-phase terminal of the operational amplifier U9. The output signal of the operational amplifier U9 is fed back to the ground terminal through the resistor R16 and the resistor R17. The signal at the resistor R17 terminal is fed back to the inverting terminal of the operational amplifier U9 so that the operational amplifier U9 amplifies and outputs the amplitude of the initial memory signal. The output signal of the operational amplifier U9 is fed back to the first input terminal of the AND gate U2. The connector P3 is used to obtain the matching start signal. After the matching module feeds back the initial demand current / demand voltage signal and the matching current signal to the topological circuit, the matching start signal is fed back to the topological circuit again. The signal is fed back to the second input terminal of the AND gate U2 through the connector P3. The AND gate U2 outputs, and the output signal of the AND gate U2 is fed back to the gate of the MOS tube Q1 and the gate of the MOS tube Q2. The resistor R5 is used to discharge the parasitic capacitance of the gate of the MOS tube Q1 and the gate of the MOS tube Q2. When the AND gate U2 outputs, the voltage difference between the gate of the MOS tube Q1 and the source of the MOS tube Q1 is higher than the conduction threshold, and the MOS tube Q1 is turned on. The voltage difference between the gate of the MOS tube Q2 and the source of the MOS tube Q2 is higher than the conduction threshold, and the MOS tube Q2 is turned on. In this way, the topology circuit enables the operational amplifier U1 to output the remaining required matching current / voltage signal after obtaining the matching start signal.

[0039] The matching start signal is synchronously fed back to the gate of MOS tube Q7 and the gate of MOS tube Q8. When the connector P3 end does not obtain the matching start signal feedback, the power signal passes through resistor R11, MOS tube Q7 source, MOS tube Q7 drain, and resistor R12 to the ground end. The capacitor C3 end has an initial potential, and the power signal passes through resistor R15, resistor R9, and resistor R10 to the ground end. The signal at the resistor R10 end is fed back to the inverting end of the operational amplifier U8, and the operational amplifier U8 is cut off. When the connector P3 end obtains the matching start signal feedback When the voltage difference between the gate of MOS tube Q7 and the source of MOS tube Q7 is higher than the conduction threshold, MOS tube Q7 is cut off, the voltage difference between the gate of MOS tube Q8 and the source of MOS tube Q8 is higher than the conduction threshold, MOS tube Q8 is turned on, the potential of capacitor C3 decreases, and the signal at the end of capacitor C3 is fed back to the ground terminal through the drain of MOS tube Q8, the source of MOS tube Q8, and resistor R14. The signal at the end of resistor R14 is fed back to the in-phase terminal of op amp U8, and op amp U8 outputs. When the amplitude of the signal at the end of capacitor C3 is lower than the amplitude of the signal at the end of resistor R10, The operational amplifier U8 is cut off again, and the output signal of the operational amplifier U8 is fed back to the gate of the MOS tube Q3. The resistor R6 is used to discharge the parasitic capacitance of the gate of the MOS tube Q3. When the operational amplifier U8 outputs, the voltage difference between the gate of the MOS tube Q3 and the source of the MOS tube Q3 is higher than the conduction threshold, the MOS tube Q3 is turned on, and the signal at the capacitor C4 end is connected to the ground terminal through the drain of the MOS tube Q3 and the source of the MOS tube Q3, and the capacitor C4 end is to the ground potential. When the operational amplifier U8 is cut off, the MOS tube Q3 is cut off, and the amplitude of the signal at the capacitor C4 end rises to the amplitude of the signal at the output end of the operational amplifier U1. The signal at the capacitor C4 end is the second memory end signal, and the signal at the capacitor C4 end is fed back to the in-phase end of the operational amplifier U4. The output end of the operational amplifier U4 and the inverting end of the operational amplifier U4 are negatively feedback connected, and the operational amplifier U4 follows the output capacitor C4 end signal. At this time, the second memory end signal is the memory signal of the remaining required matching current / voltage signal, so that when the matching module feeds back the matching start signal each time, the signal at the second memory end is cleared first, and then the remaining required matching current / voltage signal is memorized.

[0040] The output signal of the operational amplifier U4 is fed back to the in-phase terminal of the operational amplifier U5 through the diode D3. When the connector P3 receives the signal feedback, the signal passes through the base and emitter of the transistor Q5 to increase the potential of the capacitor C2. At the same time, the base and emitter of the transistor Q5 are forward biased, and the transistor Q5 is turned on. The signal at the connector P3 is synchronously fed back to the gate of the MOS tube Q6. The resistor R13 is used to discharge the parasitic capacitance of the gates of the MOS tubes Q6, Q7, and Q8. When the connector When the P3 terminal loses signal feedback, the voltage difference between the gate of the MOS tube Q6 and the source of the MOS tube Q6 is higher than the conduction threshold, the MOS tube Q6 is turned on, and the signal at the capacitor C2 terminal passes through the source of the MOS tube Q6, the drain of the MOS tube Q6, and the resistor R8 to the ground terminal. The signal at the resistor R8 terminal is fed back to the in-phase terminal of the operational amplifier U7, and the signal at the resistor R9 terminal is fed back to the inverting terminal of the operational amplifier U7. The operational amplifier U7 outputs. When the signal amplitude at the capacitor C2 terminal is lower than the signal amplitude at the resistor R9 terminal, the operational amplifier U7 is cut off, and the signal at the output terminal of the operational amplifier U7 is fed back to the MOS tube Q4 gate, resistor R7 is used to discharge the parasitic capacitance of the gate of MOS tube Q4. When the operational amplifier U7 outputs, the voltage difference between the gate of MOS tube Q4 and the source of MOS tube Q4 is higher than the conduction threshold, MOS tube Q4 is turned on, and the signal at the capacitor C1 end is connected to the ground terminal through the drain of MOS tube Q4 and the source of MOS tube Q4, and the capacitor C1 end is connected to the ground potential. At this time, the memory signal of the first memory end is cleared. When the operational amplifier U7 is turned off, the potential of the capacitor C1 end rises, and the potential of the capacitor C1 end rises to the potential of the capacitor C4 end. At this time, the memory signal of the first memory end is the memory signal of the remaining required matching current / voltage signal. Therefore, after the matching module feeds back the matching start signal for the first time, the initial required current / voltage memory signal memorized by the first memory end is cleared first, and then the signal amplitude of the second memory end is memorized. When the matching module feeds back the matching signal again, the remaining required matching current / voltage signal output by the operational amplifier U1 at this time is the difference between the amplitude of the remaining required matching current signal calculated for the first time and the matching current signal fed back for the second time.

[0041] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A photovoltaic inverter topology circuit, characterized in that: The invention comprises a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors and a plurality of diodes. The operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R2 and the source of the MOS tube Q2 in the same phase, connected to one end of the resistor R3 and the source of the MOS tube Q1 in the opposite phase, and connected to the other end of the resistor R3 in the output end; the operational amplifier U5 is connected to the cathode of the diode D4 in the same phase, connected to the cathode of the diode D2 and one end of the capacitor C1 in the opposite phase, and connected to the anode of the diode D2 in the output end; the operational amplifier U6 is connected to the output end and one end of the resistor R1 in the opposite phase; the gate of the MOS tube Q1 is connected to the gate of the MOS tube Q2, and the drain is connected to one end of the resistor R4; the drain of the MOS tube Q2 is connected to the other end of the resistor R1; the anode of the diode D4 is connected to the end of the connector P1; the other end of the resistor R4 is connected to the end of the connector P2; the other end of the capacitor C1 and the other end of the resistor R2 are grounded.

2. The photovoltaic inverter topology circuit according to claim 1, characterized in that: It also includes an AND gate, wherein the operational amplifier U9 among the plurality of operational amplifiers is connected to one end of the resistor R1 in the same phase, connected to one end of the resistor R16 and the resistor R17 in the opposite phase, and its output is connected to the first input end of the AND gate U2 and the other end of the resistor R16; the second input end of the AND gate U2 is connected to the connector P3 end, and its output is connected to the gate of the MOS tube Q1; and the other end of the resistor R17 is grounded.

3. The photovoltaic inverter topology circuit according to claim 2, characterized in that: The source of the MOS tube Q7 among the plurality of MOS tubes is connected to one end of the resistor R11, the gate is connected to the gate of the MOS tube Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS tube Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS tube Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

4. The photovoltaic inverter topology circuit according to claim 3, characterized in that: The operational amplifier U8 among the plurality of operational amplifiers is connected to the source of the MOS tube Q8 in the same phase terminal, connected to the resistor R9 and one end of the resistor R10 in the opposite phase terminal, and connected to the gate of the MOS tube Q3 at the output terminal; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19; the other end of the resistor R10 and the source of the MOS tube Q3 are grounded.

5. The photovoltaic inverter topology circuit according to claim 4, characterized in that: The operational amplifier U3 among the plurality of operational amplifiers is connected to the output end of the operational amplifier U1 in the same phase terminal, connected to the same phase terminal of the operational amplifier U4, the cathode of the diode D1, one end of the capacitor C4, and the drain of the MOS tube Q3 in the opposite phase terminal, and connected to the anode of the diode D1 in the output end; the operational amplifier U4 is connected to the output end and the anode of the diode D3 in the opposite phase terminal; The cathode of the diode D3 is connected to the cathode of the diode D4; the other end of the capacitor C4 is grounded.

6. The photovoltaic inverter topology circuit according to claim 2, characterized in that: It also includes a triode, wherein the operational amplifier U7 among the plurality of operational amplifiers is connected to the drain of the MOS tube Q6 and one end of the resistor R8 in the same phase terminal, connected to the other end of the resistor R9 in the opposite phase terminal, and connected to the gate of the MOS tube Q4 at the output terminal; the drain of the MOS tube Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS tube Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS tube Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS tube Q4, the resistor R8, and the other end of the resistor R13 are grounded.

7. The photovoltaic inverter topology circuit according to claim 1, characterized in that: One end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

8. The photovoltaic inverter topology circuit according to claim 4, characterized in that: One end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

9. The photovoltaic inverter topology circuit according to claim 6, characterized in that: One end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4 , and the other end is grounded.

10. A photovoltaic inverter control method, characterized in that: The steps include: S1. Obtaining initial demand signals and matching signals based on transformer parameters and photovoltaic module parameters; S2. Obtain a matching start signal, and calculate and memorize the remaining required matching signals; S3. Obtain a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the remaining matching signal is recalculated and memorized based on the matching parameters of this time; S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

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