Method and device for balancing neutral-point potential of three-level converter suitable for unbalanced load

Abstract

The invention discloses a neutral-point potential balancing method and device for a three-level converter suitable for an unbalanced load, and belongs to the technical field of three-level converter control, and the method comprises the steps: 1, carrying out the positive and negative sequence separation of a sampling signal, and achieving the output of a three-phase balanced voltage; step 2, calculating an ideal zero-sequence component needing to be added in the modulated wave; step 3, analyzing the adjustment capability of adding the ideal zero-sequence component, and if the adjustment capability is satisfied, executing step 4; if not, skipping to step 7; 4, correcting a modulation wave symbol in the ideal zero-sequence component; 5, designing a potential regulator of the zero-sequence voltage based on the corrected modulation wave symbol; 6, performing amplitude limiting on the sum of the zero-sequence component generated by the potential regulator and the ideal zero-sequence component; step 7, carrying out midpoint balance by using an external balance circuit; and the three-level converter stops running, and the process is ended. According to the invention, neutral-point potential balance of the three-level converter is realized by adding the zero-sequence component in modulation.

Description

Technical Field

[0001] The present invention belongs to the technical field of three-level converter control, and particularly relates to a method and device for balancing the neutral point potential of a three-level converter applicable to unbalanced loads. Background Technique

[0002] Three-level converters have been widely used due to their relatively simple structure and high-voltage high-power application characteristics. Three-level converters need to operate stably under various conditions such as unbalanced loads and unbalanced grid voltages to achieve the given power output. Therefore, the control methods of three-level converters, such as the balance of the DC-side neutral point potential and the smooth switching between grid-connected and off-grid of the converter, have always been the key technologies in the research of three-level topologies. There are technical defects in the control of three-level converters, which will cause neutral point shift, generate low-order harmonics in the output voltage, and external unbalanced conditions will also inject negative-sequence current into the neutral point, aggravating the neutral point potential shift. Currently, the commonly used methods for controlling the neutral point voltage balance include external circuits and improved modulation. The modulation methods are further divided into setting the time factor to change the action time of positive and negative small vectors and adding a zero-sequence component to the modulation wave.

[0003] There are some different circuit topologies for the external balancing method. For example, using a multi-tap transformer and two three-phase rectifier circuits to obtain two independent DC voltage sources for power supply; adding different converters to the neutral point of the bus capacitor to inject or extract current into the neutral point, and using the front-end Boost circuit to control the neutral point voltage balance; adopting a back-to-back structure to control the neutral point voltage balance, etc., can effectively maintain the neutral point potential balance. However, all external circuits require the operation of switching devices, resulting in power losses.

[0004] In the modulation method, setting the time factor is essentially based on the fact that the positive and negative small vectors in SVPWM have opposite effects on the neutral point potential, and the balance of the neutral point potential is maintained by changing the action time of the positive and negative small vectors. The main research is divided into two parts: one part is the improvement of the design of the control method itself, and the other part is the improvement of the setting of the time factor. However, this method can only be applied in the vector modulation method. The method of adding a zero-sequence component is to achieve charge conservation within a unit time by adding a zero-sequence component to the modulation wave, thereby maintaining the balance of the neutral point potential.

[0005] Unbalanced three-phase output voltage may lead to system instability, motor heating and vibration. It causes an increase in system losses and a decrease in the overall efficiency of the system. Under unbalanced operating conditions, both the power grid and the electrical load are negatively affected. Large-capacity three-phase inverter power supplies usually require to drive hybrid loads, and it is of great significance to suppress unbalanced operating conditions. Under unbalanced operating conditions, positive and negative sequence separation control is first required to control and achieve output targets, such as outputting balanced three-phase voltage or current, etc. Under unbalanced loads, when balanced three-phase voltage is required, the negative sequence current in the three-phase current will affect the balance of the neutral point potential, resulting in an exacerbation of the neutral point potential offset, affecting the stable operation of the system, causing uneven pressure on the DC-side capacitors, and leading to problems such as device failures. Summary of the Invention

[0006] To make up for the deficiencies of the prior art, the present invention proposes a neutral point potential balancing method and device for a three-level converter applicable to unbalanced loads. By separating the positive and negative sequences of the sampled signals and then controlling them respectively, balanced three-phase voltage output is achieved. By adding a zero-sequence component in modulation, the influence brought by unbalanced current, especially the negative sequence current component, is eliminated.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] In the first aspect, the present invention provides a neutral point potential balancing method for a three-level converter applicable to unbalanced loads, including the following steps:

[0009] Step 1: Separate the positive and negative sequences of the sampled voltage signal and current signal to obtain the positive and negative sequence components of the voltage signal and current signal, and control the positive and negative sequence components of the voltage signal and current signal respectively to output balanced three-phase voltage;

[0010] Step 2: Calculate the ideal zero-sequence component that needs to be added to the modulation wave to achieve neutral point potential balance under ideal conditions;

[0011] Step 3: Analyze the regulation ability of adding the ideal zero-sequence component. If the regulation ability is satisfied, execute Step 4; if not, jump to Step 7;

[0012] Step 4: Correct the modulation wave symbol in the ideal zero-sequence component;

[0013] Step 5: Design a potential regulator for the zero-sequence voltage based on the corrected modulation wave symbol;

[0014] Step 6: Limit the amplitude of the finally added zero-sequence voltage component. The finally added zero-sequence voltage component is the sum of the zero-sequence component generated by the potential regulator and the ideal zero-sequence component. Superimpose the amplitude-limited finally added zero-sequence voltage component on the modulation wave to obtain an improved modulation wave, and use the improved modulation wave to output the switching control signal of the three-level converter, so that the DC-side neutral point potential remains balanced;

[0015] Step 7: Use an external balancing circuit for midpoint balancing. If the three-level converter has not stopped running, jump to Step 1; if the three-level converter has stopped running, end the process.

[0016] Furthermore, in the said Step 2, the calculation formula for the ideal zero-sequence component to be added to the modulation wave is:

[0017]

[0018] where i np0 = [-sign(v a )·i a -sign(v b )·i b -sign(v c )·i c ;

[0019] i npav = (1 - v a ·sign(v a ))·i a + (1 - v b ·sign(v b ))·i b + (1 - v c ·sign(v c ))·i c ;

[0020] where C is the capacitance value of the upper DC capacitor C 1 and the lower DC capacitor C 2 , U dc1 is the upper DC capacitor voltage, U dc2 is the lower DC capacitor voltage, i npav is the average midpoint current, T s represents the unit switching period, f s represents the switching frequency, i np0 and i npav are intermediate variables, v a , v b , v c are the three-phase modulation wave amplitudes of the converter, i a , i b , i c represent the three-phase output currents of the converter, and sign is the sign verification function.

[0021] Furthermore, the said Step 3 includes the following steps:

[0022] Step 3.1: Calculate the ideal zero-sequence component V 0The interval is calculated by the formula:

[0023]

[0024] where δ is the midpoint voltage unbalance degree, and the maximum value, intermediate value, and minimum value of the three-phase modulation wave amplitude in the per-unit control are denoted as V max 、V mid 、V min ;

[0025] Step 3.2: Simplify to obtain the maximum value V o and the minimum value V omax of the ideal zero-sequence component V omin in the per-unit control as:

[0026]

[0027] Step 3.3: Use s to represent the sign of V mid +V o to characterize the sign change of the modulation wave;

[0028] According to the value of s and the range of -V mid , analyze the maximum and minimum values of the required added zero-sequence component V o . The maximum and minimum values are the upper and lower bounds of the limit controllable zero-sequence voltage range;

[0029] Step 3.3: Estimate the ideal zero-sequence component V in the per-unit control according to 0 , where V dc is the bus voltage on the DC side; if V 0 is within the limit controllable voltage range, execute Step 4; if not, jump to Step 7.

[0030] Furthermore, Step 4 includes the following steps: Determine whether sign(v mid ) = sign(v mid +v 0 ) holds: If it does not hold, change the sign of sign(v mid ) = sign(v mid +v 0 ) in the intermediate variables i npav and i np0 , and update the ideal zero-sequence component; if it holds, do not update the ideal zero-sequence component; where sign(v mid ) is the intermediate value of the three-phase modulation wave amplitude.

[0031] Furthermore, in Step 5, the zero-sequence component v' 0 generated by the potential regulator is:

[0032]

[0033] Among them, C is the capacitance value of the upper DC capacitor C and the lower DC capacitor C of the three-level converter, U is the voltage of the upper DC capacitor, U is the voltage of the lower DC capacitor, f represents the switching frequency, and i takes the value of the amplitude of the three-phase positive-sequence current. 1 and the lower DC capacitor C 2 of the capacitance value, U dc1 is the voltage of the upper DC capacitor, U dc2 is the voltage of the lower DC capacitor, f s represents the switching frequency, i m takes the value of the amplitude of the three-phase positive-sequence current, is the phase difference between the modulation wave and the output current.

[0034] Further, in the step 5, the transfer function of the potential regulator is:

[0035]

[0036] In the formula: W NPVR is the transfer function of the regulator, s is the Laplace operator, K CP is the proportional coefficient of the PI regulator; K CI is the integral coefficient; τ c is the time constant.

[0037] Further, in the step 6, the final added zero-sequence voltage component is limited by the following formula:

[0038]

[0039] Among them, v 0 is the ideal zero-sequence component, v' 0 is the output result of the potential regulator, v max is the maximum value among the amplitudes of the three-phase modulation waves, v min is the minimum value among the amplitudes of the three-phase modulation waves.

[0040] In a second aspect, the present invention provides a neutral-point potential balancing device for a three-level converter applicable to unbalanced loads, including:

[0041] at least one processor; and,

[0042] a memory communicatively connected to the at least one processor; wherein,

[0043] the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for balancing the neutral-point potential of a three-level converter applicable to unbalanced loads as described in any one of the first aspects of the present invention.

[0044] In a third aspect, the present invention provides a computer-readable storage medium storing a computer program, characterized in that when the computer program is executed by a processor, it implements the method for balancing the neutral point potential of a three-level converter applicable to unbalanced loads according to any one of the first aspects of the present invention.

[0045] In a fourth aspect, the present invention provides a computer program product including a computer program, characterized in that when the computer program is executed by a processor, it implements the steps of the method for balancing the neutral point potential of a three-level converter applicable to unbalanced loads according to any one of the first aspects of the present invention.

[0046] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0047] The neutral point potential control method combining the ideal zero-sequence component and the potential regulator provided by the present invention realizes the neutral point potential balance of the three-level converter by superimposing the ideal zero-sequence component and the zero-sequence component generated by the potential regulator on the modulation wave; the potential recovery can be effectively and quickly realized through the ideal feedforward, improving the dynamic performance of the neutral point balance; the voltage fluctuation and distortion rate at steady state are reduced by the feedback of the zero-sequence component generated by the potential regulator. At the same time, it is possible to judge whether an external balancing circuit needs to be adopted by analyzing the extreme value of the zero-sequence component. The external circuit itself requires switching devices to be turned on, which causes relatively large power loss. The external circuit is not turned on within the controllable range and plays a guarantee role when out of control. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a flow chart of the method for balancing the neutral point potential of a three-level converter applicable to unbalanced loads provided by the present invention;

[0050] Figure 2 It is a structural topology diagram of a T-type three-level grid-connected converter in an embodiment of the present invention;

[0051] Figure 3 It is a basic dq-axis decoupling control block diagram of the present invention;

[0052] Figure 4 It is a mathematical model diagram of the potential feedback regulator in an embodiment of the present invention;

[0053] Figure 5 It is a potential balance control block diagram in an embodiment of the present invention;

[0054] Figure 6a In the embodiment of the present invention, the negative sequence current generated by the converter under unbalanced conditions exacerbates the potential offset;

[0055] Figure 6b It is the potential regulation waveform diagram of the converter in the embodiment of the present invention after adding the zero sequence component;

[0056] Figure 7 It is the potential balance process diagram of the converter in the embodiment of the present invention;

[0057] Figure 8a In the embodiment of the present invention, the negative sequence current generated by the converter under unbalanced conditions exacerbates the potential offset;

[0058] Figure 8b It is the potential regulation waveform diagram of the converter in the embodiment of the present invention after adding the zero sequence component;

[0059] Figure 9 It is the effect diagram of the potential balance dynamic and steady-state semi-physical experiment of the converter in the embodiment of the present invention;

[0060] Figure 10a In the embodiment of the present invention, the negative sequence current generated by the converter under unbalanced conditions exacerbates the potential offset;

[0061] Figure 10b It is the potential regulation waveform diagram of the converter in the embodiment of the present invention after adding the zero sequence component;

[0062] Figure 11 It is the effect diagram of the potential balance dynamic and steady-state experiment of the converter in the embodiment of the present invention. Specific embodiments

[0063] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0065] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can also be another element in the middle. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be another element in the middle at the same time. The orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. used in this article is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0066] Unless otherwise defined, all technical and scientific terms used in this article have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this article are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this article includes any and all combinations of one or more of the related listed items.

[0067] Embodiment 1

[0068] Refer to Figure 1 , a neutral point potential balancing method for a three-level converter applicable to unbalanced loads, characterized in that it stably operates under various actual working conditions and maintains the balance of the three-phase output voltage and the DC side neutral point potential. It includes the following steps:

[0069] Step 1: Separate the positive and negative sequences of the sampled voltage signal and current signal, and realize the output of three-phase balanced voltage by controlling the positive and negative sequences respectively.

[0070] Design an all-pass filter The amplitude-frequency characteristic is 1, and the phase-frequency characteristic has a 90° delay for 50Hz. It is used to generate a 90° phase delay for the fundamental frequency of 50Hz to construct a phase-shifting circuit link Obtain the transformation matrix; this transformation matrix is used for the positive and negative sequence separation of the sampled voltage and current signals. The following is the process of positive and negative sequence separation of voltage.

[0071] Convert the measured three-phase voltage signal from the abc coordinate system to the αβ coordinate system to obtain the components of the three-phase voltage on the α and β axes. According to the instantaneous symmetrical component method, based on the transformation matrix, the three-phase positive sequence voltage and the three-phase negative sequence voltage can be obtained from the three-phase voltage on the α and β axes. Formulas (1) and (2) are the formulas for transforming the three-phase voltage signal:

[0072]

[0073] Among them, u ap, u bp , u cp is the three-phase positive-sequence voltage; u an , u bn , u cn is the three-phase negative-sequence voltage; u α , u β are the components of the three-phase voltage on the α and β axes.

[0074] The positive-sequence and negative-sequence parts of the voltage signal and current signal after positive-negative sequence separation are controlled separately. The control process is as follows: perform dq transformation, decouple the components of the voltage and current on the d and q axes, and then independently control the voltage and current signals on the dq axes to achieve the voltage or current control target. The decoupling control process is as Figure 3 shown.

[0075] Figure 3 is the control block diagram of circuit modeling based on represents the d-axis component of the current reference value before filtering represents the q-axis component of the current reference value before filtering, represents the d-axis component of the actual current value before filtering, represents the q-axis component of the actual current value before filtering, represents the d-axis component of the current reference value after filtering, represents the q-axis component of the current reference value after filtering represents the d-axis component of the actual current value after filtering, represents the d-axis component of the actual current value after filtering; represents the d-axis component of the given value of the output voltage of the converter after filtering, represents the q-axis component of the given value of the output voltage of the converter after filtering, represents the d-axis component of the actual output voltage of the converter after filtering, represents the q-axis component of the actual output voltage of the converter after filtering; ω b represents the fundamental angular frequency of the power grid, L m , R m , C f Filter inductor, inductor in parallel with resistor, capacitor.

[0076] When the control target is three-phase voltage balance, that is, control the negative-sequence component of the three-phase voltage to be 0, and the positive-sequence component outputs the required rated voltage value. Thus, control the converter to output three-phase balanced voltage, and the positive and negative sequences of the three-phase current participate in the control as the current inner loop.

[0077] Step 2: Calculate the zero-sequence component that needs to be added to the modulation wave to achieve midpoint potential balance under ideal conditions.

[0078] After control, the per-unit value of the parameters is carried out, and the ideal zero-sequence component added at this time is set to v 0 .

[0079] According to the analysis of different switch states, the current i np (t) injected into the midpoint within unit time can be expressed as the synthesis of the currents controlled by the switch states:

[0080] i np (t) = (1 - |S a |)i a + (1 - |S b |)i b + (1 - |S c |)i c (3)

[0081] where, i a , i b , i c represent the three-phase output currents of the converter. S a , S b , S c represent the switch states of phases a, b, and c respectively. When S a = -1, 0, 1 are used to represent the three working states of a phase bridge arm. 1 means the bridge arm is connected to the high level, 0 means the bridge arm is connected to the midpoint, and -1 means the bridge arm is connected to the low level.

[0082] The average charge ΔQ 1 flowing into the midpoint within the unit switching period can be expressed as:

[0083]

[0084] where, v a , v b , v c are the amplitudes of the three-phase modulation waves of the converter. i npav is the average midpoint current, T s represents the unit switching period. sign is the sign verification function. When v a is positive, sign(v a ) is 1; when v a is 0, sign(v a ) is 0; when v a is negative, sign(v a ) is -1.

[0085] After superimposing the ideal zero-sequence component v x on the modulation wave v 0 , the modulation wave after adding the ideal zero-sequence component is x = a, b, c represents one of the three phases a, b, c. First, assume that adding the zero-sequence component does not change the sign of the modulation wave, and the average charge ΔQ flowing into the midpoint within a unit switching period 2 is:

[0086]

[0087] where, are the modulation waves after adding the ideal zero-sequence components to phases a, b, and c respectively.

[0088] It can be seen that after superimposing the zero-sequence component v 0 , the change in the charge ΔQ flowing into the neutral point is:

[0089] ΔQ = [-sign(v a )·i a -sign(v b )·i b -sign(v c )·i c ·v 0 ·T s = i np0 ·v 0 ·T s (6)

[0090] where, i np0 = [-sign(v a )·i a -sign(v b )·i b -sign(v c )·i c , i np0 is an intermediate variable;

[0091] In the actual working condition, there will also be many of the above-mentioned influences. Take the potential offset generated by them as the midpoint charge amount Q 0 at the initial state, which is expressed as:

[0092] Q 0 = C(U dc1 - U dc2 ) (7)

[0093] where, the capacitance values of the upper DC capacitor C 1 and the lower DC capacitor C 2 are the same and both are C, U dc1 is the voltage of the upper DC capacitor, and U dc2 is the voltage of the lower DC capacitor.

[0094] According to the charge conservation, the magnitude of the superimposed ideal zero-sequence component v 0 is:

[0095]

[0096] Among them, f s represents the switching frequency, and i npav = (1 - v a ·sign(v a ))·i a + (1 - v b ·sign(v b ))·i b + (1 - v c ·sign(v c ))·i c , where i npav is an intermediate variable.

[0097] Step 3: Analyze the regulation ability of the superimposed ideal zero-sequence component v 0 .

[0098] Define the ratio of the voltage difference ΔU between the upper and lower DC capacitors to the total DC voltage U dc as the midpoint voltage unbalance degree δ:

[0099]

[0100] The interval of the ideal zero-sequence component V 0 without per-unit control is:

[0101]

[0102] Among them, the maximum value, intermediate value, and minimum value of the three-phase modulation wave amplitudes without per-unit control are denoted as V max , V mid , V min .

[0103] After simplification, the maximum value V o and minimum value V omax of the ideal zero-sequence component V omin without per-unit control are:

[0104]

[0105] Use s to represent the sign of V mid + V o to characterize the sign change of the modulation wave. The value-taking situations of s in different cases are summarized in Table 1 as follows.

[0106] Table 1 Value-taking of s

[0107]

[0108] The ideal zero-sequence component V without per-unit controlo The value range is limited. According to the value of s and -V mid range, analyze the zero-sequence component V o required to be added in each case o-1 of the extreme point V o-2 and V o-3 as shown in Table 2.

[0109] Table 2 V o Value of extreme point

[0110]

[0111] The maximum and minimum values among them are the upper and lower bounds of the limit-controllable zero-sequence voltage range. Obtained by ideal calculation Among them, V dc is the bus voltage on the DC side; estimate from this. If V 0 is within the limit-controllable voltage range, continue with Step 4. If not satisfied, jump to Step 7.

[0112] Step 4: Verify and update the modulation wave symbol in the ideal zero-sequence component.

[0113] Let the maximum, intermediate, and minimum values of the amplitudes of the three-phase modulation waves v x after per-unit transformation be denoted as v max , v mid , v min respectively. Only the intermediate value term among the amplitudes of the three-phase modulation waves may change sign after adding the zero-sequence component. Verify the sign of the intermediate value sign(v mid ) of the amplitudes of the three-phase modulation waves to determine whether sign(v mid ) = sign(v mid + v 0 ) holds. If it holds, the estimated value of the assumed zero-sequence injection voltage is correct; otherwise, correct sign(v mid ) = -sign(v mid + v 0 ), change its sign in in p av and in p0 , and update the zero-sequence component.

[0114] Step 5: Design a potential regulator for the zero-sequence voltage. The zero-sequence component v' 0 generated by the potential regulator is used as the feedback of the DC-side capacitor voltage difference, combined with the ideal zero-sequence component, and superimposed on the modulation wave to obtain the improved modulation wave v' x ;

[0115] If the zero-sequence component v' 0, the average charge ΔQ flowing into the midpoint within a unit switching period 2 is:

[0116]

[0117] where v y (y = a, b, c) is the phase voltage with opposite sign to the other two-phase voltages, and i y is the phase current corresponding to v y . The modulation waves after adding the zero-sequence components v' 0 generated by the regulator to the three phases a, b, and c respectively are:

[0118] The average value over an inverter period is:

[0119]

[0120] where i m takes the value of the amplitude of the positive-sequence current of the three phases, is the phase difference between the modulation wave and the output current.

[0121] Thus, using the average current to replace the instantaneous current, we get

[0122]

[0123] Considering the initial charge again, the zero-sequence component v' 0 generated by the regulator is:

[0124]

[0125] The transfer function of the designed NPVR (Neutral Point Voltage Regulator) regulator is:

[0126]

[0127] In the formula: W NPVR is the transfer function of the regulator, s is the Laplace operator, K CP is the proportional coefficient of the PI regulator; K CI is the integral coefficient; τ c is the time constant. Thus, the overall control structure is as shown in Figure 4 . Figure 4 Among them, ΔU * is the given value of the upper and lower capacitor voltage difference, ΔU is the upper and lower capacitor voltage difference, i * is the given value of the current injected into the neutral point of the DC side, and i is the current injected into the neutral point of the DC side. Determine K CP and K according to the control frameworkCI 。

[0128] Then the open-loop transfer function of the midpoint potential is

[0129]

[0130] The closed-loop transfer function of the midpoint potential is:

[0131]

[0132] Step 6: Limit the amplitude of the finally added zero-sequence voltage component.

[0133] As Figure 5 shown, v 0 is the ideal zero-sequence component, v' 0 is the output result of the potential regulator. The two are combined and added to the modulation wave v x , generating the improved modulation wave v' x . The finally added zero-sequence voltage component is the sum of the zero-sequence component generated by the potential regulator and the ideal zero-sequence component.

[0134] Set the constraint conditions to ensure that the improved modulation wave v x is always within the carrier range.

[0135]

[0136] Among them, v max is the maximum value among the amplitudes of the three-phase modulation waves, and v min is the minimum value among the amplitudes of the three-phase modulation waves.

[0137] Use the improved modulation wave v x as the final modulation wave to output the switching control signal of the three-level converter, so that the midpoint potential of the DC side remains balanced.

[0138] Step 7: Use an external balancing circuit for midpoint balancing. Adjust the duty cycle according to the voltage difference between the upper and lower capacitors on the DC side to adjust the current injected into the midpoint, so that the midpoint charge is conserved per unit time and the neutral point potential remains balanced. If the three-level converter does not stop running, jump to Step 1. If the three-level converter stops running, end.

[0139] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0140] To avoid the deficiencies of the prior art, the present invention proposes a neutral point potential balancing method based on the combination of the ideal zero-sequence component and the potential regulator. By adding the zero-sequence component to the three-phase modulation wave, the action time of different switching states is changed, thereby regulating the current injected into the neutral point, and thus maintaining the neutral point potential balance. Through this method, the control range and control ability of the control method for the potential can also be analyzed.

[0141] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0142] Figure 2 For the T-type three-level grid-connected converter test system, the DC-side input bus voltage, C 1 、C 2 are the bus capacitors, U dc , through the three-phase three-level switching devices S a1 、S a2 、S a3 、S a4 ,S b1 、S b2 、S b3 、S b4 ,S c1 、S c2 、S c3 、S c4 operate to output a three-level square wave, which passes through the three-phase LCL filter circuit composed of L m1 、R m 、C f 、L m2 to filter out the noise and output three-phase sinusoidal signals, which are connected to the power grid through the three-phase grid-connected switch. u x (x = a, b, c) is the output voltage before three-phase filtering, u fx (x = a, b, c) is the capacitor voltage, u gx (x = a, b, c) is the converter output voltage, i mx (x = a, b, c) is the converter output current, Z gx (x = a, b, c) is the load carried by the three phases; Figure 3 is the control block diagram based on circuit modeling and dq-axis decoupling control.

[0143] Figure 4 is the mathematical model diagram of the potential feedback regulator, where i * is the average current extracted from the neutral point caused by the zero-sequence component v 0 ' within a carrier period, i is the original average current extracted from the neutral point within a carrier period, i 0 is the average current extracted from the neutral point with the addition of the zero-sequence component v 0The average current extracted from the midpoint is used to calculate the ideal zero-sequence component v 0 and the output result v' of the potential regulator 0 . The two are combined and added to the modulation wave v x to generate the improved modulation wave v' x .

[0144] Figure 5 The midpoint potential control block diagram added for the overall zero-sequence component, i x where x = a, b, c.

[0145] The DC side inputs 800V and operates under the three-phase unbalanced conditions of 10 ohms, 15 ohms, and 20 ohms through positive and negative sequence separation to output a three-phase balanced voltage. The small and medium vectors in the positive and negative sequence currents inject current into the midpoint, thus generating a potential offset. Figure 6a and Figure 6b are the simulation effect comparison diagrams for the potential balance of the converter. Before balance, a large amount of zero-sequence current is injected due to the unbalanced condition, resulting in an aggravated potential offset as Figure 6a shown. After adding the zero-sequence component, the potential regulation is as Figure 6b shown. Figure 7 is the simulation diagram of the potential balance process. By using the above method, the midpoint potential imbalance can be quickly and effectively suppressed, Figure 6a compared with Figure 7 it can be seen that the method has good dynamic performance, Figure 6b it can be seen that the voltage distortion rate at steady state is low and the voltage fluctuation range is small. In Figures 6 and Figure 7 the red line is the voltage of the lower capacitor and the black line is the voltage of the upper capacitor.

[0146] Figure 8a , Figure 8b and Figure 9 are respectively the potential balance effect comparison and dynamic and steady-state effects in the hardware-in-the-loop experiment. Figure 8a and 8b in the green line is the voltage of the upper capacitor and the orange line is the voltage of the lower capacitor Figure 9 in the red line is the voltage of the upper capacitor and the purple line is the voltage of the lower capacitor. The conclusion is the same as that of the simulation. Experiments are carried out with a 300V DC input, Figure 10a , Figure 10b and Figure 11 are respectively the potential balance effect comparison and dynamic and steady-state effects in the physical experiment. Figure 10a and Figure 10b in the dark blue line is the voltage of the upper capacitor and the light blue line is the voltage of the lower capacitor. The conclusion is the same as that of the hardware-in-the-loop experiment and the simulation. This proves that the method can achieve the expected midpoint potential control effect.

[0147] Embodiment 2

[0148] This embodiment provides a neutral point potential balancing device for a three-level converter applicable to unbalanced loads, including a processor and a memory, which are connected by a bus; the memory is used to store computer programs, and the computer programs include program instructions. The processor is used to execute the program instructions stored in the computer storage medium to implement the neutral point potential balancing method for the three-level converter applicable to unbalanced loads of the present invention. The specific content of this method has been introduced in detail in Embodiment 1 and will not be elaborated in this embodiment.

[0149] In this specification, specific examples are used to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads, characterized in that: The following steps are involved: Step 1, separating the positive and negative sequences of the sampled voltage and current signals to obtain the positive and negative sequence components of the voltage and current signals, respectively controlling the positive and negative sequence components of the voltage and current signals, and outputting a three-phase balanced voltage; Step 2: calculate the ideal zero-sequence component that needs to be added to the modulation wave to achieve midpoint potential balance under ideal conditions; Step 3: Analyze the regulation capability of adding the ideal zero-sequence component. If the regulation capability is satisfied, proceed to step 4. If not satisfied, jump to step 7; Step 4, correcting the modulation wave sign in the ideal zero-sequence component; Step 5: Based on the corrected modulation wave sign, design a potential regulator of the zero-sequence voltage; Step 6: limiting the zero-sequence voltage component finally added, wherein the zero-sequence voltage component finally added is the sum of the zero-sequence component generated by the potential regulator and the ideal zero-sequence component, superimposing the zero-sequence voltage component finally added after limiting on the modulation wave to obtain an improved modulation wave, and using the improved modulation wave to output a switch control signal of the three-level converter, so that the DC side midpoint potential remains balanced; Step 7: Use an external balancing circuit to perform midpoint balancing. If the three-level converter does not stop running, jump to step 1. The three-level converter stops running and the process ends.

2. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads according to claim 1, characterized in that: In step 2, the calculation formula for the ideal zero-sequence component to be added to the modulation wave is: where i np0 = [-sign(v a )·i a -sign(v b )·i b -sign(v c )·i c ; i npav =(1-v a ·sign(v a ))·i a +(1-v b ·sign(v b ))·i b +(1-v c ·sign(v c ))·i c ; Where, C is the capacitance value of the upper DC capacitor C1 and the lower DC capacitor C2 of the three-level converter, U dc1 is the upper DC capacitor voltage, U dc2 is the lower DC capacitor voltage, i npav is the average midpoint current, T s Represents the unit switching period, f s represents the switching frequency, i np0 and i npav is the intermediate variable, v a , v b , v c is the three-phase modulation wave amplitude of the converter, i a ,i b ,i c represents the three-phase output current of the converter, and sign is the sign verification function.

3. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads according to claim 1, characterized in that: The step 3 comprises the following steps: Step 3.1, calculate the interval of the ideal zero-sequence component V0 in the unper-unit control, the calculation formula is: Among them, δ is the midpoint voltage imbalance, and the maximum, middle and minimum values ​​of the three-phase modulation wave amplitude in the unregulated control are recorded as V max 、V mid 、V min ; Step 3.2: Simplify and obtain the ideal zero-sequence component V without per-unit control o The maximum value V omax and minimum value V omin for: Step 3.3: Use s to represent V mid +V o The sign of is used to characterize the sign change of the modulated wave; According to the value of s and -V mid range, analyze the need to add zero sequence component V in each case o The maximum and minimum values ​​are the upper and lower limits of the controllable zero-sequence voltage range; Step 3.3: According to Estimate the ideal zero-sequence component V0 in the unregulated control, where V dc is the bus voltage on the DC side; if V0 is within the controllable voltage range, execute step 4; if not, jump to step 7.

4. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads according to claim 1, characterized in that: The step 4 comprises the following steps: judging sign(v mid )=sign(v mid +v0) is true: If not, change sign(v mid )=sign(v mid +v0) in the intermediate variable i npav with i np0 The sign in , and update the ideal zero-sequence component; if it is true, do not update the ideal zero-sequence component; where, sign(v mid ) is the middle value of the three-phase modulation wave amplitude.

5. The method for balancing the midpoint potential of a three-level converter suitable for unbalanced load according to claim 1, characterized in that: In step 5, the zero-sequence component v'0 generated by the potential regulator is: Where, C is the capacitance value of the upper DC capacitor C1 and the lower DC capacitor C2 of the three-level converter, U dc1 is the upper DC capacitor voltage, U dc2 is the lower DC capacitor voltage, f s represents the switching frequency, i m The value is the amplitude of the three-phase positive sequence current, is the phase difference between the modulation wave and the output current.

6. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads according to claim 1, characterized in that: In step 5, the transfer function of the potential regulator is: Where: W NPVR is the regulator transfer function, s is the Laplace operator, K CP is the proportional coefficient of the PI regulator; K CI is the integral coefficient; τ c is the time constant.

7. A method for balancing the midpoint potential of a three-level converter suitable for unbalanced loads according to claim 1, characterized in that: In step 6, the zero-sequence voltage component finally added is limited by the following formula: Among them, v0 is the ideal zero-sequence component, v'0 is the output result of the potentiometer regulator, and v max is the maximum value of the three-phase modulation wave amplitude, v min It is the minimum value among the three-phase modulation wave amplitudes.

8. A three-level converter midpoint potential balancing device suitable for unbalanced load, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the three-level converter neutral point potential balancing method applicable to unbalanced loads according to any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for balancing the midpoint potential of a three-level converter applicable to an unbalanced load according to any one of claims 1 to 7 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for balancing the midpoint potential of a three-level converter applicable to an unbalanced load are implemented as described in any one of claims 1 to 7.

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