Timing frequency and phase detection method, circuit and phase detector

Abstract

The present application relates to a timing frequency and phase detection method, circuit and phase detector. The method comprises: when a rising edge of a reference signal is detected, a first control signal is output; the first control signal is used to indicate that a first upper switch enters a closed state; when the voltage across the second upper switch is stable, a second control signal is output based on the first control signal; the second control signal is used to indicate that the second upper switch enters a closed state. The method can reduce the power consumption of a charge pump and improve the energy efficiency of the charge pump.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a timing frequency and phase discrimination method, circuit and phase detector. Background Art

[0002] The phase frequency detector plays a very important role in the phase-locked loop. The phase frequency detector compares the feedback signal output by the divider with the reference signal of the external input circuit in frequency and phase, and generates UP and DOWN signals. The charge pump in the phase-locked loop is controlled by the UP and DOWN signals to charge or discharge. The charge pump is constrained by non-ideal factors such as charge sharing, resulting in current mismatch. The existing charge pump eliminates the current mismatch caused by charge sharing by adopting a current steering structure. At the same time, the phase frequency detector is required to generate a UPB signal that is opposite to the UP signal, and a DOWNB signal that is opposite to the DOWN signal.

[0003] The inventors have found through research that the existing frequency and phase detectors can cause the charge pump to have problems of high power consumption and low energy efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a timing frequency and phase detection method, circuit and phase detector that can reduce the power consumption of the charge pump and improve energy efficiency in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a timing frequency and phase discrimination method, which is applied to a phase-locked loop, wherein the phase-locked loop includes a charge pump, and the charge pump includes a first upper switch and a second upper switch; wherein the closed state of the first upper switch is used to maintain a stable voltage across the second upper switch; the method includes:

[0006] When a rising edge of the reference signal is detected, a first control signal is output; the first control signal is used to instruct the first upper switch to enter a closed state;

[0007] When the voltage across the second upper switch is stable, a second control signal is output based on the first control signal; the second control signal is used to instruct the second upper switch to enter a closed state.

[0008] In one embodiment, the charge pump further comprises a first lower switch and a second lower switch; wherein the closed state of the first lower switch is used to maintain a stable voltage across the second lower switch; and the method further comprises:

[0009] When a rising edge of the feedback signal is detected, a third control signal is output; the third control signal is used to instruct the first lower switch to enter a closed state;

[0010] When the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch to enter a closed state.

[0011] In one embodiment, the method is applied to a timing frequency discrimination circuit in a phase-locked loop; the circuit comprises a frequency discrimination unit and a timing conversion unit connected to each other; the frequency discrimination unit comprises a first trigger;

[0012] When a rising edge of the feedback signal is detected, the step of outputting a third control signal comprises:

[0013] The frequency and phase discrimination unit obtains the rising edge data of the feedback signal, and outputs a first level signal based on the rising edge data of the feedback signal; the first level signal is output by a first trigger triggered by the rising edge data of the feedback signal;

[0014] The timing conversion unit outputs a third control signal according to the rising edge data of the first level signal.

[0015] In one embodiment, the step of outputting a fourth control signal based on the third control signal includes:

[0016] The timing conversion unit performs delay processing on the first level signal according to the falling edge data of the third control signal to obtain a fourth control signal; wherein the falling edge of the third control signal is aligned with the rising edge of the fourth control signal.

[0017] In one embodiment, the method is applied to a timing frequency discrimination circuit in a phase-locked loop; the circuit comprises a frequency discrimination unit and a timing conversion unit connected to each other; the frequency discrimination unit comprises a second trigger;

[0018] When a rising edge of the reference signal is detected, the step of outputting a first control signal comprises:

[0019] The frequency and phase detection unit obtains the rising edge data of the reference signal, and outputs a second level signal based on the rising edge data of the reference signal; the second level signal is output by a second trigger triggered by the rising edge data of the reference signal;

[0020] The timing conversion unit outputs a first control signal according to rising edge data of the second level signal.

[0021] In one embodiment, the step of outputting the second control signal based on the first control signal includes:

[0022] The timing conversion unit performs delay processing on the second level signal according to the falling edge data of the first control signal to obtain a second control signal; wherein the falling edge of the first control signal is aligned with the rising edge of the second control signal.

[0023] In one embodiment, the phase-locked loop further includes a low-pass filter; and the method further includes:

[0024] If the frequency of the reference signal is equal to the frequency of the feedback signal, a phase comparison is performed on the reference signal and the feedback signal;

[0025] When the phase comparison result shows that the phase of the reference signal leads the phase of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter;

[0026] When the phase comparison result shows that the phase of the feedback signal is ahead of the phase of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter;

[0027] When the result of the phase comparison is that there is no phase difference between the reference signal and the feedback signal, the first control signal and the third control signal are both used to instruct the charge pump not to charge or discharge the low-pass filter.

[0028] In a second aspect, the present application further provides a timing frequency and phase discrimination circuit, which is applied to a phase-locked loop, wherein the phase-locked loop includes a charge pump, and the charge pump includes a first upper switch and a second upper switch; wherein the closed state of the first upper switch is used to maintain a stable voltage across the second upper switch; the circuit includes: a frequency and phase discrimination unit and a timing conversion unit;

[0029] The frequency and phase discrimination unit is used to connect to an external input circuit and obtain a reference signal of the external input circuit;

[0030] The timing conversion unit is connected to the frequency and phase detection unit, and is used to connect to the charge pump. When the rising edge of the reference signal is detected, the first control signal is output; the first control signal is used to indicate that the first upper switch enters a closed state; when the voltage across the second upper switch is stable, the second control signal is output based on the first control signal; the second control signal is used to indicate that the second upper switch enters a closed state.

[0031] In one embodiment, the charge pump further includes a first lower switch and a second lower switch; wherein the closed state of the first lower switch is used to maintain a stable voltage across the second lower switch; and the circuit further includes:

[0032] The frequency and phase detection unit is also used to connect to the frequency divider of the phase-locked loop to obtain the feedback signal of the frequency divider;

[0033] The timing conversion unit is also used to output a third control signal when a rising edge of the feedback signal is detected; the third control signal is used to instruct the first lower switch to enter a closed state; when the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch to enter a closed state.

[0034] In a third aspect, the present application also provides a phase detector, comprising the above-mentioned timing frequency detection and phase detection circuit.

[0035] The above-mentioned timing frequency and phase detection method, circuit and phase detector output a first control signal to instruct the first upper switch to enter a closed state when a rising edge of a reference signal is detected, so that the voltage across the second upper switch is stable. When the voltage across the second upper switch is stable, a second control signal can be output to close the second upper switch. In this way, when a rising edge of a reference signal is detected, the first control signal is output, so that the charge pump is prevented from remaining closed when the reference signal does not have a rising edge, causing the charge pump to always have current, thereby reducing the power consumption of the charge pump and improving the energy efficiency of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of the structure of a current steering charge pump in an embodiment;

[0037] Figure 2 A schematic diagram of a first flow chart of a timing frequency and phase discrimination method in an embodiment;

[0038] Figure 3 is a flow chart of a step of outputting a first control signal when a rising edge of a reference signal is detected in one embodiment;

[0039] Figure 4 It is a schematic diagram of a second flow chart of a timing frequency and phase discrimination method in a specific embodiment;

[0040] Figure 5 It is a timing diagram of the output signal of the frequency and phase detection unit in one embodiment when the phase of the reference signal leads the phase of the feedback signal;

[0041] Figure 6 It is a timing diagram of the output signal of the frequency and phase detection unit in one embodiment when the phase of the feedback signal leads the phase of the reference signal;

[0042] Figure 7 It is a timing diagram of the output signal of the frequency and phase detection unit in one embodiment when the phase of the reference signal is equal to the phase of the feedback signal;

[0043] Figure 8 A schematic diagram of the structure of a timing frequency and phase discrimination circuit in one embodiment;

[0044] Fig. 9 A structural block diagram of a timing frequency and phase discrimination device in an embodiment;

[0045] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] The existing phase frequency detector will cause the charge pump to have high power consumption and low energy efficiency. Specifically, taking the current rudder charge pump as an example, the output signals of the existing phase frequency detector are UP, UPB, DOWN and DOWNB, and the current rudder charge pump has an additional current path. The timing of the existing phase frequency detector makes the current rudder charge pump always have current when working, resulting in high power consumption and low energy efficiency of the charge pump. For example, Figure 1 As shown, the current rudder charge pump includes switches S1, S2, S3 and S4. The existing frequency and phase detector outputs an UP signal to indicate that switch S1 enters a closed state, a UPB signal to indicate that switch S3 enters a closed state, a DOWN signal to indicate that switch S2 enters a closed state, and a DOWNB signal to indicate that switch S4 enters a closed state. Since the UP signal and the UPB signal are mutually inverse signals, and the DOWN signal and the DOWNB signal are mutually inverse signals, that is, the current rudder charge pump always has two switches in a closed state at the same time, so that the current rudder charge pump always has current when working, resulting in the problem of high power consumption and low energy efficiency of the charge pump.

[0048] Based on the above reasons, the present application provides a timing frequency and phase detection method, circuit and phase detector that can reduce the power consumption of a charge pump and improve energy efficiency.

[0049] In one embodiment, Figure 2 As shown, a timing frequency and phase discrimination method is provided, which is applied to a phase-locked loop, wherein the phase-locked loop includes a charge pump. Figure 1 Taking the charge pump in the example as an example, the charge pump includes a first upper switch S3 and a second upper switch S1; wherein the closed state of the first upper switch S3 is used to keep the voltage across the second upper switch S1 stable; the method includes:

[0050] Step S202: when a rising edge of the reference signal is detected, output a first control signal; the first control signal is used to instruct the first upper switch S3 to enter a closed state.

[0051] The rising edge is the moment when the low level (digital "0") changes to the high level (digital "1"). The reference signal is the input signal of the external input circuit, which is generally a fixed signal and can be set according to actual needs, and is not specifically limited here.

[0052] Specifically, when a rising edge of the reference signal is detected, a first control signal is output to instruct the first upper switch S3 to enter a closed state. After the first upper switch S3 remains in the closed state for a certain period of time, the voltage across the second upper switch S1 can be stabilized. As an example, the closed state of the first upper switch S3 is mainly used to keep the voltage at the upper end of the second upper switch S1 stable, that is, to keep the voltage of the X node stable.

[0053] Step S204: when the voltage across the second upper switch S1 is stable, output a second control signal based on the first control signal; the second control signal is used to instruct the second upper switch S1 to enter a closed state.

[0054] Specifically, after the first upper switch S3 remains in the closed state for a certain period of time, the voltage across the second upper switch S1 is stabilized, thereby avoiding the problem of current mismatch caused by non-ideal factors such as charge sharing in the charge pump when the second upper switch S1 is closed. Therefore, when the voltage across the second upper switch S1 is stable, the second control signal can be output according to the first control signal to instruct the second upper switch S1 to enter the closed state.

[0055] In some specific embodiments, when a rising edge of a reference signal is detected, a first control signal is output to instruct the first upper switch to enter a closed state so that the voltage across the second upper switch is stable. When the voltage across the second upper switch is stable, a second control signal can be output to close the second upper switch. In this way, when a rising edge of a reference signal is detected, the first control signal is output to prevent the first upper switch of the charge pump from remaining closed when the reference signal does not have a rising edge, thereby preventing the charge pump from always having current, thereby reducing the power consumption of the charge pump and improving the energy efficiency of the charge pump.

[0056] In one embodiment, Figure 1 As shown, the charge pump further includes a first lower switch S4 and a second lower switch S2; wherein the closed state of the first lower switch S4 is used to keep the voltage across the second lower switch S2 stable; the method further includes:

[0057] When a rising edge of the feedback signal is detected, a third control signal is output; the third control signal is used to instruct the first lower switch S4 to enter a closed state;

[0058] When the voltage across the second lower switch S2 is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch S2 to enter a closed state.

[0059] The feedback signal may be a signal output by a frequency divider of a phase-locked loop.

[0060] Specifically, when a rising edge of the feedback signal is detected, a third control signal is output to instruct the first lower switch S4 to enter a closed state. When the first lower switch S4 remains in a closed state for a certain period of time, the voltage across the second lower switch S2 can be stabilized, thereby avoiding the problem of current mismatch caused by non-ideal factors such as charge sharing in the charge pump when the second lower switch S2 is closed. Therefore, when the voltage across the second lower switch S2 is stable, a fourth control signal can be output according to the third control signal to instruct the second lower switch S2 to enter a closed state. As an example, the closed state of the first lower switch S4 is mainly used to keep the voltage at the lower end of the second lower switch S2 stable, that is, to keep the voltage of the Y node stable.

[0061] In some specific embodiments, when a rising edge of the feedback signal is detected, a third control signal is output to instruct the first lower switch to enter a closed state so that the voltage across the second lower switch is stable. When the voltage across the second lower switch is stable, a fourth control signal can be output to close the second lower switch. In this way, when a rising edge of the feedback signal is detected, the third control signal is output, which can prevent the first lower switch of the charge pump from remaining closed when the reference signal does not have a rising edge, causing the charge pump to always have current, thereby further reducing the power consumption of the charge pump and improving the energy efficiency of the charge pump.

[0062] In one embodiment, the method is applied to a timing frequency discrimination circuit in a phase-locked loop; the circuit comprises a frequency discrimination unit and a timing conversion unit connected to each other; the frequency discrimination unit comprises a first trigger;

[0063] When a rising edge of the feedback signal is detected, the step of outputting a third control signal comprises:

[0064] The frequency and phase discrimination unit obtains the rising edge data of the feedback signal, and outputs a first level signal based on the rising edge data of the feedback signal; the first level signal is output by a first trigger triggered by the rising edge data of the feedback signal;

[0065] The timing conversion unit outputs a third control signal according to the rising edge data of the first level signal.

[0066] The first level signal may be an UP signal; and the rising edge data is data that can be obtained by the frequency and phase detection unit when a rising edge occurs.

[0067] Specifically, if the feedback signal has a rising edge, the frequency detection and phase detection unit can obtain the rising edge data of the feedback signal; the first trigger in the frequency detection and phase detection unit is triggered by the rising edge data of the feedback signal, and outputs the first level signal based on the result of the triggering of the rising edge data of the feedback signal. The timing conversion unit inputs the first level signal, and outputs the third control signal according to the rising edge data of the first level signal.

[0068] In one embodiment, the rising edge of the first level signal is aligned with the rising edge of the third control signal, that is, if the timing conversion unit detects that the first level signal has a rising edge, it outputs the third control signal.

[0069] In one embodiment, the step of outputting a fourth control signal based on the third control signal includes:

[0070] The timing conversion unit performs delay processing on the first level signal according to the falling edge data of the third control signal to obtain a fourth control signal; wherein the falling edge of the third control signal is aligned with the rising edge of the fourth control signal.

[0071] The fourth control signal may be a signal obtained by delaying the first level signal, or may be a signal obtained by delaying the UP signal.

[0072] Specifically, the timing conversion unit delays the rising edge of the first level signal to the falling edge of the third control signal according to the falling edge data of the third control signal to obtain the fourth control signal, so that the rising edge of the fourth control signal is aligned with the falling edge of the third control signal.

[0073] In one embodiment, the method is applied to a timing frequency discrimination circuit in a phase-locked loop; the circuit includes a frequency discrimination unit and a timing conversion unit connected to each other; the frequency discrimination unit includes a second trigger;

[0074] like Figure 3 As shown, when a rising edge of a reference signal is detected, the step of outputting a first control signal comprises:

[0075] Step S302, the frequency and phase detection unit obtains the rising edge data of the reference signal, and outputs a second level signal based on the rising edge data of the reference signal; the second level signal is output by a second trigger triggered by the rising edge data of the reference signal;

[0076] Step S304: the timing conversion unit outputs a first control signal according to the rising edge data of the second level signal.

[0077] The second level signal may be a DOWN signal.

[0078] Specifically, if the reference signal has a rising edge, the frequency and phase discrimination unit can obtain the rising edge data of the reference signal; the second trigger in the frequency and phase discrimination unit is triggered by the rising edge data of the reference signal, and outputs the second level signal based on the result of the triggering of the rising edge data of the reference signal. The timing conversion unit inputs the second level signal, and outputs the first control signal according to the rising edge data of the second level signal.

[0079] In one embodiment, the rising edge of the second level signal is aligned with the rising edge of the first control signal, that is, if the timing conversion unit detects that the second level signal has a rising edge, it outputs the first control signal.

[0080] In one embodiment, the step of outputting the second control signal based on the first control signal includes:

[0081] The timing conversion unit performs delay processing on the second level signal according to the falling edge data of the first control signal to obtain a second control signal; wherein the falling edge of the first control signal is aligned with the rising edge of the second control signal.

[0082] The second control signal may be a signal obtained by delaying the second level signal, or may be a signal obtained by delaying the DOWN signal.

[0083] Specifically, the timing conversion unit delays the rising edge of the second level signal to the falling edge of the third control signal according to the falling edge data of the first control signal to obtain the second control signal, so that the rising edge of the second control signal is aligned with the falling edge of the first control signal.

[0084] In one embodiment, the phase-locked loop further includes a low-pass filter; and the method further includes:

[0085] If the frequency of the reference signal is equal to the frequency of the feedback signal, a phase comparison is performed on the reference signal and the feedback signal;

[0086] When the phase comparison result shows that the phase of the reference signal leads the phase of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter;

[0087] When the phase comparison result shows that the phase of the feedback signal is ahead of the phase of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter;

[0088] When the result of the phase comparison is that there is no phase difference between the reference signal and the feedback signal, the first control signal and the third control signal are both used to instruct the charge pump not to charge or discharge the low-pass filter.

[0089] Specifically, according to the principle of the phase-locked loop, the phase-locked loop can realize automatic tracking of the frequency of the reference signal and the frequency of the feedback signal, as well as phase synchronization of the reference signal and the phase of the feedback signal. It can be understood that phase synchronization means that there is no phase difference between the reference signal and the feedback signal. If the frequency of the reference signal is equal to the frequency of the feedback signal, the reference signal and the feedback signal can be compared in phase to perform phase synchronization.

[0090] When the phase comparison result shows that the phase of the reference signal is ahead of the phase of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter; when the phase comparison result shows that the phase of the feedback signal is ahead of the phase of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter. The charge pump charges and discharges the low-pass filter to change the tuning voltage of the voltage-controlled oscillator (VCO) in the phase-locked loop accordingly, thereby changing the resonant frequency of the VCO. The output signal of the VCO passes through the frequency divider and inputs a new feedback signal to the frequency detection and phase detection unit. In the closed-loop feedback system thus constructed, the frequency detection and phase detection circuit continuously dynamically adjusts the control signal to achieve phase synchronization.

[0091] When the phase comparison result shows that there is no phase difference between the reference signal and the feedback signal, the first control signal and the third control signal can be used to reset the frequency and phase detection unit and instruct the charge pump not to charge or discharge the low-pass filter.

[0092] In one of the embodiments, if the frequency of the reference signal is not equal to the frequency of the feedback signal, a frequency comparison is performed on the reference signal and the feedback signal;

[0093] When the result of the frequency comparison is that the frequency of the reference signal is greater than the frequency of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter.

[0094] When the result of the frequency comparison is that the frequency of the feedback signal is greater than the frequency of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter.

[0095] In one embodiment, the charge pump comprises a current steering type charge pump; the first control signal, the second control signal, the third control signal and the fourth control signal are all at a high level.

[0096] In a specific embodiment, Figure 4 As shown, the timing frequency and phase discrimination method includes the following steps:

[0097] Step S401, when a rising edge of a reference signal is detected, a frequency and phase detection unit obtains rising edge data of the reference signal, and outputs a second level signal based on the rising edge data of the reference signal; the second level signal is output by a second trigger triggered by the rising edge data of the reference signal.

[0098] Step S402: The timing conversion unit outputs a first control signal according to the rising edge data of the second level signal, where the first control signal is used to instruct the first upper switch to enter a closed state.

[0099] Step S403, when the voltage across the second upper switch is stable, the timing conversion unit delays the second level signal according to the falling edge data of the first control signal to obtain a second control signal; wherein the second control signal is used to indicate that the second upper switch enters a closed state; and the falling edge of the first control signal is aligned with the rising edge of the second control signal.

[0100] Step S404, when a rising edge of the feedback signal is detected, the frequency and phase detection unit obtains the rising edge data of the feedback signal, and outputs a first level signal based on the rising edge data of the feedback signal; the first level signal is output by a first trigger triggered by the rising edge data of the feedback signal.

[0101] Step S405 : The timing conversion unit outputs a third control signal according to the rising edge data of the first level signal, where the third control signal is used to instruct the first lower switch to enter a closed state.

[0102] Step S406, when the voltage across the second lower switch is stable, the timing conversion unit delays the first level signal according to the falling edge data of the third control signal to obtain a fourth control signal; wherein the fourth control signal is used to indicate that the second lower switch enters a closed state; and the falling edge of the third control signal is aligned with the rising edge of the fourth control signal.

[0103] In a specific embodiment, Figure 5 , 6 As shown in , 7, when a rising edge of the reference signal is detected, a first control signal is output to instruct the first upper switch to enter a closed state, wherein the level width of the first control signal can be set according to actual conditions, as long as the voltage across the second upper switch can be kept stable; when the voltage across the second upper switch is stable, based on the first control signal, a second control signal is output to instruct the second upper switch to enter a closed state, wherein the falling edge of the first control signal is aligned with the rising edge of the second control signal, that is, at the moment when the second upper switch enters the closed state, the first upper switch enters the open state.

[0104] When a rising edge of the feedback signal is detected, a third control signal is output to instruct the first lower switch to enter a closed state, wherein the level width of the third control signal can be set according to actual conditions, as long as the voltage across the second lower switch can be kept stable; when the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal to instruct the second lower switch to enter a closed state, wherein the falling edge of the third control signal is aligned with the rising edge of the fourth control signal, that is, at the moment when the second lower switch enters the closed state, the first upper switch enters an open state.

[0105] In one embodiment, if Figure 5 , 6 As shown in , 7, due to the delay of the trigger in the frequency detection and phase detection unit, the delay of the gate circuit itself in the frequency detection and phase detection unit and the delay of the timing conversion unit, the rising edge of the reference signal is not aligned with the rising edge of the first control signal, and the rising edge of the feedback signal is not aligned with the rising edge of the third control signal.

[0106] In one embodiment, if Figure 5 As shown, if the phase of the reference signal leads the phase of the feedback signal, the second control signal is output first, and then the fourth control signal is output. When the second control signal indicates that the first upper switch enters a closed state, the charge pump charges the low-pass filter of the phase-locked loop; when the fourth control signal indicates that the second lower switch enters a closed state, the frequency and phase detection unit enters a reset state.

[0107] In one embodiment, if Figure 6 As shown, if the phase of the feedback signal leads the phase of the reference signal, the fourth control signal is output first, and then the second control signal is output. When the fourth control signal indicates that the first lower switch enters a closed state, the charge pump discharges the low-pass filter of the phase-locked loop; when the second control signal indicates that the second upper switch enters a closed state, the frequency and phase detection unit enters a reset state.

[0108] In one embodiment, if Figure 7 As shown, if the phase of the phase feedback signal of the reference signal is the same, the second control signal and the fourth control signal are output simultaneously. When the second control signal indicates that the second upper switch enters a closed state and the fourth control signal indicates that the second lower switch enters a closed state, the frequency and phase detection unit enters a reset state.

[0109] In one embodiment, in the case of the reference signal and the feedback signal, there is a capacitor at the switch node of the charge pump, and the second control signal and the fourth control signal have a certain rise and fall time. When the pulses of the second control signal and the fourth control signal have not been established, the frequency detection and phase detection unit is reset, so that the second upper switch and the second lower switch of the charge pump cannot be closed. Therefore, a delay unit is added to the reset loop of the frequency detection and phase detection unit, so that when the second control signal instructs the charge pump to charge the low-pass filter, the fourth control signal is output. In this case, if the level width of the fourth control signal is d, the level width of the second control signal is the phase difference between the reference signal and the feedback signal plus d; when the fourth control signal instructs the charge pump to discharge the low-pass filter, the second control signal is output. In this case, if the level width of the second control signal is d, the level width of the fourth control signal is the phase difference between the reference signal and the feedback signal plus d.

[0110] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0111] In one embodiment, Figure 8 As shown, a timing frequency and phase discrimination circuit is provided, which is applied to a phase-locked loop. The phase-locked loop includes a charge pump. Figure 1 Taking the charge pump in the example as an example, the charge pump includes a first upper switch S2 and a second upper switch S1; wherein the closed state of the first upper switch S2 is used to keep the voltage across the second upper switch S1 stable; the circuit includes: a frequency and phase detection unit 810 and a timing conversion unit 820;

[0112] The frequency and phase detection unit 810 is used to connect to an external input circuit and obtain a reference signal of the external input circuit;

[0113] The timing conversion unit 820 is connected to the frequency detection and phase detection unit, and is used to connect to the charge pump. When the rising edge of the reference signal is detected, a first control signal is output; the first control signal is used to indicate that the first upper switch enters a closed state; when the voltage across the second upper switch is stable, a second control signal is output based on the first control signal; the second control signal is used to indicate that the second upper switch enters a closed state.

[0114] The external circuit may be a circuit for inputting a reference signal, or may be a reference clock, and the frequency and phase of the reference clock may be set according to actual needs.

[0115] In one embodiment, the charge pump further includes a first lower switch and a second lower switch; wherein the closed state of the first lower switch is used to maintain a stable voltage across the second lower switch; and the circuit further includes:

[0116] The frequency and phase detection unit is also used to connect to the frequency divider of the phase-locked loop to obtain the feedback signal of the frequency divider;

[0117] The timing conversion unit is also used to output a third control signal when a rising edge of the feedback signal is detected; the third control signal is used to instruct the first lower switch to enter a closed state; when the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch to enter a closed state.

[0118] In one embodiment, a phase detector is provided, comprising the above-mentioned timing frequency and phase detection circuit.

[0119] In one embodiment, a phase-locked loop is provided, comprising the above-mentioned phase detector, charge pump, low-pass filter, voltage-controlled oscillator and frequency divider.

[0120] Based on the same inventive concept, the embodiment of the present application also provides a timing frequency discrimination and phase discrimination device for implementing the timing frequency discrimination and phase discrimination method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more timing frequency discrimination and phase discrimination device embodiments provided below can refer to the limitations of the timing frequency discrimination and phase discrimination method above, and will not be repeated here.

[0121] In one embodiment, Fig. 9 As shown, a timing frequency and phase detection device is provided, which is applied to a phase-locked loop, the phase-locked loop includes a charge pump, the charge pump includes a first upper switch and a second upper switch; wherein the closed state of the first upper switch is used to keep the voltage across the second upper switch stable; the device includes: a first control signal output module and a second control signal output module, wherein:

[0122] The first control signal output module 910 is used to output a first control signal when a rising edge of the reference signal is detected; the first control signal is used to instruct the first upper switch to enter a closed state.

[0123] The second control signal output module 920 is used to output a second control signal based on the first control signal when the voltage across the second upper switch is stable; the second control signal is used to instruct the second upper switch to enter a closed state.

[0124] In one embodiment, the charge pump further comprises a first lower switch and a second lower switch; wherein the closed state of the first lower switch is used to maintain a stable voltage across the second lower switch; and the device further comprises:

[0125] The third control signal output module is used to output a third control signal when a rising edge of the feedback signal is detected; the third control signal is used to instruct the first lower switch to enter a closed state.

[0126] The fourth control signal output module is used to output a fourth control signal based on the third control signal when the voltage across the second lower switch is stable; the fourth control signal is used to instruct the second lower switch to enter a closed state.

[0127] In one embodiment, the third control signal output module includes a first level output unit and a third control signal output unit.

[0128] The first level output unit is used to obtain the rising edge data of the feedback signal, and output the first level signal based on the rising edge data of the feedback signal; the first level signal is output by the first trigger triggered by the rising edge data of the feedback signal;

[0129] The third control signal output unit is used to output a third control signal according to the rising edge data of the first level signal.

[0130] In one embodiment, the fourth control signal output module includes a first level delay unit; the first level delay unit is used to delay the first level signal according to the falling edge data of the third control signal to obtain a fourth control signal; wherein the falling edge of the third control signal is aligned with the rising edge of the fourth control signal.

[0131] In one embodiment, the first control signal output module includes a second level output unit and a first control signal output unit.

[0132] The second level output unit is used to obtain the rising edge data of the reference signal, and output the second level signal based on the rising edge data of the reference signal; the second level signal is output by the second trigger triggered by the rising edge data of the reference signal.

[0133] The first control signal output unit is used for outputting the first control signal according to the rising edge data of the second level signal.

[0134] In one embodiment, the second control signal output module includes a second level delay unit; the second level delay unit is used to delay the second level signal according to the falling edge data of the first control signal to obtain a second control signal; wherein the falling edge of the first control signal is aligned with the rising edge of the second control signal.

[0135] In one embodiment, the apparatus further comprises a phase comparison module.

[0136] The phase comparison module is used to compare the phases of the reference signal and the feedback signal if the frequency of the reference signal is equal to the frequency of the feedback signal;

[0137] When the phase comparison result shows that the phase of the reference signal leads the phase of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter;

[0138] When the phase comparison result shows that the phase of the feedback signal is ahead of the phase of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter;

[0139] When the result of the phase comparison is that there is no phase difference between the reference signal and the feedback signal, the first control signal and the third control signal are both used to instruct the charge pump not to charge or discharge the low-pass filter.

[0140] In one embodiment, the first control signal, the second control signal, the third control signal and the fourth control signal are all at a high level.

[0141] Each module in the above-mentioned timing frequency discrimination and phase discrimination device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0142] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.10As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a timing frequency discrimination and phase discrimination method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse, etc.

[0143] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0144] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0145] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0146] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0147] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0148] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A timing frequency and phase discrimination method, characterized in that: The method is applied to a phase-locked loop, the phase-locked loop includes a charge pump, the charge pump includes a first upper switch, a second upper switch, a first lower switch, and a second lower switch; wherein the closed state of the first upper switch is used to keep the voltage across the second upper switch stable; the closed state of the first lower switch is used to keep the voltage across the second lower switch stable; the method includes: When a rising edge of the reference signal is detected, a first control signal is output; the first control signal is used to instruct the first upper switch to enter a closed state; When the voltage across the second upper switch is stable, outputting a second control signal based on the first control signal; the second control signal is used to instruct the second upper switch to enter a closed state; When a rising edge of the feedback signal is detected, a third control signal is output; the third control signal is used to instruct the first lower switch to enter a closed state; When the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch to enter a closed state.

2. The method according to claim 1, characterized in that The method is applied to a timing frequency discrimination and phase discrimination circuit in the phase-locked loop; the circuit comprises a frequency discrimination and phase discrimination unit and a timing conversion unit connected to each other; The frequency and phase discrimination unit comprises a first trigger; When a rising edge of the feedback signal is detected, the step of outputting a third control signal comprises: The frequency and phase discrimination unit obtains the rising edge data of the feedback signal, and outputs a first level signal based on the rising edge data of the feedback signal; the first level signal is output by the first trigger triggered by the rising edge data of the feedback signal; The timing conversion unit outputs the third control signal according to the rising edge data of the first level signal.

3. The method according to claim 2, characterized in that The step of outputting a fourth control signal based on the third control signal comprises: The timing conversion unit performs delay processing on the first level signal according to the falling edge data of the third control signal to obtain the fourth control signal; wherein the falling edge of the third control signal is aligned with the rising edge of the fourth control signal.

4. The method according to any one of claims 1 to 3, characterized in that: The method is applied to a timing frequency discrimination and phase discrimination circuit in the phase-locked loop; the circuit comprises a frequency discrimination and phase discrimination unit and a timing conversion unit connected to each other; The frequency and phase discrimination unit includes a second trigger; When a rising edge of the reference signal is detected, the step of outputting a first control signal comprises: The frequency and phase discrimination unit obtains the rising edge data of the reference signal, and outputs a second level signal based on the rising edge data of the reference signal; the second level signal is output by the second trigger triggered by the rising edge data of the reference signal; The timing conversion unit outputs the first control signal according to the rising edge data of the second level signal.

5. The method according to claim 4, characterized in that The step of outputting a second control signal based on the first control signal comprises: The timing conversion unit delays the second level signal according to the falling edge data of the first control signal to obtain the second control signal; wherein the falling edge of the first control signal is aligned with the rising edge of the second control signal.

6. The method according to any one of claims 1 to 3, characterized in that: The phase-locked loop also includes a low-pass filter; the method also includes: If the frequency of the reference signal is equal to the frequency of the feedback signal, performing a phase comparison on the reference signal and the feedback signal; When the result of the phase comparison is that the phase of the reference signal leads the phase of the feedback signal, the first control signal is used to instruct the charge pump to charge the low-pass filter; When the result of the phase comparison is that the phase of the feedback signal leads the phase of the feedback signal, the third control signal is used to instruct the charge pump to discharge the low-pass filter; When the result of the phase comparison is that there is no phase difference between the reference signal and the feedback signal, the first control signal and the third control signal are both used to instruct the charge pump not to charge or discharge the low-pass filter.

7. A timing frequency and phase detection circuit, characterized in that: Applied to a phase-locked loop, the phase-locked loop includes a charge pump, the charge pump includes a first upper switch, a second upper switch, a first lower switch and a second lower switch; wherein the closed state of the first upper switch is used to keep the voltage across the second upper switch stable; the closed state of the first lower switch is used to keep the voltage across the second lower switch stable; the circuit includes: a frequency and phase detection unit and a timing conversion unit; The frequency and phase discrimination unit is used to connect to an external input circuit to obtain a reference signal of the external input circuit; The timing conversion unit is connected to the frequency and phase detection unit, and is used to connect to the charge pump, and outputs a first control signal when a rising edge of a reference signal is detected; the first control signal is used to instruct the first upper switch to enter a closed state; when the voltage across the second upper switch is stable, a second control signal is output based on the first control signal; the second control signal is used to instruct the second upper switch to enter a closed state; The frequency and phase discrimination unit is also used to connect to the frequency divider of the phase-locked loop to obtain a feedback signal of the frequency divider; The timing conversion unit is also used to output a third control signal when a rising edge of the feedback signal is detected; the third control signal is used to instruct the first lower switch to enter a closed state; when the voltage across the second lower switch is stable, a fourth control signal is output based on the third control signal; the fourth control signal is used to instruct the second lower switch to enter a closed state.

8. A phase detector, characterized in that: Comprising the circuit of claim 7.

Images