A fuzzy control clock servo algorithm based on IEEE 1588 protocol

Abstract

The present invention relates to the technical field of clock servo algorithms and discloses a fuzzy control clock servo algorithm based on the IEEE 1588 protocol. The algorithm uses fuzzy control technology to effectively resolve boundary errors within a short period in the initial stage of a PI servo and minimize noise introduction. When the system is stable, the algorithm also has a good frequency response to suppress noise, thereby further improving the accuracy of a traditional PI servo algorithm based on PTP Ethernet hardware timestamps and providing sufficient stability in microsystems or synchronous motion systems used in robots and precision machinery.

Description

Technical Field

[0001] The present invention relates to the technical field of clock servo algorithms, and in particular to a fuzzy control clock servo algorithm based on the IEEE 1588 protocol. Background Art

[0002] As distributed systems replace centralized systems, real-time processing becomes a challenge for existing network systems. For all devices in a distributed network to work together, they must maintain a common or global time. Typically, time in embedded systems is determined using crystal oscillators and counters. External devices and network modules also use phase-locked loops and crystal frequency technology to establish this time. However, crystals are heterogeneous and their frequencies are unstable due to temperature, humidity, and age. As a result, all devices in the system maintain different times. Accurate time maintenance is difficult in systems such as robotics, integrated circuit assembly systems, and computer numerical control systems. Furthermore, since distributed systems share information over a network, noise from magnetic fields or the operating environment can cause packet loss. Therefore, a common time concept is essential for secure data exchange between nodes. Ethernet, with its high speed, large bandwidth, and short cycle times, is used at all levels of many industrial architectures. Ethernet ensures smooth data transmission from higher layers to lower layers with minimal packet loss, and vice versa. However, periodic and schedule information must be guaranteed. In other words, the time in a network system must be the same across every connected device. Therefore, time synchronization is crucial in real-time systems.

[0003] In time synchronization, two issues need to be considered: time offset and time deviation. Time offset (or rate offset) is the relative difference in the time value of two devices at a specific moment. Time deviation (or rate deviation) is the clock drift between time systems with the same normal frequency and can be called the "first-order derivative" of time offset. Phase synchronization compensates for time offset, and frequency synchronization enables clocks to run at the same rate. Therefore, time synchronization needs to include phase synchronization and frequency synchronization. The IEEE 1588 standard is an attractive new method that can synchronize multiple nodes in one or two steps. The Precision Time Protocol (PTP) is a brief description of IEEE 1588 for precise synchronization. It can be implemented using software alone or a combination of auxiliary hardware and software. When using hardware with timestamps, PTP is accurate to the nanosecond level.

[0004] The IEEE 1588 standard has been researched and implemented using both software and hardware. Because PTP uses timestamps to calibrate the time between slave and master nodes, the accuracy of the synchronization method depends on the timestamp location. Using a software approach, the trigger timing is close to the operating system, resulting in relatively high jitter and time offset within 100 microseconds. Using hardware-based timestamps, the trigger timing is executed within or near the physical layer, resulting in less jitter than software-based approaches and nanosecond accuracy.

[0005] IEEE 1588 proposes clock offset compensation, but does not consider frequency compensation, so it cannot provide full time synchronization. Therefore, improving its performance is an important research area. Summary of the Invention

[0006] (1) Technical problems solved

[0007] In view of the deficiencies in the prior art, the present invention provides a fuzzy control clock servo algorithm based on the IEEE 1588 protocol to solve the above problems.

[0008] (2) Technical solution

[0009] To achieve the above object, the present invention provides the following technical solutions: a fuzzy control clock servo algorithm based on IEEE1588 protocol, including the introduction of PI servo algorithm with fuzzy control logic: First, the clock synchronization model transfer function using addend register can be expressed as

[0010] Gp(s)=Ts(s) / U(s)=Kc*T / s (a)

[0011] Where Ts(s) is the output value of the slave node clock, U(s) is the input value of the clock module, T is the time synchronization period, Kc is the clock synchronization constant, and s is a complex number.

[0012] The PI clock servo uses the compensation algorithm described below, which is represented by the transfer function:

[0013] Gc(s)=Kp+Ki / s (b)

[0014] Where Kp is the proportional gain, Ki is the integral gain, and s is a complex number.

[0015] The enhanced algorithm is based on the clock synchronization model using addend registers, combined with the general PI clock server algorithm and fuzzy control logic.

[0016] The transfer function of the closed loop is obtained through (a) and (b):

[0017] H(s)=(kp*s+ki) / (s*s+kp*s+ki) (c)

[0018] Where kp = Kp Kc T, ki = Ki Kc T.

[0019] Preferably, the closed-loop clock servo system can be expressed as a second-order system with a natural frequency ωn and a damping coefficient ζ, as shown in (d)

[0020] H(s)=(2*ζ*ωn+ωn*ωn) / (s*s+2*ζ*ωn+ωn*ωn) (d)

[0021] where ωn*ωn=ki, and 2*ζ*ωn=kp.

[0022] Preferably, in the above transfer function, the response time, noise reduction, and overshoot time (also called overshoot time) are determined by ωn and ζ, and the two poles of the transfer function (p1, ) will affect the stability of the clock servo system ωn, and the response time is Therefore, when the damping coefficient is constant, the natural frequency will determine the quality of the clock servo. If ωn is small, the response time will be large, and vice versa. However, when ωn is small, the noise reduction will be enhanced. If s = jω, the bandwidth BW of the clock servo can be expressed by (e).

[0023]

[0024] Preferably, in equation (e), when the damping coefficient is fixed, the bandwidth of the clock servo is proportional to the natural frequency. Therefore, changing the natural frequency value will change the bandwidth of the clock servo. A larger bandwidth will be equal to a larger cutoff frequency (and vice versa). In addition, a larger bandwidth is equal to a faster acquisition time. In the initial stage, the system requires a larger bandwidth to reach the boundary error in a short time. At this time, the offset contains more random noise. When the system is stable, a suitable bandwidth is required to suppress the noise. Therefore, the fuzzy controller PI clock servo is used to adapt to the clock servo bandwidth. The absolute time offset |e| and the offset derivative de are two inputs of the fuzzy block controller. In order to smooth the bandwidth BW of the clock servo, the incremental bandwidth ΔBW is added to the previous bandwidth BWt-1 to replace the system bandwidth.

[0025] (3) Beneficial effects

[0026] Compared with the existing technology, the present invention provides a fuzzy control clock servo algorithm based on the IEEE 1588 protocol. The fuzzy control technology is used to effectively solve the boundary error of reaching the boundary within a short period in the initial stage of the PI servo and minimize the introduction of noise. When the system is stable, it can also have a good frequency response to suppress noise, thereby further improving the accuracy of the traditional PI servo algorithm based on PTP Ethernet hardware timestamps. It can provide sufficient stability in microsystems or synchronous motion systems such as those used in robots and precision machinery. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the clock model for a simple time correction algorithm;

[0028] Figure 2 This is a schematic diagram of network time synchronization based on the IEEE 1588 protocol of the present invention;

[0029] Figure 3 A schematic diagram of a clock synchronization model using an addend register according to the present invention;

[0030] Figure 4 Schematic diagram of the enhancement algorithm of the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] See also Figure 1 , Figure 1 This is a clock model for a simple time correction algorithm, which uses a sample-and-hold circuit and an integrator circuit. The transfer function of the clock model is expressed as follows:

[0033]

[0034] Where Kc is the clock model constant, Ts(s) is the output value from the clock (local time), U(s) is the input value of the clock module, and T is the time synchronization period.

[0035] In this model, PI (Proportional Integral) is used to correct time offset and clock rate. A conventional general method introduces a method to implement this compensation using only software (PI clock servo), which is a simple linear compensation and does not provide sufficient accuracy to meet the requirements of precise systems.

[0036] In addition, many factors affect its accuracy, including delay time, latency, and queue delay in the operating system. Methods for improvement include:

[0037] 1) Synchronization can be optimized by using a temperature-compensated oscillator or oven-controlled oscillator to provide a local clock. In addition, some applications use a grandmaster clock with high-resolution timestamps at the physical layer. Such systems can improve synchronization in the network, but they also increase costs.

[0038] 2) Using the integrated square error method: A deadbeat PI controller (optimal PI servo) is designed to minimize the integrated square time offset. The KP and KI parameters are fixed and belong to the time synchronization period and clock model parameters, respectively. Using this method, the slave clock can track the master clock within one time synchronization period, but there is a trade-off between the coverage time and the time offset. If the time offset is large, the clock cannot reduce the noise caused by the quantization error.

[0039] 3) A frequency compensation based on a fraction of the master clock and the slave clock: This method looks like ratio compensation and provides offset and rate offset correction. The algorithm is good, but some noise cannot be reduced.

[0040] 4) Improvement based on 3): Add a filter to suppress random noise and quantization error. A simple and effective way to improve synchronization performance is to use a low-pass filter. However, it introduces a time constant λ into the response (transfer function) of the clock server.

[0041] 5) Improvement based on 4): Kalman filter (KF) can also be used to reduce quantization error. When using KF, it is necessary to clearly determine the process noise (Q) and measurement noise (R), because the filter performance depends on the ability to correctly determine R and Q. KF improves time synchronization performance, but the clock server still takes many cycles to reach the offset boundary value, which makes it unsuitable for real-time systems with many devices, because devices in real-time systems need to be synchronized for processing in a short time. In addition, KF requires offline determination of clock server parameters, which is not conducive to noisy network systems.

[0042] The IEEE 1588 protocol ensures high performance in information transmission across many industrial architectures. It can achieve very low errors in demanding control-level devices such as actuators, sensors, drives, and motors. This is because when time is synchronized, the sampling times of motion controllers are also synchronized, and message scheduling tasks are strictly managed. This summarizes the aforementioned improvement methods and proposes the following fuzzy control clock servo algorithm.

[0043] See also Figure 2 , Figure 2The following is a diagram of a common high-precision implementation of the Precision Time Protocol (PTP). To facilitate understanding of the enhanced algorithm, the working principle and implementation process of time synchronization in an environment with Ethernet PTP hardware timestamp support are briefly described:

[0044] The IEEE 1588 standard defines a protocol that allows for precise clock synchronization in measurement and control systems implemented using technologies such as network communications, local computing, and distributed objects. The protocol is applicable to systems communicating over local area networks that support multicast messaging, including (but not limited to) Ethernet. The protocol is used to synchronize heterogeneous systems, including clocks with different inherent accuracy, resolution, and stability. The protocol supports sub-microsecond system-wide synchronization accuracy with minimal network and local clock computing resources. This message-based protocol, also known as the Precision Time Protocol (PTP), is transmitted over UDP / IP. The system / network is divided into master and slave nodes for distributing timing / clock information. Figure 2 The protocol describes the technology used to synchronize slave nodes with a master node by exchanging PTP messages, where:

[0045] The master node broadcasts the PTPSync message to all its nodes. The Sync message contains the reference time information of the master device. The time when the message leaves the master system is t1. For Ethernet ports, this time must be captured in the MII (Media Independent Interface, the same below).

[0046] The slave receives the Sync message and uses its timing reference to capture the exact time t2.

[0047] The master then sends a Follow_up message to the slave, which contains the t1 information for later use.

[0048] The slave device sends a Delay_Req message to the master device, indicating the exact time t3 at which the frame leaves the MII.

[0049] The master node receives the message and captures the exact time t4 at which it enters its system.

[0050] The master sends the t4 information to the slave in the Delay_Resp message.

[0051] The slave device uses the four values ​​t1, t2, t3, and t4 to synchronize its local timing reference time to the timing reference time of the master device.

[0052] Most of the protocol implementation occurs in software, above the UDP layer. However, as mentioned above, hardware support is required to capture the exact time when a specific PTP packet enters or leaves the MII Ethernet port. This timing information must be captured and returned to the software to implement PTP correctly and with high accuracy.

[0053] Reference time source:

[0054] To obtain a time snapshot, the central processing unit requires a reference time in a 64-bit format (divided into two 32-bit channels, the upper 32 bits provide time in seconds, and the lower 32 bits represent time in nanoseconds). The reference time format is defined in the IEEE1588 specification.

[0055] The PTP reference clock input is used to generate the reference time (also called system time) internally and capture timestamps. The frequency of this reference clock must be greater than or equal to the resolution of the timestamp counter. The synchronization accuracy target between the master and slave nodes is approximately 100ns.

[0056] The generation, update, and modification of the system time are described in "System Time Correction Method".

[0057] The accuracy of obtaining the timestamp (time snapshot) depends on the PTP reference clock input period, the characteristics of the oscillator (drift) and the frequency of the synchronization process. Due to the synchronization from the Tx and Rx clock input domain to the PTP reference clock domain, the uncertainty of the timestamp latch value is 1 reference clock period. If we increase the uncertainty due to resolution, we will add half the reference clock period to the timestamp.

[0058] Frame transmission using the PTP feature:

[0059] When the SFD of a frame is output on the MII, a timestamp is captured. Frames that require timestamp capture can be controlled on a per-frame basis. In other words, each transmitted frame can be marked to indicate whether a timestamp must be captured for the frame. Normally transmitted frames are not processed in this way to identify PTP frames. Frame control is performed through the control bits in the transmit descriptor. The captured timestamp is returned to the application in the same way as the status is provided to the frame. The timestamp is sent back in the corresponding transmit descriptor together with the transmit status of the frame, thereby automatically connecting the timestamp to a specific PTP frame. The 64-bit timestamp information is written back to the TDES2 and TDES3 fields, where TDES2 stores the lower 32 significant bits of the timestamp (TDES represents the Ethernet MAC (MediaAcessControl, the same below) layer hardware-related transmit descriptor symbol table).

[0060] Using PTP feature frame reception:

[0061] After enabling the IEEE1588 timestamp function, the Ethernet MAC captures the timestamps of all frames received on the MII. The MAC provides the timestamp immediately after the frame is received. The captured timestamp is returned to the application in the same way as the frame status is provided. The timestamp is sent back together with the reception status of the frame and placed in the corresponding receive descriptor. The 64-bit timestamp information is written back to the RDES2 and RDES3 fields, where RDES2 saves the lower 32 significant bits of the timestamp (RDES represents the Ethernet MAC layer hardware-related receive descriptor symbol table).

[0062] System time correction method:

[0063] The 64-bit PTP time is updated using the PTP input reference clock HCLK. The PTP time is used as the source for obtaining a snapshot (timestamp) of the Ethernet frame transmitted or received on the MII. The system time counter can be initialized or corrected using a coarse or fine correction method.

[0064] In the coarse correction method (used when the time offset is large), the initial value or offset value is written to the timestamp update register. For initialization, the system time counter will write the value in the timestamp update register, while for system time correction, the offset value (timestamp update register) is added to or subtracted from the system time.

[0065] In the fine correction method (used when the time offset is small), the frequency drift of the slave clock (reference clock) relative to the master clock (as defined in IEEE1588) is corrected over a period of time. This is different from the coarse correction method that corrects in a single clock cycle. The longer correction time helps to maintain linear time and does not introduce drastic changes (or large jitter) in the reference time between PTPSync message intervals. In this method, the accumulator adds the contents of the addend register, such as Figure 3 As shown, the arithmetic carry generated by the accumulator is used as a pulse to increment the system time counter.

[0066] The accumulator and addend registers are 32-bit registers, where the accumulator acts as a high-precision multiplier or divider.

[0067] See also Figure 3 , Figure 3 To show Figure 2 The model of the way it is represented, Figure 3 The transfer function of the clock synchronization model can be expressed as

[0068] Gp(s)=Ts(s) / U(s)=Kc*T / s (a)

[0069] Where Ts(s) is the output value of the slave node clock, U(s) is the input value of the clock module, T is the time synchronization period, Kc is the clock synchronization constant, and s is a complex number.

[0070] As mentioned above, we know that the IEEE1588 protocol can compensate for large time offsets. However, it is not stable enough for use in microsystems or synchronized motion systems (such as those used by robots or precision machinery). Our clock servo is implemented according to the IEEE1588 protocol to achieve high-performance offset compensation (correction) at the nanosecond level. PI compensation is used for time offset and rate offset compensation. The PI controller filter can reduce noise, but the KP and KI parameters are fixed during design. Therefore, if time synchronization requires a higher frequency, this design cannot meet the requirements.

[0071] See also Figure 4 , a fuzzy control clock servo algorithm based on IEEE1588 protocol, including the introduction of PI servo algorithm with fuzzy control logic: Generally speaking, a PI clock servo uses the compensation algorithm described below, that is, the transfer function representation:

[0072] Gc(s)=Kp+Ki / s (b)

[0073] Where Kp is the proportional gain, Ki is the integral gain, and s is a complex number.

[0074] based on Figure 3 The clock model is combined with the general PI clock server algorithm and the fuzzy control logic to obtain an enhanced algorithm, such as Figure 4 .

[0075] The transfer function of the closed loop is obtained through (a) and (b):

[0076] H(s)=(kp*s+ki) / (s*s+kp*s+ki) (c)

[0077] where kp = Kp Kc T and ki = Ki Kc T

[0078] The closed-loop clock servo system can be expressed as a second-order system with a natural frequency ωn and a damping coefficient ζ, as shown in (d)

[0079] H(s)=(2*ζ*ωn+ωn*ωn) / (s*s+2*ζ*ωn+ωn*ωn) (d)

[0080] where ωn*ωn=ki, and 2*ζ*ωn=kp

[0081] In the above transfer function, the response time, noise reduction, and overshoot time (also called overshoot time) are determined by ωn and ζ. The two poles of the transfer function (p1, ) will affect the stability of the clock servo system ωn, and the response time is Therefore, when the damping coefficient is constant, the natural frequency will determine the quality of the clock servo. If ωn is small, the response time will be large, and vice versa. However, when ωn is small, the noise reduction will be enhanced. If s = jω, the bandwidth BW of the clock servo can be expressed by (e).

[0082]

[0083] In equation (e), when the damping coefficient is fixed, the bandwidth of the clock servo is proportional to the natural frequency. Therefore, changing the natural frequency value will change the bandwidth of the clock servo. A larger bandwidth will equal a larger cutoff frequency (and vice versa). In addition, a larger bandwidth equals a faster acquisition time. In the initial stage, the system requires a larger bandwidth to reach the boundary error in a short time. At this time, the offset contains more random noise. When the system is stable, a suitable bandwidth is required to suppress the noise. Therefore, the fuzzy controller PI clock servo is used to adapt the clock servo bandwidth. The absolute time offset |e| and the offset derivative de are the two inputs of the fuzzy block controller. In order to smooth the bandwidth BW of the clock servo, the incremental bandwidth ΔBW is added to the previous bandwidth BWt-1 to replace the system bandwidth (such as Figure 4 ).

[0084] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A fuzzy control clock servo algorithm based on the IEEE 1588 protocol, including the introduction of a PI servo algorithm with fuzzy control logic, characterized by: First, the transfer function of the clock synchronization model using the addend register is expressed as Gp(s)=Ts(s) / U(s)=Kc*T / s (a); Where Ts(s) is the output value of the slave node clock, U(s) is the input value of the clock module, T is the time synchronization period, Kc is the clock synchronization constant, and s is a complex number; The PI clock server uses the compensation algorithm described below. The compensation algorithm is: Gc(s)=Kp+Ki / s (b); Where Kp is the proportional gain, Ki is the integral gain, and s is a complex number; Based on the clock synchronization model using addend registers, combined with the general PI clock server algorithm and fuzzy control logic, an enhanced algorithm is obtained; The transfer function of the closed loop is obtained through (a) and (b): H(s)=(kp*s+ki) / (s*s+kp*s+ki) (c); Where kp=Kp*Kc*T, ki=Ki*Kc*T.

2. The fuzzy control clock servo algorithm based on the IEEE 1588 protocol according to claim 1, characterized in that: The closed-loop clock servo system is represented as a second-order system with a natural frequency ωn and a damping coefficient ζ, as shown in (d) H(s)=(2*ζ*ωn+ωn*ωn) / (s*s+2*ζ*ωn+ωn*ωn) (d); where ωn*ωn=ki, and 2*ζ*ωn=kp.

3. The fuzzy control clock servo algorithm based on the IEEE 1588 protocol according to claim 2, characterized in that: In the transfer function (d), the response time, noise reduction, and overshoot time are determined by ωn and ζ. The two poles of the transfer function (d) affect the stability of the clock servo system. The expressions of the two poles are , the response time is , therefore, when the damping coefficient is constant, the natural frequency ωn will determine the quality of the clock servo. If ωn is small, the response time is large, and if ωn is large, the response time is small. However, when ωn is small, the noise reduction will be enhanced. The bandwidth BW of the clock servo is represented by (e); (e)。 4. The fuzzy control clock servo algorithm based on the IEEE 1588 protocol according to claim 3, characterized in that: In equation (e), when the damping coefficient is fixed, the bandwidth of the clock servo is proportional to the natural frequency. Changing the natural frequency value will change the bandwidth of the clock servo. A larger bandwidth will equal a larger cutoff frequency, which means a faster acquisition time. In the initial stage, the system requires a larger bandwidth to reach the boundary error in a short time. At this time, the offset contains more random noise. When the system is stable, a suitable bandwidth is required to suppress the noise. The fuzzy controller PI clock servo adapts to the clock servo bandwidth. The absolute time offset |e| and the offset derivative de are two inputs of the fuzzy block controller. In order to smooth the bandwidth BW of the clock servo, the incremental bandwidth ΔBW is added to the previous bandwidth BWt-1 to replace the system bandwidth.

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