Power Management for Multi-Plane Read Operations

Abstract

The present invention describes apparatuses and techniques for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether a block identified by the read command is fully programmed or partially programmed. If it is fully programmed, the read command is executed while applying a common read pass voltage to unprogrammed word lines of the corresponding block. If the block is not fully programmed, the control circuit determines the last programmed word line. If the last programmed word lines in each block are not equal, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher programmed blocks and applying a lower read pass voltage to the unprogrammed word lines of one or more lower programmed blocks.

Description

BACKGROUND OF THE INVENTION

[0001] The present technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in various electronic devices. For example, non-volatile semiconductor memories are used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be vertically arranged in a three-dimensional (3D) stacked memory structure or horizontally arranged in a two-dimensional (2D) memory structure. An example of a 3D memory structure is a bit cost scalable (BiCS) architecture that includes a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be serially arranged into NAND strings (e.g., NAND chains), for example, where a select gate transistor is provided at the end of the NAND string to selectively connect the channel of the NAND string to a source line or a bit line. However, there are various challenges in operating such memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a block diagram of an example memory device.

[0006] Figure 1B illustrates Figure 1A an example of the temperature sensing circuit 116 of.

[0007] Figure 2 is a block diagram illustrating Figure 1A one embodiment of the sensing block 51 of.

[0008] Figure 3 illustrates Figure 1A an exemplary implementation of the power control circuit 115 for supplying voltage to a block of memory cells in a plane of.

[0009] Figure 4 is a perspective view of an exemplary memory die 400 in accordance with Figure 1A where memory cell blocks are provided in respective planes P0 - P3, and the meta block 410 includes blocks B0-0 to B3-0.

[0010] Figure 5 illustrates Figure 1A an exemplary transistor 520 in the memory structure 126 of.

[0011] Figure 6A illustratesFigure 4 Exemplary cross-sectional view of a portion of block B0-0 including NAND strings 700n and 710n.

[0012] Figure 6B Shows Figure 6A A close-up view of the stacked region 622.

[0013] Figure 7A Depicts Figure 4 And Figure 6A An exemplary view of the NAND strings in block B0-0 in accordance with

[0014] Figure 7B Shows a memory cell in WL3 of sub-block SB0 connected to Figure 7A having a corresponding NAND string, bit line, and sense circuit.

[0015] Figure 7C Shows Figure 7A And Figure 7B An exemplary view of NAND string 700n showing the overdrive voltage of channel 700a during a read operation, where WLn = WL3 is the selected word line.

[0016] Figure 8A Shows different processes that can be performed by a control circuit in conjunction with a read operation to reduce current consumption.

[0017] Figure 8B Shows Figure 8A An exemplary read process in accordance with

[0018] Figure 8C Shows Figure 8A Another exemplary read process in accordance with

[0019] Figure 8D Shows Figure 8A An exemplary programming operation in accordance with step 809.

[0020] Figure 8E Shows an exemplary table 119 maintained by Figures 8A to 8D for use in conjunction with Figure 1A RAM 122b.

[0021] Figure 9A Shows a first exemplary configuration of corresponding block groups B0-0 to B0-3, where the blocks have the same boundary word lines and a common read pass voltage Vread_UP_base is applied to the unprogrammed word lines.

[0022] Figure 9BShows a second exemplary configuration of corresponding block groups B0-0 to B0-3, where block B0-0 has a higher boundary word line than blocks B1-0 to B3-0, and a lower read pass voltage Vread_UP_L1 is applied to the unprogrammed word lines of B1-0 to B3-0.

[0023] Figure 9C Shows a third exemplary configuration of corresponding block groups B0-0 to B0-3, where blocks B0-0 and B1-0 have higher boundary word lines than blocks B2-0 and B3-0, and a lower read pass voltage Vread_UP_L2 is applied to the unprogrammed word lines of B2-0 and B3-0.

[0024] Figure 9D Shows a fourth exemplary configuration of corresponding block groups B0-0 to B0-3, where blocks B0-0 to B2-0 have higher boundary word lines than block B3-0, and a lower read pass voltage Vread_UP_L3 is applied to the unprogrammed word lines of B3-0.

[0025] Figure 10A Shows Figures 9A to 9D A graph of the read pass voltage of unprogrammed word lines as a function of the number of less programmed blocks, where the read pass voltage is lower when the number of less programmed blocks is larger.

[0026] Figure 10B Shows Figures 9A to 9D A graph of the read pass voltage of unprogrammed word lines as a function of the WLn position, where the read pass voltage is higher when the WLn position is closer to the last programmed word line.

[0027] Figure 11A Shows an exemplary Vth distribution of a group of memory cells having one bit per cell and two data states.

[0028] Figure 11B Shows an exemplary Vth distribution of a group of memory cells having three bits per cell and eight data states.

[0029] Figure 12A Shows Figure 8D And Figure 11B Exemplary voltage signals used in the programming operation.

[0030] Figure 12B Shows Figure 12A Examples of verification voltages used in different programming cycles.

[0031] Figure 13 Shows Figure 12A Exemplary voltage signals used to perform the programming operation.

[0032] Figure 14A shows exemplary voltage signals (curves 1400 to 1404) for performing a read operation on intermediate page data that are consistent with Figures 8A to 8C and Figure 11B

[0033] Figure 14B shows exemplary voltage signals for performing a read operation on lower page data that are consistent with Figures 8A to 8C and Figure 11B

[0034] Figure 14C shows exemplary voltage signals for performing a read operation on upper page data that are consistent with Figures 8A to 8C and Figure 11B

[0035] Figure 14D shows exemplary voltage signals for performing a read operation on a page of data that are consistent with Figures 8A to 8C and Figure 11A DETAILED DESCRIPTION

[0036] The present invention describes apparatuses and techniques for managing power consumption when performing a multi-plane read operation.

[0037] In some memory devices, memory cells are joined together, such as in NAND strings in a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select gate transistors (referred to as SGD transistors) located at the drain side of the NAND string connected to a bit line; and one or more source-side select gate transistors (referred to as SGS transistors) located at the source side of the NAND string or other memory string or group of connected memory cells connected to a source line. Additionally, the memory cells can be arranged with a common control gate line (e.g., word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. The memory cells can be connected in other types of strings and can also be connected in other ways.

[0038] In a 3D memory structure, the memory cells can be arranged in stacked vertical NAND strings, where the stack includes alternating conductive layers and dielectric layers. The conductive layers serve as word lines connected to the memory cells. Each NAND string can have a column shape that intersects with the word lines to form the memory cells. In a 2D memory structure, the memory cells can be arranged in horizontal NAND strings on a substrate.

[0039] In some cases, memory cell blocks are arranged in different planes on a substrate on one or more dies, such as Figure 4 ​​​​As shown. In addition, blocks in different planes can be grouped into meta-blocks and read simultaneously in a multi-plane read operation. The meta-blocks form data units that can be read by a host device. The multi-plane read operation can involve corresponding blocks in all planes (in which case it is a full-plane read operation) or fewer than all corresponding blocks in the planes. In addition, a meta-block can include blocks having the same relative position in each plane, such as Figure 4 meta-block 410 in, which includes the first block in each plane, such as B0-0 to B3-0. Alternatively, a meta-block can include blocks having different relative positions in their planes. For example, in Figure 4 , the meta-block can include B0-0 (the first block in P0) and B1-1 to B3-1 (the second blocks in P1-P3), respectively.

[0040] However, a multi-plane read operation may consume a significant amount of current. Specifically, it has been observed that current consumption increases when read operations occur in blocks that are partially programmed in different amounts. Both the average and peak current consumption should be kept within specified limits. The average current consumption should be limited to optimize the battery life of the memory device, and the peak current consumption should be limited to avoid failures of the memory device due to voltage drops.

[0041] The techniques provided herein solve the above and other problems. In one aspect, when a multi-plane read command is received at the control circuit of a memory device, the control circuit determines whether the blocks identified by the read command are fully programmed or partially programmed. If it is fully programmed, the read command is executed simultaneously on the selected word lines in each block while applying a common read pass voltage to the erased (unprogrammed) word lines of the corresponding blocks. If the corresponding blocks are not all fully programmed, the control circuit determines the boundary word lines in each corresponding block, i.e., the last programmed word line. If the boundary word lines in each corresponding block are equal, the read command is executed simultaneously on the selected word lines in each block while applying a common read pass voltage to the unprogrammed word lines of the corresponding blocks. If the boundary word lines in each corresponding block are not equal, the read command is executed simultaneously on the selected word lines in each block while applying a base read pass voltage to the unprogrammed word lines of one or more higher programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower programmed blocks.

[0042] When the number of less programmed blocks is large, the lower read pass voltage can be lower. By reducing the read pass voltage, the voltage over-drive of the memory cells is reduced, resulting in reduced current consumption.

[0043] In another aspect, if the corresponding blocks are not all fully programmed and the boundary word lines in each corresponding block are not equal, then the full-plane read command is replaced by one or more alternative read commands. For example, the more highly programmed blocks can be read by themselves in a single-plane read operation while the other corresponding blocks are inactive and thus do not consume current. In another approach, the corresponding blocks are read in independent read operations that can start at different times to reduce current. The independent read operations can be partially or non-overlapping in time.

[0044] In another aspect, when the memory device is powered on and before a read command is received, it is initially determined whether the corresponding blocks are fully programmed, and if they are not fully programmed, their boundary word lines are determined. The multi-plane prefetch operation can use this information to avoid reading blocks in which the boundary word lines are not equal to reduce current consumption.

[0045] These and other features will be discussed further below.

[0046] Figure 1A is a block diagram of an exemplary memory device. A memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. A memory die 108 or chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable via word lines by a row decoder 124 and is addressable via bit lines by a column decoder 132. The read / write circuitry 128 includes a plurality of sense blocks 51, 52, ……, 53 (sense circuitry) and allows parallel reading or programming of pages of memory cells. Generally, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller can be separate from the memory die. Commands and data are transferred between a host 140 and the controller 122 via a data bus 120 and between the controller and one or more memory dies 108 via lines 118.

[0047] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure can include one or more arrays of memory cells, the one or more arrays of memory cells including 3D arrays. The memory structure can include a monolithic 3D memory structure in which multiple memory levels are formed above (rather than within) a single substrate (such as a wafer) without an intermediate substrate. The memory structure can include any type of non-volatile memory that is monolithically formed in one or more physical levels of an array of memory cells having an active region disposed above a silicon substrate. The memory structure can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0048] The control circuit 110 cooperates with the read / write circuit 128 to perform memory operations on the memory structure 126, and includes a state machine, an on-chip address decoder 114, a power control module 115 (power control circuit), a temperature sensing circuit 116, and a Vread setting circuit 117. A storage area 113 may be provided, for example, for operation parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuits).

[0049] The on-chip address decoder 114 provides an address interface between the hardware address used by the host or memory controller and the hardware addresses used by the decoders 124 and 132. The power control module 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. The power control module may include drivers for the word lines, SGS and SGD transistors, and source lines. See also Figure 3 . In one method, the sense block may include a bit line driver. The temperature sensing circuit 116 may detect the temperature of the memory device during the lifespan of the memory device (e.g., every minute). The Vread magnitude in the Vread setting circuit 117 may be adjusted based on the temperature. For example, as the temperature increases, Vread may decrease because the current in the NAND string channel is larger. Generally, the temperature sensing circuit is configured to provide a temperature indication for setting a relatively low read pass voltage when the temperature is relatively high. The Vread setting circuit 117 may set the read pass voltage (Vread) during a read operation. For example, see Figures 9A to 10B .

[0050] For a specific example implementation of the temperature sensing circuit, see Figure 1B . The circuits 116 and 117 may include hardware, software, and / or firmware for performing the processes described herein.

[0051] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or a combination of the control circuit 110, the state machine 112, the decoders 114 and 132, the power control module 115, the temperature sensing circuit 116, the Vread setting circuit 117, the sense blocks 51, 52...53, the read / write circuit 128, the controller 122, etc.

[0052] The off-chip controller 122 (which is circuitry in one implementation) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an Error Correction Code (ECC) engine 245. The ECC engine can correct many read errors. The RAM 122b may be DRAM, which includes a storage location 122c for uncommitted data. During programming, a copy of the data to be programmed is stored in the storage location 122c until programming is successfully completed. In response to successful completion, the data is erased from this storage location and committed or released to the memory cell block. The storage location 122c may store one or more word lines of data.

[0053] The RAM 122b may also include a table 119 that stores information about the blocks used (such as the last programmed word line). See Figure 8E .. In one approach, the system uses two areas to store information about the blocks used. Specifically, a Logical to Physical (L2P) table (stored in the memory structure 126) and a temporary table for open blocks (stored in the RAM 122b). Whenever the system opens a new block for use, information is written to the tables in the array to ensure that in the event of losing the data in the RAM, it knows where to look for the table. If the system receives an indication that a power cycle is planned, it will dump all the information from the RAM 122b to the array to keep it there for later retrieval. If power is suddenly cut off, the system loses the information and must, for example, perform some search of the open blocks by using its previously saved list to recover the information.

[0054] A memory interface 122d may also be provided. The memory interface that communicates with the ROM, RAM, and the processor is circuitry that provides an electrical interface between the controller and the memory die. For example, the memory interface may change the format or timing of signals, provide buffers, isolate electrical surges, latch I / O, etc. The processor may issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122d.

[0055] The memories in the controller 122 such as ROM 122a and RAM 122b include code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functions described herein. Alternatively or in addition, the processor may access code from a subgroup 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.

[0056] For example, the controller may use code to access memory structures, such as for programming operations, read operations, and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller during the boot or startup process and enables the controller to access the memory structures. The controller may use the code to control one or more memory structures. Upon power-up, the processor 122e fetches the boot code from the ROM 122a or the subgroup 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers that perform basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0057] The controller, such as the RAM 122b and / or the control circuit 110, may store parameters indicating the expected number of failed bits in a block. These parameters may include, for example, the number of bits per cell stored in the memory cells, a portion of the word lines programmed in the block or sub-block, a portion of the sub-blocks programmed in the block, the strength of the ECC processing for storing and reading data in the block, the duration of the pre-read voltage pulse (if used), and the read accuracy, such as the bit line or word line voltage settling time and the number of sensing passes.

[0058] Generally speaking, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed further below, and providing voltage waveforms, including those discussed further below. The control circuit may be configured to execute instructions for performing the functions described herein.

[0059] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable devices (RAM, ROM, flash memory, hard disk drive, solid-state memory), and the one or more processor-readable devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0060] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0061] A semiconductor memory device includes volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices; non-volatile memory devices such as resistive random access memory (ReRAM), phase change resistive random access memory (PCRAM), electrically erasable programmable read only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0062] The memory device may be formed by passive elements and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching memory element such as an antifuse or a phase change material, and an optional steering element such as a diode or a transistor. Additionally, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include an element containing a charge storage region such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

[0063] Multiple memory elements may be configured such that they are connected in series or such that each element can be accessed individually. By way of non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND string is an example of a set of serially connected transistors that includes memory cells and SG transistors.

[0064] A NAND memory array may be configured such that the array is composed of multiple strings of memory, where the strings are composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element can be accessed individually, such as a NOR memory array. The NAND memory configuration and the NOR memory configuration are examples, and the memory elements may be configured in other ways.

[0065] Semiconductor memory elements located within and / or on a substrate may be arranged two-dimensionally or three-dimensionally, such as a 2D memory structure or a 3D memory structure.

[0066] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in the x-y direction plane) that extends substantially parallel to the main surface of the substrate that supports the memory elements. The substrate can be a wafer on or in which the layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after their formation. As a non-limiting example, the substrate can include a semiconductor such as silicon.

[0067] The memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, the memory elements can be arranged in a non-conventional configuration or a non-orthogonal configuration. Each of the memory elements can have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] A 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface of the substrate).

[0069] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns that extend substantially perpendicular to the main surface of the substrate, i.e., in the y direction), where each column has multiple memory elements. These columns can be arranged, for example, in a 2D configuration in the x-y plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0070] By way of non-limiting examples, in a 3D NAND memory array, the memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations can be envisioned, where some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. A 3D memory array can also be designed to be in a NOR configuration and in a ReRAM configuration.

[0071] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers that are at least partially located within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic array, the layers that make up each memory device level of the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between the memory device levels or have intermediate layers between the memory device levels.

[0072] 2D arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Additionally, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0073] Associated circuitry is typically required to operate and communicate with the memory elements. As a non-limiting example, a memory device can have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. The associated circuitry can be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations can be located on a separate controller chip and / or on the same substrate as the memory elements.

[0074] Those skilled in the art will recognize that the technology is not limited to the 2D and 3D exemplary structures described, but encompasses all relevant memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0075] Figure 1B An example of Figure 1A the temperature sensing circuit 116 is shown. The circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-based output voltage provided to an analog-to-digital (ADC) converter 129. Vbg is a voltage independent of temperature. The voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels by a resistor divider circuit.

[0076] The ADC compares Voutput with voltage levels, selects the closest match among the voltage levels, and outputs the corresponding digital value (VTemp) to the processor 122e. This is the data indicating the temperature of the memory device. In one method, the ROM fuse 123 stores data that correlates the matching voltage levels with temperature. Then, the processor uses the temperature to set temperature-based parameters in the memory device, such as by using a comparison circuit.

[0077] Vbg is obtained by applying the base-emitter voltage (Vbe) across the transistor 131b and the voltage drop across the resistor R2. The bipolar transistor 133a has a larger area (factor N) than the transistor 133b. The PMOS transistors 131a and 131b are of equal size and arranged in a current mirror configuration such that the currents I1 and I2 are substantially equal. It follows that Vbg = Vbe + R2×I2 and I1 = Ve / R1, so I2 = Ve / R1. Thus, Vbg = Vbe + R2×kT ln(N) / R1xq, where T is the temperature, k is the Boltzmann constant, and q is the unit of charge. The source of the transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and the resistor R3 is the output voltage Voutput. The gate of the transistor 134 is connected to the same terminals as the gates of the transistors 131a and 131b, and the current through the transistor 134 mirrors the current through the transistors 131a and 131b.

[0078] Figure 2 is a block diagram showing Figure 1A an embodiment of the sense block 51. The individual sense block 51 is divided into one or more core parts called sense circuits 60 - 63 or sense amplifiers and a common part called the management circuit 190. In one embodiment, each sense circuit is connected to a corresponding bit line and NAND string, and the common management circuit 190 is connected to a group of multiple (e.g., four or eight) sense circuits. Each sense circuit in the group communicates with the associated management circuit via the data bus 176. Thus, there is one or more management circuits that communicate with the sense circuits of a group of storage elements (memory cells).

[0079] For example, the sense circuit 60 operates during a programming cycle to provide a precharge / program - inhibit voltage to an unselected bit line or a program - enable voltage to a selected bit line. See also Figure 13Vbl in it. The unselected bit lines are connected to unselected NAND strings and unselected memory cells therein. The unselected memory cells can be the memory cells in the unselected NAND strings, where the memory cells are connected to the selected or unselected word lines. The unselected memory cells can also be the memory cells in the selected NAND strings, where the memory cells are connected to the unselected word lines. The selected bit lines are connected to the selected NAND strings and the selected memory cells therein.

[0080] The sense circuit 60 also operates during the verify test in the programming cycle to sense the memory cells, so as to determine whether it has completed programming by reaching the assigned data state (e.g., as indicated by its Vth exceeding the verify voltage of the assigned data state). The sense circuit 60 also operates during the read operation to determine the data state to which the memory cells have been programmed. The sense circuit performs sensing by determining whether the conduction current in the connected bit lines is higher or lower than a predetermined threshold level. This indicates whether the Vth of the memory cells is lower or higher than the word line voltage, respectively.

[0081] The sense circuit may include a selector 56 or a switch connected to the transistor 55 (e.g., nMOS). Based on the voltages at the control gate 58 and the drain 57 of the transistor 55, the transistor can operate as a pass gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to transfer the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, when precharging and suppressing the unselected NAND strings, a programming suppression voltage such as 1V - 2V can be transferred. Alternatively, a programming enable voltage such as 0V can be transferred to allow programming in the selected NAND strings. The selector 56 can transfer the power supply voltage Vdd (e.g., 3V - 4V) to the control gate of the transistor 55 to make it operate as a pass gate.

[0082] When the voltage at the control gate is lower than the voltage on the drain, the transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg - Vth, where Vcg is the voltage on the control gate 58, and Vth (e.g., 1V) is the threshold voltage of the transistor 55. This assumes that the source line is 0V. This mode can be used during sensing operations such as read and verify operations. Thus, the transistor 55 sets the bit line voltage based on the voltage output by the selector 56. For example, the selector 56 can transfer Vbl_sense + Vth (e.g., 1.5V) to the transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. The Vbl selector 173 can transfer a relatively high voltage such as Vdd to the drain 57 to provide the source follower mode during the sensing operation, and the relatively high voltage is higher than the control gate voltage on the transistor 55.

[0083] The Vbl selector 173 can transfer one of multiple voltage signals. For example, the Vbl selector can transfer a program inhibit voltage signal that increases from an initial voltage (e.g., 0V) to a program inhibit voltage such as Vbl_unsel (also referred to as Vbl_inh) for the corresponding bit lines of unselected NAND strings during a programming cycle. The Vbl selector 173 can transfer a program enable voltage signal such as 0V for the corresponding bit lines of the selected NAND strings during a programming cycle. The Vbl selector can receive voltage signals from the first voltage source, the second voltage source, and the third voltage source 340a - 440c in Figure 3 respectively, and select one of these signals, for example, based on a command from the processor 192.

[0084] In one method, the selector 56 of each sense circuit can be controlled separately from the selectors of other sense circuits. The Vbl selector 173 of each sense circuit can also be controlled separately from the Vbl selectors of other sense circuits.

[0085] During sensing, the sense node 171 is charged until an initial voltage Vsense_init, such as 3V. Then, the sense node is transferred to the bit line via the transistor 55, and the amount of attenuation of the sense node is used to determine whether the memory cell is in a conductive state or a non - conductive state. Specifically, the comparison circuit 175 determines the amount of attenuation by comparing the sense node voltage with a trip voltage during sensing. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non - conductive state and its Vth is higher than the verification voltage. For example, the sense node latch 172 is set to 0 or 1 by the comparison circuit 175 based on whether the memory cell is in a conductive state or a non - conductive state respectively. The data in the sense node latch can be a bit read by the processor 192 and used to update the trip latch 174. Subsequently, for the next programming cycle, the processor can use the bit in the trip latch and the assigned data states in the latches 194 - 197 to determine whether the memory cell and the NAND string are selected or not selected for programming in the programming cycle, so as to transfer appropriate enable or inhibit bit line voltages to the bit lines respectively. The latches 194 - 197 can be regarded as data latches or user data latches because they store the data to be programmed into the memory cells.

[0086] The management circuit 190 includes a processor 192, four sets of exemplary data latches 194 - 197 respectively for the sensing circuits 60 - 63, and an I / O interface 196 coupled between the data latch sets and the data bus 120. A set of three data latches can be provided for each sensing circuit, for example, including individual latches LDL, MDL, and UDL. In some cases, a different number of data latches can be used. In a three - bits - per - cell embodiment, LDL stores the bit for the lower - page data, MDL stores the bit for the middle - page data, and UDL stores the bit for the upper - page data.

[0087] The processor 192 performs calculations to determine the data stored in the sensed memory cell and stores the determined data in the set of data latches. Each set of data latches 194 - 197 is used to store the data bits determined by the processor 192 during a read operation and the data bits imported from the data bus 120 during a programming operation, where these data bits represent the write data to be programmed into the memory. The I / O interface 196 provides an interface between the data latches 194 - 197 and the data bus 120.

[0088] During a read, the operation of the system is under the control of the state machine 112, which controls the provision of different control - gate voltages to the addressed memory cell. As it steps through the various predefined control - gate voltages corresponding to the various memory states supported by the memory, the sensing circuit can trip at one of these voltages, and the corresponding output will be provided to the processor 192 from the sensing circuit via the data bus 176. At this time, the processor 192 determines the resulting memory state by considering the trip event of the sensing circuit and the information about the control - gate voltage applied via the input line 193 from the state machine. Then, it calculates the binary encoding of the memory state and stores the resulting data bits into the data latches 194 - 197.

[0089] Some embodiments may include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) such that each output line is wired ORed together. In some embodiments, the output lines are inverted before being connected to the wire OR. This configuration enables the rapid determination of when the programming process is complete during a programming verification test because the state machine receiving the wire OR can determine when all programmed bits have reached the desired level. For example, when each bit reaches its required electrical level, a logic zero for that bit will be sent to the wire OR (or the data one is inverted). When all bits output data 0 (or the data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine would need to read the wire OR eight times, or logic could be added to the processor 192 to accumulate the results of the relevant bit lines such that the state machine only needs to read the wire OR once. Similarly, by correctly choosing the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0090] During a programming or verification operation of a memory cell, the data to be programmed (write data) is stored in a data latch bank 194 - 197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell may store data indicating when the memory cell is enabled for reprogramming based on the programming pulse magnitude.

[0091] Under the control of the state machine, a programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incremented by one step from the previous programming pulse in the process, which is called incremental step pulse programming. After each programming voltage is a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When the two are consistent, the processor 192 sets the bit line to a programming inhibit mode, such as by updating its latch. This prohibits further programming of the memory cell coupled to the bit line even if additional programming pulses are applied to its control gate.

[0092] Each set of data latches 194 - 197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers such that the parallel data stored therein is converted to serial data for the data bus 120 and vice versa. All the data latches corresponding to the read / write blocks of the memory cells can be connected together to form a block shift register so that data blocks can be input or output through serial transmission. Specifically, the read / write circuit module group is adjusted such that its group of data latches shifts data into or out of the data bus in sequence as if they were part of a shift register of the entire read / write block.

[0093] The data latches indicate when certain milestones of the programming operation are reached for the associated memory cells. For example, the latch can identify that the Vth of the memory cell is below a specific verification voltage. The data latches indicate whether the memory cell currently stores one or more bits from a page of data. For example, the LDL latch can be used to store the next page data. When the next page bit is stored in the associated memory cell, the LDL latch is flipped (e.g., from 0 to 1). For three bits per cell, the MDL or UDL latch is flipped when the middle or upper page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell finishes programming.

[0094] Figure 3 is shown Figure 1A An exemplary specific implementation of the power control circuit 115 for supplying voltage to a block of memory cells in a plane is shown. In one method, the shown circuit can be repeated for each plane of the die. In this example, the memory structure 126 includes a group 310 of four associated blocks B0 - 0 to B0 - 3, and another group 311 of four associated blocks B0 - 4 to B0 - 7. The blocks can be in one or more planes. Figure 1A The row decoder 124 of supplies voltage to the word lines and the select gates of each block via transfer transistors 322. The row decoder provides a control signal to the transfer transistor that connects the block to the row decoder. In one method, the transfer transistors of each group of blocks are controlled by a common control gate voltage. Thus, all the transfer transistors of a group of blocks are turned on or off at a given time. If the transfer transistor is on, the voltage from the row decoder is supplied to the corresponding control gate line or word line. If the transfer transistor is off, the row decoder is disconnected from the corresponding control gate line or word line such that the voltage floats on the corresponding control gate line or word line.

[0095] For example, the control gate line 312 is connected to the transfer transistor groups 313, 314, 315, and 316, which are in turn connected to the control gate lines B0-4, B0-5, B0-6, and B0-7, respectively. The control gate line 317 is connected to the transfer transistor groups 318, 319, 320, and 321, which are in turn connected to the control gate lines B0-0, B0-1, B0-2, and B0-3, respectively.

[0096] Generally, programming or reading operations are performed on one selected block at a time in a block. An erase operation can be performed on a selected block or sub-block. The row decoder can connect the global control line 302 to the local control line 303. The control line represents a conductive path. Voltage is provided on the global control lines of many voltage drivers. Some voltage drivers can provide voltage to the switch 350 connected to the global control line. Control the transfer transistor 324 to transfer voltage from the voltage driver to the switch 350.

[0097] The voltage driver can include a selected data word line (WL) driver 347 that provides voltage on the selected data word line during a programming or reading operation. The driver 347 can provide a pre-charge voltage and a programming voltage on WLn during the programming cycle of the programming operation. The driver 348 can be used for unselected data word lines, and the dummy word line drivers 349 and 349a can be used to provide voltage on the Figure 6A dummy word lines WLDD and WLDS in, respectively. For example, the driver 348 can be used to apply a pre-charge voltage and a pass voltage on the unselected word line during the programming cycle of the programming operation. See also Figure 13 VWL_unsel in.

[0098] The voltage driver can also include a separate SGD driver for each sub-block. For example, as in Figure 7A , SGD drivers 346, 346a, 346b, and 346c can be provided for SB0, SB1, SB2, and SB3, respectively. In one option, the SGS driver 345 is common for different sub-blocks in the block.

[0099] Various components including the row decoder can receive commands from a controller such as the state machine 112 or the controller 122 to perform the functions described herein.

[0100] The well voltage driver 330 provides the voltage Vsl to the well region 611b in the substrate via the control line 332 ( Figure 6A ). The well voltage driver 330 is an example of a source line driver, where the well region 611b is a source line, for example, a conductive path connected to the source extreme of the NAND string. In one method, the well region 611a is common for the block. The blocks also share a set of bit lines 342.

[0101] The bit line voltage driver 340 includes a voltage source that supplies voltage to the bit lines. For example, the bit line voltage driver may include a first voltage source 340a configured to output a program inhibit voltage signal. This signal increases from an initial level such as 0V to a final peak level such as Vbl_unsel to precharge the channels of the corresponding NAND strings and prevent programming of the memory cells in the NAND strings.

[0102] The bit line voltage driver may further include a second voltage source 340b configured to output a program enable voltage signal. This signal may have a fixed voltage such as 0V, which allows programming of selected memory cells in the corresponding NAND strings. The bit line voltage driver may further include a third voltage source 340c configured to output a fixed voltage Vbl_sense, which allows sensing of selected memory cells in the corresponding NAND strings. Sensing may be performed during a read or verify test. The voltage sources 340a, 340b, and 340c may be connected to a sense circuit and used to supply voltage to, for example Figure 2 the Vbl selector 173.

[0103] In a stacked memory device such as Figures 4 to 7C illustrated, multiple sets of connected memory cells may be arranged in NAND strings that extend vertically upward from a substrate. In one method, the bottom (or source extreme) of each NAND string contacts the substrate, such as a well region, and the top (or drain extreme) of each NAND string is connected to a corresponding bit line.

[0104] Figure 4 is a perspective view of an exemplary memory die 400 in accordance with Figure 1A where memory cell blocks are disposed in respective planes P0 - P3, and the meta block 410 includes blocks B0 - 0 to B3 - 0. The memory die includes a substrate 401, an intermediate region 402 where the memory cell blocks are formed, and an upper region 403 where one or more upper metal layers are patterned to form bit lines. The planes P0 - P3 represent respective isolation regions formed in the substrate 401. Additionally, block sequences 405, 415, 425, and 435 of n blocks labeled B0 - 0 to B0 - n - 1, B1 - 0 to B1 - n - 1, B2 - 0 to B2 - n - 1, and B3 - 0 to B3 - n - 1 are formed in P0 - P3, respectively. Each plane may have associated row and column control circuits, such as Figure 1A the row decoder 124, read / write circuit 128, and column decoder 132 of

[0105] In one method, control circuits 110 that may be located in the peripheral region of the die may be shared between the planes. Each plane may have a separate set of bit lines.

[0106] By providing memory cell blocks in multiple planes, parallel operations can be performed within the planes. Additionally, the blocks within a meta-block can be simultaneously read as data units during a multi-plane read operation. Typically, the same selected word lines and page types are read in each block, and the read operations occur concurrently. In some cases, the blocks within a meta-block may contain related data. The blocks within a meta-block can be arranged on a common die or extend across multiple dies.

[0107] The substrate 201 can also carry the circuitry beneath the blocks, as well as one or more lower metal layers that are patterned in conductive paths to carry signals of the circuitry.

[0108] In this example, memory cells are formed in vertical NAND strings within the blocks. Each block includes a stacked region of memory cells, where the alternating stacked layers represent word lines. In one possible approach, each block has opposing stratified sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths. Although four planes are shown as an example, other examples may use fewer (e.g., two) planes or more (e.g., eight) planes. One plane per die is also possible.

[0109] Although the above example relates to a 3D memory device with vertically extending NAND strings, the techniques provided herein are also applicable to 2D memory devices where the NAND strings extend horizontally on a substrate.

[0110] Figure 5 An exemplary transistor 520 in the memory structure 126 is shown. Figure 1A The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and can represent, for example, a memory cell or a select gate transistor. The drain end of the transistor is optionally connected to a bit line BL via one or more other transistors in the NAND string, and the source end of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string.

[0111] Figure 6A An exemplary cross-sectional view of a portion of the block B0-0 including NAND strings 700n and 710n is shown. Figure 4 In this example, the NAND strings 700n and 710n are in different sub-blocks. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers can be rectangular plates having a height in the z direction, a width in the y direction, and a length in the x direction.

[0112] The stack is depicted as including one layer but can optionally include one or more layers of alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers in which memory holes are formed during the manufacturing process.

[0113] The conductive layer includes SGS, WLDS, WL0 - WL95, WLDD, and SGD(0). WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not eligible to store user data. Dummy memory cells may have the same structure as data memory cells, but the controller considers such memory cells ineligible to store any type of data including user data. One or more dummy memory cells may be provided at the drain and / or source extremities of the NAND strings of the memory cells to provide a gradual transition of the channel voltage gradient. WL0 - WL95 are data word lines connected to data memory cells that are eligible to store user data. By way of example only, the stack includes ninety - six data word lines. DL is an exemplary dielectric layer.

[0114] The top 653 and bottom 650 of the stack are depicted. WL95 is the top - most data word line or conductive layer, and WL0 is the bottom - most data word line or conductive layer.

[0115] Each NAND string includes memory holes 618 or 619 filled with material that forms memory cells adjacent to the word lines. For example, the region 622 of the stack is shown in more detail in Figure 6B

[0116] The stack is formed on a substrate 611. In one method, the well region 611a (see also Figure 3 ) is an n - type source diffusion layer or well in the substrate. The well region contacts the source extremities of each string of memory cells in the block. In one possible embodiment, the n - type well region 611a is in turn formed in a p - type well region 611b, which is in turn formed in an n - type well region 611c, which is in turn formed in a p - type semiconductor substrate 611d. In one method, the n - type source diffusion layer may be shared by all blocks in a plane and form a source line SL that provides voltage to the source extremities of each NAND string in the block.

[0117] The NAND string 700n has a source extremity 613 at the bottom 616b of the stack 610 and a drain extremity 615 at the top 616a of the stack. Metal - filled slits may be provided periodically across the stack as local interconnects extending through the stack, such as to connect the source line to a line above the stack. The slits may be used during the formation of the word lines and subsequently filled with metal. The vias may be connected to the drain extremity of the NAND string at one end and to the bit line at the other end.

[0118] In one method, a block of memory cells includes a stack of alternating control gates and dielectric layers, and the memory cells are arranged in vertically - extending memory holes in the stack.

[0119] In one method, each block includes a trapezoidal edge, where vertical interconnects are connected to each layer, including the SGS, WL, and SGD layers, and extend upward to a horizontal path of a voltage driver.

[0120] Figure 6B A close-up view of the stacked region 622 is shown. Figure 6A Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory holes. The SGD transistor 716 connected to SGD(0), the dummy memory cell 715 connected to WLDD, and the data memory cells 712 - 714 connected to WL93 - WL95 are depicted respectively.

[0121] Multiple layers can be deposited, for example, using atomic layer deposition along the sidewall (SW) of the memory hole 629 and / or within each word line layer. For example, each pillar 685 or column formed of the material within the memory hole may include a blocking oxide layer 663, a charge trapping layer 664 or film, such as silicon nitride (Si3N4) or other nitrides, a tunnel layer 665 (e.g., gate oxide), a channel 660 (e.g., including polysilicon), and a dielectric core 666 (e.g., including silicon dioxide). The word line layer may include a metal blocking layer 661 and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690 - 694 are provided. In this example, all layers except the metal are provided within the memory hole. In other methods, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars can form the columnar active regions (AA) of the NAND string.

[0122] Each NAND string or group of connected transistors includes a channel that continuously extends from a select gate transistor at one or more source extremes to a select gate transistor at one or more drain extremes. For example, channels 700a, 710a, 720a, and 730a continuously extend from the source extreme to the drain extreme of each NAND string in NAND strings 700n, 710n, 720n, and 730n respectively.

[0123] Each memory hole in the memory holes can be filled with multiple annular layers, which include a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each memory hole in the memory holes is filled with a bulk material, and the multiple annular layers are located between the core region and the word line in each memory hole in the memory holes.

[0124] The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate. In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0125] When programming a memory cell, electrons are stored in a portion of a charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and pass through the tunneling layer. The Vth of the memory cell increases proportionally with the amount of charge stored. During an erase operation, the electrons return to the channel.

[0126] While the above examples relate to 3D memory devices having vertically-extended NAND strings, the techniques provided herein are also applicable to 2D memory devices in which the NAND strings extend horizontally on a substrate. Both 2D and 3D NAND strings can have polysilicon channels with grain boundary traps. Moreover, these techniques can also be applied to memory devices having other channel materials.

[0127] Figure 7A Depicts a NAND string in block B0-0 Figure 4 and Figure 6A consistent with. An exemplary view of the NAND strings in the sub-blocks of the block. The NAND strings are arranged in a 3D configuration in the sub-blocks of the block. Each sub-block includes a plurality of NAND strings, and an example NAND string is depicted. For example, SB0, SB1, SB2, and SB3 respectively include example NAND strings 700n, 710n, 720n, and 730n. The NAND strings have data word lines, dummy word lines, and select gate lines Figure 6A consistent with. Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. The NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3 respectively. Programming of the block can be performed based on a word line programming order. One option is to program the memory cells in different word line portions located in different sub-blocks, one sub-block at a time, before programming the memory cells in the next word line. For example, this can involve programming WL0 in SB0, SB1, SB2, and SB2, then programming WL1 in SB0, SB1, SB2, and SB2, and so on. For example, the word line programming order can start from WL0 (source extreme word line) and end at WL95 (drain extreme word line).

[0128] The NAND strings 700n, 710n, 720n, and 730n respectively have channels 700a, 710a, 720a, and 730a. Additionally, the NAND string 700n includes an SGS transistor 701, a dummy memory cell 702, data memory cells 703 - 714, a dummy memory cell 715, and an SGD transistor 716. The NAND string 710n includes an SGS transistor 721, a dummy memory cell 722, data memory cells 723 - 734, a dummy memory cell 735, and an SGD transistor 736. The NAND string 720n includes an SGS transistor 741, a dummy memory cell 742, data memory cells 743 - 754, a dummy memory cell 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763 - 774, a dummy memory cell 775, and an SGD transistor 776.

[0129] This example depicts an SGD transistor at the drain end of each NAND string and an SGS transistor at the source end of each NAND string. In one method, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3) respectively. In another method, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0130] After erasing a memory cell block during an erase operation, programming can be performed, where the memory cells are programmed according to a word line programming order. For example, programming can start from the word lines on the source side of the block and proceed to the word lines on the drain side of the block, one word line at a time. For example, when there are four sub - blocks ( Figure 7A ), the word lines can also be programmed in a sub - block programming order extending from SB0 to SB3. For example, first, a part of the memory cells of WLn in SB0 is programmed, then a part of the memory cells of WLn in SB1, a part of the memory cells of WLn in SB2, and then a part of the memory cells of WLn in SB3 are programmed. WLn refers to the word line selected for programming. The programming operation can include one or more sets of increasing programming voltages or pulses, and this one or more sets of increasing programming voltages or pulses are applied to the word line during corresponding programming cycles (also known as programming - verification iterations), such as Figure 12A shown. A verification test can be performed after each programming voltage to determine whether the memory cell has been programmed. Programming is complete when the memory cell is in an assigned data state represented by a threshold voltage (Vth) distribution, such as Figure 11A or Figure 11B shown.

[0131] Figure 7B shows a memory cell of WL3 in sub-block SB0 connected to Figure 7A , having corresponding NAND strings, bit lines, and sense circuits. Figure 7A The memory cell 706 and the channel 700a of the NAND string 700n in SB0 of Figure 2 are shown together with the corresponding bit line BL0. SB0 also includes memory cells 706a, 706b, and 706c in NAND strings 701n, 702n, and 703n respectively, the memory cells having channels 700b, 700c, and 700d respectively and connected to bit lines BL1, BL2, and BL3 respectively. Bit lines BL0 - BL3 are connected to

[0132] the sense circuits 60 - 63 of

[0133] Figure 7C shows Figure 7A and Figure 7B an exemplary view of the NAND string 700n of

[0134] which shows the overdrive voltage of the channel 700a during a read operation, where WLn = WL3 is the selected word line. The programming word lines 797 on the source side of WL3 include WL0 - WL2, the programming word lines 796 on the drain side of WL3 include WL4 - WL6, where WL6 is the last programmed word line, and the unprogrammed word lines 795 of the block include WL7 - WL95. The source side of a word line is the side facing the source end of the NAND string, and the drain side of a word line is the side facing the drain end of the NAND string.

[0135] During a read operation, the channel of each unselected memory cell will have an applied read pass voltage (Vread) such that the memory cell has an overdrive based on Vread - Vth, where Vth is the threshold voltage of the memory cell. The overdrive is high enough to cause channel inversion, which provides unselected memory cells in a strongly conductive state such that a selected memory cell can be sensed without interference from unselected memory cells in the NAND string. However, the Vth of the memory cells will vary such that the overdrive varies. Specifically, erased memory cells of an unprogrammed word line will have a relatively high overdrive compared to programmed memory cells. Thus, the current in the NAND string can be higher than the optimal current, resulting in increased current consumption during the sense operation. Another issue is that due to the programming order discussed in conjunction with Figure 8D the number of unprogrammed word lines can be different in different blocks of a meta block.

[0136] Figure 8A Illustrated are different processes that can be performed by a control circuit in conjunction with a read operation to reduce current consumption. The control circuit can include on-chip circuitry such as control circuit 110 and / or off-chip circuitry such as Figure 1A the controller 122 in. Different processes include detecting a power-on event 800, receiving a multi-plane read command 801, determining whether a block is fully programmed 802, identifying the last programmed word line in a block that is not fully programmed 803, determining whether the last programmed word lines in the corresponding blocks of the multi-plane read command are equal 804, performing a multi-plane read command with a common baseline read pass voltage for the unprogrammed word lines of the corresponding blocks 805, performing a multi-plane read command with different read pass voltages for the unprogrammed word lines of the corresponding blocks 806, performing one or more alternative read operations 807 (e.g., single-plane read operation or independent read operation), performing a prefetch read operation 808, and programming a block 809. In Figure 8B and Figure 8C examples of processes 800 - 808 are discussed, and process 809 is discussed in an example of Figure 8D Illustrated is an exemplary read process consistent with

[0137] Figure 8B Figure 8A Figure 8A Step 810 includes powering on the memory device. Typically, a power-on event is detected by the control circuit. Step 811 includes receiving a multi-plane read command that identifies a corresponding block in a corresponding plane. For example, the read command can be issued by a host 140. When using multi-level cells, the read command can identify the same selected word line and the same page type (e.g., lower, middle, or upper) in each block of the corresponding block.

[0138] Step 812 includes determining whether each of the identified corresponding blocks is fully programmed. In one approach, the control circuit accesses a table such as Figure 8E for this determination. The table can be stored in a non-volatile location such that it is retained after the memory device is powered off and then powered on again. In one embodiment, the L2P table is stored in the Figure 1A memory structure 126. Decision step 813 determines whether each block identified in the read command is fully programmed. If decision step 813 is true, then step 814 performs a multi-plane read command at the same read pass voltage (Vread_P) on the unprogrammed word lines of each corresponding block identified in the read command.

[0139] If decision step 813 is false, then step 815 identifies the last programmed word line in each corresponding block identified in the read command. For example, a binary search process can be performed, which can include, for example, reading the word line at the middle between the first and last word lines of the block to determine which half of the block contains the last programmed word line. For example, if the middle word line is programmed, then this means that the last programmed word line is between the middle word line and the last word line of the block. The block is then further divided to determine which 1 / 4, 1 / 8, 1 / 16, etc. of the block contains the last programmed word line until the last programmed word line is identified. Another technique is to start from the edge word lines of the block and read each word line one by one until the transition between the programmed word line and the unprogrammed word line is detected. The identity of the last programmed word line can be stored in the Figure 8E table. In one embodiment, the information of the last programmed word line is stored in the Figure 1A volatile memory 122b. When a sudden power-off event occurs, the information is lost.

[0140] Step 816 determines whether the last programmed word lines in the block are equal. For example, in Figure 7C , WL6 is the last programmed word line. Then, step 816 will determine whether WL6 is the last programmed word line in each block identified in the read command. Figure 8E The table of Figure 9A can be used for this purpose. At decision step 817, if the last programmed word lines are equal, then step 818 performs a multi-plane read command with an equally reduced baseline read pass voltage, such as Vread_UP_base (lower than Vread_P of step 814), on the unprogrammed word lines of each corresponding block identified in the read command. See Figure 9A .

[0141] If decision step 817 is false, then the last programmed word lines in each corresponding block identified in the read command are not equal. See Figures 9B - 9DThree options are shown. In the first option, step 819 includes performing a multi-plane read operation on the unprogrammed word lines of one or more fewer programmed blocks with a lower reduced read pass voltage, such as Vread_UP_L1, Vread_UP_L2, and Vread_UP_L3 (lower than Vread_UP_base of step 818), compared to the unprogrammed word lines of one or more more programmed blocks. The fewer programmed blocks are those whose last programmed word line is closer to its first programmed word line compared to the distance from the last programmed word line to the first programmed word line in the more programmed blocks. The method of step 819 may increase the complexity of the chip but allows for faster verification of the memory device.

[0142] In the second option, step 820 includes performing a single-plane read operation on one or more more programmed blocks without reading one or more fewer programmed blocks. Current consumption is reduced when one or more fewer programmed blocks are inactive while one or more more programmed blocks are being read. Potentially, each block identified in the read operation can be read sequentially in the single-plane read operation.

[0143] In the third option, step 821 includes performing an independent read operation on the corresponding blocks.

[0144] Figure 8C Another exemplary read process is shown in accordance with Figure 8A Step 830 includes powering on the memory device. Step 831 includes scanning a lookup table, such as Figure 8E , to determine whether all blocks in the table are fully programmed. This occurs before a read command identifies a specific block. Decision step 832 determines whether the block is fully programmed. If decision step 832 is true, then step 833 instructs the control circuit to enter the standby mode and wait for a read command from the host. If decision step 832 is false, then step 834 identifies the blocks in the lookup table that are not fully programmed. Step 835 identifies the last programmed word line in each block that is not fully programmed and stores the corresponding data in a table, such as Figure 8E . Step 836 involves performing a multi-plane prefetch operation based on the data that includes equal last programmed word lines.

[0145] The prefetch operation is performed to prepare for a read command, and the prefetch operation may include instructions or data that the control circuit may need in response to the read command. The prefetch operation may involve retrieving data from a slower memory to a faster memory. For example, the slower memory may be a solid-state drive that includes non-volatile storage unit blocks, such as those in Figure 4 , while the faster memory may be a volatile memory such as RAM. See, for example, RAM 122b in Figure 1A .

[0146] Figure 8D Another is shown in accordance withFigure 8A Exemplary programming operations consistent with step 809. When the corresponding blocks are arranged in a meta-block, programming may involve WL0 in each corresponding block in sequence, WL1 in each corresponding block in sequence, and so on. Depending on the amount of data to be programmed, when the corresponding blocks are programmed unequally, the programming operation may end, as Figures 9B to 9D shown. Some blocks will be more programmed blocks, while other blocks will be less programmed blocks. As discussed, this can result in increased current consumption. Alternatively, when the corresponding blocks are programmed equally, the programming operation may end, as Figure 9A shown.

[0147] Step 840 starts a programming operation for the corresponding blocks in the corresponding plane. Step 841 sets the word line index n = 0 to represent the first word line in each block. Step 842 selects WL(n) to be programmed. Step 843 sets the plane index i = 0 to represent the first plane P0. Step 844 selects the plane (i) to be programmed. Step 845 programs WL(n) in the corresponding blocks of the plane in plane (i). If decision step 846 indicates that there is a next plane to be programmed, then step 848 increments the plane index i, and step 845 programs the same word line in the next plane. If decision step 846 indicates that there is no next plane to be programmed, then decision step 847 determines whether there is a next word line (WL) to be programmed. If decision step 847 is true, then step 849 increments the WL index n, and step 842 selects the next word line. If decision step 847 is false, then step 850 indicates that the programming operation is complete.

[0148] Figure 8E Illustrates an exemplary table 119 maintained by Figures 8A to 8D for use in conjunction with Figure 1A RAM 122b. As described above, this table may store data indicating whether a block is fully programmed. The data may be obtained and stored for all blocks or for selected blocks identified by a read command before receiving the read command. The table may also store data identifying the last programmed word line. In some cases, information about whether a block is fully programmed is stored in non-volatile memory such that it is available when the chip is powered on, while the identification of the last programmed block is stored in volatile memory such that it is lost after a power cycle and must be determined again.

[0149] In an exemplary embodiment, the table includes a first column that identifies blocks consistent with Figure 4 e.g., B0-0 to B0-n-1, B1-0 to B1-n-1, B2-0 to B2-n-1, and B3-0 to B3-n-1. The second column may include bits indicating whether the block is fully programmed, e.g., 0 for no and 1 for yes. The third column may identify the last programmed word line. In this example, consistent with Figure 4The meta-block consistent B0-0, B1-0, B2-0, and B3-0 have last programmed word lines or boundary word lines respectively called WLb(P0), WLb(P1), WLb(P2), and WLb(P3).

[0150] In one method, the control circuit is configured to perform multiple programming cycles, where each programming cycle programs one word line in each corresponding block in a programming order such that the last programmed word line of one or more less programmed blocks is one word line away in the programming order from the last programmed word line of one or more more programmed blocks.

[0151] See also Figures 9A to 9D , which respectively show the word lines WL0(P0)-WL95(P0), WL0(P1)-WL95(P1), WL0(P2)-WL95(P2), and WL0(P3)-WL95(P3) of blocks B0-0, B1-01, B2-0, and B3-0. For example, each word line in the block is marked, starting from WL0 and ending at WL95. Additionally, the boundary word line or last programmed word line is shown as WLb. In some cases, one or more adjacent word lines near the boundary word line are also shown. The long dashed boxes indicate blocks having the same read-through voltage for unprogrammed word lines. Additionally, in this example, the selected word lines WLn(P0)-WLn(P3) are programmed word lines other than the last programmed word line in the corresponding block.

[0152] For word lines, the dashed boxes represent unprogrammed word lines, while the solid boxes represent programmed word lines. WLn is the selected word line being read and receives the control gate read voltage Vcgr. In this example, its adjacent word lines WLn-1 and WLn+1 receive an elevated read-through voltage VreadK. The remaining programmed word lines receive Vread_P (P represents programmed). The unprogrammed word lines receive a version of Vread_UP (UP represents unprogrammed). In Figure 10A and Figure 10B the relative values of the voltages can be seen in the example. In one method, VreadK > Vread_P > Vread_UP_base > Vread_UP_L1 > Vread_UP_L2 > Vread_UP_L3 > Vcgr.

[0153] Figure 9AShows a first exemplary configuration of corresponding block groups B0-0 to B0-3, where the blocks have the same boundary word lines and a common read pass voltage Vread_UP_base is applied to the unprogrammed word lines. In block group 900, the boundary word lines WLb(P0)-WLb(P3) are all in the same relative position within their blocks. A programming word line group 901 on the source side of WLn and a programming word line group 902 on the drain side of WLn are applied with Vread_P. A baseline read pass voltage Vread_UP_base is applied to a group of unprogrammed word lines 903. Vread_UP_base is Figures 9A to 9D the highest Vread voltage of the unprogrammed word lines in

[0154] Figure 9B Shows a second exemplary configuration of corresponding block groups B0-0 to B0-3, where block B0-0 has a boundary word line WLb(P0) that is respectively higher than the boundary word lines WLb(P1)-WLb(P3) of blocks B1-0 to B3-0, and a lower read pass voltage Vread_UP_L1 is applied to the unprogrammed word lines of B1-0 to B3-0. Specifically, WLb(P0) is a word line other than WLb(P1)-WLb(P3). That is, compared with the distance between WLb(P1)-WLb(P3) and WL95, WLb(P0) is a word line closer to the last word line WL95. This is due to Figure 8D the programming technique of

[0155] as discussed. Vread_UP_L1 is lower than Vread_UP_base. Specifically, Vread_P is applied to the programming word line groups 901a and 902a in a group of blocks 911 including B1-0 to B3-0. Vread_UP_L1 is applied to a group of unprogrammed word lines 903a in block group 911. Vread_P is applied to the programming word line groups 901b and 904(910) in B0-0. Vread_UP_base is applied to a group of unprogrammed word lines 905 in B0-0. In this example, B0-0 is a more programmed block, while B1-0 to B3-0 are less programmed blocks.

[0156] Figure 9C Shows a third exemplary configuration of corresponding block groups B0-0 to B0-3, where blocks B0-0 and B1-0 respectively have boundary word lines WLb(P0) and WLb(P1) that are higher than the boundary word lines WLb(P2) and WLb(P3) of blocks B2-0 and B3-0, and a lower read pass voltage Vread_UP_L2 is applied to the unprogrammed word lines of B2-0 and B3-0. Vread_UP_L2 is lower than Vread_L1.

[0157] Specifically, Vread_P is applied to the programmed word line groups 901c and 902b in a set of blocks 921 including B2-0 and B3-0. Vread_UP_L2 is applied to a set of unprogrammed word lines 903b in the block group 921. Vread_P is applied to the programmed word line groups 901d and 904a in a set of blocks 920 including B0-0 and B1-0. Vread_UP_base is applied to a set of unprogrammed word lines 905a in the block group 920. In this example, B0-0 and B1-0 are more programmed blocks, while B2-0 and B3-0 are less programmed blocks.

[0158] Figure 9D A fourth exemplary configuration of the respective block groups B0-0 to B0-3 is shown, where blocks B0-0 to B2-0 each have a boundary word line WLb(P0)-WLb(P2) higher than the boundary word line WLb(P3) of block B3-0, and a lower read pass voltage Vread_UP_L3 is applied to the unprogrammed word lines of B3-0. Vread_UP_L3 is lower than Vread_L2.

[0159] Specifically, Vread_P is applied to the programmed word line groups 901e and 902c in block B3-0. Vread_UP_L3 is applied to a set of unprogrammed word lines 903c in the block group 931 including B3-0. Vread_P is applied to the programmed word line groups 901f and 904b in a set of blocks 930 including B0-0 to B2-0. Vread_UP_base is applied to a set of unprogrammed word lines 905b in the block group 930. In this example, B0-0 to B2-0 are more programmed blocks, and B3-0 is a less programmed block.

[0160] Figure 10A Shows a graph of the read pass voltage of the unprogrammed word lines as a function of the number of Figures 9A to 9D less programmed blocks in accordance with, where the read pass voltage is lower when the number of less programmed blocks is larger. In Figures 9A to 9D , the number of less programmed blocks is 0-3 respectively. For the less programmed blocks, the read pass voltage of the unprogrammed word lines can be reduced to offset the otherwise increased current consumption. As mentioned, reducing the read pass voltage reduces the overdrive and thus also reduces the current. The read pass voltage is still high enough to provide the associated unselected memory cells in a conductive state, thereby allowing the sensing of the selected memory cells.

[0161] Figure 10AIndicates that when the number of less programmed blocks is relatively high, the lower read pass voltages (Vread_UP_L1, Vread_UP_L2, or Vread_UP_L3) are relatively low. Also shown are the relative magnitudes of Vread_UP_base, Vread_P, and VreadK.

[0162] Figure 10B Shows a graph of the read pass voltage of an unprogrammed word line as a function of the WLn position Figures 9A to 9D consistent with, where the read pass voltage is higher when the WLn position is closer to the last programmed word line. When the WLn position is closer to the last programmed word line, the number of unprogrammed word lines present is relatively small. Thus, the need to reduce the overdrive voltage is reduced, allowing the read pass voltage to be larger. Vread_UP_base, Vread_UP_L1, Vread_UP_L2, and Vread_UP_L3 can each increase as the WLn position gets closer to the last word line.

[0163] When the WLn position is relatively close to the first word line, the number of unprogrammed word lines is relatively high. Thus, Figure 10B Indicates that when the number of unprogrammed word lines of less programmed blocks is relatively high, the lower read pass voltage is relatively low. Additionally, when the number of unprogrammed word lines of the corresponding block is relatively high, the baseline read pass voltage Vread_UP_base is relatively low.

[0164] Figure 11A Shows an exemplary Vth distribution of a set of memory cells having one bit per cell and two data states. In Figure 11A and Figure 11B the vertical axis depicts the number of memory cells on a logarithmic scale, while the horizontal axis depicts the Vth of the memory cells on a linear scale. The techniques provided herein can be used for single-layer cells and multi-layer cells.

[0165] Each memory cell can be associated with a data state according to the write data in a program command. Based on the data state of the memory cell, the memory cell will remain in an erased (Er) state or be programmed to a programmed data state. For example, in a one-bit-per-cell memory device, there are two data states, including an erased state and a programmed state. In a two-bits-per-cell memory device, there are four data states, including an erased state and three programmed data states, which are referred to as A data state, B data state, and C data state. In a three-bits-per-cell memory device, there are eight data states, including an erased state and seven programmed data states, which are referred to as A data state, B data state, C data state, D data state, E data state, F data state, and G data state. In a four-bits-per-cell memory device, there are sixteen data states, including an erased state S0 and fifteen data states S1 - S15. Each data state can be represented by a series of threshold voltages (Vth) in the memory cell.

[0166] After programming the memory cell, the data can be read back in a read operation. The read operation can involve applying a series of read voltages to the word line while the sense circuit determines whether the cells connected to the word line are in a conductive state (on) or a non-conductive state (off). If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level that is expected to be between the threshold voltage levels of adjacent data states. Additionally, during the read operation, the voltage of the unselected word lines ramps up to a read-through level or a conductive level, which is high enough to place the unselected memory cells in a strongly conductive state to avoid interfering with the sensing of the selected memory cells. The word line being programmed or read is referred to as the selected word line WLn.

[0167] In a one-bit-per-cell programming operation, the memory cell remains in an erased (Er) state as represented by the Vth distribution 1100, or is programmed to a programmed state (P) as represented by the Vth distribution 1101. Programming can use a verify voltage Vv and one or more programming pulses. The Vth distribution 1100 of the Er state can be obtained in an erase operation using the verify voltage VvEr. The control gate read voltage VrSLC can be used to read the memory cell after programming is completed. See also Figure 14D .

[0168] Figure 11BShows an exemplary Vth distribution of a set of memory cells having three bits per cell and eight data states. In one method, at the start of a programming operation, the memory cells are initially all in the erased (Er) state, as shown by Vth distribution 1100. After a programming operation is successfully completed, the memory cells assigned to the A-G states are represented by Vth distributions 1101-1107, which have associated verification voltages VvA-VvG respectively. Read voltages VrA-VrG can be used to read the state of the memory cells during a read operation.

[0169] In an erase operation, the data memory cells transition from the Vth distribution of the programmed data state (e.g., states A-G) to the erased state. The erase operation includes an erase phase in which the memory cells are biased for erasure, followed by an erase-verify test. The erase-verify test can use an erase verification voltage VvEr applied to the word line.

[0170] In this eight-state example, the Er-G states are examples of the assigned data states, and the A-G states are examples of the programmed data states.

[0171] For multi-level and single-level memory cells, a multi-plane read operation is typically performed, unless the device enters an abnormal mode due to a high error rate. In this case, a single-plane read operation can be used. In some cases, a partially programmed block can be closed after some time by moving its data to another block. This is especially true for blocks in multi-level cells and helps manage these blocks. For single-level cells designed to provide high access rates, keeping some cells in the erased state helps reduce the latency during write operations.

[0172] Figure 12A Shows the Figure 8D and Figure 11B exemplary voltage signals used in a programming operation in accordance with. The voltage signal 1200 includes a set of programming pulses applied to the word line selected for programming, which includes an initial programming pulse 1201. The initial programming pulse has a voltage Vpgm_init, and dVpgm represents the step between consecutive programming pulses. For example, a single programming pass with fifteen programming cycles is used. As the programming operation progresses, the verification signals in each programming cycle (including the exemplary verification signal 1202) can include lower assigned data states, then intermediate assigned data states, and then higher assigned data states, as Figure 12B shown. Also see the Figure 13 signals for details of the programming cycle, for example.

[0173] The example verification signal depicts three verification voltages for simplicity. During the programming cycle, after applying a programming pulse to the selected word line, the verification signal is applied to the selected word line. The memory cells are sensed during the application of the verification signal in the verification test to determine their programming progress. The verification signal includes one or more voltages for determining whether the memory cells have been programmed to the assigned data state. The result of sensing Vth relative to the verification voltage can be used to inhibit further programming of the memory cells.

[0174] The data to be programmed or read can be arranged in pages. For example, in the case of two bits per cell, two pages of data can be stored in the memory cells connected to the word line. The data of the lower page and the upper page can be determined by reading the memory cells using read voltages VrA and VrC; and VrB, respectively.

[0175] In the case of three bits per cell, three pages of data can be stored in the memory cells connected to the word line. The data of the lower page, the middle page, and the upper page can be determined by reading the memory cells using read voltages VrA and VrE; VrB; and VrC and VrG, respectively. See also Figures 14A to 14C .

[0176] Figure 12B Illustrates in Figure 12A Examples of verification voltages used in different programming cycles. The horizontal bars are time-aligned with the programming cycle axis of Figure 12A . These bars overlap in some programming cycles, so that verification operations can be performed on multiple data states in the programming cycle. In the case of eight data states, the bars indicate that the verification voltages for states A, B, C, D, E, F, and G are applied to programming cycles 1 - 4, 3 - 6, 5 - 8, 7 - 10, 9 - 12, 11 - 14, and 12 - 15, respectively.

[0177] In one method, the programming cycle in which the verification test is performed is predetermined before the programming operation. In another method, the programming cycle in which the verification test is performed is adaptively determined as the programming progresses. For example, the B-state verification test can start in the next programming cycle after a specified portion of the A-state memory cells have passed their verification test.

[0178] Figure 13 Illustrates in relation to Figure 12AExemplary voltage signals consistent for performing programming operations. The vertical dimension represents voltage, and the horizontal dimension represents time, where the time points are t0 - t12. The depicted time period corresponds to a programming cycle and includes a pre - charge phase 1307 (t0 - t2), a programming phase 1308 (t2 - t8), and a verification phase 1309 (t9 - t12). Voltage signals 1300, 1310, 1320, 1330, and 1340 represent VWLn, VWL_unsel, Vsg, Vbl, and Vsl respectively.

[0179] During the pre - charge phase, VWLn and VWL_unsel can be set to a pre - charge voltage, e.g., 1V - 2V.

[0180] For the bit lines of unselected NAND strings, the program - inhibit voltage signal (curve 1331) ramps up from 0V to 2V, e.g., at t0, to provide a small amount of channel boost during the pre - charge phase and to inhibit programming during the programming phase. For the bit lines of selected NAND strings, a fixed voltage such as 0V (curve 1332) is applied to avoid channel boost during the pre - charge phase and to allow programming during the programming phase. The program - enable voltage signal of 0V is shown by curve 1342.

[0181] At this time, the SGD transistors of the selected and unselected sub - blocks are in a conductive state, e.g., with a voltage Vsg = 6V. This allows the bit - line voltage to be transferred to the channel. At this time, the SGS transistors of the selected and unselected sub - blocks can also be in a conductive state, with a voltage of 6V, e.g., to allow Vsl = 1V to be transferred to the source extreme of the channel.

[0182] Vsgd is set to 6V to transfer the bit - line voltage to the drain extreme of the NAND string. During the programming phase, VWLn and Vwl_unsel ramp up, e.g., starting from t3, to provide capacitive coupling of the channel of the inhibited NAND string. Then, at t5, VWLn further ramps up to the peak program - pulse level of Vpgm (curve 1301) and remains at Vpgm until t4. After the application of the program pulse, the word - line voltage ramps down during the recovery process. During the program pulse, Vsgd of the selected sub - block, Vsgd_sel (curve 1321) is high enough to provide a conductive selected SGD transistor for the selected NAND string receiving Vbl_sel = 0V, but low enough to provide a non - conductive selected SGD transistor for the inhibited NAND string receiving Vbl_unsel = 2V. Vsgd of the unselected sub - block, Vsgd_unsel (curve 1322) can be set to 0V to provide a non - conductive corresponding SGD transistor.

[0183] Subsequently, in the verification phase, one or more verification tests are performed by applying a verification signal (curve 1302) having one or more verification voltages on WLn and sensing the conductive state of the memory cells in the selected NAND strings of the selected sub-blocks for each verification voltage. The SGD and SGS transistors are in a strongly conductive state to allow sensing of the selected memory cells. During the verification test, Vbl_sense = 0.5V is applied to the bit lines.

[0184] The voltages shown are examples.

[0185] Figure 14A Shows voltages consistent with Figures 8A to 8C and Figure 11B exemplary voltage signals (curves 1400 to 1404) for performing a read operation on intermediate page data. Voltage signal 1400 shows Vcgr, i.e., the voltage applied to the selected word line WLn. The voltage increases to VrB, VrD, and VrF. Sensing is performed during each value of Vcgr to determine the data of the intermediate page. Vread represents the read pass voltage applied to the unselected word lines. Vread can have different magnitudes as described above. Vsgd represents the SGD voltage and is set at a high level to provide an SGD transistor in a conductive state. Vbl represents the bit line voltage and is set to a level such as 0.5V as part of the sensing process. Vsl represents the source line voltage and can be set to a small positive voltage in one method.

[0186] Figure 14B Shows voltages consistent with Figures 8A to 8C and Figure 11B exemplary voltage signals for performing a read operation on lower page data. Curve 1410 shows Vcgr increasing to VrA and VrE. Sensing is performed during each value of Vcgr to determine the data of the lower page. In Figures 14B to 14D the values of Vread, Vsgd, Vbl, and Vsl can be similar to those in Figure 14A .

[0187] Figure 14C Shows voltages consistent with Figures 8A to 8C and Figure 11B exemplary voltage signals for performing a read operation on upper page data. Curve 1420 shows Vcgr increasing to VrC and VrG. Sensing is performed during each value of Vcgr to determine the data of the upper page.

[0188] Figure 14D Shows voltages consistent with Figures 8A to 8C and Figure 11A exemplary voltage signals for performing a read operation on a single page of data. Curve 1430 indicates that Vcgr increases to VrSLC, at which point sensing is performed to determine the data of the single page.

[0189] Thus, it can be seen that in a specific implementation, a device includes: a plurality of planes disposed on one or more die; a plurality of memory cell blocks disposed in the plurality of planes, the plurality of blocks including corresponding blocks disposed in each plane, each corresponding block including a set of memory cells connected to a set of word lines, the set of word lines in each corresponding block including programmed word lines and unprogrammed word lines; and control circuitry. The control circuitry is configured to: receive a read command identifying a selected word line of each corresponding block, and in response to the read command, identify the last programmed word line of each corresponding block and determine whether the last programmed word lines of each corresponding block are equal; if the last programmed word lines of each corresponding block are equal, read the selected word line of the corresponding block by applying a control gate read voltage to the selected word line and applying an identical baseline read through voltage to the unprogrammed word lines of each corresponding block; and if the last programmed word lines of each corresponding block are not equal, identify one or more less programmed blocks and one or more more programmed blocks in the corresponding block based on the last programmed word lines of the corresponding block, and read the selected word line of the corresponding block by applying a control gate read voltage to the selected word line while applying a lower read through voltage that is lower than the identical baseline read through voltage to the unprogrammed word lines of the one or more less programmed blocks.

[0190] In another specific implementation, a method includes: receiving a multi-plane read command that identifies a selected word line of a corresponding block in each of a plurality of planes, each corresponding block including a set of memory cells connected to a set of word lines, the set of word lines in each corresponding block including programmed word lines and unprogrammed word lines; in response to the multi-plane read command, identifying the last programmed word line of each corresponding block and determining whether the last programmed word lines of each corresponding block are equal; if the last programmed word lines of each corresponding block are equal, execute the multi-plane read command by simultaneously reading the selected word lines of the corresponding blocks in each plane; and if the last programmed word lines of each corresponding block are not equal, perform one or more alternative read operations to supersede the multi-plane read command.

[0191] In another specific implementation, a device includes: a plurality of planes in which a plurality of memory cell blocks are disposed, each block including a set of memory cells connected to a set of word lines; a look-up table that stores data indicating whether each corresponding block is fully programmed; and control circuitry. The control circuitry is configured to access the look-up table in response to a power-on event to identify blocks that are not fully programmed, identify the last programmed word line of each block that is not fully programmed, and store data identifying the last programmed word line.

[0192] The above specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the particular purposes contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A management device, the device comprising: A plurality of planes (P0 - P3) disposed on one or more die (108); A plurality of blocks (B0 - 0 to B0 - n - 1, B1 - 0 to B1 - n - 1, B2 - 0 to B2 - n - 1, B3 - 0 to B3 - n - 1) of memory cells (703 - 714, 723 - 734, 743 - 754, 763 - 774) disposed in the plurality of planes, the plurality of blocks including corresponding blocks disposed in each plane, each corresponding block including a set of memory cells connected to a set of word lines (WL0 - WL95), the set of word lines in each corresponding block including programmed word lines and unprogrammed word lines; And Control circuitry (110, 122), the control circuitry being configured to: Receive a read command identifying a selected word line (WLn) of each corresponding block, and in response to the read command, identify the last programmed word line of each corresponding block and determine whether the last programmed word lines of each corresponding block are equal; If the last programmed word lines of each corresponding block are equal, read the selected word line of the corresponding block by applying a control gate read voltage (Vcgr) to the selected word line and applying the same baseline read - through voltage (Vread_UP_base) to the unprogrammed word lines of each corresponding block; And If the last programmed word lines of each corresponding block are not equal, identify one or more less - programmed blocks and one or more more - programmed blocks in the corresponding block based on the last programmed word lines of the corresponding block, and read the selected word line of the corresponding block by applying a control gate read voltage to the selected word line while applying a lower read - through voltage (Vread_UP_L1, Vread_UP_L2, Vread_UP_L3) lower than the same baseline read - through voltage to the unprogrammed word lines of the one or more less - programmed blocks.

2. The device according to claim 1, wherein: When the number of the less - programmed blocks is relatively high, the lower read - through voltage is relatively low.

3. The device according to claim 1 or 2, wherein: When the number of the unprogrammed word lines of the less - programmed blocks is relatively high, the lower read - through voltage is relatively low.

4. The device according to claim 1 or 2, wherein: When the number of the unprogrammed word lines of the corresponding block is relatively high, the same baseline read - through voltage is relatively low.

5. The device according to claim 1 or 2, wherein: The control circuitry is configured to perform a plurality of programming cycles, each programming cycle programming one word line in each corresponding block in a programming order such that the last programmed word line of the one or more less - programmed blocks is one word line away from the last programmed word line of the one or more more - programmed blocks in the programming order.

6. The device according to claim 1 or 2, wherein: The selected word line is a programmed word line other than the last programmed word line in the corresponding block.

7. The apparatus according to claim 1 or 2, further comprising: a temperature sensing circuit (116) configured to provide a temperature indication, wherein when the temperature is relatively high, the lower read is at a relatively low voltage.

8. The apparatus according to claim 1 or 2, wherein: the read command identifies the same selected word line and the same page type in each of the corresponding blocks.

9. A management method, the method comprising: receiving a multi-plane read command that identifies selected word lines of corresponding blocks (B0-0 to B0-n-1, B1-0 to B1-n-1, B2-0 to B2-n-1, B3-0 to B3-n-1) in each of a plurality of planes (P0-P3), each corresponding block including a set of memory cells (703-714, 723-734, 743-754, 763-774) connected to a set of word lines (WL0-WL95), the set of word lines in each corresponding block including programmed word lines and unprogrammed word lines; in response to the multi-plane read command, identifying the last programmed word line of each corresponding block and determining whether the last programmed word lines of each corresponding block are equal; if the last programmed word lines of each corresponding block are equal, performing the multi-plane read command by simultaneously reading the selected word lines of the corresponding blocks in each plane; and if the last programmed word lines of each corresponding block are not equal, performing one or more alternative read operations to replace the multi-plane read command.

10. The method according to claim 9, wherein: performing the one or more alternative read operations includes identifying a less programmed block of the corresponding block and a more programmed block of the corresponding block based on the last programmed word line of the corresponding block; and performing a single-plane read of the more programmed block without simultaneously reading the less programmed block.

11. The method according to claim 10, further comprising: performing a plurality of programming cycles, each programming cycle programming one word line in each corresponding block in a programming order such that the last programmed word line of the less programmed block is one word line away from the last programmed word line of the more programmed block in the programming order.

12. The method according to any one of claims 9 to 11, wherein: the multi-plane read command simultaneously reads the same selected word lines of the corresponding blocks in each plane and the same page type among a plurality of page types.

13. The method according to any one of claims 9 to 11, wherein: performing the one or more alternative read operations includes identifying a less programmed block of the corresponding block and a more programmed block of the corresponding block based on the last programmed word line of the corresponding block; and performing independent read operations on the more programmed block and the less programmed block.

14. The method according to claim 13, wherein: the independent read operations are independent in that the selected word line when reading the more programmed block is different from the selected word line when reading the less programmed block.

15. The method according to claim 13, wherein: The independent read operation is independent because the page type when reading the more programmed blocks is different from the page type when reading the less programmed blocks.

16. A management device, the device comprising: A plurality of planes, a plurality of memory cell blocks are arranged in the plurality of planes, and each block includes a group of memory cells connected to a group of word lines; And A control circuit, the control circuit includes a look-up table configured to store data indicating whether each corresponding block is fully programmed, and the control circuit is configured to access the look-up table in response to a power-on event to identify blocks that are not fully programmed, identify the last programmed word line of each block that is not fully programmed, and store data identifying the last programmed word line; The control circuit is configured to receive a multi-plane read command, and in response to the multi-plane read command, identify corresponding blocks in each plane, and access the data identifying the last programmed word line to determine whether the last programmed word lines of each corresponding block are equal; The control circuit is configured to, if the last programmed word lines of each corresponding block are equal, execute the multi-plane read command by simultaneously reading the selected word lines of each corresponding block, and if the last programmed word lines of each corresponding block are not equal, perform one or more alternative read operations.

17. The device according to claim 16, wherein: The control circuit is configured to perform a multi-plane prefetch operation on corresponding blocks in corresponding planes of a plurality of planes so that the data identifying the last programmed word line indicates that the last programmed word lines of each corresponding block are equal.

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