Active low power termination

Abstract

An active termination circuit includes an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line provides a signal to the input node. The first transistor is a diode connected between a high voltage source and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is a diode connected between the input node and a low voltage source. The second transistor terminates the signal when the signal is at a high logic level.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Application No. 17 / 187,308, filed February 26, 2021, which claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 065,103, filed August 13, 2020, both of which are incorporated herein by reference. Background Technology

[0003] Strong growth in demand for portable consumer electronics has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, are widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, along with their high reliability and large capacity, make these memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones, and solid-state drives.

[0004] Semiconductor memory devices are typically formed from SiP (System-in-Package) devices, which consist of multiple memory dies mounted in an offset stack on a substrate. The semiconductor dies are electrically coupled to each other and to the substrate using wire bonds attached to each die, cascading down the die stack. The demand for high performance and low power consumption is increasing. Wire bonds and other electronic packages inherently possess parasitic capacitance. Although parasitic capacitance levels have been decreasing, this reduction has not kept pace with the ever-growing bandwidth requirements for faster data throughput rates. Today, this bandwidth limitation is constrained by parasitic capacitance. A typical solution reverts to using lower impedance receiver terminations, but this lower termination impedance increases power consumption when using passive resistive terminations. Wire bonds and other electronic packages can benefit from solutions that use lower receiver termination impedances without significantly increasing power consumption.

[0005] Some such solutions employ active termination circuitry to implement feedback loops and active bias, current mirrors, and additional current sources. These features can occupy more area than can be used in die termination. Therefore, a solution is needed that provides the benefits of active termination while occupying as little space as possible within the integrated circuit. Summary of the Invention

[0006] This disclosure relates to an active termination circuit including an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line is configured to provide a signal to the input node. The first transistor is a diode connected between a high-voltage source and the input node. The first transistor is configured to terminate the signal when the signal is at a low logic level. The second transistor is a diode connected between the input node and the low-voltage source. The second transistor is configured to terminate the signal when the signal is at a high logic level.

[0007] A "high voltage source" refers to a source of voltage level used to operate a circuit during normal operation. In some embodiments, a high voltage source may be represented by the symbols Vdd or Vccq. A "low voltage source" refers to a structure, connection, or component used as ground or for grounding electrical signals. In some embodiments, a low voltage source may be represented by the symbols G, GND, Vss, or an inverted triangle.

[0008] A "high logic level" refers to one of two possible logic levels used to represent binary data and / or binary signals. Typically, a high logic level represents the binary value "1". A "low logic level" refers to one of two possible logic levels used to represent binary data and / or binary signals. Typically, a low logic level represents the binary value "0".

[0009] This disclosure also relates to a system comprising a first integrated circuit and a second integrated circuit mounted on a printed circuit board, interconnects, and an active termination circuit. The interconnects are configured to operate as transmission lines for transmitting signals between the first and second integrated circuits. The active termination circuit is formed within the first or second integrated circuit and includes the features described above for the active termination circuit disclosed herein.

[0010] Finally, this disclosure relates to a method for calibrating an active termination circuit, the active termination circuit comprising: an NMOS transistor diode connected between a high-voltage source and an input node, and a PMOS transistor diode connected between the input node and a low-voltage source. First, a target input impedance range (Rin) of the active termination circuit is received. The input impedance is measured as the input current (Ln) applied to the input node transitions between high and low logic levels. Then, it is determined whether the measured input impedance falls within the target input impedance range. Finally, in response to the input impedance falling outside the target input impedance range, the strength of one of the NMOS and PMOS transistors is calibrated. Attached Figure Description

[0011] Components with similar numbers refer to common parts in different drawings.

[0012] Figure 1 This is a schematic diagram of an integrated circuit or semiconductor die that includes multiple die bonding pads.

[0013] Figure 2 This is a schematic diagram of a memory package consisting of four memory dies with an onboard memory controller.

[0014] Figure 3 This is a schematic diagram of a memory package attached to a printed circuit board with an external memory controller.

[0015] Figure 4 The contents of the terminal circuit on the integrated circuit are shown.

[0016] Figure 5 An example of a passive terminal circuit according to the prior art is shown.

[0017] Figure 6A Is Figure 5 A graph of the voltage applied at the input of the passive terminal circuit, and Figure 6B and Figure 6C It shows the response to Figure 6A By applying voltage Figure 5 The current of the component.

[0018] Figure 7 An implementation scheme for an active low-power termination circuit is shown.

[0019] Figure 8A , Figure 8B and Figure 8C They are shown respectively Figure 7 The implementation scheme of the active termination circuit behaves for low logic, transition, and high logic input levels.

[0020] Figure 9A Is Figure 7 A graph of the voltage applied at the input of the active terminal circuit, and Figure 9B and Figure 9C It shows the response to Figure 9A The applied voltage causes the current to flow through Figure 7 The current of the component.

[0021] Figure 10A Another implementation of an active low-power termination circuit is shown.

[0022] Figure 10B One aspect of the subject matter is shown according to one implementation scheme.

[0023] Figure 10C One aspect of the subject matter is shown according to one implementation scheme.

[0024] Figure 11 It was shown as Figure 7 The desired behavior of the input node resistance as a function of the input current of an active terminal circuit.

[0025] Figure 12 It shows the use of multiple devices to change Figure 7 The effective width of the device in the implementation scheme.

[0026] Figure 13 A routine 1300 for calibrating an active termination circuit according to one embodiment is shown.

[0027] Figure 14 and Figure 15 consider Figure 7 The operation of an active terminal circuit responds to changes in the circuit and the changes in its components. Detailed Implementation

[0028] The present technology will now be described with reference to the accompanying drawings. In embodiments, the present technology relates to terminating circuitry for transmission lines, such as bonding wires for connecting memory dies of memory devices or other integrated circuits that use such interconnects to exchange signals.

[0029] A "transmission line" is a specialized cable or other structure designed to conduct alternating current or oscillating signals or voltages at radio frequencies (approximately 20 kHz to 300 GHz) or higher. The frequency is high enough to account for the fluctuating nature of the signal. Transmission lines are used for purposes such as connecting radio transmitters and receivers and their antennas (these are called feeders or feed lines), distributing cable television signals, routing calls between telephone exchange centers, connecting computer networks, and high-speed computer data buses. (Search "transmission line" and "radio frequency" on Wikipedia.com, modified May 28, 2020, accessed June 4, 2020).

[0030] A “signal” is an electrical signal (wired or wireless) transmitted from one component, circuit, driver, device, manager, or controller to another component, circuit, subcircuit, driver, device, manager, or controller. In one embodiment, the signal includes an analog signal. In another embodiment, the signal includes a digital signal. In some embodiments, the signal is configured to oscillate between high states (e.g., high voltage level, high logic level) and low states (e.g., low voltage level, low logic level). The signal may oscillate based on data values ​​transmitted along with the signal.

[0031] Signals can originate from signal sources. A “signal source” refers to a circuit, subcircuit, electronic component, hardware, software, firmware, module, logic, device, or apparatus that is configured, programmed, designed, arranged, or engineered to provide analog or digital waveforms of voltage, current, or time-varying electromagnetic waves to another structure, circuit, subcircuit, electronic component, logic, device, or apparatus.

[0032] As discussed above in the background section, lower resistance termination increases the power used. The following discussion focuses on using CMOS active devices to create termination for digital signals. Active circuitry uses multi-mode impedance during logic low to logic high and logic high to logic low transitions. The three primary modes will have higher receiver impedance in low or high modes, but during logic transitions (L to H or H to L), the receiver impedance will be low for bandwidth improvements and improved transmission line termination. In some implementations, the impedance value can be programmed via a calibration step as well as temperature compensation. This novel low-power termination architecture is an active low-power termination (ALPTib) with inherent bias.

[0033] Impedance is a measure of the resistance a circuit provides to a current when a voltage is applied.

[0034] In terms of quantity, the impedance of a two-terminal circuit element is the ratio of the complex representation of the sinusoidal voltage across its terminals to the complex representation of the current flowing through the circuit. Typically, impedance depends on the frequency of the sinusoidal voltage and its associated parasitic capacitance. (Search "impedance" on Wikipedia.com, modified May 31, 2020, accessed June 2, 2020).

[0035] "Bias" refers to a direct current (DC) current or voltage supplied to one or more terminals of an active electronic component (such as a diode or transistor) that is configured to ensure proper operation of the active electronic component.

[0036] In electronics, bias typically refers to a fixed DC voltage or current applied to the terminals of electronic components (such as diodes and transistors) in a circuit, where an AC signal is also present to establish appropriate operating conditions for the components. (Search "bias" on Wikipedia.com, modified June 28, 2020, accessed July 15, 2020). In some implementations, the AC signal may include a data signal on a transmission line.

[0037] "Electronic component" refers to any fundamental discrete device or physical entity in an electronic system that influences electrons or their associated fields. ("Electronic component" on Wikipedia, April 18, 2020, accessed May 15, 2020).

[0038] Electronic components can be passive or active. Active electronic components include transistors, diodes, integrated circuits, power supplies, etc. Passive electronic components include resistors, capacitors, and inductors, etc. ("Electronic components" from Wikipedia, April 18, 2020, modified, accessed June 16, 2020).

[0039] Traditional active termination circuit designs offer multiple components to manage bias, and these components can be scaled up to the silicon area required to implement these solutions.

[0040] In some implementations, an active termination circuit includes a pair of transistors connected in series, each transistor being diode-connected, and its control gate being suitably connected to a high-voltage source or a low-voltage source. Active termination circuits are suitable for use with junction lines carrying relatively high voltage levels (i.e., on the order of 1 volt or higher) of digital signals between integrated circuits. Dynamic termination impedance can be provided using the inherent bias of the (ALPTib) architecture. "Inherent bias" refers to a bias present within a circuit or sub-circuit due to the design and configuration of the circuit and / or its coupling with a high-voltage source (e.g., VDD) and a low-voltage source (e.g., ground). In other words, the inherent bias is provided by the circuit itself to the terminals of one or more active electronic components of the circuit. "Dynamic termination impedance" refers to the termination impedance expressed in ohms that changes over time as a signal on the transmission line changes from a low logic level to a high logic level, and vice versa.

[0041] Circuits such as those disclosed in the embodiments can utilize this inherent bias, and therefore occupy less space and draw less power, and are thus more practical for certain integrated circuit designs. In exemplary applications, various embodiments of the disclosed circuits can be configured or calibrated for operation during the die sorting stage of manufacturing. Furthermore, calibration of the disclosed embodiments may include adjustments for the temperature effects and electrical characteristics of the PMOS transistors used in embodiments implementing the disclosed solution.

[0042] Figure 1 This is a schematic diagram of a unified memory die 102 or semiconductor die including multiple die bonding pads 104, through which the unified memory die 102 can be connected to other components, such as other integrated circuits or printed circuit boards, by means of transmission lines or leads.

[0043] "Unified memory die" refers to a memory die that includes the same or substantially the same components, electronic components, circuitry, features, size, configuration, and / or capabilities as another memory die. "Pad" refers to a conductive structure used to connect traces and wire connections or pins for electrical connections.

[0044] "Wire bonding" refers to wires, typically made of aluminum, aluminum alloys, copper, silver, gold, or gold-doped wires, used for interconnecting integrated circuits, communication buses, and / or communication channels.

[0045] An "integrated circuit" refers to one or more electronic circuits, which include one or more electronic components entirely contained within a single semiconductor structure.

[0046] A “printed circuit board” or “PCB” refers to a structure that uses conductive tracks, traces, pads, and other features to mechanically support and electrically connect electrical or electronic components. These conductive tracks, traces, pads, and other features are etched from one or more copper layers laminated on and / or between layers of non-conductive substrate. Components can be soldered onto a PCB to electrically connect and mechanically secure them to the PCB. PCBs can be single-sided (one copper layer), double-sided (two copper layers on each side of a substrate), or multi-layered (outer and inner copper layers alternating with the substrate layers). Multi-layered PCBs allow for higher component density because circuit traces on the inner layers free up surface space between components. Multi-layered PCBs can include two, three, four, or more copper planes (layers for traces). (Search “printed circuit board” on Wikipedia.com, modified May 22, 2020, accessed June 4, 2020).

[0047] For example, the unified memory die 102 can be a memory die, such as 2D NAND flash memory or 3D BiCS (bit cost scaling), V-NAND, or other 3D flash memory, but other types of dies or integrated circuits can be used. These other types of semiconductor dies include, but are not limited to, controller dies (such as ASICs) or RAM (such as SDRAM, DDR SDRAM, LPDDR, and GDDR).

[0048] The unified memory die 102 or integrated circuit may include a plurality of die bonding pads 104 along the edge of the semiconductor die. Multiple dies may be combined into a package. Each die bonding pad may be referred to herein as a channel, wherein for the remainder of the die bonding pads 104 on the integrated circuit or unified memory die 102, a first die bonding pad on each die is arbitrarily referred to herein as a first channel, a second die bonding pad on each die is arbitrarily referred to herein as a second channel, and so on. In the embodiments explained below, on the die bonding pads 104 of the integrated circuit or unified memory die 102, each bonding pad in the first channel die bonding pads on the packaged die may be interconnected with each other and may be connected to a printed circuit board (PCB) or other substrate, each second channel die bonding pad on the die may be interconnected with each other and connected to a substrate, etc.

[0049] Figure 2 and Figure 3 An embodiment of multiple memory dies combined into a package is shown, wherein die bonding pads of the dies in the package are connected by a set of wire connections serving as transmission lines between the memory dies. One or more packaged memory dies may be combined with a memory controller to form a memory system, wherein the wire connections interconnecting these elements serve as a system bus.

[0050] Figure 2 This is a schematic diagram of a memory package 200 containing four unified memory dies 102 (such as a 3D NAND memory structure) located on a printed circuit board 212. The unified memory dies 102 are stacked one on top of the other, slightly offset to expose die bonding pads 104 along the edges of the unified memory dies 102, such that these pads can be connected to wire bonds 204. For simplicity, a single bonding pad connected by a single wire bond channel is shown for each unified memory die 102; however, in embodiments where there may be several (e.g., eight) such bus lines or channels, they can form a system bus.

[0051] The stack of unified memory dies 102 is attached to a printed circuit board 212, which includes bonding pads 206. Figure 2 In one embodiment, the memory package 200 includes an onboard memory controller 202 (e.g., an ASIC). The memory controller 202 includes a set of bonding pads, one of which is shown as bonding pad 208, which is also connected along a transmission line 210 to bonding pad 206 on the board. The transmission line 210 typically includes a conductor portion of, for example, approximately 5 mm in length. Figure 2 The memory package 200 can be a memory card or one of multiple packages forming a solid-state drive (SSD).

[0052] Figure 3 This is a schematic diagram of an embodiment of memory system 300, in which multiple unified memory die packages 302 do not include onboard controllers, but one or more of these packages 302 are attached to a printed circuit board 314, which includes an external memory controller 304 (e.g., an ASIC) connected to one or more memory packages 302. The memory packages 302 and... Figure 2 The memory package 200 is similarly formed, but may not include an onboard controller on the package board 306. Wire bonds 204 are again connected to bonding pads 206 on the package board 306, but instead of connecting to the onboard controller ASIC, they connect transmission lines 310 (typically about 50 to 100 mm long) on ​​the package board 306 to vias 308 or other connections to form part of the transmission lines 310, which are formed on the printed circuit board 314 and connected to bonding pads 312 of the memory controller 304. In one embodiment, the memory controller 304 is an external controller that is not formed as part of the memory package 302, but rather on the printed circuit board 314. Although in Figure 3A single memory package 302 is shown, but a memory system may include multiple such packages 302 connected to a single printed circuit board 314. The printed circuit board 314 to which one or more memory packages are attached may be part of a solid-state drive (SSD), for example, which may include many such PCBs as sub-components. Other additional integrated circuits and other components may be incorporated into the memory package 200, package 302, included on the printed circuit board 314, or in each of these components.

[0053] Wire bond 204 forms a transmission line connecting different integrated circuits (unified memory die 102, memory controller 202, and memory controller 304), printed circuit board 212, and package board 306, and printed circuit board 314 terminates or ends at the bonding pad. Electrical termination is the practice of ending transmission lines with a device that matches the characteristic impedance of the transmission line, whether it is the wire bond 204 used to connect other integrated circuits or electrical components or the transmission line (e.g., transmission line 210 and transmission line 310).

[0054] "Electrical termination," "termination," or "signal termination" refers to the practice of terminating a transmission line using a device that matches the characteristic impedance of the line. This is to prevent signal reflection at the end of the transmission line. Reflections from unterminated transmission lines can cause distortion, which can result in fuzzy digital signal levels and malfunctions in digital systems. (Search "electrical termination" on Wikipedia.com, modified July 23, 2018, accessed June 5, 2020).

[0055] There are two types of electrical terminations: passive or resistive terminations and active terminations. A passive electrical termination is a circuit that includes passive electrical components (such as a resistor or a group of resistors connected in parallel). An active electrical termination is a circuit that includes active electrical components (such as a transistor or a group of transistors configured to perform an electrical termination on an input signal).

[0056] A transistor is an electronic component configured to function as a signal amplifier or electronic switch. A transistor includes a gate terminal, a source terminal, a drain terminal, and a body terminal or a body terminal only.

[0057] A transistor may include discrete electronic or semiconductor components, or may include a structure or part of a structure or device embedded in an integrated circuit, semiconductor component, or semiconductor device. A transistor operating as a switch is configured such that its source terminal is electrically connected to a first electrical structure and its drain terminal is electrically connected to a second electrical structure.

[0058] In a switching configuration, the gate terminal of the transistor is connected to a control line. The transistor is activated by raising the voltage on the control line coupled to the gate terminal of the transistor to or above a threshold voltage, and deactivated by lowering the voltage on the control line below the threshold voltage. Activating the transistor via the control line is referred to herein as putting the transistor into the on state. The activation of the transistor forms a conductive path and / or causes the transistor to conduct current and / or allows voltage or bias to shift between the source and drain terminals.

[0059] Characteristic impedance refers to the ratio of the voltage to the current amplitude of a single signal wave propagating along a transmission line; that is, the wave propagating in one direction without reflection to the other. Characteristic impedance (usually written as Zo) is typically defined relative to a uniform transmission line. Alternatively, equivalently, when the transmission line is of infinite length, characteristic impedance can be defined as the input impedance of the transmission line. Characteristic impedance is determined by the geometry and material of the transmission line, and for a uniform transmission line, characteristic impedance does not depend on the length of the uniform transmission line. The SI unit for characteristic impedance is the ohm.

[0060] The characteristic impedance of a lossless transmission line is a purely real number with no reactive component. Energy supplied by a source at one end of such a line is transmitted through it without being dissipated in the line itself. A finite-length (lossless or lossy) transmission line terminating at one end with an impedance equal to its characteristic impedance appears to the source as an infinitely long transmission line and produces no reflections. (Search "characteristic impedance" on Wikipedia.com, modified May 17, 2020, accessed June 2, 2020). "Input impedance" refers to the impedance present at the input node when the circuit is active. An "input node" is a node in a circuit where an input signal is applied.

[0061] Termination is designed to prevent signals from reflecting off the ends of transmission lines. Reflections from unterminated transmission lines can cause distortion, resulting in blurred digital signal levels and malfunctions in digital systems. Reflections in analog signal systems can lead to video ghosting, power loss in radio transmitter transmission lines, or errors in data logic signals.

[0062] Signal termination typically involves including terminating circuitry at the beginning, middle, and / or end of a wire or cable to prevent signals from being reflected back from each end, thus preventing interference or power loss.

[0063] According to the implementation scheme, the terminal may be placed at the end of the transmission line or on various components connected along the communication bus, and is designed to match the AC impedance of the cable, thereby reducing signal reflection and power loss. In some implementation schemes, the terminal circuit may also be placed at the drive end of the wire or cable.

[0064] For example, in Figure 2 and Figure 3 In the illustrated implementation, each unified memory die 102 may include a terminal, or the terminal may be limited to the outermost memory die (e.g., Figure 2 or Figure 3 The stack shown is top uniform memory die 102. Since the memory dies of the device typically have the same design, termination circuitry can be included for each bonding pad of the memory die. In some embodiments, the termination circuitry may be active on the memory die when it is active. In other embodiments, termination on the memory die at the very end of the system bus may provide termination for any active memory die, while the termination circuitry for other memory dies is not active.

[0065] For many systems, passive resistor terminations are used, employing a combination of resistors or MOSFET switches for programmability. Their values ​​are programmed to match the characteristic impedance of the transmission line and are selected to have acceptablely low parasitic inductance and capacitance at system-dependent frequencies. Depending on the application, the signal on the terminated transmission line can be analog or digital. In many integrated circuit applications, the terminated analog signal is typically on the order of tens or hundreds of millivolts. For the primary implementations discussed herein (such as communication buses on non-volatile memory systems), the primary application may be digital signals with relatively large voltage levels (e.g., about 1.5V or more generally in the range of 1V to 5V or even higher) that extend between low and high logic levels.

[0066] A "logic level" refers to one of a finite number of states that a digital signal can occupy. While other standards exist, logic levels are typically represented by the voltage difference between the signal and ground. The range of voltage levels representing each state depends on the logic family used. In binary logic, the two levels are logic high (e.g., high logic level) and logic low (e.g., low logic level), which typically correspond to the binary digits 1 and 0, respectively. (Search "logic level" on Wikipedia.com, modified April 5, 2020, accessed July 15, 2020).

[0067] Figure 4 The diagram illustrates an integrated circuit including termination circuitry, such as a non-volatile memory circuit (e.g., a unified memory die 102). As described above, although the following discussion primarily pertains to integrated circuits of non-volatile memory systems, the techniques are readily applicable in a more general sense. More specifically, Figure 4An edge of the unified memory die 102 integrated circuit and one of its die bonding pads 104 are shown. The die bonding pad 104 is connected to an input driver 404 and an output driver 406. The input driver 404 is configured to supply signals received on the bonding pad to other internal components of the integrated circuit, and the output driver 406 is configured to supply signals from other internal components of the integrated circuit to the die bonding pad 104 and to wire connections (not shown) attached to the die bonding pad 104. In some embodiments, a termination circuit 402 may also be attached to the die bonding pad 104.

[0068] Figure 5 An example of a prior art passive termination is shown. The termination circuit is formed by a first resistor R1 502 and a second resistor R2 504. The first resistor R1 502 is connected between the high voltage source 508 level of Vdd and the input node 512, and the second resistor R2 504 is connected between the input node 512 and the low voltage source 510 level, which is considered to be ground here. To provide the input resistance Rin as seen at the input node 512, the resistance values ​​of R1 502 and R2 504 are each 2*Rin. For example, resistors R1 502 and R2 504 can be implemented as resistors or configured as MOSFETs. The resistance of the attached transmission line is denoted as Rst 506, where... Figure 2 or Figure 3 In an example of a memory package, this would correspond to the accumulated resistance (or “stacked resistance”) of the lead joints along the length of the die stack. Figure 5 The connection of Rst 506 (e.g., low voltage source 510) corresponding to a low logic state of ground is shown. Figure 5 In the middle, and in the subsequent Figure 7 , Figures 8A to 8C and Figure 10A In the diagram, the transmission line between the Rst source controller impedance and the Vin node is not shown. Figure 2 Transmission line 210, Figure 3 Transmission line 310).

[0069] In this type of passive termination circuit, low impedance Rin increases the bandwidth I / (2nRinC), where C is the parasitic capacitance of the signal input or the distributed input of the stacked dies. However, because resistors R1502 and R2504 are connected in series between the high voltage source 508 (Vdd) and the low voltage source 510 (ground), using low-resistance passive termination consumes high power, making it necessary to reduce the value of Rin to increase the current flowing in the termination circuit and the power consumption of semiconductor circuits such as memory dies. This can be referred to... Figures 6A to 6C To give an example.

[0070] Figure 6AIs Figure 5 The graph shows the voltage Vin_passive applied at the input of the passive terminal circuit as a function of time. In this example, the input voltage alternates between a high value of approximately 1.2V and a low value of just over 0.6V with a period of approximately 2ns. Figure 6B and Figure 6C The responses to each are shown respectively. Figure 6A The input waveform corresponds to the current fa1 through R1 501 and the current fa2 through R2 503.

[0071] like Figure 6B As shown, when the received input Vin_passive is high, the voltage at the node below R1 501 is high and fa1 is low; and when the received input Vin_passive is low, the voltage at the node below R1 501 is low and fa1 is high.

[0072] like Figure 6C As shown, when the received input Vin_passive is high, the voltage at the node above R2 503 is high, and fa2 is high; and when the received input Vin_passive is low, the voltage at the node above R2 503 is low, and fa2 is low. Therefore, fa1 is out of phase with Vin_passive for half a cycle, while fa2 is in phase. However, in both cases, the low values ​​of fa1 and fa2 are non-zero, resulting in a constant current flowing through R1 501 and R2 503. Figures 6A to 6C The graph is based on a specific set of period, resistance, and power supply level values, so the graph will vary depending on the different implementation values, but it is an illustrative example of general behavior.

[0073] To provide low-impedance receiver termination with lower power than resistive termination, this disclosure proposes an implementation scheme as a low-power termination architecture, namely, active low-power termination (ALPT). As described below, the ALPT architecture system is characterized by lower power / current consumption than passive resistive termination. It may also include programmable termination impedance.

[0074] "Termination impedance" refers to the impedance configured to terminate, reduce, or stop signal reflections on a transmission line. Termination impedance can be expressed in ohms and is also called terminating resistance, and can exist in the transmitter circuit of the sending signal and / or the receiver circuit of the receiving signal. In the case of discussing termination impedance in relation to the input signal entering the circuit, termination impedance can also be called input impedance.

[0075] Figure 7An active termination circuit 700 is shown, which is a first embodiment of an active low-power termination circuit. An "active termination circuit" refers to a circuit configured to provide electrical termination using active electronic components. Typically, an active termination circuit is coupled to a high-voltage source such as VDD or VCCQ and a low-voltage source such as ground. In some embodiments, the active termination circuit is formed within a common semiconductor die that includes other electronic components and circuitry for performing other functions. In such embodiments, the active termination circuit may be referred to as a die-on active termination circuit or a die-on active resistive circuit.

[0076] and Figure 5 In a neutral-terminal circuit, the input is received between a pair of passive resistors connected in series; in an active-terminal circuit, the input is received between a pair of active electronic components. Figure 7 In this circuit, input for termination is received at input node 702 between the first transistor T1 704 and the second transistor T2 708. The first transistor T1 704 is connected between the high voltage source 706 (Vdd) and input node 702, and the second transistor T2 708 is connected between input node 702 and low voltage source 710 (ground). Figure 7 In the embodiment shown, the first transistor T1 704 can be implemented as an NMOS transistor, and the second transistor T2 708 can be implemented as a PMOS transistor. Although the active low-power termination (ALPTib) with inherent bias described herein (such as regarding...) Figure 7 and Figure 10A The embodiments shown are primarily described in relation to their use on integrated circuits in non-volatile memory systems, but the technique can be applied to other bus lines that require low power and low impedance to achieve higher bandwidth.

[0077] An "NMOS transistor" or "n-channel MOS FET transistor" refers to a three-terminal active electronic component configured to operate as a transistor, and is an n-channel metal-oxide-semiconductor insulated-gate field-effect transistor. NMOS transistors operate in a complementary manner to PMOS transistors.

[0078] A "PMOS transistor" or "p-channel MOS FET transistor" refers to a three-terminal active electronic component configured to operate as a transistor, and is a metal-oxide-semiconductor insulated-gate field-effect transistor with a p-channel. PMOS transistors operate in a complementary manner to NMOS transistors.

[0079] Both the first transistor T1 704 and the second transistor T2 708 are diode-connected, with the control gate of the first transistor T1 704 connected to a high-voltage source 706 and the control gate of the second transistor T2 708 connected to a low-voltage source 710. The voltage level at input node 702 will vary depending on the signal on the terminated line. This helps to provide termination capabilities with several advantages when terminating lines carrying digital signals, as described below. Figures 8A to 8C , Figures 9A to 9C and Figure 11 Further description.

[0080] Figure 7 The termination circuit is a "bolt-in" implementation of an active termination circuit because it can be incorporated into existing circuit designs by being designed to operate with existing logic inputs and outputs. This allows the use of predefined logic masks (i.e., accepting existing voltage ranges). Figure 7 The design also has the advantage of enabling node attachment. See the following text about... Figures 8A to 8C and Figures 9A to 9C To be further described, Figure 7 The design can consume less power than passive terminal circuits and, as further described below, can be tuned and calibrated so that the CMOS size of the circuit will be balanced to match different logic states and processes.

[0081] The first transistor T1 704 and the second transistor T2 708 are connected in series between the high voltage source 706 (Vdd) and the low voltage source 710 (ground). Figure 7 The terminal circuit acts as a push-pull circuit relative to the input node 702. Push-pull circuits are commonly used for amplifier outputs. In bipolar designs, a push-pull circuit is an emitter follower. In CMOS designs, such as... Figure 7 As shown, the push-pull circuit is a source follower. In a source follower circuit, the impedance of the source follower is determined by the transconductance of the transistor. The transconductance of the source follower is determined by the device size and current, as well as other CMOS technology parameters that also help determine the transconductance (e.g., oxide thickness Tox). See below for further details. Figure 10A The discussion that followed Figure 7 and Figure 10A The termination circuitry can be calibrated to adjust for effective device size, thereby addressing variations in processing and the design impedance of transmission line 712. This transconductance facilitates the inherent bias current 718, which allows the solution to operate with lower power consumption than conventional solutions.

[0082] Figure 7 The terminal circuit utilizes this push-pull configuration as an input. For example... Figure 2 or Figure 3As shown, in order to be used in a memory system in which lead bonding is used as a communication bus between a unified memory die 102 and a memory controller 202 or memory controller 304, the terminated signal will be a digital signal with a low logic value (e.g., ground), a high logic value (e.g., Vdd), or a transition level between the two. Logic low, transition, and high will produce different operating conditions, and are respectively related to Figure 8A , Figure 8B and Figure 8C As shown.

[0083] In short, Figure 7 The active termination circuit 700 includes an input node 702 connected to a transmission line 712, which is configured to provide a signal to the input node 702. The active termination circuit 700 also includes a first transistor T1 704 diode connected between a high-voltage source 706 and the input node 702, configured to terminate the signal in response to a signal at a low logic level. The active termination circuit 700 also includes a second transistor T2 708 connected between the input node 702 and a low-voltage source 710, configured to terminate the signal in response to a signal at a high logic level.

[0084] In one embodiment, the active termination circuit 700 may have at least one of a first transistor T1 704 and a second transistor T2 708, which is calibrated to provide termination impedance to the signal on the transmission line 712 within a target input impedance range based on the temperature range in which the active termination circuit 700 is configured to operate. "Target input impedance range" refers to an impedance range from low to high values ​​within which the input impedance is expected, designed, or configured to remain within that range.

[0085] In one embodiment, the active termination circuit 700 may have a first transistor T1 704 including an NMOS transistor and a second transistor T2 708 including a PMOS transistor. In another embodiment, the first transistor T1 704 may include an NPN bipolar transistor, the second transistor T2 708 may include a PNP bipolar transistor, and the high voltage source 706 may be less than or equal to 1.4 volts.

[0086] An "NPN bipolar transistor" refers to a three-terminal bipolar transistor with a negatively doped emitter, a positively doped base, and a negatively doped collector. A "PNP bipolar transistor" refers to a three-terminal bipolar transistor with a positively doped emitter, a negatively doped base, and a positively doped collector.

[0087] exist Figure 8A , Figure 8B and Figure 8CIn each of them, the input push-pull elements NMOS transistor T1 802 and PMOS transistor T2 804 are from Figure 7 The termination circuitry is shown. The input node of the push-pull element is connected to a transmission line, such as by connecting the termination circuitry on the memory die to a lead of a line or channel of the communication bus of the controller 808. The source termination impedance of the controller is represented as resistor Rst 810.

[0088] Figure 8A The diagram illustrates the case where the input node is at a low logic level 806 when the signal from controller 808 is at a logic low value to ground. In this case, the input node of the termination circuit is therefore connected to ground via Rst 810. As shown, current 812 can primarily originate from Vdd through NMOS transistor T1 802, which operates in its saturation region 818, while PMOS transistor T2 804 is largely non-conductive, operating in its cutoff region 820.

[0089] The "saturation region" or "active region" refers to the state or operating mode of a transistor where current flows between the source and drain terminals. A MOSFET transistor in the saturation region has a gate voltage greater than its threshold voltage. In circuits where the transistor operates as a switch, it is considered "on" when in the saturation region.

[0090] The "cutoff region" or "subthreshold region" refers to the state or operating mode of a transistor where no current flows and no conduction occurs between the source and drain terminals. A MOSFET transistor in the cutoff region has a gate voltage equal to or less than its threshold voltage. In circuits where the transistor operates as a switch, it is considered "off" when in the cutoff region.

[0091] The inherent bias on the terminals of NMOS transistor T1 802 and PMOS transistor T2 804 (similar to the bias for...) Figure 7 The inherent bias 718 shown in the first transistor T1 704 and the second transistor T2 708 introduced in the diagram allows each transistor to operate alternately in the saturation region 818 and the cutoff region 820 as the signal transitions between low and high logic levels. The NMOS transistor T1 802 and the PMOS transistor T2 804 can be calibrated to provide a dynamic termination impedance to the signal on the transmission line over a target input impedance range, wherein the dynamic termination impedance changes as the signal transitions between low and high logic levels.

[0092] Figure 8BThe diagram illustrates the case where the input node transitions between logic states 814 when the signal from controller 808 changes from low to high or from high to low. In this case, the voltage level applied to the line is the intermediate value of Vdd / 2. The input node of the termination circuit is therefore connected to the level of Vdd / 2 via Rst 810. In this case, the voltage level from the terminated input line will be at or near the voltage level on the input node. Current in the termination circuit will flow through NMOS transistor T1 802 and PMOS transistor T2 804, both of which will operate in their saturation region 818.

[0093] Figure 8C The diagram illustrates the case where the input node is at a high logic level 816 when the signal from controller 808 is at a logic high value for Vdd. In this case, the input node of the termination circuit is therefore connected to Vdd via Rst 810. Current in the termination circuit will flow primarily from Vdd to ground through PMOS transistor T2 804, operating in its saturation region 818, and NMOS transistor T1 802 will be largely non-conductive, operating in its cutoff region 820.

[0094] Advantageously, in some embodiments, sufficient termination impedance, also known as dynamic termination impedance, is provided when the signal changes level between low and high logic levels. In one embodiment, in response to a signal with a low logic level, a first transistor, such as NMOS transistor T1 802, operates in the saturation region, and a second transistor, such as PMOS transistor T2 804, operates in the cutoff region. Similarly, in response to a signal with a high logic level, the second transistor (such as PMOS transistor T2 804) operates in the saturation region, and the first transistor (such as NMOS transistor T1 802) operates in the cutoff region.

[0095] In some implementations, in Figure 8B and Figure 8C as well as Figure 8A and Figure 8C Between the states shown, one of the transistors (e.g., NMOS transistor T1 802 and / or PMOS transistor T2 804) can transition from the saturation region 818 to the cutoff region 820, but may not fully enter the cutoff region. This state is referred to herein as the "partially off" state. One of the NMOS transistors T1 802 and / or PMOS transistor T2 804 in the "partially off" state can provide an increased terminating impedance to the input signal.

[0096] Figure 9A , Figure 9B and Figure 9C They are shown respectively in Figure 7The voltage applied at input node 702, and the current flowing in the first transistor T1 704 and the second transistor T2 708 in response. Therefore, Figure 9A , Figure 9B and Figure 9C It is used for Figure 5 passive terminal Figure 6A , Figure 6B and Figure 6C The active low-power terminal counterpart. More specifically, Figure 9A Is Figure 7 A graph showing the voltage Vin_active applied at the input of the active terminal circuit 700 as a function of time. In this example, as... Figure 6A As shown, the input voltage is at a high value of approximately 1.2V with a period of approximately 2ns (corresponding to...). Figure 8C ) and low values ​​just above 0.6V (corresponding to) Figure 8A Alternating between ) Figure 9B and Figure 9C The responses to each are shown respectively. Figure 9A The input waveform and the corresponding current I through the first transistor T1 704 T1 and the corresponding current I through the second transistor T2 708 T2 .

[0097] As shown in Figure 19B, when the received input Vin_active is high (corresponding to...) Figure 8C When the logic is high (in the high logic state), the voltage at input node 702 is high, and the current path is through Rst 810 to the second transistor T2 708 and then to ground, and I T1 It is low; and when the received input Vin_passive is low (corresponding to, for example) Figure 8A When the logic is low (in the low logic state), the voltage at input node 702 is low, and the current path is from Vdd through the first transistor T1 704 to Rst 810 and then to ground, and I T1 For high and I T2 It is low.

[0098] like Figure 9C As shown, when the received input Vin_active is high, the voltage at input node 702 is high, the second transistor T2 708 is turned on, and I... T2 The voltage is high; and when the received input Vin_passive is low, the voltage at input node 702 is low, the second transistor T2 708 is turned off, and I... T2 It is low. Therefore, compared with Figure 6B and Figure 6C fa1 and fa2 behave similarly, I T1 It is out of phase with Vin_active for half a cycle, while IT2 Same phase. However, with Figure 6B and Figure 6C The passive terminal shown is different, I T1 and I T2 Both have low current levels of zero or near zero, and high values ​​are shifted downwards by a corresponding amount. For example, by... Figure 6B and Figure 6C and Figure 9B and Figure 9C A comparison shows that I T1 and I T2 The combined current is reduced to approximately half of the combined current of fa1 and fa2, resulting in significant power savings. Figures 6A to 6C Same, Figures 9A to 9C The graphs are based on a specific set of period, resistance, and power supply level values, so the graphs will vary depending on the implementation values; however, both sets of graphs are based on the same set of assumptions and are comparable for the examples of relative power savings.

[0099] Figure 10A Implementation shown Figure 7 The system 1000a introduces an active termination circuit 700. System 1000a includes a first integrated circuit 1002 mounted on a printed circuit board 1004 and a second integrated circuit 1006 mounted on the same board. An interconnect 1008 is configured to operate as a transmission line for transmitting a signal 1020 between the first integrated circuit 1002 and the second integrated circuit 1006. An "interconnect" refers to a structure configured, designed, arranged, manufactured, or programmed to transmit signals between a transmitter and a receiver. The interconnect 1008 is connected to a bonding pad 1010, which is connected to a die bonding pad 1014 via a wire bond 1012.

[0100] The active termination circuit 700 formed within the first integrated circuit 1002 or the second integrated circuit 1006 or both may include an input node 702, such as Figure 7 The input node, as introduced herein, is configured to receive signal 1020 via interconnect 1008.

[0101] The active termination circuit 700 may also include a first transistor T1 704 and a second transistor T2 708 connected in series with a diode connection between the high voltage source and the low voltage source, as previously mentioned. Figure 7 As described. The first transistor T1 704 can be an NMOS transistor T1 802 (see...). Figure 8A The second transistor T2 708 can be a PMOS transistor T2 804 (see also...). Figure 8ANMOS transistor T1 802 can have its gate and drain terminals each connected to a high-voltage source and its source terminal connected to the input node 702, such that NMOS transistor T1 802 terminates signal 1020 in response to a signal 1020 at a low logic level. PMOS transistor T2 804 can have its gate and drain terminals each connected to a low-voltage source and its source terminal connected to the input node 702, such that PMOS transistor T2 804 terminates signal 1020 in response to a signal 1020 at a high logic level.

[0102] In one embodiment, the NMOS and PMOS transistors of the active termination circuit 700 can be calibrated to provide dynamic termination impedance to signals from interconnect 1008. The dynamic termination impedance can change as signal 1020 transitions between low and high logic levels. The NMOS and PMOS transistors may include inherent biases present when they alternate between saturation and cutoff regions.

[0103] System 1000a can be implemented using a first integrated circuit 1002, which includes a memory controller, such as, for example Figure 3 The memory controller 304 introduced herein, and the second integrated circuit 1006 may be a die, such as, for example, a unified memory die 102, including a non-volatile memory die controller 1016 and a non-volatile memory array 1018. "Non-volatile memory" refers to a type of storage or memory device, component, or apparatus that retains stored data when power is cut off or removed from the non-volatile memory. "Die controller" refers to a set of circuits, circuit systems, logic, or components configured to manage the operation of a die. In one embodiment, the die controller is an integrated circuit. In another embodiment, the die controller is a combination of discrete components. In yet another embodiment, the die controller is a combination of one or more integrated circuits and one or more discrete components. In other embodiments, the second integrated circuit 1006 may include similar volatile memory components, such as a volatile memory die controller and a volatile memory array. "Volatile memory" or "volatile memory medium" means any hardware, device, component, element, or circuit configured to retain variable physical properties for representing binary values ​​of zero or one, such that the variable physical properties will revert to a default state where they no longer represent binary values ​​when the primary power supply is removed or unless the binary value is refreshed using the primary power supply.

[0104] Examples of volatile memory media include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate random access memory (DDR RAM), or other random access solid-state memories. While volatile memory media are referred to herein as “memory media,” in various embodiments, volatile memory media may be more generally referred to as volatile memory. In some embodiments, data stored in volatile memory media is addressable at the byte level, meaning that data in the volatile memory media is organized as bytes (8 bits) of data, each byte having a unique address, such as a logical address.

[0105] System 1000a can also be implemented as system 1000b, which includes a stack of unified memory dies 102 coupled in series with each other via a set of lead bonding 204. A “unified memory die stack” refers to a group of two or more unified memory dies arranged in a stacked configuration relative to each other. In one embodiment, each member of the group of unified memory dies is disposed directly above or directly below another unified memory die or substrate.

[0106] In one implementation, each unified memory die in the stack is positioned relative to the other dies to form a ladder structure, wherein each unified memory die is one of the "steps" of the ladder.

[0107] Active termination circuits (e.g., active termination circuits 1024, 1026, 1028, and 1030) may reside within each unified memory die 102 of the stack. Temperature sensor 1032 may be configured to sense the temperature of one of the first integrated circuit 1002 and / or the second integrated circuit 1006, in this embodiment, the first and second integrated circuits may be one or more of the memory controller 304 and the unified memory die 102, respectively. "Temperature sensor" refers to a device, component, circuit, system, logic, chip, or circuitry configured to detect, sense, and / or measure the temperature of an object, apparatus, circuit, part, ambient air, etc. An example of a temperature sensor is a semiconductor-based temperature sensor that may be manufactured together with a semiconductor.

[0108] System 1000b may include a controller 1016 implemented as a non-volatile memory die ( Figure 10A The second integrated circuit 1006 (shown in the figure). In some embodiments, each unified memory die 102 may include a non-volatile memory die controller 1016 (shown in the figure). Figure 10B(Not shown in the image), when the unified memory die 102 communicates with the non-volatile memory storage controller 1022, the non-volatile memory die controller is used as a second integrated circuit 1006.

[0109] System 1000b may also include a first integrated circuit 1002 implemented as a non-volatile memory storage controller 1022, which is similar in many respects to memory controller 304. In other embodiments, the first integrated circuit 1002 may include similar volatile memory components, such as a volatile memory die controller or a volatile memory controller.

[0110] The non-volatile memory controller 1022 may store a set of calibration settings 1034 for one or more transistors in a first transistor T1 704 (e.g., in an embodiment where the first transistor T1 704 includes one or more programmably parallel-connected NMOS transistors) and a second transistor T2 708 (e.g., in an embodiment where the second transistor T2 708 includes one or more programmably parallel-connected PMOS transistors). "Memory controller" refers to any hardware, device, component, element, or circuitry configured to manage data operations on a non-volatile memory medium, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the memory controller is configured to store data on and / or read data from the non-volatile memory medium to transfer data to / from one or more non-volatile memory devices, etc.

[0111] "Calibration settings" refer to one or more of the following: settings, values, characteristics, parameters, attributes, etc., which are set to improve or optimize the performance, accuracy, and / or operation of a set of logic, circuits, software, hardware, firmware, systems, subsystems, devices, apparatuses, or logic units, components, equipment, or parts.

[0112] Calibration setting 1034 can calibrate, define, or determine, as needed, a set of NMOS transistors and / or a set of PMOS transistors, respectively used as the first transistor T1704 and the second transistor T2708. For example, as per [reference to...] Figure 12 In more detail, calibration setting 1034 can define which switches are off and / or which switches are on to define the number and type and / or organization of switches for a group of NMOS transistors and / or a group of PMOS transistors.

[0113] Active electronic components, such as transistors, can function differently at varying ambient temperatures. Therefore, in some embodiments, the non-volatile memory controller 1022 may change the calibration settings 1034 of the NMOS and PMOS transistors in response to a temperature sensor 1032 sensing a temperature below or above a temperature threshold. In one embodiment, the non-volatile memory controller 1022 may be configured to change the calibration settings 1034 for the set of PMOS transistors when the temperature sensed by the temperature sensor 1032 is greater than or equal to about 100°C and when the temperature is less than or equal to about -25°C.

[0114] Figure 10C A graph 1000c is provided showing the dynamic termination impedance 1040 (input impedance Rin) over a temperature range. Depending on the application, the NMOS calibration library 714 and / or the PMOS calibration library 716 may require predefined input impedances within a target input impedance range. Some applications may require a target input impedance range of ±15% 1036, while others may require a target input impedance range of ±10% 1038.

[0115] Figure 1000c illustrates the performance of an NMOS transistor between -40°C and 125°C, falling within both the ±15% target input impedance range 1036 and the ±10% target input impedance range 1038. Therefore, calibration settings are not required, and thus the NMOS calibration library 714 can include a single NMOS transistor. Figure 1000c also illustrates the performance of a PMOS transistor used to provide input impedance between -40°C and 125°C, which primarily remains within the ±15% target input impedance range 1036 at approximately -25°C to 95°C, but falls outside the ±10% target input impedance range 1038.

[0116] Therefore, calibration settings can be set for a group of switches connecting multiple PMOS transistors to the PMOS calibration library 716 for use as... Figure 7 The second transistor T2 708 is used. When the temperature sensor detects a temperature below approximately -25°C, the stored calibration settings can be used to recalibrate the PMOS calibration library 716. The non-volatile memory storage controller 1022 and / or the die controller can monitor the temperature and change the calibration settings as needed.

[0117] Figure 11 The previous actions were shown Figure 7 The desired behavior of the resistance Rin at the input node 702 is introduced by the current Iin at the input node 702 as a function of the active terminal circuit 700. The values ​​of Rin and Iin are related as Rin = d(Vin) / d(Iin). Figure 11The curve has three regions, corresponding to logic low (Iin > 0.005mV), logic high (Iin < -0.005mV), and the transition region in between. In digital signals, when the signal is in a high logic state or a low logic state, the signal is in a stable value (“stable state”), and Rin is matched to the controller source terminal (i.e., Figures 8A to 8C The impedance of the transmission line (Rst 810) is not critical; however, during conversion, it is desirable for Rin to match the line resistance as closely as possible to improve bandwidth. This is in Figure 11 As shown, the Rin curve is flat across the central logic state transition range, but curves upwards in the logic low and logic high regions. This differs from the case when using analog signals, where the Rin value is flat across the entire signal range. To account for process variations during the formation of the termination circuit and to set Rin to a target value, the termination circuit can be trimmed.

[0118] Calibration can be achieved by adjusting the values ​​of one or more of the first transistor T1 704 and / or NMOS calibration library 714, and the second transistor T2 708 and / or PMOS calibration library 716. Figure 7 Active termination circuits. For example, such as Figure 12 As shown, the effective width of PMOS transistor T2 804 can be changed by selectively connecting multiple PMOS transistors in parallel.

[0119] Figure 12 A PMOS calibration library 716 is shown, which may include a PMOS transistor T2 804 and / or an alternative to the previously discussed PMOS transistor T2 804. Although not shown, Figure 7 The NMOS calibration library 714 can be arranged similarly, replacing the PMOS transistors shown with NMOS transistors. This configuration allows for calibration based on... Figure 10B The calibration settings introduced herein configure the strength of the implemented transistors by setting various switches to the open or closed state. "Strength" refers to the impedance level of a transistor or group of transistors connected in parallel in an active termination circuit.

[0120] As illustrated herein, the PMOS calibration library 716 can be implemented as multiple devices that can be connected in parallel between the IN node and ground, wherein a set of switches 1208 are located at the gate terminal 1204 of the parallel devices, and the source terminal 1202 is directly connected to IN and the drain terminal 1206 is directly connected to ground. "Gate terminal" refers to the terminal of a transistor that serves as the control terminal of the transistor. Typically, depending on the type of transistor and the technology used to implement the transistor, changes in current or voltage or other bias applied to the gate terminal cause the transistor to enter or switch to the saturation region, cutoff region, or active region.

[0121] A "source terminal" refers to a terminal of a transistor that serves as a source of charge carriers (holes or electrons), depending on the type of transistor and the technology used to implement it. A "drain terminal" refers to a terminal of a transistor that serves as a drain or sink for charge carriers (holes or electrons), depending on the type of transistor and the technology used to implement it.

[0122] The effective width of the PMOS transistor T2 804 is the combined width of those devices in a parallel connection whose gates are connected to node G. During calibration, the effective width of the PMOS transistor T2 804 is set by the devices in the parallel connection whose gates are connected to node G by their switches being in the closed state and whose gates are kept unconnected by their switches being in the open state. "Closed state" refers to a switching state in which current flows between the two terminals of the switch. The switch is considered closed. "Open state" refers to a switching state in which no current flows between the two terminals of the switch. The switch is considered open. Calibration settings can define which switches are open or which are closed, or a combination of these two states for that group of switches.

[0123] In one embodiment, each PMOS transistor in the PMOS calibration library 716 may have the same or common type, size, shape, and configuration. In another embodiment, PMOS transistors of different types, sizes, shapes, and / or configurations may include the PMOS calibration library 716.

[0124] A similar arrangement can be used to calibrate the effective width of the NMOS transistor T1 802. Similar alternating positions for the switches in parallel devices can be located at the drain, with the source and gate directly connected. Methods of implementing a single functional transistor using multiple physical transistors connected in parallel are well known in the art. This illustration is intended to provide an example and not to limit the scope of the solutions disclosed herein to any particular method or configuration.

[0125] Figure 13 Routine 1300 according to one embodiment is shown. Routine 1300 may begin at block 1302 with the target input impedance range (Rin) of the active termination circuit. The active termination circuit may include, for example... Figure 7 The diodes introduced in the first transistor T1 704 and the second transistor T2 708 are connected, or as... Figure 8A The NMOS transistor T1 802 and PMOS transistor T2 804 introduced in the process.

[0126] In block 1304, an input current (Iin) can be applied to the input node of the active termination circuit. In block 1306, this input node can be switched between high and low logic levels. In this way, the input impedance of the active termination circuit can be measured during the switching (block 1308). If it is determined in decision block 1310 that the measured input impedance falls within the target input impedance range, then routine 1300 can end.

[0127] If it is determined in decision block 1310 that the measured input impedance does not fall within the target input impedance range, calibration of the strength of one of the NMOS and PMOS transistors can begin at block 1312. If it is determined in decision block 1314 that the calibration settings need to be changed, routine 1300 can proceed to block 1316. In block 1316, one or more additional transistors from a set of transistors can be connected in parallel to adjust the NMOS or PMOS transistor.

[0128] If it is determined in decision block 1314 that the transistor strength is not adjusted by changing the calibration settings, routine 1300 may proceed to block 1318. In block 1318, the strength of the NMOS or PMOS transistor can be adjusted based on the operating temperature range. After blocks 1316 and 1318, the process loops back to block 1304 to jitter the input current for the configuration of the NMOS and / or PMOS transistors, and the input impedance response is checked again in block 1308.

[0129] Used for repair Figure 7 One embodiment of the calibration process for the active termination circuit 700. In some embodiments, the PMOS transistor T2 804 may be calibrated first. In other embodiments, as further discussed below, the effective width of the NMOS transistor T1 802 may also be calibrated. Figure 13 In the process, the parameters of the NMOS transistor T1 802 can be formed by... Figure 7 The circuit is produced by technological processes. Figure 13 The process can begin at step block 1302, where the parameters of the NMOS transistor T1 802 are set by processing and receiving the target Rin value. Then, Figure 13 The process can change the strength of the PMOS transistor T2 804. The strength of the PMOS transistor T2 804 can be changed by connecting and disconnecting it. Figure 12 The device shown is used to make changes.

[0130] The processes in boxes 1304, 1306, and 1308 can be found by referring to... Figure 14 To illustrate, Figure 14 Showing different PMOS intensities Figure 7 The Iin behavior of the active terminal circuit 700 to Rin. Figure 14 Different lines can correspond to access and disconnection, for example... Figure 12 The different configurations of the NMOS transistor T1 802 shown exhibit different flatness at the Iin value. (See above regarding...) Figure 11 In digital signal applications, what is desired is flatness in the region near Iin = 0 corresponding to logic transitions. For Figure 11 The value range in the range means that the configuration of a single device provides the flattest curve between -0.005mV and 0.005mA, where behavior outside this range (corresponding to high and low logic states) is less important.

[0131] The processes in boxes 1304, 1306, and 1308 can be found by referring to... Figure 15 To illustrate, Figure 15 Showing different PMOS intensities Figure 7 The Iin behavior of the active terminal circuit 700 to Rin. Figure 15 Different lines can correspond to access and disconnection. Figure 12 Different devices. Different intensities of the PMOS transistor T2 804 exhibit different flatness at the Iin value. As mentioned above regarding... Figure 11 In digital signal applications, what is desired is flatness in the region near Iin = 0 corresponding to logic transitions. For Figure 11 The range of values ​​in the range means that Figure 12 The configuration of a single device provides the flattest curve between -0.005mV and 0.005mA, where behavior outside this range (corresponding to high and low logic states) is less important.

[0132] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0133] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is mentioned as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the two elements. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0134] For the purposes of this document, the terms “top” and “bottom,” “upper” and “lower,” and “vertical” and “horizontal,” and their forms, as used herein, are used herein by way of example and for illustrative purposes, and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms “substantially” and / or “about” mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, an acceptable manufacturing tolerance is ±2.5% of a given dimension. Embodiments of this technology will now be explained with reference to the following figures.

[0135] For the purposes of this document, the term "based on" may be understood as "at least partially based on". "Logic" refers to machine memory circuitry, non-transitory machine-readable media, and / or circuitry through which the material and / or material energy configuration includes control and / or program signals and / or settings and values ​​(such as resistance, impedance, capacitance, inductance, current / voltage levels, etc.), which can be applied to affect the operation of a device. Magnetic media, electronic circuitry, electrical and optical memory (volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software itself (however, it does not exclude machine memory that includes software and thus forms the configuration of things).

[0136] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0137] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0138] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An active termination circuit, the active termination circuit comprising: An input node, the input node being connected to a transmission line, the transmission line being configured to provide a signal to the input node; A first transistor diode is connected between a high-voltage source and the input node. The first transistor is configured to terminate the signal in response to the signal being at a low logic level, wherein a first control gate of the first transistor is connected to the high-voltage source. A second transistor diode is connected between the input node and the low-voltage source. The second transistor is configured to terminate the signal in response to the signal being at a high logic level, wherein the second control gate of the second transistor is connected to the low-voltage source. In this embodiment, at least one of the first transistor and the second transistor is calibrated to provide a termination impedance to the signal on the transmission line within a target input impedance range, based on the temperature range in which the active termination circuit is configured to operate.

2. The active termination circuit according to claim 1, further comprising inherent biases on the terminals of the first transistor and the second transistor, such that each transistor alternately operates in a saturation region and a cutoff region when the signal transitions between the high logic level and the low logic level.

3. The active terminal circuit according to claim 1, wherein, The first transistor and the second transistor are calibrated to provide dynamic termination impedance to the signal on the transmission line within a target input impedance range, wherein the dynamic termination impedance changes as the signal transitions between the low logic level and the high logic level.

4. The active terminal circuit according to claim 1, wherein, The first transistor includes an NMOS transistor, and the second transistor includes a PMOS transistor.

5. The active termination circuit of claim 4, wherein the PMOS transistor comprises a set of PMOS transistors configured to be coupled in parallel with the input node and the low voltage source based on a calibration setting, the calibration setting determining which PMOS transistors in the set are coupled in parallel.

6. The active terminal circuit of claim 1, wherein the first transistor comprises an NPN bipolar transistor, and the second transistor comprises a PNP bipolar transistor, and the high voltage source is less than or equal to 1.4 volts.

7. The active terminal circuit according to claim 1, wherein, In response to a signal with a low logic level, the first transistor operates in the saturation region and the second transistor operates in the cutoff region; and in response to a signal with a high logic level, the second transistor operates in the saturation region and the first transistor operates in the cutoff region.

8. The active terminal circuit of claim 1, wherein the first transistor comprises a set of transistors configured to be connected in parallel via a set of switches, the set of switches being configured to one of an open state and a closed state based on a calibration setting.

9. The active termination circuit of claim 1, wherein the second transistor comprises a set of transistors configured to be connected in parallel via a set of switches, the set of switches being configured to one of an open state and a closed state based on a calibration setting.

10. The active terminal circuit of claim 1, wherein the strength of at least one of the first transistor and the second transistor is configurable.

11. A memory system, comprising: A first integrated circuit, the first integrated circuit being mounted on a printed circuit board; A second integrated circuit is mounted on the printed circuit board; Interconnectors configured to operate as transmission lines for transmitting signals between the first integrated circuit and the second integrated circuit; and An active termination circuit, formed within one of the first integrated circuit and the second integrated circuit, the active termination circuit comprising: An input node, configured to connect to the interconnect and configured to receive signals from the interconnect; An NMOS transistor having a gate terminal and a drain terminal each connected to a high voltage source and a source terminal connected to the input node, the NMOS transistor being configured to terminate the signal in response to the signal being at a low logic level; and A PMOS transistor having a gate terminal and a drain terminal each connected to a low-voltage source and a source terminal connected to the input node, the PMOS transistor being configured to terminate the signal in response to the signal being at a high logic level; and At least one of the NMOS transistors and the PMOS transistors is calibrated to provide a termination impedance to the signal on the transmission line within a target input impedance range, based on the temperature range in which the active termination circuit is configured to operate.

12. The memory system of claim 11, wherein the NMOS transistor and the PMOS transistor of the active termination circuit are calibrated to provide dynamic termination impedance to the signal from the interconnect, wherein the dynamic termination impedance changes as the signal transitions between the low logic level and the high logic level, and the NMOS transistor and the PMOS transistor include an inherent bias that exists due to the NMOS transistor and the PMOS transistor alternately transitioning between saturation and cutoff regions.

13. The memory system of claim 11, wherein the first integrated circuit is a non-volatile memory storage controller, and the second integrated circuit is a non-volatile memory die controller.

14. The memory system of claim 11, wherein the first integrated circuit is a non-volatile memory controller, and the second integrated circuit is a unified memory die; The memory system also includes: A stack of unified memory dies, each unified memory die being coupled in series with each other via lead bonding; and The active termination circuitry is located within each unified memory die in the stack of unified memory dies.

15. The memory system of claim 11, further comprising: A temperature sensor configured to sense the temperature of one of the first integrated circuit and the second integrated circuit; Storage controller, the storage controller being configured to: The system stores a set of calibration settings for calibrating one or more of the NMOS and PMOS transistors. and In response to the temperature sensor sensing a temperature below or above a temperature threshold, the calibration setting of one of the NMOS and PMOS transistors is changed.

16. The memory system according to claim 15, wherein, The storage controller is also configured to change the calibration settings of the PMOS transistor in response to the temperature sensed by the temperature sensor being greater than or equal to about 100°C and less than or equal to about -25°C.

17. A method for calibrating an active termination circuit, the method comprising: The target input impedance range (Rin) of the receiving active termination circuit, the active termination circuit comprising: An NMOS transistor diode is connected between a high-voltage source and an input node; and A PMOS transistor diode, wherein the PMOS transistor diode is connected between the input node and the low voltage source; The input impedance is measured when the input current (Ln) applied to the input node transitions between high and low logic levels; Determine whether the measured input impedance falls within the target input impedance range; and In response to the input impedance falling outside the target input impedance range, the strength of one of the NMOS and PMOS transistors is calibrated; and The input node is connected to a transmission line configured to provide a signal to the input node; and At least one of the NMOS transistors and the PMOS transistors is calibrated to provide a termination impedance to the signal on the transmission line within a target input impedance range, based on the temperature range in which the active termination circuit is configured to operate.

18. The method of claim 17, wherein: One of the NMOS transistors and the PMOS transistors includes a set of transistors, each of which is a common transistor type, configured to be connected in parallel via a set of switches, which are set to one of an open state and a closed state based on calibration settings. and The calibration of the strength of one of the NMOS and PMOS transistors includes changing the calibration settings such that one or more additional transistors from the set of transistors are connected in parallel as one of the NMOS and PMOS transistors.

19. The method of claim 17, wherein calibrating the intensity of one of the NMOS transistors and the PMOS transistor comprises adjusting the intensity of one of the NMOS transistors and the PMOS transistor based on the operating temperature range of the active termination circuit.

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