Hybrid erase mode for high data retention in memory devices

Abstract

This invention describes an apparatus and technique for performing an erase operation on a group of memory cells, wherein the erase operation includes a full word line erase phase to save time, followed by an odd word line erase phase to improve data retention. A transition to the odd word line erase phase can be triggered when the memory cell passes a first verification test indicating that a threshold voltage of the memory cell has decreased to below a first voltage. Alternatively, the transition can be triggered when a threshold number of erase-verification iterations have been performed. The erase operation can be completed when the memory cell passes a second verification test indicating that the threshold voltage of the memory cell has decreased to below a second voltage, which is less than the first voltage.

Description

Background Technology

[0001] This technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series to form NAND strings, for example, where select-gate transistors are located at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an example memory device.

[0006] Figure 1B yes Figure 1A A block diagram of the arrangement of the memory device 100, wherein the control circuitry 130 on the first die 130a communicates with the memory structure 126 on a separate second die 126b.

[0007] Figure 1C It shows Figure 1A Example of temperature sensing circuit 116.

[0008] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0009] Figure 3 It shows Figure 1A An exemplary specific implementation of a power control circuit 115 for supplying voltage to a block of memory cells in a plane.

[0010] Figure 4 Is with Figure 1A A perspective view of a consistent exemplary memory die 400, wherein blocks are arranged in corresponding planes P0 and P1.

[0011] Figure 5 It shows Figure 1A An exemplary transistor 520 in the memory structure 126.

[0012] Figure 6 It shows Figure 4 An exemplary cross-sectional view of block B0-0, including a portion of NAND strings 700n and 710n.

[0013] Figure 7A It shows the relationship with Figure 4 and Figure 6 An exemplary view of the NAND string in consistent block B0-0.

[0014] Figure 7B It shows Figure 7A An exemplary top view of block B0-0, which has corresponding NAND strings, bit lines, and sensing circuitry.

[0015] Figure 8A It shows the relationship with Figure 7A The word line voltage during the full word line erase process of the NAND string 700n is consistent.

[0016] Figure 8B It shows the relationship with Figure 7A The word line voltage during the erase process of the 700n NAND string with consistent odd-number lines.

[0017] Figure 8C It shows the relationship with Figure 7A The word line voltage during the erase process of the 700n NAND string with consistent even-number lines.

[0018] Figure 8D It shows the relationship with Figure 7A Word line voltage during the full word line verification process of NAND string 700n consistent with the word line.

[0019] Figure 8E It shows the relationship with Figure 7A The word line voltage during the verification process of the 700n NAND string with consistent odd-number lines.

[0020] Figure 8F It shows the relationship with Figure 7A The word line voltage during the verification process of the even-numbered lines of the NAND string 700n is consistent.

[0021] Figure 9A This shows the result after the full word line erase operation. Figure 7A A portion of the NAND string 700n shows hole accumulation in the charge trapping layer (CTL) 664, including inter-word line CTL regions 664a, 664b and 664c.

[0022] Figure 9B This shows what happens after programming. Figure 9AA portion of the NAND string 700n, in which holes are held in the inter-word line CTL regions 664a, 664b and 664c, thereby attracting electrons and causing data retention loss in the memory cells.

[0023] Figure 9C This shows the result after the odd-number lines were erased. Figure 7A A portion of the NAND string 700n shows hole accumulation in the charge trapping layer (CTL) 664, where no holes are present in the inter-word line CTL regions 664a, 664b and 664c.

[0024] Figure 9D This shows the result after the even-number lines have been erased. Figure 9C A portion of the NAND string 700n shows hole accumulation in the charge trapping layer (CTL) 664, where no holes are present in the inter-word line CTL regions 664a, 664b and 664c.

[0025] Figure 9E This shows what happens after programming. Figure 9D A portion of the NAND string 700n, in which no holes exist in the inter-word line CTL areas 664a, 664b and 664c, thereby improving data retention in the memory cells.

[0026] Figure 10A The threshold voltage (Vth) distribution of an eight-state memory device is shown.

[0027] Figure 10B An exemplary Vth distribution in an erasure operation is shown.

[0028] Figure 10C The threshold voltage (Vth) distribution of a four-state memory device is shown.

[0029] Figure 11A A flowchart of an exemplary erasure operation is shown.

[0030] Figure 11B It shows the relationship with Figure 11A The flowchart of an exemplary full-word line stage of the consistent erase operation in step 1090.

[0031] Figure 11C It shows the relationship with Figure 11A Follow step 1091 consistently Figure 11B The flowchart of the first exemplary parity phase of the erase operation is shown, in which both odd and even number lines are verified simultaneously.

[0032] Figure 11D It shows the relationship with Figure 11A Follow step 1091 consistently Figure 11BThe flowchart of the second exemplary parity phase of the erase operation is shown, in which the odd and even number lines are verified separately.

[0033] Figure 12 It shows the relationship with Figure 11B and Figure 11C Exemplary waveforms in a consistent erase operation.

[0034] Figure 13 It shows the relationship with Figure 11B and Figure 11D Exemplary waveforms in a consistent erase operation. Detailed Implementation

[0035] This invention describes an apparatus and technique for performing an erase operation on a set of memory cells, wherein the erase operation includes a full word line erase phase to save time, followed by an odd word line erase phase to improve data retention.

[0036] In some memory devices, memory cells are joined together, such as in NAND strings within a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select-gate transistors (called SGD transistors) at the drain end of the NAND string's connection bit line; and one or more source-side select-gate transistors (called SGS transistors) at the source end of the NAND string or other memory strings or connected groups of memory cells at the source end of the connection source line. The select-gate transistor is also called the select gate. Furthermore, memory cells may be arranged with a common control gate line (e.g., a word line) serving as the control gate. A set of word lines extends from the source side of the block to the drain side of the block. See, for example, [link to relevant documentation]. Figure 7A Memory cells can be connected in other types of serial connections, and can also be connected in other ways.

[0037] In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings on a substrate, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have a pillar shape intersecting the word lines to form the memory cell. Furthermore, each NAND string includes individual layers extending vertically within the stack. See, for example... Figure 6 The NAND string 700n contains a channel 660 and a charge trapping layer 664. The source terminal 700s of the NAND string is connected to the substrate 611, and the drain terminal 700d of the NAND string is connected to the bit line BL0. See, for example, [link to documentation]. Figure 6 .

[0038] In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate.

[0039] Erasing memory cells within a block typically involves one or more erase-verify iterations, also known as erase cycles, where each iteration involves one or more instances of channel boosting, followed by verification testing, until the erase operation is complete. In each erase-verify iteration, the channel voltage is boosted while the word line voltage is held low, for example, equal to or close to 0V. Channel boosting is achieved by applying one or more erase pulses to the block. See also Figure 12 and Figure 13 The voltage signal. In one method, an erase pulse is applied to the substrate, causing holes to be injected into the channel via the source terminals of the NAND string. In another method, the channel is boosted by generating holes at the source and / or drain terminals of the NAND string using gate-induced drain leakage (GIDL). This involves providing strong reverse bias to the SGS and / or SGD transistors, respectively.

[0040] The boost voltage in the channel generates a large channel-to-gate voltage, which drives holes into the charge trapping layer, thereby lowering the threshold voltage (Vth) of the memory cell. A verification test, as a sensing operation, can be performed after the erase pulse is applied to determine whether the Vth of the memory cell has decreased below the verification voltage. Verification tests typically test the erase level of a set of NAND strings by sensing the current in those strings, such as in combination with... Figure 7B The erase operation is complete when all or almost all NAND string groups pass the verification test.

[0041] The erase operation can use two types of erase modes. One of them is called full-line erase (…). Figure 8A In this method, memory cells connected to each word line in the block are erased simultaneously, for example, during the erase-verify iteration. Full word line verification is typically performed after a full word line erase. Figure 8D In this method, memory cells connected to each word line undergo verification testing simultaneously during the erase-verify iteration. This approach is efficient because simultaneous erasure and verification consumes minimal time. However, in the case of a full word line erase, data retention in the memory cells may be compromised due to hole accumulation in the charge trapping layer of the NAND string between word lines. See also Figure 9A This is known as inter-word-line hole accumulation. It causes electrons to move laterally within the charge-trapping layer after programming. The problem becomes more severe when memory cells are erased to a lower Vth to achieve a larger Vth budget (e.g., a larger spacing between the Vth distributions of adjacent data states). The problem is also more pronounced in 3D NAND where the charge-trapping layer is monolithic.

[0042] In another method known as full odd-even word line erasure (or striped word line erasure or alternative word line erasure), memory cells connected to odd-numbered lines are erased separately from those connected to even-numbered lines. See also Figure 8B and Figure 8C Verification testing can be performed in two different ways, such as using parity word line erasure. In the first method, the memory cells connected to each word line are simultaneously subjected to verification testing during the erase-verification iterations. See also: Figure 8D In another approach, memory cells connected to odd-numbered lines are tested separately from those connected to even-numbered lines. See also: Figure 8E and Figure 8F Odd / even word line erasure reduces hole accumulation in the charge trapping layer of the NAND string between word lines. See also: Figures 9C to 9E However, there is a time loss due to erasing odd and even number lines separately.

[0043] The technology provided herein addresses the aforementioned and other problems. In one aspect, the erase operation performs a full word line erase phase followed by an even word line erase phase. A transition from the full word line erase phase to the even word line erase phase can be triggered when a memory cell passes a first verification test indicating that the threshold voltage of the memory cell has decreased to below a first voltage. Alternatively, the transition can be triggered when a threshold number of erase-verification iterations have been performed. A second verification test can be performed during the even word line erase phase instead of the first verification test. Furthermore, the erase operation can be completed when a memory cell passes a second verification test indicating that the threshold voltage of the memory cell has decreased to below a second voltage, which is less than the first voltage.

[0044] During the erase operation, an erase voltage can be applied to charge the channel of the NAND string, where the erase voltage is increased through erase-verify iterations. For example, the erase voltage can be gradually increased in each erase-verify iteration after the initial erase-verify iteration of the erase operation. By performing a full word line erase at a relatively low erase voltage, the erase time is minimized when the risk of inter-word line hole accumulation is low, as this risk is also relatively low when the erase voltage and therefore the channel voltage are relatively low. Furthermore, by performing parity word line erase at a relatively high erase voltage, the risk of inter-word line hole accumulation is reduced compared to using a full word line erase. There is a trade-off that parity word line erase takes more time compared to a full word line erase. However, the combination of erase time and the risk of inter-word line hole accumulation is optimized.

[0045] The transition to parity word line erasure can be optimized based on factors such as temperature, the number of program-erase cycles, the number of data states to be programmed in the memory cell, and the position of the sub-blocks when verifying the sub-blocks of the block individually during the erase operation.

[0046] These and other features will be discussed further below.

[0047] Figure 1A This is a block diagram of an exemplary storage device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may reside on a die 127 separate from the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0048] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0049] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, on-chip address decoder 114, power control circuitry 115, temperature sensing circuitry 116, and program-erase (PE) cycle counter 117. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is software-programmed. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0050] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control circuitry 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operation. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3 In one approach, the sensing block may include a bit line driver. Temperature sensing circuitry 116 can detect the temperature of the memory device over its lifetime (e.g., per minute). PE cycle counter 117 can track the number of PE cycles for each block or other group of memory cells in the memory device. The number of PE cycles can be used to adjust the verification voltage during verification testing, as discussed further below.

[0051] Circuits 116 and 117 may include hardware, software, and / or firmware for performing the processes described herein.

[0052] In some specific implementations, some components of the components may be combined. In various designs, one or more components (alone or in combination) of the components other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoders 114 and 132, power control circuit 115, temperature sensing circuit 116, PE cycle counter 117, sensing blocks 51, 52…53, read / write circuit 128, controller 122, etc. A state machine is a circuit that controls the operation of control circuit 110. In some implementations, the state machine is implemented or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0053] The off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct numerous read errors. RAM 122b may be, for example, DRAM storing uncommitted data. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, the data is erased from RAM 122b and committed or released to a memory cell block. RAM 122b may store data for one or more word lines.

[0054] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0055] The memories in controller 122, such as ROM 122a and RAM 122b, include code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor may access the code from a subgroup 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0056] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122e fetches boot code from ROM 122a or subgroup 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0057] The controller, such as RAM 122b and / or control circuitry 110, may store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits per cell stored in the memory cell, a portion of the word line programmed in the block or sub-block, a portion of the sub-block programmed in the block, the strength of the ECC processing used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage settling time and the number of sense passes.

[0058] Generally, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. Control circuitry may be configured to execute instructions for performing the functions described herein.

[0059] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0060] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0061] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices; non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0062] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0063] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0064] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0065] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0066] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0067] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0069] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xy-plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0070] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0071] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0072] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0073] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0074] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0075] Figure 1B yes Figure 1A A block diagram of the arrangement of a memory device 100, wherein control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The techniques described herein can be implemented using a control die 130a incorporated into one or more memory dies 126b, wherein the memory die includes the memory structure 126, and the control die includes control circuitry 130 representing all or a subset of the peripheral circuitry of the memory structure. The control circuitry may reside on one die, while multiple memory cells may reside on another die.

[0076] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a set of circuitry that performs memory operations (e.g., write, read, erase, etc.) on the memory structure. Control circuitry may include state machine 112, memory area 113, on-chip address decoder 114, power control circuitry 115, temperature sensing circuitry 116, and PE cycle counter 117. In another embodiment, a portion of read / write circuitry 128 is located on control die 130a, while another portion of read / write circuitry is located on memory die 126b. For example, read / write circuitry may include a sense amplifier. This sense amplifier may be located on the control die and / or the memory die.

[0077] The term "memory die" can refer to a semiconductor die containing non-volatile memory cells for storing data. The term "control circuit die" can refer to a semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0078] Figure 1C It shows Figure 1A An example of a temperature sensing circuit 116. This circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-based output voltage supplied to the analog-to-digital converter (ADC) 129. Vbg is a temperature-independent voltage. A voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels using a resistor divider circuit.

[0079] The ADC compares Voutput with the voltage level and selects the closest match, outputting the corresponding digital value (VTemp) to the processor 122e. This is data indicating the temperature of the memory device. In one approach, ROM fuse 123 stores data that correlates the matched voltage level with temperature. The processor then uses the temperature to set temperature-based parameters in the memory device, such as by utilizing comparator circuitry.

[0080] Vbg is obtained by applying a base-emitter voltage (Vbe) and a voltage drop across resistor R2 across transistor 131b. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are of equal size and arranged in a current mirror configuration, such that currents I1 and I2 are approximately equal. Therefore, Vbg = Vbe + R2 × I2 and I1 = Ve / R1, thus I2 = Ve / R1. Therefore, Vbg = Vbe + R2 × kT ln(N) / R1 × q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge. The source of transistor 134 is connected to the supply voltage Vdd, and the node between the transistor's drain and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0081] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51. The individual sensing block 51 is divided into one or more core portions referred to as sensing circuits 60-63 or sensing amplifiers, and a common portion referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with its associated management circuitry via a data bus 176. Therefore, there are one or more management circuits communicating with the sensing circuitry of a group of memory elements (memory cells).

[0082] For example, sensing circuit 60 operates during a programming cycle to provide a precharge / programming-suppress voltage to an unselected bit line or a programming-enable voltage to a selected bit line. The unselected bit line is connected to an unselected NAND string and an unselected memory cell therein. The unselected memory cell can be a memory cell within an unselected NAND string, where the memory cell is connected to either a selected or unselected word line. Alternatively, the unselected memory cell can be a memory cell within a selected NAND string, where the memory cell is connected to an unselected word line. The selected bit line is connected to a selected NAND string and a selected memory cell therein.

[0083] The sensing circuit 60 also operates during a verification test in the programming cycle to sense memory cells, thereby determining whether they have been programmed by reaching an assigned data state (e.g., as indicated by a verification voltage Vth exceeding the assigned data state). The sensing circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sensing circuit 60 also operates during an erase operation during the verification test to determine whether multiple memory cells have a Vth below the verification voltage. As further described below, verification tests can be performed on memory cells connected to all word lines in a block or on memory cells connected to odd or even number lines. The sensing circuit performs sensing by determining whether the conduction current in the connected bit lines is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0084] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a gate-clamped or bit-line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a gate-to-bit-line (BL) to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming suppression voltage such as 1V-2V may be passed when pre-charging and suppressing unselected NAND strings. Alternatively, a programming enable voltage such as 0V may be passed to allow programming in selected NAND strings. Selector 56 may pass a supply voltage Vdd (e.g., 3V-4V) to the control gate of transistor 55 to make it operate as a gate-to-bit line.

[0085] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes the source line is 0V. This mode can be used during sensing operations such as read and verification operations. Therefore, transistor 55 sets the bit line voltage based on the voltage output of selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57 to provide a source follower mode during sensing operations, said relatively high voltage being higher than the control gate voltage on transistor 55.

[0086] Vbl selector 173 can transmit one of a plurality of voltage signals. For example, during a programming cycle, the Vbl selector can transmit a programming suppression voltage signal that increases from an initial voltage (e.g., 0V) to a programming suppression voltage (e.g., Vbl_inh) for the corresponding bit line of an unselected NAND string. Vbl selector 173 can also transmit a programming enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during a programming cycle. The Vbl selector can be based on, for example, commands from processor 192. Figure 3 The BL voltage driver 340 selects the voltage signal.

[0087] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0088] During sensing, sensing node 171 is charged up to an initial voltage Vsense_init, such as 3V. The sensing node is then passed to bit lines via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during sensing. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sensing node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the comparator circuit 175 sets the sensing node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. The data in the sensing node latch can be read by processor 192 and used to update bits of trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected for or not for programming in the programming cycle, thereby passing the appropriate enable or suppress bit line voltage to the bit line respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0089] The management circuitry 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sensing circuits 60-63, and an I / O interface 196 coupled between the data latch sets and the data bus 120. Each sensing circuit may be provided with a set of three data latches, for example, including individual latches LDL, MDL, and UDL. In some cases, different numbers of data latches may be used. In a three-bit implementation per unit, the LDL stores bits for the next page of data, the MDL stores bits for intermediate page data, and the UDL stores bits for the previous page of data.

[0090] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits imported from data bus 120 during a programming operation; these data bits represent write data to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0091] During a read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. The processor 192 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 193 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 194-197.

[0092] Some implementations may include multiple processors 192. In one implementation, each processor 192 will include output lines (not shown) such that each output line is wired-ORed together. In some implementations, the output lines are inverted before being connected to the wires or lines. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the wires or lines can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wire or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wires or lines eight times, or logic can be added to the processor 192 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the wires or lines once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0093] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 194-197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0094] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0095] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers, such that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0096] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0097] Figure 3 It shows Figure 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to memory cell blocks in a plane is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four associated blocks B0-0 through B0-3 and another set of four associated blocks B0-4 through B0-7. See also... Figure 4 A block can lie in one or more planes. Figure 1AThe line decoder 124 provides voltage to the word lines and the select gate control lines for each block via a transfer transistor 322. In one approach, a separate line decoder is provided for each block. The line decoder provides a control signal to the transfer transistor, which connects the block to the line decoder. In another approach, the transfer transistors for each group of blocks are controlled by a common control gate voltage. Therefore, all transfer transistors in a group of blocks are either on or off at a given time. If a transfer transistor is on, voltage from the line decoder is provided to the corresponding control gate line or word line. If a transfer transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing voltage to float on the corresponding control gate line or word line.

[0098] For example, control gate line 312 is connected to transmission transistor groups 313-316, which are in turn connected to control gate lines B0-4 to B0-7, respectively. Control gate line 317 is connected to transmission transistor groups 318-321, which are in turn connected to control gate lines B0-0 to B0-3, respectively.

[0099] Typically, programming or reading operations are performed one at a time on a selected block. Erasing operations can be performed on a selected block or a sub-block. The line decoder connects global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is provided on the global control line of many voltage drivers. Some voltage drivers can provide voltage to switch 350 connected to the global control line. Control transfer transistor 324 is used to transfer voltage from the voltage driver to switch 350.

[0100] The voltage driver may include a selected data word line (WL) driver 347 that provides voltage on the selected data word line during programming or read operations. Driver 347 may provide a pre-charge voltage and a programming voltage on WLn during a programming cycle of a programming operation. Driver 348 may be used for unselected data word lines, and dummy word line drivers 349 and 349a may be used respectively for... Figure 6 Voltage is provided on the dummy word lines WLDD and WLDS.

[0101] The voltage driver may also include a separate SGD driver for each sub-block. For example, such as in Figure 7A In this block, SGD drivers 346, 346a, 346b, and 346c may be provided for SB0, SB1, SB2, and SB3, respectively. The SGD drivers provide voltage to control lines connected to the control gate of the SGD transistor (drain-side selected gate transistor). In one option, the SGS driver 345 is common to different sub-blocks within the block and provides voltage to control lines connected to the control gate of the SGS transistor (source-side selected gate transistor).

[0102] Various components, including the line decoder, can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0103] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b, for example, via conductive path 682. See also Figure 6 In one approach, the p-well region 611b is common to the block. The Vp-well can be... Figure 12 and Figure 13 The Verase in the block is the same. The block also shares a set of bit lines 342. The source line (SL) voltage driver 331 provides voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via local interconnect 651.

[0104] Bit line voltage driver 340 includes a voltage source that supplies voltage to bit line 342. The bit line voltage used for sensing in the erase verification test may be, for example, 0.5V.

[0105] In such Figures 4 to 7B In the stacked memory device shown, multiple sets of interconnected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source end) of each NAND string contacts the substrate, for example, a well region, and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0106] Figure 4 Is with Figure 1A A perspective view of a consistent exemplary memory die 400, wherein blocks are disposed in corresponding planes P0 and P1. The memory die includes a substrate 611, an intermediate region 402 in which memory cell blocks are formed, and an upper region 403 in which one or more upper metal layers are patterned to form bit lines. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 611. Additionally, a first block sequence 405 (labeled B0-0 to B0-n-1) of n blocks is formed in P0, and a second block sequence 415 (labeled B1-0 to B1-n-1) of n blocks is formed in P1. Each plane may have associated row and column control circuitry, such as... Figure 1A The row decoder 124, the read / write circuit 128, and the column decoder 132.

[0107] In one approach, control circuitry 110, which can be located in a peripheral region of the die, can be shared between planes. Each plane may have a separate set of bit lines.

[0108] By providing memory cell blocks in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0109] The substrate 611 may also carry circuitry beneath the block, as well as one or more lower metal layers patterned in conductive paths to carry circuit signals. For example, the commands in FIG10 provide pass / fail states for erase operations in planes P0 and P1.

[0110] In this example, memory cells are formed in vertical NAND strings within a block. Each block includes a stacked area of ​​memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to an upper metal layer to form connections with conductive paths. While two planes are shown as an example, other examples may use four or more planes. One plane per die is also possible.

[0111] While the examples above relate to 3D memory devices with vertically extending NAND strings, the techniques presented herein are also applicable to 2D memory devices in which the NAND strings extend horizontally on a substrate.

[0112] Figure 5 It shows Figure 1A An exemplary transistor 520 in the memory structure 126. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may, for example, represent a memory cell or a select gate transistor. The drain terminal of the transistor is optionally connected to the bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to the source line SL via one or more other transistors in the NAND string.

[0113] Figure 6 It shows Figure 4 An exemplary cross-sectional view of block B0-0 including a portion of NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers may be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0114] The stack is described as comprising one, but optionally one or more, alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers, wherein memory vias are formed during the manufacturing process.

[0115] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). The conductive layer connected to the control gate of the memory cell is called a word line, and the conductive layers connected to the control gates of the source-side select-gate transistor and the drain-side select-gate transistor are called source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not qualified to store user data. A dummy memory cell may have the same structure as a data memory cell, but the controller considers that the memory cell unqualified to store any type of data, including user data. One or more dummy memory cells may be provided at the drain and / or source ends of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cell that are qualified to store user data. By way of example only, the stack includes ninety-six data word lines. DL is an exemplary dielectric layer.

[0116] The top 610t and bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0117] NAND strings are formed by etching memory vias in a stack and then depositing multiple thin layers of material along the sidewalls of the memory vias. Memory cells are formed in regions where word lines intersect with the multiple thin layers, and select-gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers. For example, drain-side select-gate transistor 716 is formed where the SGD control line intersects with the multiple thin layers, source-side select-gate transistor 701 is formed where the SGS control line intersects with the multiple thin layers, topmost data memory cell 714 is formed where the WL95 word line intersects with the multiple thin layers, and bottommost data memory cell 703 is formed where the WL0 word line intersects with the multiple thin layers.

[0118] Multiple thin layers may form a ring layer and may be deposited, for example, using atomic layer deposition. These layers may include, for example, a barrier oxide layer 663, a charge trapping layer 664 or film (such as silicon nitride (Si3N4) or other nitrides), a tunneling layer 665 (e.g., gate oxide), and a channel 660 (e.g., comprising polysilicon). A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. Word lines or control lines may comprise a metal, such as tungsten. In this example, all layers are disposed within memory vias. In other methods, some of the layers may be disposed within word line or control line layers. Multiple thin layers form columnar active regions (AA) of a NAND string.

[0119] Stacked on substrate 611. In one method, the substrate includes a p-well region 611a connected to the source end of the NAND string (see also...). Figure 3The p-well region may include an epitaxial region 612 that extends upward adjacent to the source-side selected gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 to receive a source line voltage and a p+ contact 612b connected to a conductive path 682 to receive a p-well voltage. The local interconnect 651 may include a conductive material 651b, such as a metal surrounded by an insulating material 651a, to prevent metal-to-metal conduction with adjacent word lines. In one possible embodiment, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0120] The NAND string 700n has a source end 700s connected to the p-well at the bottom 610b of the stack 610. The NAND string 700n also has a drain end 700d connected to the bit line BL0 via a bit line contact 680 containing n-type material at the top 610t of the stack.

[0121] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate.

[0122] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and then through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the channel of the NAND string is charged, such as by applying a positive erase pulse to the substrate via local interconnect 651, causing electrons to return from the charge trapping layer to the channel.

[0123] Figure 7A It shows the relationship with Figure 4 and Figure 6 An exemplary view of the NAND strings in block B0-0. The NAND strings are arranged in a 3D configuration within sub-blocks of the block. Each sub-block includes multiple NAND strings, with one example NAND string depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have... Figure 6Consistent data word lines, dummy word lines, and select gate lines. Each sub-block comprises a set of NAND strings extending in the x-direction and having a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Block programming can be based on word line programming order. One option is to program memory cells in different word line portions within different sub-blocks one at a time, before programming memory cells in the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, and SB3, then programming WL1 in SB0, SB1, SB2, and SB3, and so on. For example, the word line programming order could start with WL0 (source end word line) and end with WL95 (drain end word line).

[0124] In an erase operation, the entire block is usually erased, but partial erasure is also possible.

[0125] Multiple memory cells of B0-0 are arranged in NAND strings, wherein each NAND string includes a continuous charge trapping layer along the length of the NAND string. NAND strings 700n, 710n, 720n, and 730n have channels 700a, 710a, 720a, and 730a, respectively. Additionally, NAND string 700n includes an SGS transistor 701, dummy memory cells 702, data memory cells 703-714, dummy memory cells 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, dummy memory cells 722, data memory cells 723-734, dummy memory cells 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, dummy memory cells 742, data memory cells 743-754, dummy memory cells 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-774, a dummy memory cell 775, and an SGD transistor 776.

[0126] This example illustrates one SGD transistor at the drain terminal of each NAND string and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0127] Figure 7B It shows Figure 7AAn exemplary top view of block B0-0, showing the corresponding NAND strings, bit lines, and sensing circuitry. The view is in the xy-plane. Each circle represents a NAND string. In this example, sixteen NAND strings are shown for each sub-block. SB0 includes... Figure 7A The NAND string 700n and the additional NAND strings 700n1-700n15. SB1 includes... Figure 7A The NAND string 710n and the additional NAND strings 710n1-710n15. SB2 includes... Figure 7A The NAND string 720n and the additional NAND strings 720n1-720n15. SB3 includes... Figure 7A The NAND string 730n and the additional NAND strings 730n1-730n15.

[0128] A set of bit lines BL0-BL15 are connected to NAND strings. Each bit line is connected to a corresponding set of NAND strings, including one NAND string per sub-block. For example, BL0 is connected to NAND strings 700n, 710n, 720n, and 730n in a set of NAND strings 799, BL1 is connected to NAND strings 700n1, 710n1, 720n1, and 730n1, and so on. Each bit line is also connected to... Figure 2 The corresponding sensing circuits are identical to those of sensing circuits 60-63. For example, BL0-BL15 are connected to sensing circuits SC0-SC15 respectively.

[0129] In the verification test of the erase operation, verification voltage VvEr1 or VvEr2 is applied to the word line. See also Figure 12 and Figure 13 Simultaneously, each sensing circuit senses the current on the corresponding bit line based on the sum of the currents in the corresponding NAND strings connected to the bit line. For example, SC0 can sense the current on BL0 based on the currents in NAND strings 700n, 710n, 720n, and 730n. Therefore, the verification test may involve sensing the current in a set of NAND strings connected to each bit line. If the current is higher than a specified level, for example, if the threshold voltage of the memory cells in a set of NAND strings is lower than a verification voltage, then the set of NAND strings passes the verification test. If all or almost all of the NAND strings in the set of NAND strings pass the verification test, then the block passes the verification test. In other words, if no or no more than a specified portion of a set of NAND strings in a block fails the verification test, then the block passes the verification test. In another possible approach, one sub-block is sensed at a time for each bit line.

[0130] When a verification voltage is applied to the word line, the NAND string either passes or fails the verification test. The NAND string fails the verification test when the sensed current in the NAND string is less than a specified level. A failure indicates that Vth is higher than the verification voltage of one or more memory cells in the NAND string. Conversely, the NAND string passes the verification test when the sensed current in the NAND string is greater than a specified level. A failure indicates that Vth is lower than the verification voltage of all memory cells in a group of NAND strings. See also: Figure 9D Various examples of verification tests are shown in Figure 9H.

[0131] For example, a set of NAND strings that may include all NAND strings in a block or sub-block can be considered to have passed the verification test if all or almost all of the NAND strings pass the verification test. For example, a verification test can be passed if no more than 1%-5% of the NAND strings fail the verification test. In practice, it is simpler for the circuit to count the number of NAND strings that fail the verification test than to count the number of NAND strings that pass the verification test.

[0132] Figures 8A to 8C Examples of word line voltages in different erase processes are shown. As mentioned at the beginning, an erase operation can be performed using, for example, a full word line erase process or an odd-even word line erase process. In a full word line erase, all word lines are held at a low erase enable voltage (Ven), such as 0V, while the channels of the NAND string are charged. This generates a large channel-to-control gate electric field for each memory cell, which drives hole injection into the trapping layer, thereby reducing the Vth of the memory cell. In an odd-even word line erase, odd-numbered lines are held at Ven, while even-numbered lines are held at a higher erase suppressor voltage (Vinh), such as 10V, while the channels are charged. When Ven is applied to the word lines, this generates a large channel-to-control gate electric field for each memory cell connected to the odd-numbered lines, causing the memory cells connected to the odd-numbered lines to be erased. However, when Vinh is applied to the word lines, the channel-to-control gate electric field is not large enough for erasure, causing the memory cells connected to the even-numbered lines to not be erased. Individually, before or after erasing memory cells connected to odd-numbered lines, even-numbered lines are held in Ven and odd-numbered lines are held in Vinh, while the channel is charged such that memory cells connected to even-numbered lines are erased, while memory cells connected to odd-numbered lines are not erased.

[0133] Additionally, when using parity / evenness word lines for erasure, the verification process can involve simultaneous verification testing of all memory cells, such that verification tests of memory cells connected to odd-numbered word lines are performed concurrently with those connected to even-numbered word lines. Alternatively, the verification process can involve verification tests of memory cells connected to odd-numbered word lines, which are performed separately before or after the verification tests of memory cells connected to even-numbered word lines.

[0134] Figure 8A It shows the relationship with Figure 7A The word line voltage during the full word line erase process is consistent across the NAND string 700n. For example, applying Ven = 0V to all data word lines WL0-WL95 causes the memory cells connected to these word lines (including memory cells 703-714) to be erased. Dummy word lines can receive Vinh. The NAND channel can be charged by applying an erase voltage to the substrate and / or from the drain using GIDL.

[0135] Figure 8B It shows the relationship with Figure 7A The word line voltage during the erase process of the 700n NAND string is consistent with the odd number lines. Ven = 0V is applied to the odd number lines (e.g., WL1, WL3…WL95), while Vinh = 10V is applied to the even number lines (e.g., WL0, WL2…WL94).

[0136] Figure 8C It shows the relationship with Figure 7A The word line voltage during the erase process of the even-numbered lines of the NAND string 700n is consistent. Ven = 0V is applied to the even-numbered lines (e.g., WL0, WL2…WL94), while Vinh = 10V is applied to the odd-numbered lines (e.g., WL1, WL3…WL95).

[0137] Figure 8D It shows the relationship with Figure 7A The word line voltages are consistent across the entire word line of the NAND string (700n). While sensing the current in the NAND string, a verification voltage VvEr is applied to each word line. The verification voltage can be VvEr1 or VvEr2, such as... Figure 10A and Figure 10B As shown. Compared to the parity verification process, the full-word line verification process is optimal in terms of time consumption.

[0138] Figure 8E It shows the relationship with Figure 7AThe word line voltages during the verification process of the 700n NAND string are consistent with the odd-numbered lines. Memory cells connected to the odd-numbered lines undergo verification testing by applying a verification voltage VvEr to these word lines. During the verification test, a voltage Vread (such as 8V) is applied to the even-numbered lines to provide the associated memory cells in a strongly conductive state, such that the sensed current in the NAND string will be primarily based on the threshold voltage of the memory cells connected to the odd-numbered lines.

[0139] Figure 8F It shows the relationship with Figure 7A The word line voltages during the parity verification process of the NAND string 700n are consistent even-numbered lines. Memory cells connected to even-numbered lines undergo verification testing by applying a verification voltage VvEr to these word lines. During the verification test, Vread is applied to odd-numbered lines to provide the associated memory cells in a strongly conductive state, such that the sensed current in the NAND string will be primarily based on the threshold voltage of the memory cells connected to even-numbered lines. The parity verification process tends to ensure that memory cells are erased more evenly.

[0140] Figure 9A This shows the result after the full word line erase operation. Figure 7A A portion of the NAND string 700n shows hole accumulation in a charge trapping layer (CTL) 664, including inter-word line CTL regions 664a, 664b, and 664c. This portion of the NAND string includes memory cells 703-706 and associated word lines WL0-WL3, respectively. Figures 9A to 9E The diagram also shows a barrier oxide (BOX) layer 663, a charge trapping layer (CTL) 664, a tunneling oxide layer (TUN) 665, and a channel (CH) 660. Holes are represented by "+", and electrons by "-". The inter-word line CTL regions 664a, 664b, and 664c refer to the regions of the NAND string located between word lines WL0 and WL1, WL1 and WL2, and WL2 and WL3, respectively.

[0141] During erasure, the channel voltage is boosted by the erase pulse while the word line voltage is maintained at Ven = 0V. Therefore, holes in the channel are injected into the portion of the CTL directly adjacent to the word line. For example, CTL portions 664d-664g are directly adjacent to WL0-WL3, respectively. Furthermore, holes can also be injected into the inter-word line CTL regions due to edge fields (indicated by oblique arrows). This is more likely to occur when the erase voltage magnitude is high. For example, when using incremental step pulse erasure, the erase voltage Verase is higher than... Figure 12 and Figure 13The verase gradually increases in each erase-verify iteration after the initial erase-verify iteration. Therefore, when the verase is higher, it is more likely that holes will be injected into the inter-word line CTL region during a later erase-verify iteration of the erase operation. After the erase operation, as shown... Figure 9B The programming operation is performed as shown.

[0142] Figure 9B This shows what happens after programming. Figure 9A A portion of the NAND string 700n contains holes held in inter-word line CTL regions 664a, 664b, and 664c, which attract electrons and cause data retention loss in the memory cell. During word line programming, electrons are injected into the portion of the CTL directly adjacent to the word line. This is indicated by the electrons “-” in CTL portions 664d-664g. However, holes remain in the inter-word line CTL regions 664a-664c. Holes move towards the memory cell within the CTL and, during lateral charge movement within the CTL, attract some electrons away from the memory cell, resulting in data retention loss. This movement is indicated by double arrows. This is undesirable as it can lead to uncorrectable read errors.

[0143] Figure 9C This shows the result after the odd-number lines were erased. Figure 7A A portion of the NAND string 700n is shown, illustrating hole accumulation in the charge trapping layer (CTL) 664, where holes are absent in the inter-word line CTL regions 664a, 664b, and 664c. During the erasure of memory cells connected to WL1 and WL3, Vinh = 10V is applied to WL0 and WL2, creating an edge field (indicated by the diagonal arrows), which reduces hole accumulation in the inter-word line CTL regions. Conversely, holes accumulate in the CTL regions 664e and 664g, which are directly adjacent to WL1 and WL3, respectively.

[0144] Figure 9D This shows the result after the even-number lines have been erased. Figure 9C A portion of the NAND string 700n shows hole accumulation in the charge trapping layer (CTL) 664, where no holes are present in the inter-word line CTL regions 664a, 664b, and 664c. In contrast to... Figure 9C In a similar scenario, during the erasure of memory cells connected to WL0 and WL2, the Vinh applied to WL1 and WL3 generates an edge field (indicated by the slanted arrows), which reduces hole accumulation in the inter-word line CTL regions. Conversely, holes accumulate in the CTL regions 664d and 664f, which are directly adjacent to WL0 and WL2, respectively.

[0145] Figure 9E This shows what happens after programming. Figure 9DA portion of the NAND string 700n contains no holes in the inter-word line CTL regions 664a, 664b, and 664c, thus improving data retention in the memory cells. When memory cells connected to WL0-WL3 are programmed, electrons accumulate in the CTL regions 664d-664g, which are directly adjacent to WL0-WL3, respectively. Because there are no holes or only a reduced number of holes in the inter-word line CTL regions, data retention is improved.

[0146] Figure 10A The threshold voltage (Vth) distribution of an eight-state memory device is shown. As an example, eight data states, or three bits per cell, are illustrated. The techniques described herein can be applied to other modes involving one or more bits per cell. Figure 10A and Figure 10B In the diagram, the vertical axis depicts the number of memory cells on a logarithmic scale, while the horizontal axis depicts the threshold voltage on a linear scale. The Vth distribution can represent all memory cells connected to a word line or within a block. After erasing the block, a Vth distribution of 1000 is obtained, indicating the erase state. The erase operation is complete when the Vth of all or almost all memory cells is below the verification voltage VvEr2.

[0147] The memory cells are then programmed. Each memory cell will have an assigned data state. Some memory cells are assigned to the erase state and are not programmed. In this example, most memory cells are programmed to higher states, such as AF, represented by Vth distributions 1001-1007 respectively. These memory cells undergo verification testing using verification voltages VvA-VvG. Programming higher-state memory cells may interfere with erase-state memory cells, resulting in a broadened and upward-shifted Vth distribution 1001. Additionally, after programming, the data retention loss result is a broadening of the Vth distribution, including a reduction in the lower tail of the Vth distribution. For example, due to the data retention loss, Vth distributions 1001-1007 transform into Vth distributions 1011-1017 respectively.

[0148] Figure 10B An exemplary Vth distribution during an erase operation is shown. In this example, five erase pulses are applied in the corresponding erase-verify iteration. After the first erase pulse, the threshold voltage of the memory cell (e.g., ...) is... Figure 10AThe threshold voltage of the memory cell (as shown) transitions to Vth distribution 1020. The memory cell fails the verification test of its Vth relative to the first verification voltage VvEr1. After the second erase pulse, the threshold voltage of the memory cell transitions to Vth distribution 1021. The memory cell passes the verification test of its Vth relative to VvEr1. In this case, region 1021a of Vth distribution 1021 represents the count of memory cells or NAND strings or groups of NAND strings that failed the verification test. The count is less than the threshold level and is therefore considered to have passed the verification test.

[0149] After the third erase pulse, the threshold voltage of the memory cell changes to Vth distribution 1022. The memory cell fails the verification test that tests its Vth relative to a second verification voltage VvEr2 lower than VvEr1. After the fourth erase pulse, the threshold voltage of the memory cell changes to Vth distribution 1023. The memory cell again fails the verification test that tests its Vth relative to VvEr2. After the fifth erase pulse, the threshold voltage of the memory cell changes to Vth distribution 1024. The memory cell passes the verification test that verifies its Vth relative to VvEr2. In this case, region 1024a of Vth distribution 1024 represents the count of memory cells or NAND strings or groups of NAND strings that failed the verification test. The count is less than the threshold level and is therefore considered to have passed the verification test. The count used to determine the pass or fail status of the verification test can be the same or different for the first and second verification tests.

[0150] Generally speaking, the control circuit can count the number of NAND strings that pass or fail the verification test to determine whether a group of memory cells has passed or failed the verification test.

[0151] Figure 10C The threshold voltage (Vth) distributions of a four-state memory device are shown. Vth distribution 1030 represents the erase state immediately following the erase, and Vth distributions 1032, 1034, and 1036 represent states A, B, and C, respectively, without data retention loss. Vth distribution 1031 represents the erase state with programming interference, and Vth distributions 1033, 1035, and 1037 represent states A, B, and C, respectively, with data retention loss. Figure 10AIn contrast, with a smaller number of data states, there are typically larger intervals between adjacent Vth distributions. Therefore, a greater amount of data retention loss can be accommodated without leading to uncorrectable read errors. Thus, the erase operation can be adjusted to have a longer full-word erase phase before transitioning to the parity word-line erase phase. This can be achieved, for example, by using a lower VvEr1. In other words, when erasing multiple memory cells, VvEr1 is likely to be lower when the number of data states to be stored by those multiple memory cells is small. When erasing multiple memory cells, VvEr1 is likely to be higher when the number of data states to be stored by those multiple memory cells is large, such that VvEr1 is an increasing function of the number of data states. Alternatively, when erasing multiple memory cells, VvEr1 - VvEr2 (the amount by which VvEr1 exceeds VvEr2) is likely to be smaller when the number of data states to be stored by those multiple memory cells is small. VvEr1 - VvEr2 can be an increasing function of the number of data states.

[0152] For example, using sixteen data states. In this case, VvEr1 or VvEr1-VvEr2 can be greater than the case using eight data states.

[0153] In one method, control circuitry is configured to set a first voltage for a first verification test as an incremental function of the number of data states to which the memory cell will be programmed. Therefore, the first voltage is larger when the number of data states is large. For example, the memory cell may be located in a block designated by the control circuitry to store a specific number of data states, or bits per cell. The memory device may include different blocks designated to store different numbers of data states.

[0154] Figure 11A A flowchart of an exemplary erase operation is shown. Step 1090 includes erasing multiple memory cells using a full word line erase until a first verification test is passed. See also Figure 11B An exemplary implementation is provided. Step 1091 includes further erasing the plurality of memory cells using full parity word line erasure until a second verification test is passed. See also... Figure 11C or Figure 11D An exemplary specific implementation.

[0155] Figure 11B It shows the relationship with Figure 11AStep 1090 is a flowchart of an exemplary full-word-line phase of a consistent erase operation. Step 1100 begins an erase operation for a set of memory cells arranged in a NAND string, wherein the set of memory cells is connected to a set of word lines. Step 1101 begins the full-word-line phase of the erase operation. Step 1102 initializes the erase voltage Verase. Step 1103 includes applying Verase to the substrate to charge the channels of the NAND string, while applying an erase enable voltage to all word lines (e.g., all data word lines). Step 1104 includes performing a first verification test by applying a first voltage VvEr1 to all word lines while sensing the current in the NAND string.

[0156] Step 1105 determines whether the first verification test has passed. If step 1105 is false, step 1107 increments Verase and returns to step 1103. Each pass through steps 1103-1105 represents an example of an erase-verify iteration. If step 1105 is true, step 1106 begins the parity phase of the erase operation. When step 1105 is true, erase milestones for multiple memory cells have been reached. This may include, for example... Figure 11C or Figure 11D The process.

[0157] As mentioned, the transition to parity word line erasure can be optimized based on factors such as temperature, the number of program-erase cycles, the number of data states to be programmed in the memory cells, and the sub-block position when verifying sub-blocks of a block individually during the erase operation. For example, the control circuitry can be configured to adjust a first voltage based on the number of program-erase cycles across multiple memory cells, where the first voltage is a decreasing function of the number of program-erase cycles. This method recognizes that data retention loss can be significant when the number of PE cycles is low. By increasing the first voltage when the number of PE cycles is low, the number of erase-verify iterations performed using full word line erasure is reduced, resulting in less hole accumulation in the inter-word line CTL region. In another approach, the control circuitry is configured to sense temperature and adjust the first voltage based on the temperature, where the first voltage is an increasing function of the temperature. This method recognizes that data retention loss can be significant when the temperature is high.

[0158] In another option, such as combination Figure 10C As mentioned, the first voltage of the first verification test can be an incremental function of the number of data states to which the memory cell will be programmed.

[0159] In another option, the erased memory cells are arranged in one of several sub-blocks within a block, and the control circuitry is configured to set a first voltage based on the location of the sub-block within the block. This allows for customized verification tests for each sub-block when verifying each sub-block individually. In some cases, due to factors such as the sub-block programming order, some sub-blocks may experience significant data retention loss. For example, if the verification order is SB0, SB1, SB2, SB3 (see...) Figure 7A If ), then the memory cell of SB0 may experience a large loss of data retention because it is subjected to suppression voltage while verifying other sub-blocks.

[0160] Another option is to switch from the full word line phase to the parity phase even if the threshold number of erase-verification iterations has been performed even before the first verification test is passed. This helps avoid the accumulation of holes in the charge trapping region between word lines due to an excessive number of erase-verification iterations using the full word line process. For example, suppose the threshold number is three erase-verification iterations. The erase operation can perform three erase-verification iterations using a full word line erase, where the first verification test fails. Instead of continuing with a fourth erase-verification iteration using a full word line erase, the erase operation switches to a fourth erase-verification iteration using parity word line erase.

[0161] The control circuitry can issue commands to perform mixed erase operations, such as parity-even word line erasure (or even-odd) after a full word line erase. The control circuitry can be located on the same die as the memory cell or on a separate die. In one approach, a dedicated command exists: CMD XX:60h-Address(3cycle)-XXh => Busy(tERASE)->Ready. "60h" represents the erase block command in the first command cycle. "Address(3cycle)" represents the 3-cycle or byte address of the block to be erased. The address may contain information such as identifying the plane and block. "XXh" is a dedicated status return command. This status can be a pass / fail result for verifying the test and / or erasure operation. "Busy" indicates that the chip's ready / busy pin is busy, while "Ready" indicates that the chip's ready / busy pin is ready.

[0162] In another method, the prefix command is used in the following format: Prefix CMD YY-60h-Address(3cycle)-D0h => Busy(tERASE)->Ready. “D0h” indicates the second command cycle. Therefore, “Prefix CMD YY” precedes the normal (non-mixed) erase command, for example, for a full word line erase that does not have parity word line erasure.

[0163] In one possible approach, a hybrid erase is initiated using a pre-command transmitted to the memory chip along with the erase command. In another possible approach, detection is initiated using device parameters on the memory chip.

[0164] Commands can be issued from an off-chip controller 122 to an on-chip control circuit 110, which includes, for example, a state machine 112 related to an erase operation. The on-chip control circuit 110, including the state machine 112, can report the status of the erase operation back to the controller 122. A pre-command is a command that precedes another related command. For example, a pre-command may have a desired format and contain one or more bytes.

[0165] Figure 11C It shows the relationship with Figure 11A Follow step 1091 consistently Figure 11B The flowchart below describes the first exemplary parity phase of the erase operation, where both odd and even word lines are verified simultaneously. Step 1110 involves applying Verase to the substrate to charge the channel of the NAND string, while simultaneously applying an erase enable voltage to the odd word lines and an erase suppress voltage to the even word lines. Step 1111 involves applying Verase to the substrate to charge the channel of the NAND string, while simultaneously applying an erase enable voltage to the even word lines and an erase suppress voltage to the odd word lines. Step 1112 includes performing a second verification test by applying a second voltage VvEr2 to all word lines while simultaneously sensing the current in the NAND string.

[0166] Step 1113 determines whether the second verification test has passed. If step 1115 is false, then step 1115 increments Verase and returns to step 1110. Each pass through steps 1110-1112 represents an example of the erase-verify iteration. If step 1113 is true, then the erase operation is successfully completed at step 1114.

[0167] It should be noted that a maximum number of erase-verify iterations can be performed during the erase operation, such that if the erase operation is not completed within the maximum number of erase-verify iterations, the erase operation fails.

[0168] The order of steps 1110 and 1111 can be reversed. The odd-even phase may involve erasing the odd-number lines first, or erasing the even-number lines first.

[0169] Figure 11D It shows the relationship with Figure 11A Follow step 1091 consistently Figure 11BFlowchart of the second exemplary parity stage of the erase operation of a flowchart, where odd and even digit lines are verified separately. Step 1120 includes applying Verase to the substrate to charge the channels of the NAND strings, while applying an erase enable voltage to the odd digit lines and an erase inhibit voltage to the even digit lines. Step 1121 includes performing a second verification test by applying a second voltage VvEr2 < VvEr1 to the odd digit lines and a pass voltage Vread to the even digit lines while sensing the current in the NAND strings. Step 1122 includes applying Verase to the substrate to charge the channels of the NAND strings, while applying an erase enable voltage to the even digit lines and an erase inhibit voltage to the odd digit lines. Step 1123 includes performing a second verification test by applying a second voltage VvEr2 < VvEr1 to the even digit lines and a pass voltage Vread to the odd digit lines while sensing the current in the NAND strings.

[0170] Step 1124 represents four possible cases resulting from the second verification test. In case 1, the odd digit lines pass and the even digit lines fail. In case 2, the odd digit lines fail and the even digit lines fail. In case 3, the odd digit lines fail and the even digit lines pass. In case 4, the odd digit lines pass and the even digit lines pass. At case 4, step 1125 is reached, indicating that the erase operation has been successfully completed. For cases 1 - 3, step 1126 increments Verase. Subsequently, for case 1, for the next erase - verification iteration including steps 1122 and 1123, step 1122 is reached. For cases 2 and 3, for the next erase - verification iteration including steps 1120 - 1123, step 1120 is reached.

[0171] In Figure 11C and Figure 11D order to bias the odd digit lines for erasure in the second stage (the odd - even word line erase stage), the control circuit is configured to apply an erase enable voltage to the odd digit lines while applying an erase inhibit voltage to the even digit lines; and in order to bias the even digit lines for erasure in the second stage, the control circuit is configured to apply an erase enable voltage to the even digit lines while applying an erase inhibit voltage to the odd digit lines. The second stage follows the first stage, which is the full word line erase stage.

[0172] Figure 12 Shows exemplary waveforms in the erase operation consistent with Figure 11B and Figure 11C In Figure 12 and Figure 13 the vertical direction represents voltage, and the horizontal direction represents a common time scale. In Figure 12The example shown contains four erase-verify iterations EV1-EV4, where the erase operation is completed after EV4. However, in other examples, additional erase-verify iterations (not shown) may be performed. Alternatively, fewer than four erase-verify iterations may be used. EV1 and EV2 are examples of one or more consecutive erase-verify iterations in the full word line phase of the erase operation, where methods such as... Figure 8D The full word line verification process in the text, and EV3 and EV4 are examples of one or more consecutive erase-verify iterations in the odd and even word line phases of the erase operation, where methods such as... Figure 8E and Figure 8F The process of verifying the odd and even word lines in the code.

[0173] Voltage signal 1200 represents the erase voltage Verase. This could be, for example, a voltage applied to the bit lines of the substrate and / or block. Erase pulses 1201, 1202, 1203, 1204, 1205, and 1206 have values ​​of Verase1, Verase2, Verase3, Verase4, and Verase4, respectively. Each erase pulse charges the channel of the NAND string in the block. The erase pulse may have an initial value of, for example, 15-20V, and increases with each erase-verify iteration.

[0174] Voltage signals 1210 and 1230 represent the Vwl_odd and Vwl_even voltages applied to each of the odd and even data word lines of the block, respectively, during the erase operation. During the erase pulse 1201 of EV1, Vwl_odd and Vwl_even are set to the voltage enable voltage Ven (such as a small positive voltage of 0V-0.5V), as represented by curves 1211 and 1231, respectively. In the first verification test that fails, Vwl_odd and Vwl_even = VvEr1 (curves 1212 and 1232). During the erase pulse 1202 of EV2, Vwl_odd and Vwl_even are set to Ven, as represented by curves 1213 and 1233, respectively. In the first verification test that passes, indicated by Pass1, Vwl_odd and Vwl_even = VvEr1 (curves 1214 and 1234). This triggers the parity phase of the erase operation.

[0175] During the first erase pulse 1203 of EV3, Vwl_odd is set to Ven (curve 1215) and Vwl_even is set to Vinh (curve 1235). No verification test is performed between erase pulses 1203 and 1204. During the second erase pulse 1204 of EV3, Vwl_odd is set to Vinh (curve 1216) and Vwl_even is set to Ven (curve 1236). In the failed second verification test, Vwl_odd and Vwl_even = VvEr2 (curves 1217 and 1237).

[0176] During the first erase pulse 1205 of EV4, Vwl_odd is set to Ven (curve 1218) and Vwl_even is set to Vinh (curve 1238). No verification test is performed between erase pulses 1205 and 1206.

[0177] During the second erase pulse 1206 of EV4, Vwl_odd is set to Vinh (curve 1219) and Vwl_even is set to Ven (curve 1239). In the second verification test, indicated by Pass2, Vwl_odd and Vwl_even = VvEr2 (curves 1220 and 1240). This triggers the completion of the erase operation.

[0178] Voltage signal 1250 represents the voltage Vsgd / sgs applied to the SGD and SGS transistors of the block. In one approach, this voltage floats during each erase pulse, as indicated by dashed line 1251, for example, during erase pulse 1201. The voltage can be coupled to a level such as 12V as the channel voltage increases. During verification testing, these transistors are driven to the pass voltage to provide a transistor in a strongly conductive state, thereby allowing sensing, as indicated by curve 1252, for example, during the first verification test of EV1.

[0179] Voltage signal 1260 represents the bit line voltage Vwl, which can float, for example, during erase pulse 1201, as indicated by dashed line 1261. Vwl can also be coupled as the channel voltage increases. During verification testing, Vwl is driven to a level such as 0.5V for sensing, thereby allowing current to flow in the NAND string, as indicated by curve 1262, for example, during the first verification test of EV1.

[0180] For the option of using GIDL to charge the channel, the SGD and / or SGS transistors can be driven with a positive voltage such as 8V while the erase pulse is applied to the bit line and / or substrate.

[0181] EV1 and EV2 are one or more initial erase-verification iterations of the erase operation using full word line erasure, and EV3 and EV4 are one or more additional erase-verification iterations of the erase operation using odd and even word lines erasure.

[0182] Figure 13 It shows the relationship with Figure 11B and Figure 11D Exemplary waveforms in a consistent erase operation. Five erase-verify iterations EV1-EV5 are shown as an example, where the erase operation completes after EV5. EV1 and EV2 are examples of one or more consecutive erase-verify iterations in the full word line phase of the erase operation, where methods such as... Figure 8D The full word line verification in the process, and EV3-EV5 are examples of one or more consecutive erase-verify iterations in the odd and even word line phases of the erase operation, where methods such as Figure 8E and Figure 8F The process of verifying the odd and even word lines in the code.

[0183] Voltage signal 1300 represents Verase. Erase pulses 1301, 1302, 1303, 1304, 1305, 1306 and 1307 have values ​​of Verase1, Verase2, Verase3, Verase4, Verase5 respectively.

[0184] Voltage signals 1310 and 1330 represent Vwl_odd and Vwl_even, respectively. During the erase pulse 1301 of EV1, Vwl_odd and Vwl_even are set to Ven, as represented by curves 1311 and 1331, respectively. In the first verification test that fails, Vwl_odd and Vwl_even = VvEr1 (curves 1312 and 1332). During the erase pulse 1302 of EV2, Vwl_odd and Vwl_even are set to Ven, as represented by curves 1313 and 1333, respectively. In the first verification test that passes, indicated by Pass1, Vwl_odd and Vwl_even = VvEr1 (curves 1314 and 1334). This triggers the parity phase of the erase operation.

[0185] During the first erase pulse 1303 of EV3, Vwl_odd is set to Ven (curve 1315) and Vwl_even is set to Vinh (curve 1335). In the second verification test performed for odd-numbered lines and which failed, Vwl_odd = VvEr2 (curve 1316) and Vwl_even = Vread (curve 1336). During the second erase pulse 1304 of EV3, Vwl_odd is set to Vinh (curve 1317) and Vwl_even is set to Ven (curve 1337). In the second verification test performed for even-numbered lines and which failed, Vwl_odd = Vread (curve 1318) and Vwl_even = VvEr2 (curve 1338).

[0186] During the first erase pulse 1305 of EV4, Vwl_odd is set to Ven (curve 1319) and Vwl_even is set to Vinh (curve 1339). In the second verification test performed for odd-numbered lines and passing as indicated by Pass2, Vwl_odd = VvEr2 (curve 1320) and Vwl_even = Vread (curve 1340). During the second erase pulse 1306 of EV4, Vwl_odd is set to Vinh (curve 1321) and Vwl_even is set to Ven (curve 1341). In the second verification test performed for even-numbered lines and failing, Vwl_odd = Vread (curve 1322) and Vwl_even = VvEr2 (curve 1342).

[0187] During the single erase pulse 1307 of EV5, Vwl_odd is set to Vinh (curve 1323) and Vwl_even is set to Ven (curve 1343). In the second verification test performed for even-numbered lines and passed as indicated by Pass2, Vwl_odd = Vread (curve 1324) and Vwl_even = VvEr2 (curve 1344).

[0188] In this example, for instance, the odd-numbered lines in EV4 and the even-numbered lines in EV5 pass the second verification test. Therefore, the erase-verification iteration where the memory cell connected to the odd-numbered line passes the second verification test can be different from the erase-verification iteration where the memory cell connected to the even-numbered line passes the second verification test. In one method, the control circuitry is configured to suppress further erasure of the memory cell connected to the odd-numbered line when the memory cell connected to the odd-numbered line passes the second verification test in the erase-verification iteration, which is different from the erase-verification iteration where the memory cell connected to the even-numbered line passes the second verification test. Alternatively, the erase-verification iteration where the memory cell connected to the odd-numbered line passes the second verification test can be the same as the erase-verification iteration where the memory cell connected to the even-numbered line passes the second verification test.

[0189] Voltage signal 1350 represents the voltage Vsgd / sgs applied to the SGD and SGS transistors of the block. In one approach, this voltage floats during each erase pulse, as indicated by dashed line 1351, for example, during erase pulse 1301. The voltage can be coupled to levels such as 12V as the channel voltage increases. During verification testing, these transistors are driven to the pass voltage to provide a transistor in a strongly conductive state, thereby allowing sensing, as indicated by curve 1352, for example, during the first verification test of EV1.

[0190] Voltage signal 1360 represents the bit line voltage Vwl, which can float, for example, during erase pulse 1301, as indicated by dashed line 1361. Vwl can also be coupled as the channel voltage increases. During verification testing, Vwl is driven to a level such as 0.5V for sensing, thereby allowing current to flow in the NAND string, as indicated by curve 1362, for example, during the first verification test of EV1.

[0191] EV1 and EV2 are one or more initial erase-verify iterations of the erase operation, and EV3-EV5 are one or more additional erase-verify iterations of the erase operation.

[0192] In Figure 12 and Figure 13 In one consistent approach, multiple memory cells are arranged in a NAND string; each NAND string includes a channel; and control circuitry is configured to charge the channel by increasing the number of cells in a set of erase-verify iterations during a first and second phase of an erase operation. For example, the control circuitry may be configured to apply an erase voltage to the NAND string using an incremental step pulse erase.

[0193] Therefore, it can be seen that in one specific embodiment, an apparatus includes: a control circuit configured to be connected to a plurality of word lines connected to a plurality of memory cells, the control circuit being configured to: perform a full word line phase of the erase operation, wherein memory cells connected to each word line are simultaneously erased in one or more of the plurality of erase-verification iterations until an erase milestone of the plurality of memory cells is reached; and in response to the plurality of memory cells reaching an erase milestone, perform an odd-even word line phase of the erase operation, wherein memory cells connected to odd-numbered word lines among the plurality of word lines are erased separately from memory cells connected to even-numbered word lines among the plurality of word lines in one or more of the plurality of erase-verification iterations.

[0194] In another specific implementation, a method includes: performing one or more initial erase-verification iterations of an erase operation on a plurality of memory cells until the plurality of memory cells pass a first verification test, the first verification test testing a threshold voltage of the plurality of memory cells relative to a first voltage, a plurality of word lines being connected to the plurality of memory cells, and each of the one or more initial erase-verification iterations simultaneously erasing memory cells connected to each of the plurality of word lines; and when the first verification test is passed, performing one or more additional erase-verification iterations of an erase operation on the plurality of memory cells until the plurality of memory cells pass a second verification test, the second verification test testing a threshold voltage of the plurality of memory cells relative to a second voltage lower than the first voltage, and each of the one or more additional erase-verification iterations erasing memory cells connected to odd-numbered word lines separately from memory cells connected to even-numbered word lines.

[0195] In another embodiment, an apparatus includes: a control circuit configured to be connected to a plurality of word lines connected to a plurality of memory cells, and configured to: erase the plurality of memory cells in a first phase of the erase operation until a threshold voltage of the plurality of memory cells drops below a first voltage; and in response to the threshold voltage of the plurality of memory cells dropping below the first voltage, erase the plurality of memory cells in a second phase of the erase operation until the threshold voltage of the plurality of memory cells drops below a second voltage, the second voltage being less than the first voltage, wherein each of the plurality of word lines is simultaneously biased for erasing in the first phase, and odd-numbered word lines are biased for erasing separately from even-numbered word lines in the second phase.

[0196] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus for performing an erase operation, comprising: control circuitry (110, 122) configured to be connected to a plurality of word lines (WL0-WL95) connected to a plurality of memory cells (703-714, 723-734, 743-754, 763-774), and to perform, for the plurality of memory cells, a plurality of erase-verify iterations in an erase operation, the circuitry configured to: perform a full word line phase of the erase operation in which memory cells connected to each of the word lines are simultaneously erased in one or more of the plurality of erase-verify iterations until an erase milestone of the plurality of memory cells is reached; and in response to the plurality of memory cells reaching the erase milestone, perform an odd-even word line phase of the erase operation in which memory cells connected to odd word lines (WL1, WL3...WL95) of the plurality of word lines are erased separately from memory cells connected to even word lines of the plurality of word lines in one or more of the plurality of erase-verify iterations; and wherein the control circuitry is configured to perform a first verify test on the plurality of memory cells during the full word line phase of the erase operation, and to perform a second verify test on the plurality of memory cells during the odd-even word line phase of the erase operation; the first verify test is configured to test threshold voltages of the plurality of memory cells relative to a first voltage (VvEr1); and the second verify test is configured to test threshold voltages of the plurality of memory cells relative to a second voltage (VvEr2) that is lower than the first voltage; and wherein the control circuitry is configured to simultaneously perform the first verify test on the memory cells connected to each of the plurality of word lines during the full word line phase of the erase operation, and to separately perform the second verify test on memory cells connected to the odd word lines (WL1, WL3...WL95) from memory cells connected to the even word lines (WL0, WL2...WL94) during the odd-even word line phase of the erase operation; and wherein the control circuitry is configured to refrain from further erasing the memory cells connected to the odd word lines when the memory cells connected to the odd word lines pass the second verify test in an erase-verify iteration that is different from an erase-verify iteration in which the memory cells connected to the even word lines pass the second verify test.

2. The apparatus of claim 1, wherein: the control circuitry is configured to determine that the milestone is reached when the plurality of memory cells pass the first verify test.

3. The apparatus of claim 1 or 2, wherein: the control circuitry is configured to determine that the erase operation is complete when the plurality of memory cells pass the second verify test.

4. The apparatus of claim 1 or 2, wherein: the control circuit is configured to determine that the milestone is reached when a threshold number of erase-verify iterations have been completed.

5. The apparatus of claim 1 or 2, wherein: the control circuit is configured to adjust the first voltage based on a number of program-erase cycles of the plurality of memory cells; and the first voltage is a decreasing function of the number of program-erase cycles.

6. The apparatus of claim 1 or 2, wherein: the control circuit is configured to sense a temperature and adjust the first voltage based on the temperature; and the first voltage is an increasing function of the temperature.

7. The apparatus of claim 1 or 2, wherein: the control circuit is configured to set the first voltage as an increasing function of a number of data states to which the plurality of memory cells are to be programmed.

8. The apparatus of claim 1 or 2, wherein: the control circuit (122) is located on one die (127) and the plurality of memory cells are located on another die (108).

9. A method for performing an erase operation, comprising: performing one or more initial erase-verify iterations (EV1, EV2) of an erase operation on a plurality of memory cells (703-714, 723-734, 743-754, 763-774) until the plurality of memory cells pass a first verify test, the first verify test testing threshold voltages of the plurality of memory cells with respect to a first voltage (VvEr1), a plurality of word lines (WL0-WL95) being connected to the plurality of memory cells, and each of the one or more initial erase-verify iterations erasing memory cells connected to each of the plurality of word lines simultaneously; when passing the first verify test, performing one or more additional erase-verify iterations (EV3, EV4) of the erase operation on the plurality of memory cells until the plurality of memory cells pass a second verify test, the second verify test testing threshold voltages of the plurality of memory cells with respect to a second voltage (VvEr2) lower than the first voltage, and each of the one or more additional erase-verify iterations erasing memory cells connected to odd word lines (WL1, WL2...WL95) of the plurality of word lines separately from memory cells connected to even word lines (WL0, WL2...WL94) of the plurality of word lines; performing the first verify test on the memory cells connected to each of the plurality of word lines simultaneously in each of the one or more initial erase-verify iterations; and performing the second verify test on memory cells connected to odd word lines of the plurality of word lines separately from memory cells connected to even word lines of the plurality of word lines in the one or more additional erase-verify iterations; and wherein the method further comprises inhibiting the memory cells connected to the odd digit line from further erasing when the memory cells connected to the odd digit line pass the second verify test in an erase-verify iteration that is different from an erase-verify iteration in which the memory cells connected to the even digit line pass the second verify test.

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