Refresh operation of memory cells based on read error sensitivity

Abstract

Apparatuses and techniques are described for periodically refreshing word line voltages in blocks of memory cells based on the susceptibility of the blocks to read errors. One source of read errors is delayed read disturbance, which is caused by low word line voltages during idle periods of a memory device. In one aspect, the periodic refresh operation is optimized based on factors such as the number of bits per cell in the block and the number of program-erase (P-E) cycles. For example, at high P-E cycles, the magnitude of the refresh voltage for a single-level cell (SLC) block can be 0 V or lower, while the magnitude of the refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage.

Description

BACKGROUND

[0001] The present technology relates to storage devices and operations of memory devices.

[0002] Semiconductor memory devices have become more prevalent for use in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials, such as floating gates, or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in three-dimensional (3D) stacked memory structures, or arranged horizontally in two-dimensional (2D) memory structures. One example of a 3D memory structure is a bit cost scalable (BiCS) architecture that includes a stack of alternating conductive layers and dielectric layers.

[0004] For example, memory devices include memory cells that can be arranged in blocks. However, there are various challenges in operating such memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0005] FIG. 1A is a block diagram of an example memory device.

[0006] FIG. 1B depicts an example of a temperature sensing circuit 116 of FIG. 1A

[0007] FIG. 2 is a block diagram showing one embodiment of a sensing block 51 of FIG. 1A

[0008] FIG. 3 shows an example implementation of a power control circuit 115 of FIG. 1A

[0009] FIG. 4 is a perspective view of a memory device 400 including blocks BLKO-BLK3 of FIG. 3 in an example 3D configuration.

[0010] FIG. 5 depicts an example transistor 520.

[0011] FIG. 6 shows an example cross-sectional view of a portion of a block BLKO of FIG. 4 including NAND strings 700n and 710n.

[0012] FIG. 7A depicts a portion of a block BLKO of FIG. 4 and FIG. 6 ​​​An exemplary view of a NAND string in a consistent block BLK0.

[0013] FIG. 7B An exemplary view of memory cells in a sub-block SB0 connected to FIG. 7A WL3 with respective NAND strings, bit lines, and sense circuitry.

[0014] FIG. 8A An exemplary Vth distribution of SLC memory cells storing one bit per cell.

[0015] FIG. 8B An exemplary Vth distribution of MLC memory cells storing two bits per cell.

[0016] FIG. 8C An exemplary Vth distribution of MLC memory cells storing three bits per cell.

[0017] FIG. 9A A plot of the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations, showing the effect of delay read disturbance (DRD) for low ambient temperature and a small number of P-E cycles.

[0018] FIG. 9B A plot of the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations, showing the effect of DRD for low ambient temperature and a large number of P-E cycles.

[0019] FIG. 9C A plot of the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations, showing the effect of DRD for high ambient temperature and a small number of P-E cycles.

[0020] FIG. 9D A plot of the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations, showing the effect of DRD for high ambient temperature and a large number of P-E cycles.

[0021] FIG. 10 A plot of the maximum upper tail Vth of erased state memory cells as a function of the number of read operations for the case of a refresh operation with high amplitude Vread (plot 1000), a refresh operation with medium amplitude Vint (plot 1001), and a refresh operation with low amplitude Vss = 0 V (plot 1002).

[0022] FIG. 11A A flowchart of an exemplary process for refreshing word line voltages.

[0023] FIG. 11B Depicting FIG. 1A An exemplary table of storage locations 119 for each unit bit.

[0024] FIG. 11C Depicting FIG. 1A An exemplary table of the refresh voltage amplitude setting circuit 127.

[0025] FIG. 12A The first example of a voltage signal during a read operation is depicted.

[0026] FIG. 12B A second example of a voltage signal during a readout operation is depicted.

[0027] FIG. 13 Examples of word line voltages during refresh operations for high, medium, and low amplitude pulses are depicted.

[0028] FIG. 14A Examples of word line voltages during read operations and refresh operations with high-amplitude pulses Vread are depicted.

[0029] FIG. 14B Examples of word line voltages during read operations and refresh operations with medium-amplitude pulses Vint are depicted.

[0030] FIG. 14C Examples of word line voltages during read operations and refresh operations with low-amplitude pulses Vss are depicted.

[0031] FIG. 15 Examples of SLC and MLC blocks in a refresh operation are depicted. Detailed Implementation

[0032] This invention describes an apparatus and technique for periodically refreshing word line voltages in a memory device.

[0033] In memory devices, memory cells can be arranged in, for example, FIG. 4 In the block sequence depicted, memory cells can be joined together, for example, in a NAND string, such as... FIG. 7A As depicted. Furthermore, memory cells can be arranged in a 2D or 3D structure. In a 3D memory structure, memory cells can be arranged as stacked vertical NAND strings, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have a pillar shape intersecting the word lines to form a memory cell. In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate. The memory cells in the block can undergo programming, reading, and erasing operations.

[0034] Each memory cell can be associated with a data state in accordance with write data in a program command. Based on the data state of that memory cell, the memory cell will remain in an erased state or be programmed to a programmed data state. For example, in a one bit per cell block, there are two data states, including an erased state and a programmed state. See, e.g., Figure 1 1 1 of FIG. 8A In a two bit per cell block, there are four data states, including an erased state and three higher data states, referred to as A, B, and C data states. See, e.g., Figure 1 12 of FIG. 8B In a three bit per cell block, there are eight data states, including an erased state and seven higher data states, referred to as A, B, C, D, E, F, and G data states. See, e.g., Figure 1 13 of FIG. 8C In a four bit per cell block, there are sixteen data states, including an erased state and fifteen higher data states. Blocks with a single bit per cell are referred to as single level cell (SLC) blocks, while blocks with multiple bits per cell are referred to as multi-level cell (MLC) blocks.

[0035] After programming a memory cell, the data can be read back in a read operation. The read operation can involve applying a series of read voltages to a selected word line while sensing circuitry determines whether the cells connected to the selected word line are in a conductive state (on) or a non-conductive state (off). If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level expected to be between the threshold voltages of adjacent data states. During the read operation, a pass voltage, such as 8-9V, is applied to unselected word lines to provide associated memory cells in a strong conductive state.

[0036] However, when the memory cell is idle, the Vth of the memory cell can vary between programming operations or read operations based on a change in the word line voltage. In particular, the word line voltage can rise from a channel coupling of the NAND string. For example, in one possible coupling rise mechanism, a pass voltage is applied to a word line during a sensing operation, such as a read operation or a verify test of a program operation, and subsequently ramps down to 0V. This ramp down causes a falling coupling of the channel voltage. See, e.g., curve 1231 of FIG. 12A and curve 1271 of FIG. 12B This falling coupling subsequently dissipates, and the channel voltage increases to a nominal level, close to 0V, while the word line voltage is floating. See, e.g., curve 1232 of FIG. 12A and curve 1272 of FIG. 12B This causes the word line voltage to rise to a positive voltage, such as about 4-5V. See, e.g., curve 1204 of FIG. 12A and curve 1272 of FIG. 12BThe positive word line voltage is desirable because it tends to keep the Vth of the memory cell at a stable level. Over time, such as over the course of a few minutes, the word line voltage discharges, causing the Vth of the memory cell to shift. See FIG. 8A-8C .

[0037] When the word line voltage of a block is at a discharge, the block is in a first read or cold read state. This can occur when the memory device is powered on or when the coupled-up word line voltage has discharged after a sensing operation. When the word line voltage of a block is coupled-up, the block is in a second read or hot read state. This can occur only after a sensing operation has been performed.

[0038] A refresh operation can be performed periodically to maintain the positive word line voltage during idle time. The refresh operation can involve applying a refresh voltage to a word line at a pass voltage level and subsequently floating the word line voltage.

[0039] However, a type of disturbance known as delayed read disturbance (DRD) can increase the upper tail Vth of the erased state memory cells, as depicted in FIG. 8A to FIG. 8C 、 FIG. 9A to FIG. 9D and FIG. 10 This can cause uncorrectable read errors. This disturbance is caused by the coupled-up word line voltage that provides weak programming of the erased state memory cells. DRD is a function of various factors, such as the number of read operations, the time period between consecutive read operations, the number of program-erase (P-E) cycles, and the operating temperature of the memory device. DRD is particularly severe for heavily cycled blocks and can accelerate in severity at higher temperatures. DRD is also more severe for SLC blocks than for MLC blocks.

[0040] The technology provided herein addresses the above and other issues. In one aspect, a periodic refresh operation is performed for a block, where the refresh operation is optimized based on factors such as the number of bits per cell in the block, temperature, and the number of P-E cycles. For example, the magnitude of the refresh voltage in the refresh operation can be lower for SLC blocks than for MLC blocks. The magnitude can also be lower when the number of P-E cycles is high. The magnitude can range from a high voltage (such as a read pass voltage) to an intermediate voltage to 0 V or even a negative voltage.

[0041] These and other features will be discussed further below.

[0042] FIG. 1Ais a block diagram of an example memory device. The memory device 100, such as a non-volatile storage system, can include one or more memory dies 108. The memory die 108 or chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuits 128 include a plurality of sense blocks 51, 52,..., 53 (sense circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., removable storage card) as the one or more memory dies 108. The controller can be separate from the memory dies. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 141.

[0043] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure can include one or more arrays of memory cells including a 3D array. The memory structure can include a monolithic 3D memory structure in which multiple levels of memory are formed above (rather than in) a single substrate, such as a wafer, without intervening substrates. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure can be in a non-volatile memory device having circuitry associated with operation of the memory cells, whether the associated circuitry is above the substrate or within the substrate.

[0044] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine, an on-chip address decoder 114, a power control module 115 (power control circuitry), a temperature sensing circuit 116, a clocking circuit 117, a P-E cycle count circuit 118, a storage location for bits per cell 119, and a refresh voltage amp. setting circuit 127. Storage area 113 can be provided, for example, for operational parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented in hardware (e.g., electrical circuitry) entirely.

[0045] On-chip address decoders 114 provide an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 115 controls the power and voltages provided to the word lines, select gate lines, bit lines, and source lines during memory operations. The power control module can include drivers for the word lines, SGS and SGD transistors, and source lines. See also FIG. 3 A. In one approach, the sense block can include a bit line driver. Temperature sensing circuit 116 can detect the temperature of the memory device during the life of the memory device (e.g., every minute). Timing circuit 117 can count time and determine when the elapsed time has passed a threshold for initiating a refresh operation of the block as discussed herein. See, e.g., FIG. 11A of group 1107 in FIG. 11.

[0046] P-E cycle count circuit 118 can track the number of program-erase (P-E) cycles of the block and classify the block into a class based on the number of P-E cycles. For example, the block can be classified into a first class, a second class, and a third class that respectively represent the beginning, middle, and end of the life of the block. The classification of the SLC block can be different from the classification of the MLC block because the SLC block can typically experience more P-E cycles in its life than the MLC block. Further, the blocks can be reclassified periodically and the number of blocks per group can change over time. In another example, the block is classified based on whether the number of P-E cycles is above or below a threshold. See, e.g., threshold P-E_thl and P-E_th2 in FIG. 11. FIG. 11C

[0047] Per-cell bit storage location 119 can include a table that indicates the number of bits per cell for each block of memory cells. See, e.g., FIG. 11B In one approach, the block is classified as an SLC block or an MLC block.

[0048] Refresh voltage amplitude setting circuit 127 can use information for circuits 116-119 and circuit 127 to set the optimal refresh voltage amplitude for each block in a group of blocks involved in a refresh operation. For example, circuit 127 can evaluate the number of P-E cycles for a block by comparing the number of P-E cycles to a threshold, such as P-E_thl for SLC blocks and P-E_th2 for MLC blocks. See FIG. 11C Circuit 127 can also take into account the number of bits per cell from per-cell bit storage location 119 and the temperature from temperature sensing circuit 116.

[0049] See example implementations of temperature sensing circuits in FIG. 1B ​Circuits 116-119 and circuit 127 can include hardware, software, and / or firmware for performing processes described herein.

[0050] In some implementations, some of the components can be combined. In various designs, one or more of the components other than the memory structure 126, alone or in combination, can be considered at least one control circuit that is configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit can include any of the control circuit 110, state machine 112, decoders 114 and 132, power control module 115, temperature sensing circuit 116, timing circuit 117, P-E cycle count circuit 118, sense blocks 51, 52...53, read / write circuits 128, controller 122, etc., or combinations thereof.

[0051] The off-chip controller 122 (circuit in one embodiment) can include a processor 122e, memory such as ROM 122a and RAM 122b, and an error correcting code (ECC) engine 245. The ECC engine can correct a number of read errors. The RAM 122b can be DRAM that includes storage locations 122c for uncommitted data. During programming, a copy of the data to be programmed is stored in the storage locations 122c until the programming is successfully completed. In response to successful completion, the data is erased from the storage locations and committed or released to the memory cell blocks. The storage locations 122c can store one or more word lines of data.

[0052] A memory interface 122d can also be provided. The memory interface, in communication with the ROM, RAM, and processor, is circuitry that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide a buffer, isolate electrical surges, latch I / O, etc. The processor can issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122d.

[0053] The memory, such as the ROM 122a and RAM 122b, in the controller 122 includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively, or in addition, the processor can access code from a subset of the memory structure 126a, such as a reserved area of memory cells in one or more word lines.

[0054] For example, the controller can use code to access the memory structure, such as for program, read, and erase operations. The code can include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller and enables the controller to access the memory structure during a boot or startup process. The controller can use the code to control one or more memory structures. Upon power up, the processor 122e fetches the boot code from the ROM 122a or subset 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0055] The controller, e.g., RAM 122b and / or control circuitry 110, can store parameters indicative of the expected number of failing bits in a block. These parameters can include, for example, the number of bits per cell stored in the memory cells, a portion of the word lines programmed in a block or sub-block, a portion of the sub-blocks programmed in a block, a strength of ECC processing used to store and read data in a block, a duration of a pre-read voltage pulse if used, and a read precision, such as bit line or word line voltage settling time and number of sense passes.

[0056] Generally, the control code can include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms, including those discussed further below. The control circuitry can be configured to execute instructions for performing the functions described herein.

[0057] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable memory devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0058] Other types of non-volatile memory can be used in addition to NAND flash memory.

[0059] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in a NAND or a NOR configuration.

[0060] The memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as resistive-switching or phase-change materials, and optional steering elements, such as diodes or transistors. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0061] Multiple memory elements can be configured so that they are connected in series or so that each element can be individually accessed. By way of non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and SG transistors.

[0062] A NAND memory array can be configured so that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0063] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure.

[0064] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an x-y directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer on or in which layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. As non-limiting examples, the substrate can comprise a semiconductor, such as silicon.

[0065] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in a non-regular or non-orthogonal configuration. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0066] A 3D memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the major surfaces of the substrate and the x and y directions are substantially parallel to the major surfaces of the substrate).

[0067] As a non-limiting example, a 3D memory structure can be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns that extend substantially perpendicular to the major surfaces of the substrate, i.e., in the y direction) with each column having a plurality of memory elements. These columns can be arranged, for example, in a 2D configuration in the x-y plane, resulting in a 3D arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0068] By way of non-limiting example, in a 3D NAND memory array, the memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations are contemplated in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. A 3D memory array can also be designed in a NOR configuration and in a ReRAM configuration.

[0069] Generally, in a monolithic 3D memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic 3D memory array can also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor, such as silicon. In a monolithic 3D array, the layers that make up each memory device level of the array are generally formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic 3D memory array can be shared between the memory device levels or have intervening layers between the memory device levels.

[0070] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of one another. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Further, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0071] Associated circuitry is generally needed to operate and communicate with the memory elements. As a non-limiting example, a memory device can have circuitry for controlling and driving the memory elements to implement functions such as programming and reading. This associated circuitry can be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations can be positioned on a separate controller chip and / or on the same substrate as the memory elements.

[0072] Those skilled in the art will recognize that the technology is not limited to the described 2D example structures and 3D example structures, but encompasses all relevant memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0073] FIG. 1B An example of a temperature sensing circuit 116 of FIG. 1A is depicted. The circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is a temperature-based output voltage provided to an analog-to-digital (ADC) converter 129. Vbg is a temperature- independent voltage. Voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels by a resistive divider circuit.

[0074] The ADC compares Voutput to the voltage levels and selects the closest match in the voltage levels and outputs the corresponding digital value (VTemp) to the processor 122e. This is the data indicative of the temperature of the memory device. In one approach, the ROM fuses 123 store data that relates the matching voltage levels to temperatures. The processor then uses the temperature to set temperature-based parameters in the memory device, such as by utilizing a comparison circuit.

[0075] Vbg is obtained by adding the base-emitter voltage (Vbe) across transistor 131b and the voltage drop across resistor R2. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are equal in size and arranged in a current mirror configuration so that currents II and I2 are substantially equal. It follows that Vbg = Vbe + R2 x I2 and II = Ve / Rl, so I2 = Ve / Rl. Thus, Vbg = Vbe + R2 x kT ln(N) / Rl x q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge. The source of transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0076] FIG. 2 is a block diagram illustrating FIG. 1A one embodiment of a sense block 51. Individual sense blocks 51 are divided into one or more core portions, referred to as sense circuits 60-63 or sense amplifiers, and a common portion, referred to as a management circuit 190. In one embodiment, each sense circuit is connected to a respective bit line and NAND string, and the common management circuit 190 is connected to a group of multiple (e.g., four or eight) sense circuits. Each sense circuit in the group communicates with the associated management circuit via a data bus 176. Thus, there is one or more management circuits in communication with a group of sense circuits of storage elements (memory cells).

[0077] As an example, the sense circuit 60 operates during a program cycle to provide a pre-charge / program-inhibit voltage to unselected bit lines or a program-enable voltage to selected bit lines. An unselected bit line is connected to an unselected NAND string and an unselected memory cell therein. The unselected memory cell can be a memory cell in an unselected NAND string where the memory cell is connected to a selected or unselected word line. The unselected memory cell can also be a memory cell in a selected NAND string where the memory cell is connected to an unselected word line. A selected bit line is connected to a selected NAND string and a selected memory cell therein.

[0078] The sense circuit 60 also operates during a verify test in a program cycle to sense the memory cell to determine if it has completed programming by reaching an assigned data state (e.g., as indicated by its Vth exceeding a verify voltage for the assigned data state). The sense circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sense circuit performs sensing by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0079] The sense circuit can include a selector 56 or switch connected to the transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and the drain 57 of the transistor 55, the transistor can operate as a pass gate or bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, when pre-charging and inhibiting an unselected NAND string, a program-inhibit voltage such as 1V to 2V can be passed. Alternatively, a program-enable voltage such as 0V can be passed to allow programming in a selected NAND string. The selector 56 can pass a supply voltage Vdd (e.g., 3V to 4V) to the control gate of the transistor 55 to cause it to operate as a pass gate.

[0080] When the voltage at the control gate is lower than the voltage on the drain, the transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage on the control gate 58 and Vth (e.g., 1 V) is the threshold voltage of the transistor 55. This assumes the source line is at 0 V. This mode can be used during sensing operations such as read operations and verify operations. Thus, the bit line voltage is set by the transistor 55 based on the voltage output by the selector 56. For example, the selector 56 can pass Vbl_sense+Vth (e.g., 1.5 V) to the transistor 55 to provide Vbl_sense (e.g., 0.5 V) on the bit line. The Vbl selector 173 can pass a relatively high voltage such as Vdd to the drain 57 that is higher than the control gate voltage on the transistor 55 to provide a source follower mode during sensing operations.

[0081] The Vbl selector 173 can pass one or more voltage signals. For example, the Vbl selector can pass a program-inhibit voltage signal that increases from an initial voltage (e.g., 0 V) to a program-inhibit voltage (e.g., the voltage Vbl_inh for the respective bit line of the unselected NAND string during a program cycle). The Vbl selector 173 can pass a program-enable voltage signal such as 0 V for the respective bit line of the selected NAND string during a program cycle. For example, the Vbl selector can select from the voltage signals of the BL voltage drivers 340 in FIG. 3B based on commands from the processor 192. FIG. 3 The Vbl selector 173 can pass one or more voltage signals. For example, the Vbl selector can pass a program-inhibit voltage signal that increases from an initial voltage (e.g., 0 V) to a program-inhibit voltage (e.g., the voltage Vbl_inh for the respective bit line of the unselected NAND string during a program cycle). The Vbl selector 173 can pass a program-enable voltage signal such as 0 V for the respective bit line of the selected NAND string during a program cycle. For example, the Vbl selector can select from the voltage signals of the BL voltage drivers 340 in FIG. 3B based on commands from the processor 192.

[0082] In one approach, the selector 56 of each sense circuit can be controlled separately from the selectors of other sense circuits. The Vbl selector 173 of each sense circuit can also be controlled separately from the Vbl selectors of other sense circuits.

[0083] During sensing, the sense node 171 is charged up to an initial voltage Vsense init, such as 3V. The sense node is then passed to the bit line via the transistor 55, and the amount of decay of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state. Specifically, the comparison circuit 175 determines the amount of decay by comparing the sense node voltage to a trip voltage at the time of sensing. If the sense node voltage decays below the trip voltage Vtrip, then the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, then the memory cell is in a non-conductive state and its Vth is above the verify voltage. The sense node latch 172 is set to 0 or 1, for example, by the comparison circuit 175 based on whether the memory cell is in a conductive state or a non-conductive state, respectively. The data in the sense node latch can be read by the processor 192 and used to update the trip latch 174 bit. Subsequently, for the next program loop, the processor can use the bits in the trip latch and the assigned data states in the latches 194-197 to determine whether the memory cell and NAND string are selected for or not selected for programming in the program loop, thereby passing the appropriate enable or inhibit bit line voltage to the bit line, respectively. The latches 194-197 can be considered data latches or user data latches because they store data to be programmed into the memory cells.

[0084] The management circuit 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sense circuits 60-63, respectively, and an I / O interface 196 coupled between the sets of data latches and the data bus 120. One set of three data latches can be provided for each sense circuit, e.g., including separate latches LDL, MDL, and UDL. In some cases, a different number of data latches can be used. In a three bits per cell implementation, LDL stores bits for a lower page of data, MDL stores bits for a middle page of data, and UDL stores bits for an upper page of data.

[0085] The processor 192 performs computations, such as determining data stored in the sensed memory cells and storing the determined data in the sets of data latches. Each set of data latches 194-197 is used to store data bits determined by the processor 192 during a read operation and to store data bits imported from the data bus 120 during a program operation, which represent write data to be programmed into the memory. The I / O interface 196 provides an interface between the data latches 194-197 and the data bus 120.

[0086] During a read, the operation of the system is under the control of the state machine 112, which controls the provision of different control gate voltages to the addressed memory cells. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuitry can trip at one of these voltages, and the corresponding output will be provided from the sense circuitry to the processor 192 via the data bus 176. At this point, the processor 192 determines the resulting memory state by considering the trip event of the sense circuitry and the information regarding the control gate voltage applied from the state machine via the input line 193. It then calculates the binary encoding of the memory state, and stores the resulting data bits into the data latches 194-197.

[0087] Some implementations can include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) such that each of the output lines is wired or wired together. In some embodiments, the output lines are inverted before being connected to the line or lines. This configuration enables a quick determination of when the programming process is complete during a program verify test, as the receiving state machine of the line or lines can determine when all programmed bits have reached the desired level. For example, when each bit reaches its required level, a logical zero for that bit will be sent to the line or lines (or data one is inverted). When all bits output a data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor is in communication with eight sense circuits, the state machine needs to read the line or lines eight times, or add logic to the processor 192 to accumulate the results of the relevant bit lines such that the state machine only needs to read the line or lines once. Similarly, by choosing the logic levels correctly, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0088] During a program or verify operation of the memory cells, data to be programmed (write data) is stored in the data latch set 194-197 from the data bus 120. During reprogramming, a respective set of data latches of the memory cells can store data indicating when to enable the memory cells to reprogram based on the programming pulse magnitude.

[0089] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0090] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0091] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0092] FIG. 3 It shows FIG. 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to memory cell blocks in a plane is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four associated blocks BLK0 to BLK3, and another set of four associated blocks BLK4 to BLK7. The blocks may be in one or more planes. FIG. 1ARow decoders 124 provide voltages to word lines and select gate control lines of each block via pass transistors 322. The row decoders provide control signals to the pass transistors that connect the blocks to the row decoders. In one approach, the pass transistors of each set of blocks are controlled by a common control gate voltage. Thus, the pass transistors of a set of blocks are all on or off at a given time. If the pass transistors are on, then the voltage from the row decoder is provided to the corresponding control gate line or word line. If the pass transistors are off, then the row decoder is disconnected from the corresponding control gate line or word line so that the voltage floats on the corresponding control gate line or word line.

[0093] For example, control gate line 312 is connected to pass transistor set 313-316, e.g., switches, which in turn are connected to control gate lines of BLK4-BLK7, respectively. Control gate line 317 is connected to pass transistor set 318-321, which in turn are connected to control gate lines of BLK0-BLK3, respectively.

[0094] Generally, programming or read operations are performed on one selected block at a time in a block. Erase operations can be performed on selected blocks or sub-blocks.

[0095] The row decoders can connect global control lines 302 to pre-switch local control lines 325 of each block. The pre-switch local control lines 325 are connected to pass transistors 322, which in turn are connected to post-switch local control lines 303, such as word lines. For example, for BLK0, pre-switch local control line 325a is connected to post-switch local control line 303a via pass transistor 318. Voltages are provided on the global control lines of many voltage drivers. Some voltage drivers can provide voltages to switches 350 connected to the global control lines. The pass transistors 324 are controlled to pass the voltages from the voltage drivers to the switches 350.

[0096] In some cases, due to the capacitance of the word lines, the delay in changing the word line voltage based on the voltage on global control lines 302 and pre-switch local control lines 325 can change. If the pass transistors 322 turn off too quickly, then in some cases it can be necessary to meet timing requirements while the word line voltage can not reach the voltage on global control lines 302 and pre-switch local control lines 325. See, for example, curves 1243 and 1243a in FIG. 12B

[0097] The voltage drivers can include a selected data word line (WL) driver 347 that provides voltages on selected data word lines during programming or read operations. Driver 347 can provide a pre-charge voltage and a program voltage on WLn during a program cycle of a program operation. Driver 348 can be used for unselected data word lines, and dummy word line drivers 349 and 349a can be used to provide voltages on dummy word lines D0 and D1, respectively, during a program operation.​FIG. 6 Dummy word lines WLDD and WLDS in the middle are provided with voltages. For example, driver 348 can be used to apply a pre-charge voltage and a pass voltage on unselected word lines during a program cycle of a program operation.

[0098] The voltage driver can also include a separate SGD driver for each sub-block. For example, such as in FIG. 7A In the middle, SGD drivers 346, 346a, 346b, and 346c can be provided for SB0, SB1, SB2, and SB3, respectively. The SGD drivers provide voltages to control lines connected to control gates of SGD transistors (drain-side select gate transistors). In one option, SGS driver 345 is common for different sub-blocks in a block, and provides voltages to control lines connected to control gates of SGS transistors (source-side select gate transistors).

[0099] Various components including the row decoders can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0100] P-well voltage driver 330 provides voltage Vp-well to p+ contact 612b in p-well region 611b, for example, via conductive path 682. See FIG. 6 In one approach, p-well region 611b is common for a block. The block also shares a set of bit lines 342. Source line (SL) voltage driver 331 provides voltage Vsl to n+ contact 612c in p-well region 611b, for example, via local interconnect 651.

[0101] Bit line voltage driver 340 includes voltage sources that provide voltages to bit lines 342, such as program-inhibit voltage signals, program-enable voltage signals, pre-charge voltage signals, and voltages for sensing. The program-inhibit voltage signals have a magnitude of 1V to 2V, for example, to inhibit programming in a NAND string. The program-enable voltage signals have a magnitude of 0V, for example, to allow programming to occur to selected memory cells in a NAND string. The pre-charge voltage signals have a magnitude of 1V to 2V, for example, to pre-charge a channel of a NAND string. The voltages for sensing can have a magnitude of 0.5V, for example, to facilitate sensing of selected memory cells in a NAND string during a read operation or a verify test.

[0102] In a stacked memory device such as shown in FIG. 4 to FIG. 7B In a stacked memory device such as shown in

[0103] FIG. 4 are included in an exemplary 3D configuration FIG. 3 A perspective view of a memory device 400 including exemplary blocks BLKO-BLK3 in an exemplary 3D configuration. On a substrate are exemplary blocks BLKO-BLK3 of memory cells (storage elements), and a peripheral region with circuitry used by the blocks. Peripheral region 404 extends along edges of each block, while peripheral region 405 is at an end of the set of blocks. The circuitry can include voltage drivers that can be connected to control gate layers, bit lines, and source lines of the blocks. In one approach, control gate layers at a common height in a block are commonly driven. Substrate 451 can also carry circuitry below the blocks and one or more lower metal layers patterned in conductive paths to carry signals of the circuitry. The blocks are formed in a middle region 452 of the memory device. In an upper region 453 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block includes a stacked region of memory cells, with alternating layers of the stack representing word lines. In one possible approach, each block has opposite delaminated sides from which vertical contacts extend upward to the upper metal layers to form connections to the conductive paths. Although four blocks are depicted as an example, two or more blocks extending in the x-direction and / or y-direction can be used.

[0104] In one possible approach, the blocks are in a plane, and a length of the plane in the x-direction represents a direction in which signal paths to word lines extend in the one or more upper metal layers (word line or SGD line direction), and a width of the plane in the y-direction represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (bit line direction). The z-direction represents a height of the memory device. The blocks can also be arranged in multiple planes.

[0105] FIG. 5 An exemplary transistor 520 is depicted. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and can represent, for example, a memory cell or a select gate transistor. The drain end of the transistor is optionally connected to a bit line BL via one or more other transistors in a NAND string, and the source end of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string.

[0106] FIG. 6 A perspective view of a memory device 400 including exemplary blocks BLKO-BLK3 in an exemplary 3D configuration. On a substrate are exemplary blocks BLKO-BLK3 of memory cells (storage elements), and a peripheral region with circuitry used by the blocks. Peripheral region 404 extends along edges of each block, while peripheral region 405 is at an end of the set of blocks. The circuitry can include voltage drivers that can be connected to control gate layers, bit lines, and source lines of the blocks. In one approach, control gate layers at a common height in a block are commonly driven. Substrate 451 can also carry circuitry below the blocks and one or more lower metal layers patterned in conductive paths to carry signals of the circuitry. The blocks are formed in a middle region 452 of the memory device. In an upper region 453 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block includes a stacked region of memory cells, with alternating layers of the stack representing word lines. In one possible approach, each block has opposite delaminated sides from which vertical contacts extend upward to the upper metal layers to form connections to the conductive paths. Although four blocks are depicted as an example, two or more blocks extending in the x-direction and / or y-direction can be used. FIG. 4An example cross-sectional view of a portion of a block BLK0 including NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. The layers can be rectangular slabs with a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0107] The stack is depicted as including one layer but can optionally include one or more layers of alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers in which memory holes are formed during fabrication.

[0108] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). Conductive layers that connect to control gates of memory cells are referred to as word lines, and conductive layers that connect to control gates of source-side select gate transistors and control gates of drain-side select gate transistors are referred to as source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers that connect to dummy memory cells that are not eligible to store user data. Dummy memory cells can have the same structure as data memory cells, but a controller considers the memory cells ineligible to store any type of data including user data. One or more dummy memory cells can be provided at the drain end and / or source end of a NAND string of memory cells to provide a gradual transition of channel voltage gradient. WL0-WL95 are data word lines that connect to data memory cells that are eligible to store user data. The stack includes ninety-six data word lines, by way of example only. DL is an example dielectric layer.

[0109] The top 610t and bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0110] NAND strings are formed by etching memory holes in the stack and then depositing multiple thin layers of material along the sidewalls of the memory holes. Memory cells are formed in regions where a word line intersects the multiple thin layers, and select gate transistors are formed in regions where SGS and SGD control lines intersect the multiple thin layers. For example, drain-side select gate transistors 716 are formed where SGD control lines intersect the multiple thin layers, source-side select gate transistors 701 are formed where SGS control lines intersect the multiple thin layers, the topmost data memory cells 714 are formed where WL95 word lines intersect the multiple thin layers, and the bottommost data memory cells 703 are formed where WL0 word lines intersect the multiple thin layers.

[0111] The multiple thin layers can form a ring-shaped layer and can be deposited, for example, using atomic layer deposition. For example, the layers can include a blocking oxide layer 663, a charge trapping layer 664 or film such as silicon nitride (Si3N4) or other nitride, a tunnel layer 665 (e.g., gate oxide), and a channel 660 (e.g., including polysilicon). A dielectric core 666 (e.g., containing silicon dioxide) can also be provided. The word lines or control lines can contain metal such as tungsten. In this example, all layers are disposed in the memory hole. In other approaches, some of the layers can be disposed in the word line or control line layers. The multiple thin layers form a pillar active area (AA) of a NAND string.

[0112] The stack is formed on a substrate 611. In one approach, the substrate includes a p-well region 611a connected to a source end of the NAND string (see also FIG. 3 ). The p-well region can include an epitaxial region 612 that extends upward adjacent to the source side select gate transistor. The p-well region can include an n+ contact 612c connected to a local interconnect 651 to receive a source line voltage and a p+ contact 612b connected to a conductive path 682 to receive a p-well voltage. The local interconnect 651 can include a conductive material 651b such as metal surrounded by insulating material 651a to prevent metal conduction with adjacent word lines. In one possible implementation, the p-well region is formed in an n-well 613 which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0113] The NAND string 700n has a source end 700s connected to a p-well at the bottom 610b of the stack 610. The NAND string 700n also has a drain end 700d connected to a bit line BLO via a bit line contact 680 containing n-type material at the top 610t of the stack.

[0114] The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate.

[0115] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. The electrons are attracted from the channel into the charge trapping layer and through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0116] FIG. 7A An example of a NAND string is shown in FIG. 4 and FIG. 6Example view of NAND strings in a consistent block BLK0. The NAND strings are arranged in a 3D configuration in sub-blocks of the block. Each sub-block includes a plurality of NAND strings, one example NAND string is depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have a common data word line, dummy word line, and select gate line. Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. The NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Programming of the block can be performed based on a word line and sub-block programming order. One option is to program memory cells in different word line portions located in different sub-blocks one sub-block at a time, before programming memory cells of the next word line. For example, this can involve programming WL0 in SB0, SB1, SB2, and SB2, then programming WL1 in SB0, SB1, SB2, and SB2, and so on. For example, the word line programming order can start at WL0 (source end word line) and end at WL95 (drain end word line). FIG. 6

[0117] Another option is to program each sub-block before proceeding to the next sub-block. For example, SB0 can be programmed in WL0-WL95, then SB1 can be programmed in WL0-WL95, and so on.

[0118] The NAND strings 700n, 710n, 720n, and 730n have channels 700a, 710a, 720a, and 730a, respectively. Additionally, the NAND string 700n includes SGS transistor 701, dummy memory cell 702, data memory cells 703-714, dummy memory cell 715, and SGD transistor 716. The NAND string 710n includes SGS transistor 721, dummy memory cell 722, data memory cells 723-734, dummy memory cell 735, and SGD transistor 736. The NAND string 720n includes SGS transistor 741, dummy memory cell 742, data memory cells 743-754, dummy memory cell 755, and SGD transistor 756. The NAND string 730n includes SGS transistor 761, dummy memory cell 762, data memory cells 763-774, dummy memory cell 775, and SGD transistor 776.

[0119] ​This example depicts one SGD transistor at the drain end of each NAND string, and one SGS transistor at the source end of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(l), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND strings.

[0120] FIG. 7B An example view of memory cells connected to WL3 in sub-block SB0 of FIG. 7A , with respective NAND strings, bit lines, and sense circuits is depicted. Depicted are memory cells 706 and channel 700a of NAND string 700n in SB0 of FIG. 7A , with respective bit line BL0. SB0 also includes memory cells 706a, 706b, and 706c in NAND strings 701n, 702n, and 703n, respectively, with channels 700b, 700c, and 700d, respectively, and connected to bit lines BL1, BL2, and BL3, respectively. Bit lines BL0-BL3 are connected to sense circuits 60-63, respectively, of FIG. 2 .

[0121] In a program cycle, memory cells 706 and 706a can be examples of selected memory cells and unselected memory cells, respectively, in which case NAND strings 700n and 701n are examples of selected NAND strings and unselected NAND strings, respectively, and bit lines BL0 and BL1 are examples of selected bit lines and unselected bit lines, respectively.

[0122] FIG. 8A An example Vth distribution of SLC memory cells storing one bit per cell is depicted. In FIG. 8A to FIG. 8C , the vertical axis represents a plurality of memory cells on a log scale, and the horizontal axis represents Vth in volts.

[0123] During a program operation, a final Vth distribution can be achieved through the use of one or more program passes. For example, each stage can use incremental step pulse programming. During a program pass, program-verify iterations are performed on selected word lines. A program-verify iteration includes a program portion, in which a program voltage is applied to a word line, followed by a verify portion, in which one or more verify tests are performed. Each program state has a verify voltage that is used for the verify test for the state.

[0124] Vth distributions 800 and 800a represent the erase state (Er) without DRD and with DRD, respectively. The higher Vth distribution 800a is caused by DRD, which increases the Vth of the upper tail of erase state memory cells. Vth distributions 801 and 801a represent the programmed data state (P) in the second read state and the first read state, respectively. The higher Vth distribution 801 is caused by the coupling up of the word line voltage, while the lower Vth distribution 801a is caused by the discharge in the word line voltage.

[0125] The verify voltage for the programmed state is Vv, and the read voltage used to distinguish between the two states is Vr.

[0126] DRD is primarily caused by residual voltages on the word line. These voltages cause temperature dependent charge jumps through traps created in the dielectric tunnel layer 665 during program-erase cycling. As long as the residual word line voltage persists, this charge movement under the influence of the residual word line voltage causes a continuous shift of the erase state up.

[0127] For SLC blocks that are particularly heavily cycled, DRD presents a reliability problem and can prevent a memory device from meeting read disturb and data retention specifications. Furthermore, DRD is expected to become severe in future memory devices if no appropriate countermeasures such as provided herein are implemented. DRD also impacts the specification on operating temperature and the qualification of memory devices based on P-E cycling. Moreover, as MLC endurance requirements increase, DRD is expected to become a concern for MLC blocks as well.

[0128] Charging the residual word line voltage helps to reduce DRD, but pushes the memory cells into the undesired first read state. Since the read voltage is tuned to the second read state, this increases read errors. The solution is to optimize the refresh operation that provides that the memory cells remain in the second read state. The refresh operation can be performed by applying a voltage signal to the word line with a high enough amplitude to maintain the programmed memory cells in the second read state while minimizing DRD of the erase state memory cells.

[0129] The optimal solution observes that the blocks that are more susceptible to DRD errors are different from the blocks that are more susceptible to first read state errors. For example, SLC blocks (especially at end of life) are more susceptible to DRD than MLC blocks. Furthermore, MLC blocks are more susceptible to first read state errors than SLC blocks due to the smaller margin between the Vth distributions of adjacent data states.

[0130] The optimal solution can adjust the amplitude of the refresh voltage signal for a block based on the block's susceptibility to DRD and first read state errors. The range of amplitudes can be from a high level such as Vread (typically the highest voltage applied to unselected word lines during read operations) to Vss or even a negative voltage (if available on the memory device).

[0131] Three example scenarios are discussed. In a first scenario, the amplitude is a high level such as Vread. This can be optimal for blocks that are not susceptible to DRD errors but need to be kept in the second read state to avoid first read state errors. Such blocks can include MLC blocks with relatively low P-E cycles, e.g., less than FIG. 11C P-E_th2 in Equation (1). See FIG. 14A is an example scenario for read operations and refresh operations using a high amplitude refresh voltage signal.

[0132] In a second scenario, the amplitude is a mid-level such as Vint1 or Vint2( FIG. 11C ). This can be optimal for blocks that are susceptible to DRD errors but need to be kept in the second read state strictly. Such blocks can include, e.g., MLC blocks with three bits per cell, MLC blocks with relatively higher P-E cycles, e.g., greater than FIG. 11C P-E_th2 in Equation (1). See FIG. 14B is an example scenario for read operations and refresh operations using a mid amplitude refresh voltage signal.

[0133] In this case, a tradeoff is made between requiring both DRD errors and first state errors to be reduced. The mid-level between the highest amplitude and the lowest amplitude can be determined based on factors such as workload (e.g., expected frequency of read operations). If the expected frequency is relatively high, the mid-level can be relatively low because read operations will provide frequent coupling up of the word line voltage. The mid-level should maintain the word line voltage in a range that is high enough to avoid first read state errors and low enough to avoid DRD errors.

[0134] In a third scenario, the amplitude is a low level such as Vss or a negative voltage( FIG. 11C ). This can be optimal for blocks that are heavily susceptible to DRD errors and do not need to be kept in the second read state. Such blocks can include SLC blocks with relatively high P-E cycles, e.g., greater than FIG. 11C P-E_th1 in Equation (1). See FIG. 14C is an example scenario for read operations and refresh operations using a mid amplitude refresh voltage signal.

[0135] In general, the characteristics of the refresh voltage signal, such as amplitude, frequency, and duration or pulse width, can be optimized taking into account factors such as operating temperature, user / system workload, number of P-E cycles, and number of bits per cell. In addition, these characteristics can be adjusted dynamically based on factors such as temperature variations, which can affect the discharge rate of the word line voltage and the magnitude of the DRD. These characteristics can also be adjusted based on variations in the precision with which programming operations affect the edges between data states, and thus the susceptibility to DRD or first read state errors. Higher precision corresponds to larger edges between adjacent states. One example of increasing the programming precision and reducing the Vth width of each state is to perform multiple pass programming operations instead of a single pass programming operation, and / or program using smaller step sizes.

[0136] For example, for MLC blocks with relatively high precision and relatively high edges between adjacent states, the refresh voltage amplitude can be relatively low. In this case, a larger Vth downshift can reduce the DRD of the erased state without causing first read state errors of the programmed states.

[0137] FIG. 8B An example Vth distribution of an MLC memory cell storing two bits per cell is depicted. The Er state without DRD and with DRD is represented by Vth distributions 810 and 810a, respectively. The A-C data states are represented by Vth distributions 811-813 in the second read state, and by Vth distributions 811a-813a in the first read state, respectively. The verify voltages are VvA-VvC, and the read voltages are VrA-VrC. In this example, the Vth downshift due to the first read state is larger for the A state than for the B and C states. For the higher data states, the coupling up voltage between the channel and the word line is typically not enough to trap more electrons in the charge trapping layer of the memory cell. This is due to the shielding effect of the electrons already present in the charge trapping layer of the memory cell and providing a high Vth. In contrast, the electrons in the charge trapping layer are more easily attracted to the control gate / word line, away from the channel, resulting in a Vth downshift. Data retention effects can also be used for the higher data states, where charges are lost from the charge trapping layer, resulting in a Vth downshift.

[0138] FIG. 8C An example Vth distribution of an MLC memory cell storing three bits per cell is depicted. The Er state without DRD and with DRD is represented by Vth distributions 820 and 820a, respectively. The A-G data states are represented by Vth distributions 821-827 in the second read state, and by Vth distributions 821a-827a in the first read state, respectively.

[0139] The verify voltages for the A-G states are VvA-VvG, respectively. A set of read voltages for the A-G states includes VrA-VrG, respectively. In one approach, the read voltages can be optimized for the second read state. In this example, the Vth distributions 821-824 for the A-D states, respectively, have a Vth shift up at the second read state. The Vth distributions 826 and 827 for the F and G states, respectively, have a small Vth shift down at the second read state.

[0140] In general, using a high amplitude for periodic refresh voltage operations is helpful for memory cells having programmed data states, but is harmful for erased state memory cells. Thus, the amplitude should be set carefully based on various factors as described herein.

[0141] In FIG. 9A to FIG. 9D the vertical axis represents the average upper tail Vth, and the horizontal axis represents the number of read operations, ranging from 1-300. The low and high ambient temperatures T_low and T_high are -25°C and 85°C, respectively, and the small and large number of P-E cycles are 37.5K and 100K, respectively. The data is for SLC blocks. No read refresh operations are performed.

[0142] FIG. 9A Curves depicting the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations are shown, illustrating the effect of delay read disturbance for low ambient temperature and small number of P-E cycles. Curves 900, 901, and 902 represent a delay of 2 minutes, 5 minutes, and 10 minutes between read operations, respectively. When the time between read operations is longer, the Vth increases faster as a function of the number of read operations.

[0143] FIG. 9B Curves depicting the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations are shown, illustrating the effect of DRD for low ambient temperature and large number of P-E cycles. Curves 910, 911, and 912 represent a delay of 2 minutes, 5 minutes, and 10 minutes between read operations, respectively. As FIG. 9A shown, the Vth increases faster when the time between read operations is longer. Additionally, the maximum value of Vth, e.g., the amount of shift up, is larger when the number of P-E cycles is larger. Thus, the DRD increases as the number of P-E cycles increases.

[0144] FIG. 9C Curves depicting the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations are shown, illustrating the effect of DRD for low ambient temperature and small number of P-E cycles. Curves 920, 921, and 922 represent a delay of 2 minutes, 5 minutes, and 10 minutes between read operations, respectively. AsFIG. 9A In contrast, when the number of P-E cycles is small, the maximum value of Vth is larger at higher temperatures.

[0145] FIG. 9D Curves depicting the average upper tail Vth of erased state memory cells as a function of the number of read operations and the delay between read operations, showing the effect of DRD on high ambient temperature and a large number of P-E cycles. Curves 930, 931, and 932 represent a delay of 2 minutes, 5 minutes, and 10 minutes between read operations, respectively. In contrast to the curves of FIG. 9, the DRD increases faster with P-E cycles when the temperature is higher. FIG. 9B In contrast, when the number of P-E cycles is small, the maximum value of Vth is larger at higher temperatures. FIG. 9A to FIG. 9D It is also indicated that the DRD increases faster with P-E cycles when the temperature is higher.

[0146] FIG. 10 Curves depicting the maximum upper tail Vth of erased state memory cells as a function of the number of read operations, for the case of refresh operations with high amplitude Vread(curve 1000), refresh operations with medium amplitude Vint(curve 1001), and refresh operations with low amplitude Vss=0V(curve 1002). This example applies to a block of SLC memory cells with 100K P-E cycles, high temperature of 85°C, and a time of one minute between read operations. In the case of curves 1000, 1001, and 1002, there is a refresh operation after each read operation.

[0147] These curves indicate that refresh operations can be optimized by adjusting the amplitude of the refresh voltage pulse, and that refresh operations with a smaller refresh voltage amplitude can help reduce read errors of erased state memory cells. For example, curve 1001 shows that a medium amplitude results in a small decrease in Vth compared to performing refresh with a high amplitude Vread(curve 1000). For example, the medium amplitude can be between Vread=8-9V and Vss=0V, in a range such as 3-5V. Curve 1002 shows that the amplitude of Vss results in a large decrease in Vth of the SLC block.

[0148] In general, refresh operations with different amplitudes lower than Vreadimprove DRD to different degrees. Since DRD is a direct function of the word line voltage, if all other variables remain constant, curve 1000 is the case with the highest word line voltage, which is optimal for keeping the program memory cells in the second read state. Curve 1002 is the case that works best for reducing DRD, since it uses the lowest word line voltage. However, this is undesirable for the program memory cells, since it tends to move these program memory cells to the first read state. Curve 1001 represents a tradeoff that slightly improves DRD while keeping the word line voltage high enough to substantially maintain the program memory cells in the second read state.

[0149] FIG. 9A to FIG. 9D It also indicates that refresh operations can be optimized based on the number of PE cycles and temperature. One approach involves performing refresh operations simultaneously in groups with similar numbers of PE cycles. If an active wear leveling process is used, this group can remain constant as the number of PE cycles increases. The number of PE cycles can be tracked by enterprise solid-state drives (SSDs) and client-side SSD systems. One solution is to classify blocks into different categories, such as beginning, middle, and end of their lifespan, based on PE cycle counter readings. Once the number of PE cycles for a block reaches a threshold, the blocks can be regrouped. Additionally, the size of a group of blocks refreshed simultaneously can vary for different categories, as the block count in each category can be different. For example, there might be fewer end-of-life blocks compared to beginning-of-life blocks.

[0150] Furthermore, blocks with the same number of bits per cell can be grouped during a refresh operation. For example, SLC blocks can be in one group, and MLC blocks can be in another. However, refresh operations can be performed on both SLC and MLC blocks simultaneously. The refresh voltage can be optimized based on the number of bits per cell in the block.

[0151] Further optimization can be performed based on temperature.

[0152] However, refresh operations typically offer the optimal trade-off between minimizing read errors caused by DRD (Read Defects) and read errors caused by memory cells entering the first read state. As a system-level solution, refresh operations can be selectively applied to blocks at higher risk of DRD or first read state errors without affecting other blocks. Refresh operations are applicable to both SLC and MLC. Refresh operations can increase the read disturbance tolerance of memory devices without increasing errors due to the transition from the first read state to the second read state, which is particularly important for end-of-life blocks. Refresh operations can help reduce failure rates, increase throughput, and reduce ECC frequency, thereby lowering costs.

[0153] FIG. 11A A flowchart depicts an exemplary process for refreshing word line voltages. Step 1100 involves programming multiple blocks, such as... FIG. 4 BLK0-BLK4 in the block. Step 1101 includes storing data indicating the number of bits per unit for each block. For example, see BLK0-BLK4. FIG. 1A Storage location 119 for each unit bit and FIG. 11B The table. Step 1102 includes, for example, reading a block in response to receiving a read command from the host device. Step 1103 includes waiting for the next read command, after which step 1102 is repeated. Read commands may be issued at different times.

[0154] Step 1104 begins a program operation for a block. This can involve step 1105, which includes accessing a storage location to identify a number of bits per cell for each block. For example, this can involve determining whether each block has SLC cells or MLC cells. There can also be MLC blocks with different numbers of bits per cell, where n is the number of bits per cell. The refresh voltage can be optimized based on different values of n. This step can involve accessing a storage location 119 of bits per cell and a table of FIG. 1A FIG. 11B Step 1106 includes applying a voltage signal to a word line of each block, where an amplitude of the voltage signal is based on the number of bits per cell. Step 1106 indicates that there is an option to set the amplitude based on a number of P-E cycles and / or a temperature. Step 1107 indicates that a wait is implemented before starting the next refresh operation. This wait can also be optimized for the block based on factors such as the number of bits per cell.

[0155] In general, refresh operations can be performed at fixed intervals. Although refresh operations are scheduled only when a read command is received at the same time, the read command can take priority and the refresh operation can be performed after the read operation is completed. See, for example, FIG. 14A to FIG. 14C .

[0156] FIG. 11B An exemplary table of storage location 119 of bits per cell of FIG. 1A In a memory device, both SLC blocks and MLC blocks can be provided. One way to distinguish the blocks is to provide a table that cross-references a block identifier to an indication of the number of bits per cell. In this example, FIG. 4 Block BLKO of

[0157] FIG. 11C An exemplary table of refresh voltage amplitude setting circuit 127 of FIG. 1A As mentioned, the amplitude of the refresh voltage signal in a refresh operation can be optimized based on factors such as the number of bits per cell and the number of P-E cycles. In this example, the number of P-E cycles is classified as low if it is below a threshold, or high if it is above a threshold. For example, for SLC blocks, the amplitude of the refresh voltage signal can be a first intermediate voltage Vinti if the number of P-E cycles is below a first threshold P-E_thi. If the number of P-E cycles is at or above P-E_thi, the amplitude of the refresh voltage signal can be 0V or a negative voltage. This approach is based on an increased susceptibility to DRD errors at higher P-E cycles for SLC blocks, where the second read state is relatively less attended to be maintained. Effectively reducing the refresh voltage signal to a low level such as Vss helps to reduce DRD errors as the number of P-E cycles increases.

[0158] ​For MLC blocks, if the number of P-E cycles is below a second threshold P-E_th2, the amplitude of the refresh voltage signal is Vhigh, such as Vread. If the number of P-E cycles is at or above P-E_th2, the amplitude of the refresh voltage signal is a second intermediate voltage Vint2. In one approach, P-E_th2 < P-E_thl. For example, P-E_th2 can be 5K in an MLC block with a 10K P-E cycle lifetime, and P-E_thl can be 50K in an SLC block with a 100K P-E cycle lifetime. Additionally, Vint2 can be greater than Vintl, as it is often more important to maintain the second read state of programmed memory cells for MLC blocks than for SLC blocks.

[0159] This approach also balances the need to maintain the second read state of programmed cells while accounting for the increased susceptibility to DRD errors at higher P-E cycles of erased cells in MLC blocks. Reducing the refresh voltage signal to an intermediate level helps to reduce DRD errors while maintaining the second read state of programmed cells as P-E cycles increase. Reducing the refresh voltage signal to 0V would likely be an overcompensation of reducing DRD errors at the expense of increasing first read state errors.

[0160] FIG. 12A A first example of voltage signals in a read operation is depicted. In this example, the word line voltage is reset to 0V at the beginning of the read operation (curve 1200). VWL represents the word line voltage. For selected word lines (word lines are read), curves 1206 and 1207 represent the read voltages for VrA and VrE, respectively. These voltages are used in the lower page read operation of memory cells storing three bits per cell. During each read voltage, a sense operation occurs. Curve 1208 represents the selected word line voltage returning to 0V.

[0161] Curves 1201-1203 represent the voltage signals for unselected word lines. The voltage increases to Vread at tO (curve 1201), remains at Vread until t5, and then decreases to 0V at t5-t6 (curve 1203). This decrease in the word line voltage couples down the channel, such that the channel voltage (Vch) decreases (curve 1231). From t6-t7, the channel voltage recovers back to 0V (curve 1232), resulting in a corresponding coupling up of the word line voltage (curve 1204). Subsequently, the word line voltage gradually decreases (curve 1205). For VWL, the solid line represents the driven voltage, and the dashed line represents the floating voltage.

[0162] Curves 1210 and 1211 represent the voltage signals for the SGD and SGS select gate transistors. The voltage is increased at to to a peak level to provide the select gate transistors in the on state, held at the peak level until t3, and then decreased to 0V at t3-t4. When Vsg is decreased below the cutoff voltage Vcutoff at t4, the select gate transistors become non-conductive, causing the channel voltage to float. The non-conduction of the select gate transistors before the unselected word line voltage is decreased at t5-t6 allows the channel voltage coupling to be reduced, as discussed. In another option, the select gate transistors are not non-conducted before the unselected word line voltage is decreased. In this case, when the unselected word line voltage drops below the Vth of the memory cells, the channel voltage begins to float, thereby shutting off the corresponding channel region.

[0163] Curve 1220 represents the voltage signal for the bit line. Vbl can be set at a small positive level such as 0.5V during a read operation.

[0164] Curves 1230-1233 represent the channel voltage. In one approach at to-t5, Vch can be set to a similar level as Vbl. As mentioned, Vch can be decreased at t5-t6 and then restored at t6-t7 due to the voltage transition on the unselected word line.

[0165] FIG. 12B A second example of voltage signals in a read operation is depicted. In this example, the unselected word line voltage transitions from a floating level (curve 1240) to Vread (curve 1242). For the selected word line, the voltage signal is initially at 0V (curve 1246) and then at the read voltage of VrA and VrE (curves 1247 and 1248, respectively). Curve 1249 represents the selected word line voltage transitioning to a final voltage Vfinal at t6.

[0166] Curves 1241-1243 represent the voltage signals for the unselected word line. The voltage is increased at to to Vread (curve 1241), held at Vread until t5, and then decreased to Vfinal (curve 1243) at t5-t6. This decrease in the word line voltage couples down the channel, causing the channel voltage (Vch) to decrease at t5-t6 (curve 1271). However, this down-coupling is less than the down-coupling in FIG. 12A From t6-t7, the channel voltage recovers back to 0V (curve 1272), causing a corresponding up-coupling of the word line voltage (curve 1244). Subsequently, the word line voltage is gradually decreased (curve 1245).

[0167] As with the example of FIG. 12, the channel voltage is not restored to 0V until after the read operation is complete. This is because the channel voltage is not restored to 0V until after the selected word line voltage is decreased to Vfinal. In this example, the selected word line voltage is decreased to Vfinal at t7-t8, and the channel voltage is restored to 0V at t8-t9. FIG. 3As mentioned, the delay of the word line voltage can be changed based on the change in the voltage on the pre-switch local control line due to the capacitance of the word line. For example, curve 1243a can represent the change in the pre-switch local control line 325a, and curve 1243 can represent the corresponding change in the word line voltage. The voltage of the pre-switch local control line 325a is cut off at t6 before the word line voltage has a chance to reach 0V or other minimum level of the pre-switch local control line. In contrast, the word line voltage reaches a final level of Vfinal > 0V.

[0168] Curves 1250 and 1251 represent the voltage signals of the SGD and SGS select gate transistors, similar to the corresponding voltage signals in FIG. 12A

[0169] Curve 1260 represents the voltage signal of the bit line, similar to the corresponding voltage signal in FIG. 12A

[0170] Curves 1270-1273 represent the channel voltages, similar to the corresponding voltages in FIG. 12A

[0171] FIG. 13 Examples of word line voltages during refresh operations for high, medium, and low amplitude pulses are depicted (curves 1300, 1310, and 1320, respectively). The dashed lines represent the floating voltage, and the solid lines represent the driven voltage. In curve 1300, curve 1301 represents the initial floating voltage of the word line of the block. The refresh operation starts at to, at which time the word line voltage is driven higher (curve 1302) to a high amplitude refresh voltage, such as Vread, then held at Vread (curve 1303) until t2, then driven lower to a final level of, for example, Vfinal (curve 1304) from t2 to t3. As discussed in connection with FIG. 12B the word line voltage can or can not reach the minimum level provided on the pre-switch control line. The word line voltage is then allowed to start floating at t3, where it floats higher (curve 1305), then starts discharging (curve 1306).

[0172] Refresh operations with high amplitude refresh voltages tend to increase the word line voltage, as depicted by comparing curves 1305 and 1306 to curve 1301. In particular, with high amplitude refresh voltages, the voltage signal is typically driven lower before being floated. This results in some discharge coupling of the channel and subsequent rise coupling of the channel and word line voltage. The rise coupling is added to the word line voltage as the floating starts to provide the increased voltage of curve 1305.

[0173] ​​​In curve 1310, two examples of initial floating voltage for the word line of the block are provided. Curve 1313 represents a low initial floating voltage, and curve 1311 represents a high initial floating voltage. The refresh operation starts at to when the word line voltage is driven higher (curve 1314) or lower (curve 1312) to Vint, then maintained at Vint (curve 1315) until t3. The word line voltage is then allowed to start floating at t3, where if the initial floating voltage is higher than Vint (curve 1311), the word line voltage can float slightly higher then discharge (curve 1316a), or if the initial floating voltage is lower than Vint (curve 1313), the word line voltage can discharge from the Vint level (curve 1316b). For example, Vint can represent Vintl or Vint2 from FIG. 11C

[0174] If the word line voltage is relatively low, the refresh operation with the mid-amplitude refresh voltage tends to increase the word line voltage, as depicted by comparing curve 1316b with curve 1313, or if the word line voltage is relatively high, the refresh operation tends to decrease the word line voltage, as depicted by comparing curve 1316a with curve 1311.

[0175] In the case of the mid-amplitude refresh voltage, the voltage signal can be driven lower before being floated, as in the case of curve 1312, so there is some drop coupling of the channel and subsequent rise coupling of the channel and word line voltage. The rise coupling is added to the word line voltage as the floating starts to provide a slightly increased voltage after t3 of curve 1316a. If the voltage signal is not driven lower before being floated, as in the case of curve 1314, there is no drop coupling of the channel and subsequent rise coupling of the channel and word line voltage.

[0176] In curve 1320, curve 1321 represents the initial floating voltage of the word line. The refresh operation starts at to when the word line voltage is driven lower (curve 1322) to a low-amplitude refresh voltage such as Vss, then maintained at Vss (curve 1323) until t3. The word line voltage is then allowed to start floating at t3, where the word line voltage can float slightly higher then discharge (curve 1324). The refresh operation with the low-amplitude refresh voltage tends to decrease the word line voltage, as depicted by comparing curve 1324 with curve 1321.

[0177] In the case of the low-amplitude refresh voltage, the voltage signal is typically driven lower before being floated, as in the case of curve 1322, so there is some drop coupling of the channel and subsequent rise coupling of the channel and word line voltage. The rise coupling is added to the word line voltage as the floating starts to provide an increased voltage after t3. In curve 1320, curve 1321 represents the initial floating voltage of the word line. The refresh operation starts at to when the word line voltage is driven lower (curve 1322) to a low-amplitude refresh voltage such as Vss, then maintained at Vss (curve 1323) until t3. The word line voltage is then allowed to start floating at t3, where the word line voltage can float slightly higher then discharge (curve 1324). The refresh operation with the low-amplitude refresh voltage tends to decrease the word line voltage, as depicted by comparing curve 1324 with curve 1321.

[0178] FIG. 14A to FIG. 14C Example time periods TP1-TP3 between refresh operations are depicted. The voltage signal for refresh operations is denoted by Rf, and the voltage signal for read operations is denoted by Rd.

[0179] Typically, refresh operations can be performed at fixed intervals as long as a read operation is not in progress. If a read operation is in progress, a wait can be implemented before performing a refresh operation, where the wait is less than the regular time period between refresh operations. In this example, the first through fourth refresh operations are performed at tl-t2, t3-t4, t7-t8, and tl l-tl2. The time period TP1 between the first read operation and the second read operation is equal to the time period TP2 between the second read operation and the third read operation. However, the time period TP3 between the third read operation and the fourth read operation is greater than TP1 and TP2 due to the wait caused by the read operation at t9-tlO.

[0180] Read operations are performed at t5-t6 and t9-tlO.

[0181] The solid line curves represent the drive voltage, and the dashed line curves represent the float voltage.

[0182] FIG. 14A An example of word line voltage during read operations and refresh operations with high amplitude pulses Vread is depicted. The high amplitude pulses of the refresh operations are represented by curves 1400, 1401, 1403, and 1405. Each refresh operation increases the word line voltage due to the use of high amplitude pulses. The Vread pulses of the read operations are represented by curves 1402 and 1404.

[0183] FIG. 14B An example of word line voltage during read operations and refresh operations with medium amplitude pulses Vint is depicted. The medium amplitude pulses of the refresh operations are represented by curves 1410, 1411, 1413, and 1415. Each refresh operation can increase or decrease the word line voltage due to the use of medium amplitude pulses. For example, the refresh pulses of curves 1410, 1413, and 1415 decrease the word line voltage, and the refresh pulse 1411 increases the word line voltage. The Vread pulses of the read operations are represented by curves 1412 and 1414.

[0184] FIG. 14C An example of word line voltage during read operations and refresh operations with low amplitude pulses Vss is depicted. The low amplitude pulses of the refresh operations are represented by curves 1420, 1421, 1423, and 1425. Each refresh operation decreases the word line voltage due to the use of low amplitude pulses. The Vread pulses of the read operations are represented by curves 1422 and 1424.

[0185] FIG. 15 An example of SLC blocks and MLC blocks in a refresh operation is depicted. An SLC block (e.g., BLKO) includes a set of memory cells 1500-1503, and a set of word lines 1505 connected to the set of memory cells. An MLC block (e.g., BLK1) includes a set of memory cells 1510-1513, and a set of word lines 1515 connected to the set of memory cells. The control circuit is configured to determine that BLKO stores one bit per cell and BLK1 stores multiple bits per cell, and is configured to periodically perform a refresh operation for both sets of word lines 1505 and 1515. Performing a refresh operation includes applying a voltage signal to the set of word lines, the voltage signal having an amplitude based on the number of bits stored per memory cell in the block. For example, the amplitude of the voltage signal applied to the set of word lines 1505 can be different than the amplitude of the voltage signal applied to the set of word lines 1515.

[0186] Thus, it can be seen in one implementation that an apparatus includes a set of memory cells arranged in NAND strings in a block, a word line connected to the set of memory cells, and a control circuit connected to the set of word lines. The control circuit is configured to determine a number of bits stored per memory cell in the block, and periodically perform a refresh operation for the set of word lines, performing a refresh operation including applying a voltage signal to the set of word lines, the voltage signal having an amplitude based on the number of bits stored per memory cell in the block.

[0187] In another implementation, a method includes determining that a first block of memory cells (BLKO) in a set of blocks (BLKO-BLK3) includes single-level memory cells (1500-1503), the single-level memory cells of the first block connected to a first set of word lines (1505), determining that a second block of memory cells in the set of blocks (BLK1) includes multi-level memory cells (1510-1513), the multi-level memory cells of the second block connected to a second set of word lines (1515), periodically performing a refresh operation for the first set of word lines including applying a voltage signal having a first amplitude (0V, Vintl) to the first set of word lines, and periodically performing a refresh operation for the second set of word lines including applying a voltage signal having a second amplitude (Vint2, Vhigh) higher than the first amplitude to the second set of word lines.

[0188] In another implementation, an apparatus includes a set of memory cells arranged in NAND strings in a block, word lines connected to the set of memory cells, and a control circuit connected to the set of word lines. The control circuit is configured to program the memory cells at a number of bits per cell, store data in a storage location indicative of the number of bits, access the data in conjunction with a refresh operation of the set of word lines, and apply, in the refresh operation, a voltage signal to the set of word lines, the voltage signal having an amplitude based on the data.

[0189] The foregoing detailed description of the application has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the application is intended to be defined by the claims appended hereto.

Claims

1. A refresh device, comprising: A set of memory cells (703-714, 723-734, 743-754, 763-774, 1500-1503, 1510-1513), the set of memory cells being arranged in NAND strings (700, 710n, 720n, 730n) within a block (BLK0-BLK3); A set of word lines (WL0-WL95, 1505, 1515) are connected to the set of memory cells; and Control circuitry (110, 122), connected to the set of word lines, is configured to: Determine the number of bits stored in each memory cell of the block; as well as Periodically perform refresh operations on the set of word lines, wherein performing the refresh operation includes applying voltage signals (1300, 1310, 1320) to the set of word lines, the voltage signals having amplitudes (Vread, Vint, Vss) based on the number of bits stored in each memory cell in the block, including applying a first amplitude voltage when the memory cell is a single-level memory cell, and applying a second amplitude voltage greater than the first amplitude when the memory cell is a multi-level memory cell; and The amplitude of the voltage signal is lower when the number of bits stored in each memory cell indicates that the memory cell is a multi-level memory cell, compared to when the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell.

2. The apparatus according to claim 1, wherein: The control circuit is configured to determine the number of program-erase cycles for the block; and When the number of bits stored in each memory cell indicates that the memory cell is a multi-level memory cell, the amplitude of the voltage signal when the number of program-erase cycles is less than a first threshold exceeds the amplitude of the voltage signal when the number of program-erase cycles is greater than the first threshold.

3. The apparatus according to claim 2, wherein: When the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell, the amplitude of the voltage signal when the number of program-erase cycles is below a second threshold exceeds the amplitude of the voltage signal when the number of program-erase cycles is above the second threshold; and The second threshold is greater than the first threshold.

4. The apparatus according to any one of claims 1 to 3, wherein: The amplitude of the voltage signal is not greater than a predetermined voltage when the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell; and When the number of bits stored in each memory cell indicates that the memory cell is a multilevel memory cell, the amplitude of the voltage signal is greater than the predetermined voltage.

5. The apparatus according to any one of claims 1 to 3, wherein: When the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell, the amplitude of the voltage signal does not exceed 0V; and When the number of bits stored in each memory cell indicates that the memory cell is a multilevel memory cell, the amplitude of the voltage signal is greater than 0V.

6. The apparatus according to any one of claims 1 to 3, wherein: When the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell, the amplitude of the voltage signal is less than 0V; and When the number of bits stored in each memory cell indicates that the memory cell is a multilevel memory cell, the amplitude of the voltage signal is greater than 0V.

7. The apparatus according to any one of claims 1 to 3, wherein: The block is located in a memory device (100), which includes multiple blocks (BLK0-BLK3). The number of bits stored in each memory cell varies across the multiple blocks; and Storage location (119) indicates the number of bits stored in each memory cell in each block of the block.

8. The apparatus according to any one of claims 1 to 3, wherein: The control circuit is configured to determine the workload of the read operation of the block, and to set the amplitude of the voltage signal to be relatively high when the workload is relatively low.

9. The apparatus according to any one of claims 1 to 3, wherein: The control circuit is configured to monitor the threshold voltage of the erased state memory cell in the set of memory cells, and to reduce the amplitude of the voltage signal when the monitoring indicates that the threshold voltage is increasing.

10. The apparatus according to any one of claims 1 to 3, wherein: The voltage signal has a duration based on the number of bits stored in each memory cell of the block; and The duration is relatively low when the number of bits stored in each memory cell is relatively high.

11. The apparatus according to any one of claims 1 to 3, wherein: The block is located in a memory device, which includes multiple blocks (BLK0-BLK3). Each of the plurality of blocks includes a set of memory cells arranged in NAND strings (700, 710n, 720n, 730n) and connected to a set of word lines (1505, 1515); The number of bits stored in each memory cell varies in different blocks of the plurality of blocks; and The control circuit is configured to periodically perform a refresh operation on the set of word lines for each block, the refresh operation comprising applying a voltage signal to the set of word lines for each block, the voltage signal having an amplitude based on the number of bits stored in each memory cell in the block, wherein the voltage signal applied to the different blocks has a different amplitude.

12. The apparatus according to any one of claims 1 to 3, wherein: The control circuit is configured to provide the voltage signal at a final level, which is a positive voltage, after providing the voltage signal at the amplitude of the refresh operation; and The control circuit is configured to float the voltage of the set of word lines after the voltage signal reaches the final level.

13. A refresh method, comprising: The first block (BLK0) of the set of blocks of memory cells (1500-1503) comprises single-level memory cells, and the single-level memory cells of the first block are connected to the first set of word lines (1505). The second block (BLK1) of the set of blocks of memory cells (1510-1513) includes multilevel memory cells, and the multilevel memory cells of the second block are connected to the second set of word lines (1515). Periodically perform refresh operations on the first group of word lines, including applying a voltage signal with a first amplitude to the first group of word lines; as well as Periodically perform refresh operations on the second group of word lines, including applying a voltage signal with a second amplitude that is higher than the first amplitude to the second group of word lines; and The amplitude of the voltage signal is lower when the number of bits stored in each memory cell indicates that the memory cell is a multi-level memory cell, compared to when the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell.

14. The method of claim 13, wherein: The first block of the determined memory cells includes single-level memory cells and the second block of the determined memory cells includes multi-level memory cells. The memory cell includes an access memory location (119) indicating the number of bits stored in each memory cell within each block of the set of blocks.

15. The method according to claim 13 or 14, further comprising: The number of program-erase cycles for the second block is determined, wherein the amplitude of the voltage signal is higher when the number of program-erase cycles is lower than the threshold compared to when the number of program-erase cycles is higher than the threshold.

16. A refresh device, comprising: A set of memory cells arranged in a NAND string within a block; A set of word lines, the set of word lines being connected to the set of memory cells; and A control circuit, connected to the set of word lines, is configured to: The memory cells are programmed using bits per memory cell; Store the data in a storage location that indicates the number of bits; Determine the number of programming-erase cycles for the block; The data is accessed by combining the refresh operation of the aforementioned set of character lines; as well as During the refresh operation, a voltage signal is applied to the set of word lines, the voltage signal having an amplitude based on the data, such that when the memory cell is programmed with a single bit of each memory cell and the number of program-erase cycles is higher than a threshold, the amplitude does not exceed 0 V, and The amplitude of the voltage signal is lower when the number of bits stored in each memory cell indicates that the memory cell is a multi-level memory cell, compared to when the number of bits stored in each memory cell indicates that the memory cell is a single-level memory cell.

17. The apparatus according to claim 16, wherein: When the quantity is higher than the threshold, the amplitude is greater than the amplitude when the quantity is not higher than the threshold.

18. The apparatus according to claim 16 or 17, wherein: The control circuit is configured as follows: When the memory cell is programmed to have multiple bits per memory cell, the amplitude is set to be greater than 0 V.

19. The apparatus according to claim 17, wherein: The control circuit is configured as follows: When the memory cell is programmed to be a single bit per memory cell, the amplitude is set to a positive voltage when the number of program-erase cycles is below the threshold.

20. The apparatus according to claim 16 or 17, wherein: The control circuit is configured as follows: When the memory cell is programmed to have multiple bits per memory cell, the amplitude is set to an intermediate voltage when the number of program-erase cycles is higher than the threshold, and the amplitude is set to a high voltage when the number of program-erase cycles is lower than the threshold, wherein the intermediate voltage is between 0 V and the high voltage.

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