3D Memory Device with a Via Structure Surrounded by a Perforated Dielectric Trench Structure and Method of Manufacturing the Same

Abstract

A three-dimensional memory device includes an alternating stack of insulating and conductive layers located above a substrate, a memory stack structure extending vertically through the alternating stack, a perforated dielectric trench structure extending vertically through the alternating stack, and an interconnection via structure that is laterally surrounded by the perforated dielectric trench structure and extends vertically through each insulating layer within the alternating stack. Each memory stack structure within the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the conductive layer. The perforated dielectric trench structure includes a plurality of lateral openings at each level of the insulating layer and does not include any openings at levels of the conductive layer. The interconnection via structure can be laterally surrounded by the perforated dielectric trench structure and can extend vertically through each insulating layer within the alternating stack.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority of U.S. Non - Provisional Patent Application Serial No. 16 / 735,854, filed on January 7, 2020, and of Continuation - in - Part Application No. 16 / 809,861, filed on March 5, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including via structures surrounded by perforated dielectric trench structures and methods of manufacturing the same. Background Art

[0004] Three - dimensional memory devices may include a memory stack structure. The memory stack structure is disposed over a substrate and extends through an alternating stack of insulating layers and conductive layers. The memory stack structure includes a vertical stack of memory elements disposed at levels of the conductive layers. Peripheral devices may be disposed on the substrate below the alternating stack and the memory stack structure. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a three - dimensional memory device including: an alternating stack of insulating layers and conductive layers disposed above a substrate; a memory stack structure extending vertically through the alternating stack, wherein each memory stack structure in the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements disposed at a level of the conductive layer; a perforated dielectric trench structure extending vertically through the alternating stack and including a plurality of lateral openings at each level of the insulating layer and not including any openings at the levels of the conductive layer; and an interconnect via structure laterally surrounded by the perforated dielectric trench structure and extending vertically through each insulating layer within the alternating stack and contacting a top surface of a lower - level metal interconnect structure.

[0006] According to another aspect of the present disclosure, there is provided a method for forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate, wherein the sacrificial material layer comprises a dielectric material; forming a row of trench region openings through the alternating stack, wherein the row of trench region openings is arranged in a pattern surrounding a region within the alternating stack; forming at least one connecting via region opening through the alternating stack within the region surrounded by the row of trench region openings; forming trench trenches by laterally expanding each trench region opening within the row of trench region openings until the trench region openings merge at the level of the sacrificial material layer; forming a perforated dielectric trench structure by filling the trench trenches with a dielectric filling material, the perforated dielectric trench structure extending vertically through the alternating stack; forming a finned dielectric pillar structure by filling at least one connecting via region opening with a dielectric filling material; forming a memory stack structure through the alternating stack; and forming an interconnect via structure that extends vertically through the finned dielectric pillar structure, wherein a remaining portion of the finned dielectric pillar structure comprises a vertical stack of dielectric material fins that laterally surround and contact the interconnect via structure.

[0007] According to one aspect of the present disclosure, there is provided a three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack of an insulating layer and a conductive layer, the alternating stack positioned over a substrate; a memory stack structure that extends vertically through the alternating stack, wherein each memory stack structure in the memory stack structure comprises a vertical semiconductor channel and a vertical stack of memory elements at the level of the conductive layer; a perforated dielectric trench structure that extends vertically through the alternating stack and comprises a plurality of lateral openings at each level of the insulating layer and no openings at the level of the conductive layer; and an interconnect via structure that is laterally surrounded by the perforated dielectric trench structure and extends vertically through each insulating layer within the alternating stack.

[0008] According to another aspect of the present disclosure, there is provided a method for forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate, wherein the sacrificial material layer comprises a dielectric material; forming a row of trench region openings through the alternating stack, wherein the row of trench region openings is arranged to

[0009] Patterns surrounding regions within an alternating stack; forming trench grooves by laterally expanding each trench region opening within a row of trench region openings at a level of a sacrificial material layer, where the trench grooves have a continuously extending volume that laterally surrounds patterned portions of the corresponding sacrificial material layer at each level of the sacrificial material layer; forming a perforated dielectric trench structure by filling the trench grooves with a dielectric fill material, the perforated dielectric trench structure extending vertically through the alternating stack; and forming a memory stack structure through the alternating stack, where each memory stack structure within the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements at a level of a conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a lower-level dielectric layer, a lower metal interconnect structure, and a source-level material layer in a process on a semiconductor substrate, according to a first embodiment of the present disclosure.

[0011] Figure 1B is Figure 1A a top view of a first exemplary structure of. The hinged vertical plane A-A' is Figure 1A the plane of the vertical cross-sectional view of.

[0012] Figure 1C is a magnified view of a source-level material layer in a process along the Figure 1B vertical plane C-C' of.

[0013] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming a first alternating stack of a first insulating layer and a first spacer material layer, according to a first embodiment of the present disclosure.

[0014] Figure 3 is a vertical cross-sectional view of a first exemplary structure after patterning a first staircase region, a first backward stepped dielectric material portion, and an interlayer dielectric layer, according to a first embodiment of the present disclosure.

[0015] Figure 4A is a vertical cross-sectional view of a first exemplary structure after forming a first memory opening, a first support opening, and a first isolation opening, according to a first embodiment of the present disclosure.

[0016] Figure 4B is Figure 4A a top view of a first exemplary structure of. The hinged vertical plane A-A' corresponds to Figure 4A the plane of the vertical cross-sectional view of.

[0017] Figure 4C is Figure 4A a top view of another region in a first exemplary structure of.

[0018] Figure 5 is a vertical cross - sectional view of a first exemplary structure after forming various sacrificial fill structures according to a first embodiment of the present disclosure.

[0019] Figure 6A is a vertical cross - sectional view of a first exemplary structure after forming an alternating stack of a second insulating layer and a second spacer material layer, a second stepped surface, and a second backward - stepped dielectric material portion according to a first embodiment of the present disclosure.

[0020] Figure 6B is Figure 6A a top - view of a first exemplary structure. The articulated vertical plane A - A’ corresponds to Figure 6A the plane of the vertical cross - sectional view.

[0021] Figure 7A is a vertical cross - sectional view of a first exemplary structure after forming second - layer memory openings, second - layer support openings, and second - layer isolation openings according to a first embodiment of the present disclosure.

[0022] Figure 7B is Figure 7A a top - view of a first exemplary structure. The articulated vertical plane A - A’ corresponds to Figure 7A the plane of the vertical cross - sectional view.

[0023] Figure 7C is Figure 7A a top - view of another region in a first exemplary structure.

[0024] Figure 8A is a vertical cross - sectional view of a first exemplary structure after forming inter - layer memory openings, inter - layer support openings, and inter - layer isolation openings according to a first embodiment of the present disclosure.

[0025] Figure 8B is Figure 8A another vertical cross - sectional view of a first exemplary structure.

[0026] Figure 8C is Figure 8A and Figure 8B a top - view of a region in a first exemplary structure. The articulated vertical plane B - B’ corresponds to Figure 8B the plane of the vertical cross - sectional view.

[0027] Figure 9 is a vertical cross - sectional view of a region of a first exemplary structure after forming a conformal etch mask material layer and a conformal cover material layer according to a first embodiment of the present disclosure. Figure 8B

[0028] Figure 10AIs a vertical cross - section of a region of a first exemplary structure after forming a patterned photoresist layer and removing the unmasked portion of a conformal cover material layer according to a first embodiment of the present disclosure.

[0029] Figure 10B Is Figure 10A A top view of the first exemplary structure of.

[0030] Figure 11 Is a vertical cross - section of a region of a first exemplary structure after removing the patterned photoresist layer according to a first embodiment of the present disclosure.

[0031] Figure 12 Is a vertical cross - section of a region of a first exemplary structure after removing the unmasked portion of a conformal etch mask material layer according to a first embodiment of the present disclosure.

[0032] Figure 13A Is a vertical cross - section of a region of a first exemplary structure after forming trench grooves by selectively isotropically etching the unmasked portion of a sacrificial material layer for an insulating layer according to a first embodiment of the present disclosure.

[0033] Figure 13B Is Figure 13A A top view of the first exemplary structure of. The hinged vertical plane A - A’ is Figure 13A The plane of the vertical cross - section of.

[0034] Figure 13C Is along Figure 13A A horizontal cross - section of a first exemplary structure of the horizontal plane C–C’. The hinged vertical plane A - A’ is Figure 13A The plane of the vertical cross - section of.

[0035] Figure 14 Is a vertical cross - section of a region of a first exemplary structure after removing the remaining portion of a conformal etch mask material layer according to a first embodiment of the present disclosure.

[0036] Figure 15 Is a vertical cross - section of a region of a first exemplary structure after forming a continuous barrier dielectric layer according to a first embodiment of the present disclosure.

[0037] Figure 16 Is a vertical cross - section of a region of a first exemplary structure after anisotropically depositing a sacrificial fill material layer according to a first embodiment of the present disclosure.

[0038] Figure 17A Is a vertical cross - section of a region of a first exemplary structure after removing a portion of the sacrificial fill material layer from inside the support opening and inside the trench grooves according to a first embodiment of the present disclosure.

[0039] Figure 17B is Figure 17A a top view of a first exemplary structure of

[0040] Figure 18A a vertical cross-section of a region of the first exemplary structure after forming a perforated dielectric trench structure and a support pillar structure, according to a first embodiment of the present disclosure.

[0041] Figure 18B is Figure 18A a top view of a first exemplary structure of Figure 18A The articulated vertical plane A-A’ is the plane of the vertical cross-section of

[0042] Figure 18C is along Figure 18A a horizontal cross-section of a first exemplary structure of Figure 18A The articulated vertical plane A-A’ is the plane of the vertical cross-section of

[0043] Figure 19 a vertical cross-section of a region of the first exemplary structure after removing a sacrificial fill material portion, according to a first embodiment of the present disclosure.

[0044] Figures 20A to 20D shows sequential vertical cross-sections of a memory opening during formation of a memory opening fill structure, according to a first embodiment of the present disclosure.

[0045] Figure 21A a vertical cross-section of a first exemplary structure after forming a memory opening fill structure, according to a first embodiment of the present disclosure.

[0046] Figure 21B is Figure 21A a top view of a first exemplary structure of

[0047] Figure 21C is along Figure 21A in the plane C-C’ of Figure 21A a horizontal cross-section of a first exemplary structure at the level of the sacrificial material layer.

[0048] Figure 22A a vertical cross-section of a first exemplary structure after forming a backside trench, according to a first embodiment of the present disclosure.

[0049] Figure 22B is along Figure 22A in the plane B-B’ of Figure 21A a horizontal cross-section of a first exemplary structure of

[0050] Figures 23A to 23EShows a sequential vertical cross-section of a memory opening filling structure and a back trench during the formation of a source level material layer according to a first embodiment of the present disclosure.

[0051] Figure 24A Is a vertical cross-section of a first exemplary structure after the formation of a back recess according to a first embodiment of the present disclosure.

[0052] Figure 24B Is Figure 24A Another vertical cross-section of the first exemplary structure of

[0053] Figure 25A Is a vertical cross-section of a first exemplary structure after the formation of a conductive layer according to a first embodiment of the present disclosure.

[0054] Figure 25B Is Figure 25A Another vertical cross-section of the first exemplary structure of

[0055] Figure 26A Is a vertical cross-section of a first exemplary structure after the formation of a dielectric wall structure in a back trench according to a first embodiment of the present disclosure.

[0056] Figure 26B Is Figure 26A Another vertical cross-section of the first exemplary structure of

[0057] Figure 27A Is a vertical cross-section of a first exemplary structure after the formation of a higher level dielectric material layer and a higher level metal interconnect structure according to a first embodiment of the present disclosure.

[0058] Figure 27B Is along Figure 27A In plane B-B' of Figure 27A A horizontal cross-section of the first exemplary structure at the level of one of the conductive layers in the conductive layer.

[0059] Figure 28A Is a vertical cross-section of a second exemplary structure after the formation of various second layer openings according to a second embodiment of the present disclosure.

[0060] Figure 28B Is along Figure 28A In plane B-B' of Figure 28A A horizontal cross-section of the second exemplary structure at the level of one of the insulating layers in the insulating layer.

[0061] Figure 28C Is Figure 28A And Figure 28B A top view of the second exemplary structure of

[0062] Figure 29A is a vertical cross - sectional view of a second exemplary structure after forming trench region openings and via connection region openings according to a second embodiment of the present disclosure.

[0063] Figure 29B is Figure 29A another vertical cross - sectional view of the second exemplary structure.

[0064] Figure 29C is Figure 29A and Figure 29B a top - view of the second exemplary structure. The articulated vertical plane B - B’ is Figure 29B the plane of the vertical cross - sectional view.

[0065] Figure 29D is along Figure 29C the articulated vertical plane D - D’ of the second exemplary structure.

[0066] Figure 29E is along a vertical plane extending across the staircase region of Figures 29A to 29D the second exemplary structure.

[0067] Figure 30A is a vertical cross - sectional view of the memory region of the second exemplary structure after forming a conformal etch mask material layer and a conformal capping material layer according to a second embodiment of the present disclosure.

[0068] Figure 30B is Figure 30A a vertical cross - sectional view of the staircase region of the second exemplary structure.

[0069] Figure 31A is a vertical cross - sectional view of a region of the second exemplary structure after forming a patterned photoresist layer according to a second embodiment of the present disclosure.

[0070] Figure 31B is Figure 31A a vertical cross - sectional view of the staircase region of the second exemplary structure.

[0071] Figure 32A is a vertical cross - sectional view of a region of the second exemplary structure after removing the unmasked portion of the conformal capping material layer according to a second embodiment of the present disclosure.

[0072] Figure 32B is Figure 32A a vertical cross - sectional view of the staircase region of the second exemplary structure.

[0073] Figure 33A is a vertical cross - sectional view of a region of the second exemplary structure after removing the patterned photoresist layer according to a second embodiment of the present disclosure.

[0074] Figure 33B is Figure 33A a vertical cross - section of the staircase area of the second exemplary structure of

[0075] Figure 34A a vertical cross - section of the area of the second exemplary structure after removing the unmasked portion of the conformal etch mask material layer, according to the second embodiment of the present disclosure.

[0076] Figure 34B is Figure 34A a vertical cross - section of the staircase area of the second exemplary structure of

[0077] Figure 35A a vertical cross - section of the area of the second exemplary structure after removing the remaining portion of the conformal cover material layer, according to the second embodiment of the present disclosure.

[0078] Figure 35B is Figure 35A a vertical cross - section of the staircase area of the second exemplary structure of

[0079] Figure 36A a vertical cross - section of the area of the second exemplary structure after forming lateral recess cavities around each opening not masked by the conformal etch mask material layer, according to the second embodiment of the present disclosure.

[0080] Figure 36B is Figure 36A a vertical cross - section of the staircase area of the second exemplary structure of

[0081] Figure 36C is Figure 36A and Figure 36B a top view of the second exemplary structure of. The hinged vertical plane A - A’ is Figure 36A the plane of the vertical cross - section of

[0082] Figure 36D is along Figure 36A the horizontal plane D - D’ of Figures 36A to 36C a horizontal cross - section of the second exemplary structure of. The hinged vertical plane A - A’ is Figure 36A the plane of the vertical cross - section of

[0083] Figure 37A a vertical cross - section of the area of the second exemplary structure after removing the conformal etch mask material layer, according to the second embodiment of the present disclosure.

[0084] Figure 37B is Figure 37A a vertical cross - section of the staircase area of the second exemplary structure of

[0085] Figure 38Ais a vertical cross - section of a region of a second exemplary structure after forming a patterned sacrificial fill material layer according to a second embodiment of the present disclosure.

[0086] Figure 38B is Figure 38A a vertical cross - section of a staircase region of a second exemplary structure.

[0087] Figure 39A is a vertical cross - section of a region of a second exemplary structure after depositing a dielectric fill material according to a second embodiment of the present disclosure.

[0088] Figure 39B is Figure 39A a vertical cross - section of a staircase region of a second exemplary structure.

[0089] Figure 40A is a vertical cross - section of a region of a second exemplary structure after planarizing the dielectric fill material and removing the patterned sacrificial fill material layer according to a second embodiment of the present disclosure. Figure 40B is Figure 40A a vertical cross - section of a staircase region of a second exemplary structure.

[0090] Figure 41A is a horizontal cross - section of a region around a finned dielectric pillar structure in a first configuration of a second exemplary structure at the level of a conductive layer according to a second embodiment of the present disclosure.

[0091] Figure 41B is a horizontal cross - section of a region around a finned dielectric pillar structure in a second configuration of a second exemplary structure at the level of a conductive layer according to a second embodiment of the present disclosure.

[0092] Figure 41C is a horizontal cross - section of a region around a finned dielectric pillar structure in a third configuration of a second exemplary structure at the level of a conductive layer according to a second embodiment of the present disclosure.

[0093] Figure 42A is a horizontal cross - section of a region around a finned dielectric pillar structure in a first configuration of a second exemplary structure at the level of an insulating layer according to a second embodiment of the present disclosure.

[0094] Figure 42B is a horizontal cross - section of a region around a finned dielectric pillar structure in a second configuration of a second exemplary structure at the level of an insulating layer according to a second embodiment of the present disclosure.

[0095] Figure 42C is a horizontal cross - section of a region around a finned dielectric pillar structure in a third configuration of a second exemplary structure at the level of an insulating layer according to a second embodiment of the present disclosure.

[0096] Figure 43A is a vertical cross - sectional view of a region of a second exemplary structure after forming a memory opening filling structure according to a second embodiment of the present disclosure.

[0097] Figure 43B is Figure 43A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0098] Figure 44A is a vertical cross - sectional view of a region of a second exemplary structure after forming a contact - level dielectric layer and a back - side trench according to a second embodiment of the present disclosure.

[0099] Figure 44B is Figure 44A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0100] Figure 45A is a vertical cross - sectional view of a region of a second exemplary structure after a source - level material layer in a source - level material layer replacement process according to a second embodiment of the present disclosure.

[0101] Figure 45B is Figure 45A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0102] Figure 46A is a vertical cross - sectional view of a region of a second exemplary structure after replacing a sacrificial material layer with a conductive layer according to a second embodiment of the present disclosure.

[0103] Figure 46B is Figure 46A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0104] Figure 47A is a vertical cross - sectional view of a region of a second exemplary structure after forming insulating spacers according to a second embodiment of the present disclosure.

[0105] Figure 47B is Figure 47A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0106] Figure 48A is a vertical cross - sectional view of a region of a second exemplary structure after forming a patterned film and various via cavities according to a second embodiment of the present disclosure.

[0107] Figure 48B is Figure 48A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0108] Figure 49Ais a vertical cross - sectional view of a region of a second exemplary structure after forming various contact via structures according to a second embodiment of the present disclosure.

[0109] Figure 49B is Figure 49A a vertical cross - sectional view of a staircase region of a second exemplary structure.

[0110] Figure 50A is a horizontal cross - sectional view of a region around a connection via structure in a first configuration of a second exemplary structure at a level of a conductive layer according to a second embodiment of the present disclosure.

[0111] Figure 50B is a horizontal cross - sectional view of a region around a connection via structure in a second configuration of a second exemplary structure at a level of a conductive layer according to a second embodiment of the present disclosure.

[0112] Figure 50C is a horizontal cross - sectional view of a region around a connection via structure in a third configuration of a second exemplary structure at a level of a conductive layer according to a second embodiment of the present disclosure.

[0113] Figure 51A is a horizontal cross - sectional view of a region around a connection via structure in a first configuration of a second exemplary structure at a level of an insulating layer according to a second embodiment of the present disclosure.

[0114] Figure 51B is a horizontal cross - sectional view of a region around a connection via structure in a second configuration of a second exemplary structure at a level of an insulating layer according to a second embodiment of the present disclosure.

[0115] Figure 51C is a horizontal cross - sectional view of a region around a connection via structure in a third configuration of a second exemplary structure at a level of an insulating layer according to a second embodiment of the present disclosure. Detailed Description

[0116] Embodiments of the present disclosure provide a three - dimensional memory device and a method of manufacturing the same. The three - dimensional memory device includes conductive via structures that extend through a stack of dielectric materials and are surrounded by perforated dielectric trench structures. Various embodiments of the three - dimensional memory device and the method of manufacturing the same are described in detail herein. Stacked insulating layers extend through the perforations in the perforated dielectric trench structures to provide enhanced stability to the device during processing.

[0117] The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Serial numbers such as "first", "second", and "third" are only used to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0118] Like reference numerals represent like or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing shared edges or surfaces. If two or more elements do not directly contact each other or between each other, the two elements are "separated" from each other or "separated" between each other. As used herein, a first element positioned "on" a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is an electrical conduction path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "structure in process" refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0119] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope smaller than the scope of the underlying or overlying structure. Additionally, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the first continuous structure. For example, the layer may be positioned between the top surface and the bottom surface of the first continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the first continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above it, and / or below it.

[0120] As used herein, if a second surface is above or below a first surface and if there is a vertical plane or a substantially vertical plane including the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that linearly extends in a direction at an angle deviating from the vertical direction by less than 5 degrees. The vertical plane or the substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature in a direction perpendicular to the vertical direction or the substantially vertical direction.

[0121] As used herein, a "memory tier" or "memory array tier" refers to a tier of a general region between a first horizontal plane corresponding to the topmost surface of an array of memory elements (i.e., a plane parallel to the top surface of the substrate) and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through the memory tier.

[0122] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of electrical dopants, and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / m) when formed as a crystalline material or when converted to a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A "doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material including electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration providing a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of electrical dopants therein. As used herein, a "metallic material" refers to a conductive material including at least one metallic element. All conductivity measurements are made under standard conditions.

[0123] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate such as a semiconductor wafer without an intervening substrate. The term "monolithic" means that the layers of each level of the array are directly deposited on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 titled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels prior to bonding, but since the memory levels were initially formed above separate substrates, such memories are not truly monolithic three-dimensional memory arrays. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using various embodiments described herein.

[0124] Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using various embodiments described herein. The monolithic three-dimensional NAND strings are positioned in a monolithic three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0125] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include one or more semiconductor chips (or "chips") that are through-bonded, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip can include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operations can be performed in each plane within the same die, although there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0126] Reference Figures 1A to 1C, showing an exemplary structure according to a first embodiment of the present disclosure. Figure 1C is Figure 1A and Figure 1B An enlarged view of the source-level hierarchical material layer 10' in the process shown. This first exemplary structure includes a semiconductor substrate 8 and semiconductor devices 710 formed thereon. The semiconductor substrate 8 may include a substrate semiconductor layer 9 at least in its upper portion. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between the semiconductor devices 710. The semiconductor devices 710 may include, for example, field effect transistors, which include corresponding transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, dielectric gate spacers 756, and a gate capping dielectric 758. The semiconductor devices 710 may include any semiconductor circuit to support the operation of the memory structure to be formed subsequently, which semiconductor circuit is generally referred to as a driver circuit, and this driver circuit is also referred to as a peripheral circuit. As used herein, a peripheral circuit refers to any one, each, or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer and / or latch, or may be any other semiconductor circuit that can be implemented external to the memory array structure of a memory device. For example, the semiconductor device may include a word line switching device for electrically biasing the word lines of the three-dimensional memory structure to be formed subsequently.

[0127] A dielectric material layer may be formed over the semiconductor device, and the dielectric material layer is referred to herein as the lower-level dielectric material layer 760. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 covering the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 covering the first dielectric material layer 764, and at least one second dielectric layer 768. The dielectric layer stack (which includes the lower-level dielectric material layer 760) may be used as a matrix for lower-level metal interconnect structures 780, which provide electrical wiring to and from the respective nodes of the landing pads of the through-memory-level interconnect vias structures to be formed in the semiconductor device and subsequently. The lower-level metal interconnect structures 780 may be formed within the dielectric layer stack of the lower-level dielectric material layer 760 and cover the field effect transistors. The lower-level metal interconnect structures 780 may include lower-level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0128] For example, a lower-level metal interconnect structure 780 may be formed within a first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers, within which various elements of the lower-level metal interconnect structure 780 are formed sequentially. Each dielectric material layer selected from the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric material layer 764 may comprise or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide). The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes of a contact device corresponding to the respective source and drain nodes or gate electrode contacts), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing pad level metal line structures 788, the landing pad level metal line structures being configured to serve as landing pads for through-memory level interconnect via structures to be formed subsequently.

[0129] The landing pad level metal line structure 788 may be formed within the topmost dielectric material layer of the first dielectric material layer 764, which may be a plurality of dielectric material layers. Each of the lower-level metal interconnect structures 780 may include a metal nitride liner and a metal fill structure. The top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 may be formed directly on the top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764.

[0130] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one second dielectric material layer 768 may comprise or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide).

[0131] An optional layer of a metallic material and a layer of a semiconductor material may be deposited over or within the patterned recesses of at least one second dielectric material layer 768 and lithographically patterned to provide an optional conductive plate layer 6 and a source level material layer 10' in the process. The optional conductive plate layer 6 (if present) provides a highly conductive conduction path for current flowing into or out of the source level material layer 10' in the process. The optional conductive material layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional conductive plate layer 6 may, for example, include a tungsten layer having a thickness in the range of 3 nm to 100 nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the conductive plate layer 6 as a diffusion barrier layer. The conductive plate layer 6 may be used as a special source line in a completed device. Additionally, the conductive plate layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor, or insulating layer. The optional conductive plate layer 6 may include a metal compound material, such as a conductive metal nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in the range of 5 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0132] The source level material layer 10' in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer, when formed, includes a source contact layer that serves as a common source region for the vertical field effect transistors of the three-dimensional memory device. In one embodiment, the source level material layer 10' in the process may include, from bottom to top, a lower source level material layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level semiconductor layer 116, a source level insulating layer 117, and an optional source select level conductive layer 118.

[0133] The lower source level material layer 112 and the higher source level semiconductor layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conduction type of the lower source level material layer 112 and the higher source level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conduction type, the lower source level material layer 112 and the higher source level semiconductor layer 116 have a doping of a second conduction type opposite to the first conduction type. The thickness of each of the lower source level material layer 112 and the higher source level semiconductor layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0134] The source level sacrificial layer 104 includes a sacrificial material that can be selectively removed with respect to the lower sacrificial liner 103 and the upper sacrificial liner 105. In one embodiment, the source level sacrificial layer 104 can include a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30 nm to 400 nm, such as 60 nm to 200 nm, but smaller and larger thicknesses can also be used.

[0135] The lower sacrificial liner 103 and the upper sacrificial liner 105 contain materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxides. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer with a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0136] The source level insulating layer 117 can include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 can be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, but smaller and larger thicknesses can also be used. The optional source select level conductive layer 118 can include a conductive material that can be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 can include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which can subsequently be converted to doped polysilicon through an annealing process. The thickness of the optional source select level conductive layer 118 can be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, but smaller and larger thicknesses can also be used.

[0137] The source level material layer 10' in the process can be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer). As used herein, a first element is located "directly above" a second element if the first element is positioned above a horizontal plane including the topmost surface of the second element and the area of the first element, and the area of the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the semiconductor substrate 8).

[0138] The optional conductive plate layer 6 and the source level material layer 10' in the process can be patterned to provide openings in areas where through-memory level interconnect via structures and through-dielectric contact via structures are to be subsequently formed. Patterned portions of the stacked conductive plate layer 6 and source level material layer 10' are present in each memory array region 100, in which a three-dimensional memory stack structure will be subsequently formed.

[0139] The optional conductive plate layer 6 and the source level material layer 10' in the process can be patterned such that the opening extends above the staircase region 200 of the contact via structure where the contact word line conductive layer is to be formed subsequently. In one embodiment, the staircase region 200 can be laterally spaced from the memory array region 100 along a first horizontal direction hd1. The horizontal direction perpendicular to the first horizontal direction hd1 is herein referred to as the second horizontal direction hd2. In one embodiment, additional openings can be formed in the region of the memory array region 100 in the optional conductive plate layer 6 and the source level material layer 10' in the process, and a three-dimensional memory array including a memory stack structure will be formed subsequently in the region of the memory array region. The peripheral device region 400 filled with a field dielectric material portion can be provided adjacent to the staircase region 200 subsequently.

[0140] The region of the combination of the semiconductor device 710 and the lower level dielectric material layer 760 and the lower level metal interconnect structure 780 is herein referred to as the lower peripheral device region 700, which is positioned below the memory level component to be formed subsequently and includes peripheral devices for the memory level component. The lower level metal interconnect structure 780 can be formed in the lower level dielectric material layer 760.

[0141] The lower level metal interconnect structure 780 can be electrically connected to an active node (e.g., the transistor active region 742 or the gate electrode 754) of the semiconductor device 710 (e.g., a CMOS device), and can be positioned at the level of the lower level dielectric material layer 760. A direct memory level interconnect via structure can be formed directly on the lower level metal interconnect structure 780 subsequently to provide an electrical connection to the memory device to be formed subsequently. In one embodiment, the pattern of the lower level metal interconnect structure 780 can be selected such that the landing pad level metal line structure 788 (which is a subset of the lower level metal interconnect structure 780 positioned at the topmost portion of the lower level metal interconnect structure 780) can provide a landing pad structure for the direct memory level interconnect via structure to be formed subsequently.

[0142] Reference Figure 2 , an alternating stack of a first material layer and a second material layer can be formed. Each first material layer can include a first material, and each second material layer can include a second material different from the first material. In an embodiment where at least another alternating stack of material layers is formed above the alternating stack of the first material layer and the second material layer subsequently, the alternating stack is herein referred to as the first layer alternating stack. The level of the first layer alternating stack is herein referred to as the first layer level, and the level of the alternating stack to be formed immediately above the first layer level is herein referred to as the second layer level, and so on.

[0143] The first alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are expressly contemplated herein.

[0144] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the source electrode layer material layer 10' in the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0145] As used herein, an alternating stack of a first element and a second element refers to a structure in which instances of the first element and instances of the second element alternate. Each instance of the first element that is an end element of a plurality of non-alternating elements is adjacent to two instances of the second element on both sides, and each instance of the second element that is an end element of a plurality of non-alternating elements is adjacent to two instances of the first element at both ends. The first element may always have the same thickness, or may have different thicknesses. The second element may always have the same thickness, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first element and instances of the second element may form units that are periodically repeated within the alternating plurality of elements.

[0146] The first alternating stack (132, 142) may include a first insulating layer 132 made of a first material and a first sacrificial material layer 142 made of a second material different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal nitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0147] The second material of the first sacrificial material layer 142 can be a sacrificial material that can be selectively removed with respect to the first material of the first insulating layer 132. As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, then the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material.

[0148] The first sacrificial material layer 142 can include an insulating material, a semiconductor material, or a conductive material. Subsequently, the second material of the first sacrificial material layer 142 can be replaced with a conductive electrode, which can be used as, for example, a control gate electrode of a vertical NAND device. In accordance with aspects of the present disclosure, the first sacrificial material layer 142 comprises a dielectric material. In one embodiment, the first sacrificial material layer 142 can be a material layer comprising silicon nitride.

[0149] In one embodiment, the first insulating layer 132 can comprise silicon oxide, and the sacrificial material layer can comprise a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) can be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0150] The thicknesses of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the pairs of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the first layer alternate stack (132, 142) can have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

[0151] The first insulating capping layer 170 can then be formed over the first layer alternate stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 can be in the range of 20 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0152] ReferenceFigure 3 The first insulating capping layer 170 and the first layer alternating stack (132, 142) can be patterned to form a first stepped surface in the staircase region 200. The staircase region 200 can include a corresponding first stepped region and a second stepped region. In the first stepped region, the first stepped surface is formed. In the second stepped region, an additional stepped surface is subsequently formed in the second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface can be formed, for example, by forming a mask layer having openings therein, etching cavities within the level of the first insulating capping layer 170 and iteratively expanding the etching region, and vertically recessing the cavities by etching each pair of a first insulating layer 132 and a first sacrificial material layer 142 positioned directly below the bottom surface of the etching cavities within the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 can be physically exposed at the first stepped surface. The cavities covering the first stepped surface are referred to herein as first stepped cavities.

[0153] A dielectric fill material (such as undoped silicate glass or doped silicate glass) can be deposited to fill the first stepped cavities. The excess portion of the dielectric fill material can be removed from above the horizontal plane including the top surface of the first insulating capping layer 170. The remaining portion of the dielectric fill material filling the region covering the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontally cross-sectional area that monotonically increases according to the vertical distance from the substrate to the top surface on which the element is present. The first layer alternating stack (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a structure in a process that is subsequently modified.

[0154] An interlayer dielectric layer 180 can optionally be deposited above the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 contains a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 can contain a doped silicate glass having an etching rate greater than that of the material of the first insulating layer 132 (which may contain undoped silicate glass). For example, the interlayer dielectric layer 180 can contain phosphosilicate glass. The thickness of the interlayer dielectric layer 180 can be in the range of 30 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0155] Reference Figures 4A to 4CVarious first layer openings (149, 129, 529) may be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 10'. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be photolithographically patterned to form various openings therethrough.

[0156] The pattern of the openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 10' to form various first layer openings (149, 129, 529) simultaneously (i.e., during the first isotropic etching process). The various first layer openings (149, 129, 529) can include a first layer memory opening 149, a first layer support opening 129, and a first layer trench opening 529. Figure 4B The position of the step S in the first layer of alternating stacking (132, 142) is shown by a dotted line.

[0157] The first layer memory openings 149 may be openings formed in the memory array region 100 through each layer within the first layer alternating stack (132, 142) and subsequently used to form a memory stack structure therein. The first layer memory openings 149 may be formed as clusters 319 of first layer memory openings 149 that are laterally spaced apart along the second horizontal direction hd2. Each cluster 319 of the first layer memory openings 149 may be formed as a two-dimensional array of first layer memory openings 149.

[0158] A subset of the first layer support openings 129 may be formed in sections of the memory array region 100 that are not filled with the first layer memory openings 149. The sections of the memory array region 100 that are not filled with the first layer memory openings 149 may be distributed over a plurality of regions within the memory array region 100. The first layer support openings 129 may include a first subset of the first layer support openings 129 formed in the stair region 200 and a second subset of the first layer support openings 129 formed between groups 339 of clusters 319 of first layer memory openings 149 laterally spaced apart along the first horizontal direction hd1 in the memory array region 100. The first subset of the first layer support openings 129 formed through the first rear stepped dielectric material portion 165 may be formed through the corresponding horizontal surfaces of the first stepped surface.

[0159] like Figure 4CAs shown, a second subset of the first layer support openings 129 may be formed between groups 339 of clusters 319 of the first layer memory openings 149 that are laterally spaced along a first horizontal direction hd1. In one embodiment, some of the first layer support openings 129 within the second subset of the first layer support openings 129 may be arranged in a straight row extending along the first direction hd1. Additional first layer support openings 129 may be provided outside of the straight row of the first layer support openings 129.

[0160] As Figure 4C shown, discrete regions that do not include the first layer memory openings 149, the first layer support openings 129, and the first layer trench region openings 529 may be provided in the memory array region 100, which is referred to herein as the opening-free region OFA. Each opening-free region OFA may be surrounded by the first layer trench region openings 529 that are arranged along the perimeter of a two-dimensional closed shape, such as a polygon (e.g., a rectangle), a generally oval shape (e.g., a circle or an ellipse), or any two-dimensional curved shape.

[0161] In one embodiment, a group of the first layer trench region openings 529 may be arranged along the perimeter of a rectangular shape. Each region where the first layer trench region openings 529 are positioned close to each other is referred to herein as a trench region MR. In one embodiment, each opening-free region OFA may be a rectangular region having a pair of longitudinal edges that extend laterally along the first horizontal direction hd1 and having a pair of lateral edges that extend laterally along a second horizontal direction hd2.

[0162] Generally speaking, the unit pattern UP of the combination of the first layer memory openings 149, the first layer support openings 129, and the first layer trench region openings 529 may be repeated along the second horizontal direction hd2. Each unit pattern UP includes groups 339 of clusters 319 of the first layer memory openings 149 that are laterally spaced along the second horizontal direction hd2 and / or laterally spaced along the first horizontal direction hd1.

[0163] In one embodiment, the first anisotropic etching process may include an initial step in which the materials of the first layer alternating stack (132, 142) and the material of the first backward stepped dielectric material portion 165 are etched simultaneously. The chemistry of the initial etching step may be alternated to optimize the etching of the first material and the second material in the first layer alternating stack (132, 142), while providing an average etching rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129, 529) may be substantially vertical or may be tapered.

[0164] After etching through the alternating stacks (132, 142) and the first back stepped dielectric material portion 165, the chemistry of the terminal portion of the first anisotropic etching process can be selected to etch through one or more dielectric materials of at least one second dielectric layer 768 at an etching rate higher than the average etching rate of the source level material layer 10' in the process. For example, the terminal portion of the anisotropic etching process can include steps of selectively etching the dielectric materials of at least one second dielectric layer 768 for the semiconductor material in the component layers in the source level material layer 10' in the process. In one embodiment, the terminal portion of the first anisotropic etching process can etch through the source select level conductive layer 118, the source level insulating layer 117, the higher source level semiconductor layer 116, the higher sacrificial liner 105, the source level sacrificial layer 104, and the lower sacrificial liner 103, and at least partially into the lower source level semiconductor layer 112. The terminal portion of the first anisotropic etching process can include at least one etch chemistry for etching the various semiconductor materials of the source level material layer 10' in the process. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0165] Optionally, the portions of the first layer memory openings 149, the first layer support openings 129, and the first layer trench region openings 529 at the level of the interlayer dielectric layer 180 can be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 can include a dielectric material (such as borosilicate glass) that has a higher etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). Isotropic etching (such as wet etching using HF) can be used to expand the lateral dimensions of the first layer memory openings 149 at the level of the interlayer dielectric layer 180. The portions of the first layer memory openings 149 located at the level of the interlayer dielectric layer 180 can be optionally widened to provide a larger landing pad for the second layer memory openings that will subsequently be formed through the second layer alternating stack (formed subsequently before the formation of the second layer memory openings).

[0166] Reference Figure 5 , sacrificial first layer opening fill portions (148, 128, 528) can be formed in the various first layer openings (149, 129, 529). For example, the sacrificial first layer fill material can be deposited simultaneously in each of the first layer openings (149, 129, 529). The sacrificial first layer fill material includes a material that can be subsequently selectively removed for the materials of the first insulating layer 132 and the first sacrificial material layer 142.

[0167] In one embodiment, the first sacrificial fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), silicon germanium alloy, germanium, III-V compound semiconductor materials, or combinations thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the first sacrificial fill material. The first sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0168] In another embodiment, the first sacrificial fill material may include a silicon oxide material having an etch rate higher than that of the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer dielectric layer 180. For example, the first sacrificial fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than that of a dense TEOS oxide in 100:1 diluted hydrofluoric acid (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process). In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the first sacrificial fill material. The first sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0169] In yet another embodiment, the first sacrificial fill material may include amorphous silicon or carbon-containing materials (such as amorphous carbon or diamond-like carbon) that can be subsequently removed by ashing, or a silicon-based polymer that can be selectively removed subsequently for the materials of the first alternating stack (132, 142).

[0170] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first alternating stack (132, 142), such as from above the interlayer dielectric layer 180. For example, the first sacrificial fill material may be recessed into the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0171] The remaining portions of the sacrificial first layer fill material include sacrificial first layer opening fill portions (148, 128, 528). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening fill portion 128. Each remaining portion of the sacrificial material in the first layer trench region opening 529 constitutes a sacrificial first layer trench opening fill portion 528. The various sacrificial first layer opening fill portions (148, 128, 528) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the first layer alternating stack (132, 142) (such as from above the top surface of the interlayer dielectric layer 180). The top surface of the sacrificial first layer opening fill portions (148, 128, 528) can be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148, 128, 528) may or may not include a cavity therein.

[0172] Reference Figure 6A and Figure 6B , a second layer structure can be formed above the first layer structure (132, 142, 170, 148). The second layer structure can include an additional alternating stack of an insulating layer and spacer material layers, and these spacer material layers can be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers can subsequently be formed on the top surface of the first layer alternating stack (132, 142). The second alternating stack (232, 242) includes a plurality of alternating third material layers and fourth material layers. Each third material layer can contain a third material, and each fourth material layer can contain a fourth material different from the third material. In one embodiment, the third material can be the same as the first material of the first insulating layer 132, and the fourth material can be the same as the second material of the first sacrificial material layer 142.

[0173] In one embodiment, the third material layer can be the second insulating layer 232, and the fourth material layer can be a second spacer material layer that provides a vertical spacing between each pair of vertically adjacent second insulating layers 232. In one embodiment, the third material layer and the fourth material layer can be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 can be at least one insulating material. The fourth material of the second sacrificial material layer 242 can be a sacrificial material that can be selectively removed with respect to the third material of the second insulating layer 232. According to an aspect of the present disclosure, the second sacrificial material layer 242 includes a dielectric material, which can be the same material as the dielectric material of the first sacrificial material layer 142. Subsequently, the fourth material of the second sacrificial material layer 242 can be replaced with a conductive electrode, which can be used as, for example, a control gate electrode of a vertical NAND device.

[0174] In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second layer stack (232, 242) can include a plurality of alternating second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0175] The third material of the second insulating layer 232 can be at least one insulating material. The insulating material that can be used for the second insulating layer 232 can be any material that can be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that can be used for the second sacrificial material layer 242 can be any material that can be used for the first sacrificial material layer 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material. In one embodiment, the first insulating layer 132 and the second insulating layer 232 can include silicon oxide, and the first sacrificial material layer 142 and the second sacrificial material layer 242 can include silicon nitride.

[0176] The thicknesses of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the pairs of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second layer alternating stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0177] The second stepped surface in the second stepped region can be formed in the staircase region 200 using the same set of processing steps as those used to form the first stepped surface in the first stepped region, where the pattern of at least one mask layer is appropriately adjusted. A second backward stepped dielectric material portion 265 can be formed above the second stepped surface in the staircase region 200.

[0178] Subsequently, a second insulating capping layer 270 can be formed above the second layer alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 can comprise silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) can comprise silicon nitride.

[0179] Generally, at least one alternating stack of an insulating layer (132, 232) and a spacer material layer (such as a sacrificial material layer (142, 242)) can be formed above the source electrode level material layer 10' in the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the staircase region on the at least one alternating stack (132, 142, 232, 242).

[0180] Reference Figures 7A to 7C , various second layer openings (249, 229, 629) can be formed through the second layer structure (232, 242, 265, 270). A photoresist layer (not shown) can be applied above the second insulating capping layer 270 and can be lithographically patterned to form various openings therethrough. The pattern of the openings can be the same as the pattern of the various first layer openings (149, 129, 529), which is the same as the sacrificial first layer opening filling portions (148, 128, 528). Thus, the photoresist layer can be patterned using the photolithography mask used to pattern the first layer openings (149, 129).

[0181] The pattern of the openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270) by a second anisotropic etching process to form various second layer openings (249, 229, 629) simultaneously (i.e., during the second anisotropic etching process). The various second layer openings (249, 229, 629) can include a second layer memory opening 249, a second layer support opening 229, and a second layer trench region opening 629.

[0182] As Figure 7C shown, the second layer memory opening 249 can be formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening fill portions 148 in the sacrificial first layer memory opening fill portion. The second layer support opening 229 can be formed directly on the top surface of a corresponding one of the sacrificial first layer support opening fill portions 128. The second layer trench region opening 629 can be formed directly on the top surface of a corresponding one of the sacrificial first layer trench region opening fill portions 528. Additionally, each second layer support opening 229 can be formed to pass through a horizontal surface within the second stepped surface, which includes the interfacial surface between the second layer alternating stack (232, 242) and the second backward stepped dielectric material portion 265. The positions of the steps S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) are shown in dashed lines in Figure 7B which shows the positions of the steps S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) in dashed lines.

[0183] A subset of the second layer support openings 229 can be formed in a section of the memory array region 100 that is not filled with the second layer memory openings 249. The sections of the memory array region 100 that are not filled with the second layer memory openings 249 can be distributed over a plurality of regions within the memory array region 100. The second layer support openings 229 can include a first subset of the second layer support openings 229 formed in the staircase region 200 and a second subset of the second layer support openings 229 that can be formed between groups 439 of clusters 419 of the second layer memory openings 249 that are laterally spaced apart along a first horizontal direction hd1 in the memory array region 100. The first subset of the second layer support openings 229 formed through the second backward stepped dielectric material portion 265 can be formed through a corresponding horizontal surface of the second stepped surface.

[0184] The second subset of the second layer support openings 229 can be formed between groups 439 of clusters 419 of the second layer memory openings 249 that are laterally spaced apart along the first horizontal direction hd1. In one embodiment, some of the second layer support openings 229 within the second subset of the second layer support openings 229 can be arranged in a straight row extending along the first direction hd1. Additional second layer support openings 229 can be provided outside the straight row of the second layer support openings 229.

[0185] As Figure 7C shown, a discrete region OFA without the second layer memory openings 249, second layer support openings 229, and second layer trench region openings 629 can be disposed in the memory array region 100 and can have the same area as the Figure 4C openings-free region OFA in. Each openings-free region OFA can be surrounded by second layer trench region openings 629 that are arranged along the perimeter of a two-dimensional closed shape, such as a polygon (e.g., rectangle), a generally oval shape (e.g., circle or ellipse), or any two-dimensional curved shape. The pattern of the second layer trench region openings 629 can be the same as the pattern of the sacrificial first layer trench region opening fill portions 528. In one embodiment, a set of second layer trench region openings 629 can be arranged along the perimeter of a rectangular shape. A set of second layer trench region openings 629 can be positioned close to each other within the respective trench region MR. In one embodiment, each openings-free region OFA can be a rectangular region having a pair of longitudinal edges that extend laterally along a first horizontal direction hd1 and having a pair of lateral edges that extend laterally along a second horizontal direction hd2.

[0186] Generally speaking, the unit pattern UP of the combination of the second layer memory openings 249, second layer support openings 229, and second layer trench region openings 629 can be repeated along the second horizontal direction hd2. Each unit pattern UP includes a group 439 of clusters 419 of first layer memory openings 149 that are laterally spaced apart along the second horizontal direction hd2 and / or laterally spaced apart along the first horizontal direction hd1.

[0187] The second anisotropic etching process can include an etching step in which the materials of the second layer alternating stack (232, 242) and the materials of the second backward stepped dielectric material portion 265 are etched simultaneously. The chemistry of the etching step can be alternated to optimize the etching of the materials in the second layer alternating stack (232, 242) while providing an average etching rate comparable to the materials of the second backward stepped dielectric material portion 265. The second anisotropic etching process can use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CFV Oa / Ar etching). The sidewalls of the various second layer openings (249, 229, 629) can be substantially vertical or can be tapered. The bottom perimeter of each second layer opening (249, 229, 629) can be laterally offset and / or can be fully positioned within the perimeter of the top surface of the underlying sacrificial first layer opening fill portions (148, 128, 528). Subsequently, the photoresist layer can be removed, for example, by ashing.

[0188] Reference Figures 8A to 8C, an etching process can be used to remove the sacrificial first - layer fill material in the sacrificial first - layer opening fill portions (148, 128, 528). This etching process selectively etches the sacrificial first - layer fill material with respect to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the inter - layer dielectric layer 180. Memory openings 49 (also referred to as inter - layer memory openings 49) are formed in each combination of the second - layer memory openings 249 and the volume of the sacrificial first - layer memory - opening fill portion 148 removed therefrom. Support openings 19 (also referred to as inter - layer support openings 19) can be formed in each combination of the second - layer support openings 229 and the volume of the sacrificial first - layer support - opening fill portion 128 removed therefrom. Trench - region openings 619 (also referred to as inter - layer trench openings 619) can be formed in each combination of the second - layer trench - region openings 629 and the volume of the sacrificial first - layer trench - region opening fill portion 528 removed therefrom.

[0189] Each group of trench - region openings 619 adjacent to each other can laterally surround a corresponding opening - free area OFA. In other words, each opening - free area OFA can be surrounded by a corresponding group of trench - region openings 619 arranged along the perimeter of the opening - free area OFA within the corresponding trench region MR. In one embodiment, each opening - free area OFA can be a rectangular region having a pair of longitudinal edges extending laterally along a first horizontal direction hd1 and a pair of lateral edges extending laterally along a second horizontal direction hd2. In this case, each group of trench - region openings 619 can include two rows of straight trench - region openings 619 arranged along the first horizontal direction hd1 and two rows of straight trench - region openings 619 arranged along the second horizontal direction hd2.

[0190] Generally, an alternating stack of insulating layers (132, 232) and sacrificial material layers (142, 242) containing dielectric material can be formed over the substrate 8. The sacrificial material layers (142, 242) contain dielectric material. Rows of discrete, laterally - spaced - apart openings, such as those embodied as trench - region openings 619, can be formed through the alternating stack {(132, 242), (232, 242)}. The rows of discrete, laterally - spaced - apart openings can be arranged to surround a pattern of regions (such as the opening - free area OFA) within the alternating stack {(132, 242), (232, 242)}.

[0191] Reference Figure 9, a conformal etch mask material layer 352 and a conformal capping material layer 354 may be sequentially deposited in each of the memory openings 49, the support openings 19, and the trench region openings 619, as well as over the second insulating capping layer 270. The conformal etch mask material layer 352 comprises a material that can act as an etch mask material for a subsequent etch process used to etch the unmasked portions of the sacrificial material layers (142, 242). For example, the conformal etch mask material layer 352 may comprise a semiconductor material such as amorphous silicon or polysilicon. The conformal etch mask material layer 352 may be deposited by a conformal deposition process such as a chemical vapor deposition process (e.g., low pressure chemical vapor deposition process). The thickness of the conformal etch mask material layer 352 may be in the range of 20 nm to 120 nm, such as 30 nm to 80 nm, although smaller and larger thicknesses may also be employed.

[0192] The conformal capping material layer 354 comprises a material that can protect the masked portions of the conformal etch mask material layer 352 during a subsequent patterning process. For example, if the conformal etch mask material layer 352 comprises a semiconductor material, the conformal capping material layer 354 may comprise silicon oxide. The conformal capping material layer 354 may be formed by thermal oxidation of the material of the conformal etch mask material layer 352 or may be formed by a conformal deposition process. The thickness of the conformal capping material layer 354 may be in the range of 5 nm to 30 nm, such as 10 nm to 20 nm, although smaller and larger thicknesses may also be employed. In the case where the conformal capping material layer 354 comprises silicon oxide formed by oxidation of the surface portion of the conformal etch mask material layer 352, due to the oxidation of the surface portion of the conformal etch mask material layer 352, the thickness of the conformal etch mask material layer 352 may be reduced by approximately half the thickness of the conformal capping material layer 354 (which is a semiconductor oxide layer).

[0193] Reference Figure 10A and Figure 10B , a patterned photoresist layer 357 may be formed over the first exemplary structure. For example, a photoresist layer may be applied over the first exemplary structure and lithographically patterned to form openings in a region including a corresponding combination of an opening-free area OFA and a surrounding trench region MR. In other words, the openings in the patterned photoresist layer 357 may be formed within the region of the rows of the trench region openings 619 and within the opening-free area OFA laterally enclosed by the rows of the trench region openings 619. The profile of each row of the trench region openings 619 may enclose a corresponding opening-free area OFA. In one embodiment, each opening through the patterned photoresist layer 357 may have a rectangular shape having a pair of longitudinal edges extending laterally along a first horizontal direction hd1 and a pair of lateral edges extending laterally along a second horizontal direction hd2.

[0194] An isotropic etching process can be performed to selectively etch the material of the conformal capping material layer 354 with respect to the material of the conformal etch mask material layer 352 to remove the exposed portions of the conformal capping material layer 354, including the portions located in the trench region openings 619. For example, if the conformal capping material layer 354 comprises silicon oxide and if the conformal etch mask material layer 352 comprises amorphous silicon, a wet etching process using diluted hydrofluoric acid can be performed to etch the unmasked portions of the conformal capping material layer 354 without etching the conformal etch mask material layer 352.

[0195] Reference Figure 11 , and subsequently the patterned photoresist layer 357 can be removed, for example, by ashing. Memory cavities 49' are present within each memory opening 49, and support cavities 19' are present within each support opening 19.

[0196] Reference Figure 12 , an isotropic etching process can be performed to selectively etch the material of the conformal etch mask material layer 352 with respect to the material of the conformal capping material layer 354. The unmasked portions of the conformal etch mask material layer 352 can be selectively etched with respect to the material of the conformal capping material layer 354. For example, if the conformal etch mask material layer 352 comprises amorphous silicon or polysilicon and if the conformal capping material layer 354 comprises silicon oxide, a wet etching process (which uses hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be employed to remove the unmasked portions of the conformal etch mask material layer 352 in the trench region openings 619 without etching the conformal capping material layer 354. The sidewalls of the trench region openings 619 are physically exposed when removing the unmasked portions of the conformal etch mask material layer 352. Each of the memory openings 49 and the support openings 19 can be covered by a layer stack of the conformal etch mask material layer 352 and the conformal capping material layer 354.

[0197] Reference Figures 13A to 13C, the conformal cover material layer 354 can be etched by a first isotropic etching process, which can be an isotropic etching process using diluted hydrofluoric acid to remove all remaining portions of the conformal cover material layer 354. A second isotropic etching process can be performed to laterally recess the physically exposed sidewalls of the sacrificial material layers (142, 242) with respect to the sidewalls of the insulating layers (132, 242), the first insulating capping layer 170, the interlayer dielectric layer 180, the second insulating capping layer 270, and the process source level material layer 10' in the trench regions MR. In one embodiment, the insulating layers (132, 242), the first insulating capping layer 170, the interlayer dielectric layer 180, the second insulating capping layer 270, and the source level insulating layer 117 can comprise silicon oxide, all layers of the process source level material layer 10' other than the source level insulating layer 117 can comprise semiconductor material, and the sacrificial material layers (142, 242) can comprise silicon nitride. In such a case, a wet etching process using hot phosphoric acid can be performed to laterally recess the sidewalls of the sacrificial material layers (142, 242) isotropically around each trench region opening 619.

[0198] The duration of the wet etching process can be selected such that the lateral recesses of the sidewalls of the sacrificial material layers (142, 242) are greater than half of the maximum value of the lateral separation distance between trench region openings 619 that laterally surround a corresponding one of the non-opening regions in the non-opening region OFA. The cavities that laterally surround the corresponding non-opening regions OFA within a set of trench region openings 619 merge with each other at each level of the sacrificial material layers (142, 242). The etching is terminated to leave dielectric material plates (142', 242') in the region OFA. The sacrificial material layers (142, 242) are protected from etching through the support openings 19 and the memory openings 49 by the etching mask material layer 352.

[0199] As Figure 13CAs shown, at each level of the sacrificial material layer (142, 242), an annular cavity 679C is formed that laterally surrounds the patterned portion of the corresponding sacrificial material layer (142, 242) in the non - opening area OFA. Each patterned portion of the sacrificial material layer (142, 242) laterally surrounded by the corresponding annular cavity 679C is referred to herein as a dielectric material plate (142’, 242’). The dielectric material plate (142’, 242’) is composed of the same material as the corresponding one of the sacrificial material layers in the sacrificial material layer (142, 242) at the same level (i.e., at the same vertical separation distance from the substrate 8) and has the same height as the corresponding sacrificial material layer. The dielectric material plate (142’, 242’) includes a first dielectric material plate 142’ that is the patterned portion of the first sacrificial material layer 142 and a second dielectric material plate 242’ that is the patterned portion of the second sacrificial material layer 242. The vertical stacking of the dielectric material plates (142’, 242’) is formed in each area laterally surrounded by the annular cavity.

[0200] A set of annular cavities 679C that laterally surround the vertical stacking of the dielectric material plates (142’, 242’) are vertically connected to each other through rows of discrete laterally spaced openings 6790, which correspond to trench - region openings 619 that vertically extend through the insulating layers (132, 232), as Figure 13B shown. Each row of laterally spaced openings 6790 vertically extends through a corresponding one of the insulating layers in the insulating layers (132, 232), and at the level of the corresponding one of the insulating layers in the insulating layers (132, 232), includes a segment of the trench - region opening 619 disposed in the same trench region MR at the Figures 8A to 8C processing step. The rows of laterally spaced openings located in the same trench region MR overlap each other in a plan (i.e., top - down) view. In other words, the area of the laterally spaced openings of any row located in the same trench region MR at the level of one of the insulating layers (132, 232) overlaps with the area of the laterally spaced openings of any other row located in the same trench region MR at the level of another insulating layer in the insulating layers (132, 232). Each row of laterally spaced openings can be arranged along the perimeter of the corresponding non - opening area OFA within the area of the trench region MR. Therefore, the overall lateral extent of each row of laterally spaced openings conforms to the shape of the corresponding non - opening area OFA.

[0201] As Figure 13BAs shown, each insulating layer (132, 232) is perforated with a row of corresponding laterally spaced openings 6790. Each laterally spaced opening 6790 within the row of laterally spaced openings may have a generally cylindrical shape and be laterally spaced from an adjacent laterally spaced opening by a corresponding intermediate portion of the insulating layer (132, 232). Thus, each insulating layer (132, 232) extends laterally from outside the region of each opening-free area (OFA) into the region of the OFA, which region of the OFA overlaps, via an array of connecting portions, with the region of the vertical stack of dielectric material plates (142’, 242’), the array of connecting portions being located between each pair of adjacent laterally spaced openings 6790 that extend vertically through the insulating layer (132, 232).

[0202] The trench groove 679 comprises a continuous combination of an annular cavity (i.e., trench) 679C at the level of the sacrificial material layer (142, 242) and a row of laterally spaced openings 6790 at the level of the insulating layer (132, 232). Each trench groove 679 extends vertically from the top surface of the second insulating capping layer 270 into the source level material layer 10’ in the process. Generally speaking, each trench groove 679 can be formed by selectively isotropically etching the unmasked portions of the sacrificial material layer (142, 242) for the insulating layer (132, 232) and by laterally expanding each trench region opening 619 within the row of trench region openings 619 at the level of the sacrificial material layer (142, 242) to form the annular cavity 679C. In one embodiment, each trench region opening 619 within the row of trench region openings 619 can be laterally expanded at the level of the sacrificial material layer (142, 242) by performing an isotropic etching process that selectively etches the material of the sacrificial material layer (142, 242) with respect to the material of the insulating layer (132, 232). Each trench groove 679 has a continuously extending volume that laterally surrounds a patterned portion of the corresponding sacrificial material layer (142, 242) at each level of the sacrificial material layer (142, 242), i.e., the dielectric material plates (142’, 242’). The remaining portion of the sacrificial material layer (142, 242) after the isotropic etching process comprises a vertical stack of dielectric material plates (142’, 242’) that is laterally surrounded by the trench grooves 679.

[0203] Each trench groove 679 can be laterally defined at its outer boundary by a set of horizontally concave and vertical sidewall segments of the corresponding sacrificial material layer (142, 242) at the level of each sacrificial material layer (142, 242), and can be laterally defined at its inner boundary by a set of horizontally concave and vertical sidewall segments of the corresponding dielectric material plate (142’, 242’) at the level of each sacrificial material layer (142, 242). Each trench groove 679 can be laterally defined by the cylindrical sidewalls of a row of corresponding discrete cylindrical openings 6790 at the level of each insulating layer (132, 232). As used herein, a horizontally concave surface refers to a surface having a concave profile in a horizontal cross-section, and a vertical surface refers to a surface having a straight profile in a vertical cross-section.

[0204] Reference Figure 14 , an isotropic etching process can be performed to remove the remaining portion of the conformal etch mask material layer 352. For example, if the conformal etch mask material layer 352 comprises a semiconductor material, a wet etching process (which employs hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to remove the conformal etch mask material layer 352.

[0205] Reference Figure 15 , a continuous blocking dielectric layer 52C can optionally be deposited on the sidewalls of the memory opening 49, the support opening 19, and the trench groove 679 by a conformal deposition process. The continuous blocking dielectric layer 52C can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the continuous blocking dielectric layer 52C can include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metal element and oxygen, or can consist essentially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the continuous blocking dielectric layer 52C can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the continuous blocking dielectric layer 52C includes alumina. Alternatively or in addition, the continuous blocking dielectric layer 52C can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0206] Reference Figure 16, a sacrificial fill material can be deposited into the unfilled volumes of the memory openings 49, the support openings 19, and the trench grooves 679. The sacrificial fill material includes a material that can be selectively removed with respect to the material of the continuous barrier dielectric layer 52C. The sacrificial fill material can fill the entire volume of the memory openings 49, the support openings 19, and the trench grooves 679. Alternatively, the sacrificial fill material can be deposited anisotropically such that it only fills the upper portion of the volume of the memory openings 49, the support openings 19, and the trench grooves 679. For example, the sacrificial fill material can include a semiconductor material such as amorphous silicon or polysilicon; or a dielectric material such as an organosilicate glass, a polymeric material, or a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial fill material can be deposited by a highly anisotropic deposition process such as a physical vapor deposition (PVD) process. The deposition of the sacrificial fill material in the memory openings 49, the support openings 19, and the trench grooves 679 and above the second insulating capping layer 270 forms a sacrificial fill material layer 359L. The highly anisotropic nature of the deposition process deposits the sacrificial fill material mainly on the upper sidewalls of the memory openings 49, the support openings 19, and the trench grooves 679, and the amount of sacrificial fill material deposited at the bottom regions of the memory openings 49, the support openings 19, and the trench grooves 679 can be negligible. In this case, voids exist in the lower regions of the memory openings 49, the support openings 19, and the trench grooves 679. The voids can exist within each annular cavity 679C at the level of the sacrificial material layer (142, 242) after the sacrificial fill material layer 359L is formed.

[0207] Reference Figure 17A and Figure 17B , a photoresist layer 367 can be applied over the first exemplary structure and can be lithographically patterned to cover all of the memory openings 49 without covering the support openings 19 or the trench grooves 679. The unmasked portions of the sacrificial fill material layer 359L can be removed by an etching process that selectively etches the material of the sacrificial fill material layer 359L with respect to the material of the continuous barrier dielectric layer 52C. An anisotropic etching process and / or an isotropic etching process can be employed. For example, if the sacrificial fill material layer 359L contains amorphous silicon or polysilicon, a wet etching process (which employs hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to remove the unmasked portions of the sacrificial fill material layer 359L. Thus, the sacrificial fill material of the sacrificial fill material layer 359L can be removed from inside the support openings 19 and the trench grooves 679 by the etching process. Subsequently, the photoresist layer 367 can be removed, for example, by ashing.

[0208] Reference Figures 18A to 18C, A dielectric material such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass can be deposited in each of the support opening 19 and the trench groove 679 by a conformal deposition process such as a chemical vapor deposition (CVD) process. The dielectric material fills each volume of the cavity within the support opening 19 and the trench groove 679, and is formed above the top surface of the second insulating capping layer 270 and the horizontal extension of the sacrificial fill material layer 359L covering the second insulating capping layer 270.

[0209] A planarization process can be performed to remove portions of the dielectric material, the sacrificial fill material layer 359L, and the continuous barrier dielectric layer 52C that cover a horizontal plane including the top surface of the second insulating capping layer 270. A recess etching process and / or a chemical mechanical planarization process can be used for the planarization process. Each remaining portion of the dielectric material filling the support opening 19 includes a dielectric support opening fill material portion 20. Each remaining portion of the dielectric material filling the corresponding remaining portion of the trench groove 679 includes a dielectric trench groove fill material portion 176. Each remaining portion of the sacrificial fill material layer 359L that remains at least at the upper end of the memory opening 49 includes a sacrificial fill material portion 359. Each remaining portion of the optional continuous barrier dielectric layer 52C (if employed) located within the support opening 19, the trench groove 679, or the memory opening 49 includes a barrier dielectric layer 52. As an optional structure, the barrier dielectric layer 52 may or may not be present in each of the memory opening 49, the support opening 19, and the trench groove 679. Each continuous combination of the barrier dielectric layer 52 (if present) and the dielectric support opening fill material portion 20 filling the support opening 19 constitutes a support pillar structure (52, 20). Each continuous combination of the barrier dielectric layer 52 (if present) and the dielectric trench groove fill material portion 176 constitutes a perforated dielectric trench structure (52, 176).

[0210] Generally speaking, the perforated dielectric trench structure (52, 176) can extend vertically through the alternating stack {(132, 242), (232, 242)}, and can be formed by optionally filling the trench groove 679 with the corresponding barrier dielectric layer 52 and with a dielectric fill material (which is the material of the dielectric trench groove fill material portion 176). Each perforated dielectric trench structure (52, 176) includes rows of dielectric column portions 172 that extend through the corresponding openings 6790 at each level of the insulating layers (132, 232). Each insulating layer in the insulating layers (132, 232) extends laterally from outside each perforated dielectric trench structure (52, 176) to inside each perforated dielectric trench structure (52, 176) (i.e., inside the no-opening area OFA) between each pair of adjacent dielectric column portions 172.

[0211] In one embodiment, each row of dielectric pillar portions 172 may be disposed along the perimeter of a respective perforated dielectric trench structure (52, 176) at a level of one of the insulating layers (132, 232). Rows of dielectric pillar portions 172 located at different levels of the insulating layers (132, 232) have area overlap with each other.

[0212] The perforated dielectric trench structures (52, 176) further include annular dielectric plate portions 174 at each level of the sacrificial material layers (142, 242), which laterally enclose respective dielectric material plates (142’, 242’). In one embodiment, the dielectric material plates (142’, 242’) comprise a material different from the insulating layers (132, 232) and comprise the same material as the sacrificial material layers (142, 242). In one embodiment, the insulating layers (132, 232) comprise silicon oxide and the dielectric material plates (142’, 242’) comprise silicon nitride. In one embodiment, each of the dielectric material plates (142’, 242’) always has a respective uniform thickness and contacts the planar bottom surface of the respective overlying insulating layer in the insulating layers (132, 232) and contacts the planar top surface of the respective underlying insulating layer in the insulating layers (132, 232). If there is a barrier dielectric layer 52, each of the dielectric pillar portions 172 may include a segment of the barrier dielectric layer 52 and a segment of the dielectric trench groove fill material portion 176, and each of the annular dielectric plate portions 174 may include a segment of the barrier dielectric layer 52 and a segment of the dielectric trench groove fill material portion 176.

[0213] In one embodiment, each of the annular dielectric plate portions 174 includes a continuous inner sidewall and a continuous outer sidewall, the continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other, and the continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other. Each laterally protruding surface is a surface having a protruding profile in a horizontal plane.

[0214] In one embodiment, each perforated dielectric trench structure (52, 176) includes a row of dielectric pillar portions 172 at each level of the insulating layers (132, 232). Each of the continuous inner sidewall and the continuous outer sidewall is laterally offset from the respective overlying row of dielectric pillar portions 172 by a uniform lateral offset distance, which may be a lateral recess distance by which the sidewalls of the sacrificial material layers (142, 242) are laterally recessed relative to the sidewalls of the insulating layers (132, 232) at Figures 13A to 13C the processing step.

[0215] Reference Figure 19 andFigure 20A , the sacrificial fill material portion 359 can be selectively removed with respect to the materials of the insulating layers (132, 232) and the sacrificial material layers (142, 242). For example, if the sacrificial fill material portion 359 comprises amorphous silicon or polycrystalline silicon, a wet etching process (which employs hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to selectively remove the sacrificial fill material portion 359 with respect to the materials of the insulating layers (132, 232) and the sacrificial material layers (142, 242). A memory cavity 49' connected to the environment is formed within each memory opening 49.

[0216] Reference Figure 20B , the charge storage layer can be conformally deposited over each of the barrier dielectric layers 52 and over the top surface of the second insulating capping layer 270. In one embodiment, the charge storage layer can be a continuous layer or a patterned discrete portion of a charge trapping material that comprises a dielectric charge trapping material (e.g., it can be silicon nitride). Alternatively, the charge storage layer can include a continuous layer or a patterned discrete portion of a conductive material (such as doped polysilicon or a metal material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed as the sacrificial material layers (142, 242) within the lateral recesses. In one embodiment, the charge storage layer comprises a silicon nitride layer. In one embodiment, the sacrificial material layers (142, 242) and the insulating layers (132, 232) can have vertically aligned sidewalls, and the charge storage layer can be formed as a single continuous layer. Alternatively, the sacrificial material layers (142, 242) can be laterally recessed with respect to the sidewalls of the insulating layers (132, 232), and a combination of deposition processes and anisotropic etching processes can be used to form the charge storage layer as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer can be in the range of 2 nm to 20 nm, although smaller and larger thicknesses can also be used.

[0217] A tunneling dielectric layer 56 can be formed over the charge storage layer. The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the monomer three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a carbon-free silicon oxide layer or a carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 can be in the range of 2 nm to 20 nm, although smaller and larger thicknesses can also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50 that stores the memory bits.

[0218] A semiconductor channel material layer 60L can be formed over the tunneling dielectric layer 56. The semiconductor channel material layer 60L can include a doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The conductivity type of the dopant in the semiconductor channel material layer 60L is referred to herein as the first conductivity type, which can be p-type or n-type. In one embodiment, the semiconductor channel material layer 60L has p-type doping, where a p-type dopant (such as boron atoms) is present at an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 range. In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polycrystalline silicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, where an n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 such as 1.0×10 14 / cm 3 to 1.0×1017 / cm 3 An atomic concentration within the range exists. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. A cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 56, 60L).

[0219] Reference Figure 20C , in an embodiment where the memory cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low-pressure chemical vapor deposition (LPCVD)) or by a self-planarizing deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating capping layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the second insulating capping layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0220] See Figure 20D , a doped semiconductor material can be deposited in the cavity covering the dielectric core 62. The doped semiconductor material has a doping with a conduction type opposite to that of the semiconductor channel material layer 60L. In one embodiment, the doped semiconductor material has an n-type doping. The deposited doped semiconductor material, portions of the semiconductor channel material layer 60L, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 covering a horizontal plane (which includes the top surface of the second insulating capping layer 270) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0221] Each remaining portion of the doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 can be in the range of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 , but smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0222] Each remaining portion of the semiconductor channel layer 60L forms a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 can be surrounded by the charge storage layer 54 and laterally surround the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together form a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, there may be no blocking dielectric layer 52 in the memory film 50 at this step, and a backside blocking dielectric layer may be formed later after the backside recess is formed. As used herein, macroscopic retention time refers to the retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0223] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 forms a memory stack structure 55. The memory stack structure 55 can be a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, multiple memory elements including portions of the charge storage layer 54, and optionally the blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 forms a memory opening fill structure 58. Each drain region 63 in the memory opening fill structure 58 is electrically connected to the upper end of a corresponding one of the vertical semiconductor channels 60. The source level material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265), the interlayer dielectric layer 180, and the memory opening fill structure 58 in the process together form a memory level component.

[0224] The memory stack structure 55 is formed by passing through the alternating stacks {(132, 142), (232, 242)}. Each memory stack structure in the memory stack structure 55 includes a vertical semiconductor channel 60 and a vertical stack of memory elements in the memory film 50 located at the level of the sacrificial material layers (142, 242). Each vertical stack of memory elements includes portions of charge storage material (i.e., portions of the charge storage layer) located at each level of the sacrificial material layer 142 and laterally spaced from the vertical semiconductor channel 60 within the same memory opening 49 by the tunneling dielectric layer 56.

[0225] Reference Figures 21A to 21C, showing a first exemplary structure after forming the memory opening fill structure 58. Each of the alternating stacks {(132,142),(232,242)} includes a platform region, where each sacrificial material layer (142,242) within the alternating stacks {(132,142) and / or (232,242)}, except for the topmost sacrificial material layer (142,242), extends further laterally than any of the overlying sacrificial material layers (142,242) within the alternating stacks {(132,142) and / or (232,242)}. The platform region includes a stepped surface of the alternating stack that extends continuously from the bottommost layer within the alternating stack {(132,142) or (232,242)} to the topmost layer within the alternating stack {(132,142) or (232,242)}. The support pillar structures (52,20) extend through the stepped surface and through the backward stepped dielectric material portion (165 or 265) covering the stepped surface.

[0226] Reference Figure 22A , Figure 22B and Figure 23A , a first contact level dielectric layer 280 may be formed over the second layer structure (232,242,270,265). The first contact level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

[0227] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be lithographically patterned to form various openings in the memory array region 100 and the staircase region 200. The openings in the photoresist layer include a first elongated opening that extends laterally along a first horizontal direction hd1 across the entire lateral extent of the memory array region 100 and the staircase region 200 along the first horizontal direction hd1. The first elongated opening extends laterally between the memory opening fill structure 58 and the group of support pillar structures 20. Additionally, the openings in the photoresist layer may include a second elongated opening that extends along the first horizontal direction hd1 between clusters of the memory opening fill structure 58 that are laterally spaced apart and positioned between a pair of adjacent first elongated openings along the first horizontal direction hd1. Each second elongated opening has a lateral extent smaller than the lateral extent of the memory array region 100 along the first horizontal direction hd1. Optionally, the openings in the photoresist layer may include discrete openings positioned between the end regions of a pair of adjacent second elongated openings.

[0228] Anisotropic etching may be performed to transfer a pattern in a photoresist layer through underlying material portions including an alternating stack {(132, 142), (232, 242)} and an upper portion of the source level material layer 10' in the process. A backside trench 79 may be formed under a first elongated opening in the photoresist layer to extend through the first contact level dielectric layer 280, the second layer structure (232, 242, 270, 265), and the first layer structure (132, 142, 170, 165) and into the source level material layer 10' in the process. The first contact level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the portions of the source level material layer 10' under the first elongated opening in the photoresist layer may be removed to form the backside trench 79. In one embodiment, the backside trench 79 may be formed between groups of memory stack structures 55 that are laterally spaced apart along a second horizontal direction. The top surface of the source level sacrificial layer 104 may be physically exposed at the bottom of each backside trench 79.

[0229] Generally, an alternating stack {(132, 232), (142, 242)} of an insulating layer 132 and sacrificial material layers (142, 242) may be formed over a semiconductor substrate 8 including a substrate semiconductor layer 9. The sacrificial material layers (142, 242) may include a dielectric material such as silicon nitride. The alternating stack {(132, 232), (142, 242)} may be etched by performing an anisotropic etching process using a patterned mask layer such as a photoresist layer. The alternating stack {(132, 232), (142, 242)} may be divided by the backside trench 79 into multiple alternating stacks {(132, 232), (142, 242)} of corresponding insulating layers (132, 232) and corresponding sacrificial material layers (142, 242).

[0230] A photoresist layer (not shown) may be applied over the first exemplary structure and may be lithographically patterned to form laterally extending linear openings that extend laterally between adjacent clusters of the memory opening fill structures 58 along a first horizontal direction hd1. The pattern of the laterally extending linear openings may be transferred through an upper set of at least one insulating layer 232 and at least one sacrificial material layer 242 to form drain select level trenches. The photoresist layer may be removed, for example, by ashing.

[0231] A dielectric fill material (such as undoped silicate glass or doped silicate glass) can be deposited in the drain select level trenches. The excess portion of the dielectric fill material can be removed from above layer 280 through a planarization process. The portion of the dielectric fill material that fills the drain select level trenches constitutes the drain select level isolation structure 72, which separates the drain select electrodes that will be formed in a later step, in place of one or more of the higher sacrificial material layers 242.

[0232] Reference Figure 23B , in an isotropic etching process, an etchant that selectively etches the material of the source level sacrificial layer 104 with respect to the materials of the first layer alternating stack (132, 142), the second layer alternating stack (232, 242), the first insulating capping layer and the second insulating capping layer (170, 270), the first contact level dielectric layer 280, the higher sacrificial liner 105, and the lower sacrificial liner 103 can be introduced into the backside trenches. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, and if the higher and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process (which uses hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to selectively remove the source level sacrificial layer 104 with respect to the higher and lower sacrificial liners (105, 103). A source cavity 109 can be formed in the volume from which the source level sacrificial layer 104 is removed.

[0233] Wet etching chemistries such as hot TMY and TMAH are selective with respect to the doped semiconductor materials of the higher source level semiconductor layer 116 and the lower source level semiconductor layer 112. Thus, using selective wet etching chemistries such as hot TMY and TMAH in the wet etching process for forming the source cavity 109 provides a larger process window for resisting variations in etching depth during the formation of the backside trenches 79. Specifically, in embodiments where the sidewalls of the higher source level semiconductor layer 116 are physically exposed during the formation of the source cavity 109 or in embodiments where the surface of the lower source level semiconductor layer 112 is physically exposed, the incidental etching of the higher source level semiconductor layer 116 and / or the lower source level semiconductor layer 112 is minimal, and structural variations of the first exemplary structure caused by the accidental physical exposure of the surface of the higher source level semiconductor layer 116 and / or the lower source level semiconductor layer 112 during the manufacturing steps do not result in device failure. Each of the memory opening fill structures 58 can be physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 can include sidewalls and bottom surfaces that are physically exposed to the source cavity 109.

[0234] Reference Figure 23C, a sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to etch various component layers of the memory film 50 sequentially from the outside to the inside, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial pads (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial pads (105, 103). The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 can be formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each memory film in the memory films for at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0235] Reference Figure 23D , a doped semiconductor material doped with a second conductivity type can be deposited on the physically exposed semiconductor surface around the source cavity 109. The second conductivity type is opposite to the first conductivity type, which is the doped conductivity type of the vertical semiconductor channel 60. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surface of at least one source-level semiconductor layer (112, 116). For example, the physically exposed semiconductor surface can include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the upper source-level semiconductor layer 116.

[0236] In one embodiment, a doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface around the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas can simultaneously flow into the processing chamber including the first exemplary structure. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the n-type dopant precursor gas such as phosphine, arsine, or stibine. In this case, the selective semiconductor deposition process grows an in-situ doped semiconductor material from the physically exposed semiconductor surface around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which can contact the sidewall of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be at 1.0×10 20 / cm3 to 2.0×10 21 / cm 3 within the range of, such as 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may be substantially composed of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0237] The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source level sacrificial layer 104 may be replaced by the source contact layer 114.

[0238] A layer stack including a lower source level semiconductor layer 112, a source contact layer 114, and a higher source level semiconductor layer 116 constitutes a source region (112, 114, 116). The source region (112, 114, 116) is electrically connected to the first end (such as the bottom end) of each of the vertical semiconductor channels 60. A layer group including the source region (112, 114, 116), a source level insulating layer 117, and a source select level conductive layer 118 constitutes the source level material layer 10, which replaces the source level material layer 10' in the replacement process.

[0239] Reference Figure 23E , an oxidation process may be performed to convert the physically exposed surface portion of the semiconductor material into a dielectric semiconductor oxide portion. For example, the surface portions of the source contact layer 114 and the higher source level semiconductor layer 116 may be converted into dielectric semiconductor oxide plates 122, and the surface portion of the source select level conductive layer 118 may be converted into an annular dielectric semiconductor oxide spacer 124.

[0240] Reference Figure 24A and Figure 24B, the sacrificial material layers (142, 242) can be selectively removed for the insulating layers (132, 232), the first and second insulating capping layers (170, 270), the first contact level dielectric layer 280, and the source contact layer 114, the dielectric semiconductor oxide plate 122, and the annular dielectric semiconductor oxide spacer 124. For example, an isotropic etching process can be used to introduce an isotropic etchant that selectively etches the material of the sacrificial material layers (142, 242) with respect to the materials of the insulating layers (132, 232), the first and second insulating capping layers (170, 270), the back-step dielectric material portions (165, 265), and the outermost layer of the memory film 50 into the backside trench 79.

[0241] The isotropic etching process can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in a gaseous phase. For example, if the sacrificial material layers (142, 242) comprise silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching bath comprising phosphoric acid, and the wet etching process selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art. The duration of the isotropic etching process can be selected such that the entire sacrificial material layers (142, 242) are removed by the isotropic etching process.

[0242] Backside recesses (143, 243) can be formed in the volume from which the sacrificial material layers (142, 242) are removed. The backside recesses (143, 243) include a first backside recess 143 that can be formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 that can be formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) can be greater than the height of the corresponding backside recess (143, 243). A plurality of backside recesses (143, 243) can be formed in the volume from which the material of the sacrificial material layers (142, 242) is removed. Each of the backside recesses (143, 243) can extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recesses (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) can have a uniform height throughout. The perforated dielectric trench structures (52, 176) protect the dielectric material plates (142’, 242’) in the open-free area OFA from etching or removal.

[0243] Reference Figure 25A and Figure 25B A backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses (143, 243) and the backside trench 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may comprise aluminum oxide. The backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be used.

[0244] At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trench 79, and over the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include elemental metals, intermetallic alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal semiconductor alloys such as metal silicides, alloys thereof, and combinations or stacks thereof.

[0245] In one embodiment, the at least one conductive material may include at least one metal material, i.e., a conductive material comprising at least one metal element. Non-limiting exemplary metal materials that may be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material for filling the backside recesses (143, 243) may be a combination of a titanium nitride layer and a tungsten fill material.

[0246] The conductive layers (146, 246) can be formed in the backside recesses (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each backside trench 79 and above the first contact level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a corresponding conductive metal nitride liner and a corresponding conductive fill material. Thus, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the backside barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the backside barrier dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0247] Residual conductive material can be removed from inside the backside trench 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes the first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes the second conductive layer 246. The sidewalls of the first conductive layer 146 and the second conductive layer 246 can be physically exposed to the corresponding backside trench 79.

[0248] Each conductive layer (146, 246) can be a conductive sheet including openings. A first subset of the openings through each conductive layer (146, 246) can be filled with the memory opening fill structure 58. A second subset of the openings through each conductive layer (146, 246) can be filled with the support pillar structures (52, 20). The via dielectric trench structures (52, 176) extend vertically through each conductive layer (146, 246).

[0249] Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The semiconductor devices in the lower peripheral device region 700 may include word line switching devices configured to control the bias voltage to the respective word lines. The memory tier assembly is positioned above the substrate semiconductor layer 9. The memory tier assembly includes at least one alternating stack {(132, 146), (232, 246)} and the memory stack structure 55 extending vertically through at least one alternating stack (132, 146, 232, 246).

[0250] Reference Figure 26A and Figure 26B , a dielectric material may be deposited in the unfilled volume of the backside trench 79. The excess portion of the dielectric material may be removed from above the top surface of the first contact tier dielectric layer 280 by a planarization process, which may employ a recess etching process or a chemical mechanical planarization process. Each remaining portion of the dielectric material filling the backside trench 79 constitutes a dielectric wall structure 76. The dielectric wall structure 76 may extend laterally along the first horizontal direction hd1 and comprise a dielectric material such as undoped silicate glass or doped silicate glass.

[0251] Reference Figure 27A and Figure 27B , an array region through-memory tier interconnect via structure 588 may be formed through the vertical stack of the insulating layers (132, 232) and the dielectric material plates (142’, 242’), and a peripheral through-memory tier interconnect via structure 488 may be formed through the back stepped dielectric material portions (165, 265). Each of the array region through-memory tier interconnect via structure 588 and the peripheral through-memory tier interconnect via structure 488 may be formed on a respective one of the landing pad tier metal line structures in the landing pad tier metal line structure 788, which are subsets of the lower tier metal interconnect structures 780 embedded in the lower tier dielectric material layer 760. Each array region through-memory tier interconnect via structure 588 is an interconnect via structure surrounded by a perforated dielectric trench structure (52, 176) and may extend vertically through each insulating layer (132, 232) and the vertical levels of the conductive layers (146, 246).

[0252] Subsequently, higher-level dielectric material layers (282, 290) and higher-level metal interconnect structures (88, 86, 286, 98, 96) can be formed. The higher-level dielectric material layers (282, 290) can include a second contact-level dielectric layer 282 and a first line-level dielectric layer 290. The higher-level metal interconnect structures (88, 86, 286, 98, 96) can include a drain contact via structure 88, a word line layer contact via structure 86, a connection via structure 286, a bit line 98, and a connection metal line 96. The drain contact via structure 88 extends through the first contact-level dielectric layer 280 and the second contact-level dielectric layer 282 and contacts a corresponding one of the drain regions in the drain region 63. The word line layer contact via structure 86 extends through the first contact-level dielectric layer 280, the second contact-level dielectric layer 282, the second backward stepped dielectric material portion 265, and optionally through the first backward stepped dielectric material portion 165, and contacts a corresponding one of the conductive layers (e.g., word lines) (146, 246). The connection via structure 286 extends through the second contact-level dielectric layer 282 and contacts the top surface of a corresponding one of the array region through-memory-level interconnect vias structure 588 and the peripheral through-memory-level interconnect vias structure 488. Thus, each of the array region through-memory-level interconnect vias structure 588 and the peripheral through-memory-level interconnect vias structure 488 can be electrically connected to the bottom surface of a higher-level metal interconnect structure in the higher-level metal interconnect structures, such as the bottom surface of the connection metal line 96. The bit line 98 is embedded in the first line-level dielectric layer 290 and contacts a corresponding subset of the drain contact via structures 88. The connection metal line 96 is embedded in the first line-level dielectric layer 290 and contacts a corresponding subset of the via structures, such as the word line layer contact via structure 86 and / or the connection via structure 286. Additional higher-level dielectric material layers (not shown) and additional higher-level metal interconnect structures (not shown) can be formed as needed.

[0253] Referring to all of the accompanying drawings and in accordance with various embodiments of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the alternating stack being positioned over a substrate 8; a memory stack structure 55 extending vertically through the alternating stack {(132, 146), (232, 246)}, wherein each memory stack structure in the memory stack structure 55 includes a vertical semiconductor channel 60 and a vertical stack of memory elements located at levels of the conductive layers (146, 246); a perforated dielectric trench structure (52, 176) extending vertically through the alternating stack {(132, 146), (232, 246)} and including a plurality of lateral openings at each level of the insulating layers (132, 232) and not including any openings at levels of the conductive layers (146, 246); and an interconnection via structure (such as an array region through-memory-level interconnection via structure) 588, the interconnection via structure being laterally surrounded by the perforated dielectric trench structure (52, 176) and extending vertically through each insulating layer (132, 232) within the alternating stack {(132, 146), (232, 246)}.

[0254] In one embodiment, the perforated dielectric trench structure (52, 176) includes rows of dielectric column portions 172 at each level of the insulating layers (132, 232), wherein each insulating layer in the insulating layers (132, 232) extends laterally from outside the perforated dielectric trench structure (52, 176) to inside the perforated dielectric trench structure (52, 176) between adjacent pairs of dielectric column portions 172.

[0255] In one embodiment, each row of dielectric column portions 172 is arranged along the perimeter of the perforated dielectric trench structure at a level of one of the insulating layers (132, 232).

[0256] In one embodiment, there is an area overlap between rows of dielectric column portions 172 located at different levels of the insulating layers (132, 232). In one embodiment, the perforated dielectric trench structure (52, 176) includes annular dielectric plate portions 174 at each level of the conductive layers (146, 246), the annular dielectric plate portions laterally surrounding corresponding dielectric material plates (142’ or 242’).

[0257] In one embodiment, the dielectric material plates (142’, 242’) comprise a material different from the insulating layers (132, 232). In one embodiment, the through-interconnect via structure 588 extends vertically through the vertical stack of the dielectric material plates (142’, 242’) and the insulating layers (132, 232) in a region (AFO) surrounded by the perforated dielectric trench structures (52, 176). In one embodiment, the insulating layers (132, 232) comprise a silicon oxide material; and the dielectric material plates (142’, 242’) comprise a silicon nitride.

[0258] In one embodiment, each of the dielectric material plates in the dielectric material plates (142’, 242’) always has a corresponding uniform thickness, and contacts the planar bottom surface of the corresponding overlying insulating layer in the insulating layers (132, 232) and contacts the planar top surface of the corresponding underlying insulating layer in the insulating layers (132, 232).

[0259] In one embodiment, each of the annular dielectric plate portions 174 in the annular dielectric plate portion includes a continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other; and a continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other.

[0260] In one embodiment, each of the continuous inner sidewall and the continuous outer sidewall is laterally offset from the corresponding overlying row of the dielectric column portions 172 by a uniform lateral offset distance.

[0261] In one embodiment, the three-dimensional memory device includes: a lower-level dielectric material layer 760 disposed between the substrate 8 and the alternating stack {(132, 146), (232, 246)}; and a lower-level metal interconnect structure 780 embedded within the lower-level dielectric material layer 760, wherein a through-interconnect via structure (such as the array region direct memory level through-interconnect via structure 588) contacts the top surface of one of the lower-level metal interconnect structures in the lower-level metal interconnect structure 780.

[0262] In one embodiment, the three-dimensional memory device includes a field-effect transistor located above the substrate 8 and including a node electrically connected to a through-interconnect via structure (such as the array region direct memory level through-interconnect via structure 588) through a subset of the lower-level metal interconnect structure 780.

[0263] In one embodiment, a 3D memory device may include: a higher-level dielectric material layer (282, 290) located above an alternating stack {(132, 146), (232, 246)}; and a higher-level metal interconnect structure (88, 86, 286, 98, 96) embedded within the higher-level dielectric material layer (282, 290), wherein an interconnect via structure (such as the array region through-memory-level interconnect via structure 588) contacts a bottom surface (such as the bottom surface of the connection metal line 96) of one of the higher-level metal interconnect structures in the higher-level metal interconnect structure (88, 86, 286, 98, 96).

[0264] In one embodiment, a vertical stack of memory elements includes portions of a charge storage layer 54 that are located at each level of a conductive layer (146, 246) and are laterally spaced from a respective one of vertical semiconductor channels 60 by a tunneling dielectric layer 56.

[0265] The perforated dielectric trench structures (52, 176) of embodiments of the present disclosure do not completely divide any insulating layer (132, 232) into separate portions. Thus, the perforated dielectric trench structures (52, 176) do not divide any alternating stack of an insulating layer (132, 232) and a sacrificial material layer (142, 242) or a conductive layer (146, 246) into separate portions. By avoiding dividing the alternating stack into two separate portions between adjacent backside trench pairs 79, tilting and flipping of portions of the alternating stack at the location of the perforated dielectric trench structures (52, 176) can be avoided. Each insulating layer (132, 232) extends laterally from outside the region surrounded by the perforated dielectric trench structure (52, 176) to inside the region surrounded by the perforated dielectric trench structure (52, 176) through a gap between columns 172 of the dielectric trench structure (52, 176) and supports adjacent alternating stacks during manufacturing steps. This improves the structural stability of the device without significantly complicating device processing. Accordingly, various embodiments of the present disclosure provide compact, stable, and reliable 3D memory devices with improved yield.

[0266] Reference Figures 28A to 28C , additional openings may be formed from within a region laterally enclosed by the trench region MR Figures 4A to 4CThe first exemplary structure leads to a second exemplary structure according to a second embodiment of the present disclosure. The area laterally enclosed by the inner perimeter of the trench region MR in the second exemplary structure includes an opening in the first layer alternating stack (132, 142), and is herein referred to as the via opening area VOA. Additional openings through the first layer alternating stack (132, 142) may be formed simultaneously with various first layer openings (149, 129, 529), and are herein referred to as first layer connection via area openings. At Figure 5 the processing step of, during the formation of the sacrificial first layer opening fill portions (148, 128, 528), the first layer connection via area openings are filled with a sacrificial fill material. At Figure 5 the processing step of, each portion of the sacrificial fill material that fills the first layer connection via area openings is herein referred to as a sacrificial first layer connection via fill portion. Subsequently, the processing steps of Figure 6A and Figure 6B may be performed, and Figures 7A to 7C the processing step of may be performed with a modification in the pattern of various second layer openings (249, 229, 629) such that additional second layer openings are formed through the second layer alternating stack (232, 242) directly on top of a corresponding one of the sacrificial first layer connection via fill portions. Each additional second layer opening formed on a corresponding one of the sacrificial first layer connection via fill portions is herein referred to as a second layer connection via area opening 309.

[0267] Thus, Figures 28A to 28C the second exemplary structure shown in may be derived from the first exemplary structure by forming sacrificial first layer connection via fill portions (which fill the corresponding first layer connection via area openings) through the first layer structure within the via opening area VOA (which is laterally surrounded by the trench region MR) and by forming second layer connection via area openings 309 through the second layer structure within the via opening area VOA. In one embodiment, multiple stacks of sacrificial first layer connection via fill portions and second layer connection via area openings 309 may be formed within the via opening area VOA. In one embodiment, multiple stacks of sacrificial first layer connection via fill portions and second layer connection via area openings 309 may be arranged in a single row or multiple rows extending laterally along a first horizontal direction hd1.

[0268] Referring to Figures 29A to 29E , the processing steps of Figures 8A to 8CThe processing steps are to use an etching process to remove the sacrificial first layer opening fill portions (148, 128, 528) and the sacrificial first layer fill material that fills the sacrificial first layer connection vias. The etching process selectively etches the sacrificial first layer fill material with respect to the materials of the first insulating layer and the second insulating layer (132, 232), the first sacrificial material layer and the second sacrificial material layer (142, 242), the first insulating capping layer and the second insulating capping layer (170, 270), and the interlayer dielectric layer 180. Memory openings 49 (also referred to as interlayer memory openings 49) are formed in each combination of the second layer memory openings 249 and the volume of the sacrificial first layer memory opening fill portion 148 removed therefrom. Support openings 19 (also referred to as interlayer support openings 19) can be formed in each combination of the second layer support openings 229 and the volume of the sacrificial first layer support opening fill portion 128 removed therefrom. Trench region openings 619 (also referred to as interlayer trench openings 619) can be formed in each combination of the second layer trench region openings 629 and the volume of the sacrificial first layer trench region opening fill portion 528 removed therefrom. Connection via region openings 329, which are referred to herein as interlayer connection via region openings 329, are formed in a respective one of the via opening regions (VOA) within the via opening region surrounded laterally by the corresponding trench region MR. Each connection via region opening 329 is formed in each combination of the second layer connection via openings 309 and the volume of the underlying sacrificial first layer connection via fill portion removed (i.e., the volume of the underlying first layer connection via opening).

[0269] Each group of trench region openings 619 adjacent to each other can surround the corresponding via opening region VOA laterally. In other words, each via opening region VOA can be surrounded by a corresponding group of trench region openings 619 that are arranged along the perimeter of the via opening region VOA within the corresponding trench region MR. In one embodiment, each via opening region OFA can be a rectangular region having a pair of longitudinal edges that extend laterally along a first horizontal direction hd1 and having a pair of lateral edges that extend laterally along a second horizontal direction hd2. In this case, each group of trench region openings 619 can include two rows of straight trench region openings 619 arranged along the first horizontal direction hd1 and two rows of straight trench region openings 619 arranged along the second horizontal direction hd2. The source level material layer 10' in the process can include an opening within each via opening region VOA. In one embodiment, the connection via region opening 329 can extend vertically through the opening within the source level material layer 10' in the process.

[0270] Generally speaking, an alternating stack of an insulating layer (132, 232) and a sacrificial material layer (142, 242) containing a dielectric material can be formed over a substrate 8. The sacrificial material layer (142, 242) contains a dielectric material. The trench region opening 619 can include a row of discrete laterally spaced-apart openings and can be formed through the alternating stack {(132, 242), (232, 242)}. The row of discrete laterally spaced-apart openings can be arranged in a pattern that surrounds a region (such as a region of a via opening area VOA within the alternating stack {(132, 242), (232, 242)}).

[0271] In one embodiment, a row of trench region openings 619 can be formed through the alternating stack {(132, 242), (232, 242)}, which includes a first layer alternating stack (132, 142) and a second layer alternating stack (232, 242). The row of trench region openings 619 can be arranged in a pattern that surrounds a region (such as a via opening area VOA located within the trench region MR) within the alternating stack {(132, 242), (232, 242)}. Generally speaking, at least one connection via region opening 329 can be formed through the alternating stack {(132, 242), (232, 242)} and a portion 768' of at least one second dielectric layer 768, which extends through a process in-source level material layer 10' and an optional conductive plate layer 6 located within the region surrounded by the row of trench region openings 619 (i.e., within the via opening area VOA). Generally speaking, by performing an anisotropic etching process using a patterned etching mask, the row of trench region openings 619 and at least one connection via region opening 329 are formed at the same processing step (such as Figures 29A to 29E of the processing steps). The row of trench region openings 619 stops on the process in-source level material layer 10'. In contrast, at least one connection via region opening 329 does not contact the process in-source level material layer 10' and extends through a portion 768' of at least one second dielectric layer 768 until it stops on one of the landing pad level wire structures 788 in the landing pad level wire structure.

[0272] Reference Figure 30A and Figure 30B shows a second exemplary structure according to a second embodiment of the present disclosure after the formation of a conformal etching mask material layer 352 and a conformal covering material layer 354. Figure 30A The vertical sectional plane of Figures 29A to 29C can be the same as the vertical sectional plane D-D' at the processing step of

[0273] Specifically, the conformal etch mask material layer 352 and the conformal capping material layer 354 can be sequentially deposited in each of the memory opening 49, the support opening 19, the trench region opening 619, and the via connection region opening 329 and over the second insulating capping layer 270. The conformal etch mask material layer 352 includes a material that can serve as an etch mask material for a subsequent etch process that is used to etch the unmasked portions of the sacrificial material layers (142, 242). For example, the conformal etch mask material layer 352 can include a semiconductor material such as amorphous silicon or polysilicon. The conformal etch mask material layer 352 can be deposited by a conformal deposition process such as a chemical vapor deposition process (e.g., a low-pressure chemical vapor deposition process). The thickness of the conformal etch mask material layer 352 can be in the range of 20 nm to 120 nm, such as 30 nm to 80 nm, although smaller and larger thicknesses can also be employed.

[0274] The conformal capping material layer 354 includes a material that can protect the masked portions of the conformal etch mask material layer 352 during a subsequent patterning process. For example, if the conformal etch mask material layer 352 includes a semiconductor material, the conformal capping material layer 354 can include silicon oxide. The conformal capping material layer 354 can be formed by thermal oxidation of the material of the conformal etch mask material layer 352 or can be formed by a conformal deposition process. The thickness of the conformal capping material layer 354 can be in the range of 5 nm to 30 nm, such as 10 nm to 20 nm, although smaller and larger thicknesses can also be employed. In the case where the conformal capping material layer 354 includes silicon oxide formed by oxidation of the surface portion of the conformal etch mask material layer 352, the thickness of the conformal etch mask material layer 352 can be reduced by approximately half the thickness of the conformal capping material layer 354, which is a semiconductor oxide layer, due to the oxidation of the surface portion of the conformal etch mask material layer 352.

[0275] Reference Figure 31A and Figure 31B, a patterned photoresist layer 357 may be formed over the second exemplary structure. For example, a photoresist layer may be applied over the second exemplary structure and lithographically patterned to form openings in regions corresponding to combinations of via opening regions VOA and surrounding trench regions MR. In other words, the openings in the patterned photoresist layer 357 may be formed in regions of rows of trench region openings 619 and within via opening regions VOA laterally enclosed by the rows of trench region openings 619. The profile of each row of trench region openings 619 may be to enclose the corresponding via opening region VOA. In one embodiment, each opening through the patterned photoresist layer 357 may have a rectangular shape having a pair of longitudinal edges extending laterally along a first horizontal direction hd1 and a pair of transverse edges extending laterally along a second horizontal direction hd2. The connecting via region openings 329 are located within the openings through the patterned photoresist layer 357. Trench region cavities 619' that are unfilled volumes of the trench region openings 619 are present within the volume of each trench region opening 619. Connecting via region cavities 329' that are unfilled volumes of the connecting via region openings 329 are present within the volume of each connecting via region opening 329. Since the photoresist layer 357 is not located within any of the long, wide, and deep trenches, the likelihood of photoresist cracking within such deep trenches is reduced. Additionally, the likelihood of spurious photoresist resolution due to radiation interference during exposure is reduced by the presence of the conformal etch mask material layer 352 located within the various openings (19, 49, etc.).

[0276] Reference Figure 32A and Figure 32B , a selective etching process may be performed to selectively etch the material of the conformal overcoat material layer 354 with respect to the material of the conformal etch mask material layer 352 to remove the exposed portions of the conformal overcoat material layer 354, including portions located within the trench region openings 619. For example, if the conformal overcoat material layer 354 comprises silicon oxide and if the conformal etch mask material layer 352 comprises amorphous silicon, a wet etching process using diluted hydrofluoric acid may be performed to etch the unmasked portions of the conformal overcoat material layer 354 without etching the conformal etch mask material layer 352.

[0277] Reference Figure 33A and Figure 33B , subsequently, the patterned photoresist layer 357 may be removed, for example, by ashing. Memory cavities 49' are present within each memory opening 49, and support cavities 19' are present within each support opening 19.

[0278] Reference Figure 34A and Figure 34B, a selective etching process can be performed to selectively etch the material of the conformal etch mask material layer 352 with respect to the material of the conformal covering material layer 354. The unmasked portion of the conformal etch mask material layer 352 can be selectively etched with respect to the material of the conformal covering material layer 354. For example, if the conformal etch mask material layer 352 comprises amorphous silicon or polysilicon and if the conformal covering material layer 354 comprises silicon oxide, a chemical dry etching (CDE) or a wet etching process (which employs hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be used to remove the unmasked portion of the conformal etch mask material layer 352 in the trench region opening 619 without etching the conformal covering material layer 354. The sidewalls of the trench region opening 619 are physically exposed when removing the unmasked portion of the conformal etch mask material layer 352. The sidewalls of the via connection region opening 329 are physically exposed when removing the unmasked portion of the conformal etch mask material layer 352. Each of the memory opening 49 and the support opening 19 can be covered by a layer stack of the conformal etch mask material layer 352 and the conformal covering material layer 354.

[0279] Reference Figure 35A and Figure 35B , the conformal covering material layer 354 can be etched by a first etching process, which can be a first isotropic etching process employing diluted hydrofluoric acid. The first isotropic etching process can be used to remove all remaining portions of the conformal covering material layer 354. In the case where the first insulating layer 132 and the second insulating layer 232 comprise silicon oxide, the first isotropic etching process can cause the physically exposed sidewalls of the first insulating layer 132 and the second insulating layer 232 to be recessed in parallel around each via connection region opening 329 and each trench region opening 619 with respect to the sidewalls of the first sacrificial material layer 142 and the second sacrificial material layer 242. The lateral recess distance of the sidewalls of the first insulating layer 132 and the second insulating layer 232 due to the first isotropic etching process can be substantially the same as the thickness of the conformal covering material layer 354, and the thickness of the conformal covering material layer can be in the range of 5 nm to 30 nm, such as 10 nm to 20 nm.

[0280] Reference Figures 36A to 36D, a second selective etching process (such as a second isotropic etching process) can be performed to laterally recess the physically exposed sidewalls of the sacrificial material layers (142, 242) relative to the sidewalls of the insulating layers (132, 242) in the trench regions MR, the first insulating capping layer 170, the interlayer dielectric layer 180, the second insulating capping layer 270, and the source level material layer 10' in the process. In one embodiment, the insulating layers (132, 242), the first insulating capping layer 170, the interlayer dielectric layer 180, the second insulating capping layer 270, and the source level insulating layer 117 can comprise silicon oxide, all layers of the source level material layer 10' in the process except the source level insulating layer 117 can comprise semiconductor material, and the sacrificial material layers (142, 242) can comprise silicon nitride. In this case, a wet etching process using hot phosphoric acid can be performed to isotropically laterally recess the sidewalls of the sacrificial material layers (142, 242) around each trench region opening 619.

[0281] The duration of the wet etching process can be selected such that the lateral recess of the sidewalls of the sacrificial material layers (142, 242) is greater than half of the maximum value of the lateral separation distance between the nearest trench region openings 619 that laterally surround a corresponding via opening region VOA in the via opening region VOA. The cavities that laterally surround the corresponding via opening regions VOA within a set of trench region openings 619 merge with each other at each level of the sacrificial material layers (142, 242). The etching is terminated to leave dielectric material plates (142', 242') in the via opening regions VOA. The sacrificial material layers (142, 242) are protected from etching through the support openings 19 and the memory openings 49 by the etching mask material layer 352.

[0282] In one embodiment, Figures 36A to 36D the processing steps of Figures 13A to 13C can be the same as the second isotropic etching process of the processing steps of Figure 36DAs shown, an annular cavity 679C that laterally surrounds a patterned portion of a corresponding sacrificial material layer (142, 242) is formed at each level of the sacrificial material layer (142, 242). Each patterned portion of the sacrificial material layer (142, 242) that is laterally surrounded by the corresponding annular cavity 679C is referred to herein as a dielectric material plate (142’, 242’). The dielectric material plate (142’, 242’) is composed of the same material as the corresponding one of the sacrificial material layers in the sacrificial material layer (142, 242) at the same level (i.e., at the same vertical separation distance from the substrate 8) and has the same height as the corresponding sacrificial material layer. The dielectric material plate (142’, 242’) includes a first dielectric material plate 142’ that is a patterned portion of the first sacrificial material layer 142 and a second dielectric material plate 242’ that is a patterned portion of the second sacrificial material layer 242. A vertical stack of the dielectric material plates (142’, 242’) is formed in each area that is laterally surrounded by the annular cavity.

[0283] A set of annular cavities 679C that laterally surround the vertical stack of the dielectric material plates (142’, 242’) are vertically connected to each other through rows of discrete laterally spaced openings 6790, and these openings correspond to trench region openings 619 that vertically extend through the insulating layers (132, 232), as Figure 36C shown. Each row of laterally spaced openings 6790 vertically extends through a corresponding one of the insulating layers in the insulating layers (132, 232), and includes, at the level of the corresponding one of the insulating layers in the insulating layers (132, 232), segments of the trench region openings 619 that are provided in the same trench region MR at the processing step of Figures 8A to 8C . The rows of laterally spaced openings located in the same trench region MR overlap each other in a plan (i.e., top view) drawing. In other words, the area of the laterally spaced openings of any row located in the same trench region MR at the level of one of the insulating layers in the insulating layers (132, 232) overlaps with the area of the laterally spaced openings of any other row located in the same trench region MR at the level of another insulating layer in the insulating layers (132, 232). Each row of laterally spaced openings can be arranged along the perimeter of the corresponding via opening area VOA within the area of the trench region MR. Therefore, the overall lateral expansion of each row of laterally spaced openings conforms to the shape of the corresponding via opening area VOA.

[0284] The trench groove 679 includes a continuous combination of an annular cavity (i.e., a groove) 679C at the level of the sacrificial material layer (142, 242) and rows of laterally spaced openings 6790 at the level of the insulating layers (132, 232). As Figure 36CAs shown, each insulating layer (132, 232) is perforated with a row of correspondingly laterally spaced openings 6790. Each laterally spaced opening 6790 within the row of laterally spaced openings may have a generally cylindrical shape and is laterally spaced from an adjacent laterally spaced opening by a corresponding intermediate portion of the insulating layer (132, 232). Thus, each insulating layer (132, 232) extends laterally from outside the region of each via opening area (VOA) into the via opening area VOA, which overlaps a region of the vertical stack of dielectric material plates (142’, 242’) through an array of connecting portions located between each pair of adjacent laterally spaced openings 6790 that extend vertically through the insulating layer (132, 232).

[0285] Each trench groove 679 extends vertically from the top surface of the second insulating capping layer 270 into the source level material layer 10’ in the process. Generally, each trench groove 679 can be formed by selectively isotropically etching the unmasked portions of the sacrificial material layers (142, 242) for the insulating layers (132, 232) and by laterally expanding each trench area opening 619 within the row of trench area openings 619 at the level of the sacrificial material layers (142, 242) to form an annular cavity 679C. In one embodiment, each trench area opening 619 within the row of trench area openings 619 can be laterally expanded at the level of the sacrificial material layers (142, 242) by a second isotropic etching process that selectively etches the material of the sacrificial material layers (142, 242) with respect to the material of the insulating layers (132, 232). Each trench groove 679 has a continuously extending volume that laterally surrounds a patterned portion of the corresponding sacrificial material layer (142, 242) at each level of the sacrificial material layers (142, 242), i.e., the dielectric material plates (142’, 242’). The remaining portions of the sacrificial material layers (142, 242) after the isotropic etching process include a vertical stack of dielectric material plates (142’, 242’) that are laterally surrounded by the trench grooves 679.

[0286] Each trench groove 679 can be laterally defined at its outer boundary by a set of horizontally concave and vertically sidewall segments of the corresponding sacrificial material layer (142, 242) at the level of each sacrificial material layer (142, 242), and can be laterally defined at its inner boundary by a set of horizontally concave and vertically sidewall segments of the corresponding dielectric material plate (142’, 242’) at the level of each sacrificial material layer (142, 242). Each trench groove 679 can be laterally defined by the cylindrical sidewalls of a row of corresponding discrete cylindrical openings 6790 at the level of each insulating layer (132, 232). As used herein, a horizontally concave surface refers to a surface having a concave profile in a horizontal cross-section, and a vertical surface refers to a surface having a straight profile in a vertical cross-section.

[0287] While forming the trench groove 679, each connection via region opening 319 can expand laterally isotropically at each level of the first sacrificial material layer 142 and the second sacrificial material layer 242. Each connection via region opening 319 expands in volume to form an expanded connection via region opening 379, which includes fin-shaped lateral recesses 379F at each level of the first sacrificial material layer 142 and the second sacrificial material layer 242. Generally speaking, each trench groove 679 can be formed by laterally expanding each trench region opening 619 within a row of corresponding trench region openings 619 until the trench region openings 619 merge at the levels of the sacrificial material layers (such as the levels of the first sacrificial material layer 142 and the second sacrificial material layer 242). Each trench groove 679 has a continuously extending volume that laterally encloses a patterned portion of the corresponding sacrificial material layer (such as the dielectric material plate (142’, 242’)) at each level of the sacrificial material layers (142, 242). Each connection via region opening 329 expands laterally to form fin-shaped lateral recesses 679F at the levels of the sacrificial material layers (142, 242), and becomes an expanded connection via region opening 379.

[0288] Reference Figure 37A and Figure 37B and, a selective etching process can be performed to remove the remaining portion of the conformal etch mask material layer 352. For example, if the conformal etch mask material layer 352 contains a semiconductor material, an isotropic wet etching process (which uses hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH)) can be employed to remove the conformal etch mask material layer 352.

[0289] Reference Figure 38A and Figure 38B, the continuous blocking dielectric layer 52C can optionally be deposited on the sidewalls of the memory opening 49, the support opening 19, the extended contact via region opening 379, and the trench groove 679 by a conformal deposition process. The continuous blocking dielectric layer 52C can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the continuous blocking dielectric layer 52C can include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metal element and oxygen, or can consist essentially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the continuous blocking dielectric layer 52C can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the continuous blocking dielectric layer 52C includes aluminum oxide. Alternatively or in addition, the continuous blocking dielectric layer 52C can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0290] A sacrificial fill material may be applied over the second exemplary structure to fill cavities within the openings (49, 19, 679, 379) of the second exemplary structure. The annular cavity 679C of the trench 679 and the fin lateral recess 379F of the extended connection via region opening 379 may or may not be filled with the sacrificial fill material. Voids may or may not be present within each portion of the sacrificial fill material within the respective openings (49, 19, 679, 379) of the second exemplary structure. The sacrificial fill material may include a photoresist material, amorphous carbon, a silicate glass material providing a high etch rate (such as borosilicate glass or organosilicate glass), or a silicon germanium alloy. The sacrificial fill material may be patterned to remove portions of the photoresist material filling the support opening 19, the trench 679, and the extended connection via region opening 379. In the case where the sacrificial fill material includes a photoresist material, the photoresist material may be patterned directly by photolithographic exposure and development. In the case where the sacrificial fill material includes a non-photoresist material, a photoresist layer (not shown) may be applied over the sacrificial fill material, which may be photolithographically patterned, and an etching process (such as a combination of an anisotropic etching process and an isotropic etching process) may be employed to remove portions of the sacrificial fill material not covered by the patterned photoresist layer, and subsequently the patterned photoresist layer is removed. A patterned sacrificial fill material layer 369 is formed that fills each of the memory openings 49 in the memory openings and does not fill any of the support opening 19, the trench 679, and the extended connection via region opening 379.

[0291] Reference Figure 39A and Figure 39B , a dielectric material layer 176L (such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass) may be deposited in each of the support opening 19, the trench 679, and the extended connection via region opening 379 using a conformal deposition process (such as a chemical vapor deposition (CVD) process). The dielectric material layer 176L fills each volume of the cavities within the support opening 19 and the trench 679 and is formed over the top surface of the second insulating capping layer 270. The dielectric material layer 176L is not formed in the memory openings 49, which are filled with the patterned sacrificial fill material layer 369.

[0292] Reference Figure 40A and Figure 40B, an etch - back planarization process can be performed to remove portions of the dielectric material layer 176L, the patterned sacrificial fill material layer 369, and the continuous barrier dielectric layer 52C that cover a horizontal plane above the top surface of the second insulating capping layer 270. A recess etch process and / or a chemical mechanical planarization process can be used for the planarization process. Each remaining portion of the dielectric material layer 176L that fills the support opening 19 includes a dielectric support opening fill material portion 20. Each remaining portion of the dielectric material layer 176L that fills the corresponding trench groove 679 includes a dielectric trench groove fill material portion 176. Each remaining portion of the dielectric material layer 176L that fills the extended connection via region opening 379 includes a finned dielectric fill material portion 276, which includes a vertical stack of dielectric fins 276F attached to a central dielectric core 276C.

[0293] Each remaining portion of the optional continuous barrier dielectric layer 52C (if employed) located within the support opening 19, the trench groove 679, or the memory opening 49 includes a barrier dielectric layer 52. As an optional structure, the barrier dielectric layer 52 may or may not be present in each of the memory opening 49, the support opening 19, and the trench groove 679. Each continuous combination of the barrier dielectric layer 52 (if present) and the dielectric support opening fill material portion 20 that fills the support opening 19 constitutes a support pillar structure (52, 20). Each continuous combination of the barrier dielectric layer 52 (if present) and the dielectric trench groove fill material portion 176 constitutes a perforated dielectric trench structure (52, 176). Each continuous combination of the barrier dielectric layer 52 (if present) and the finned dielectric fill material portion 276 that fills the corresponding extended connection via region opening 379 includes a finned dielectric pillar structure (52, 276).

[0294] Generally speaking, the perforated dielectric trench structure (52, 176) can vertically extend through the alternating stack {(132, 242), (232, 242)}, and can be formed by optionally filling the trench groove 679 with the corresponding barrier dielectric layer 52 and with a dielectric fill material, which is the material of the dielectric trench groove fill material portion 176. Each perforated dielectric trench structure (52, 176) includes a row of dielectric column portions 172 that extend through corresponding openings 6790 at each level of the insulating layers (132, 232). Each insulating layer in the insulating layers (132, 232) laterally extends from outside each perforated dielectric trench structure (52, 176) to inside each perforated dielectric trench structure (52, 176), i.e., inside each via opening area VOA, between adjacent pairs of dielectric column portions 172.

[0295] In one embodiment, each row of dielectric column portions 172 may be disposed along the perimeter of a corresponding perforated dielectric trench structure (52, 176) at a level of one of the insulating layers (132, 232). The rows of dielectric column portions 172 at different levels of the insulating layers (132, 232) have area overlap with each other.

[0296] The perforated dielectric trench structures (52, 176) further include annular dielectric plate portions 174 at each level of the sacrificial material layers (142, 242), which laterally enclose corresponding dielectric material plates (142’, 242’). In one embodiment, the dielectric material plates (142’, 242’) comprise a material different from the insulating layers (132, 232) and comprise the same material as the sacrificial material layers (142, 242). In one embodiment, the insulating layers (132, 232) comprise silicon oxide and the dielectric material plates (142’, 242’) comprise silicon nitride. In one embodiment, each of the dielectric material plates (142’, 242’) always has a corresponding uniform thickness and contacts the planar bottom surface of the corresponding overlying insulating layer in the insulating layers (132, 232) and contacts the planar top surface of the corresponding underlying insulating layer in the insulating layers (132, 232). If there is a barrier dielectric layer 52, each of the dielectric column portions 172 may include a segment of the barrier dielectric layer 52 and a segment of the dielectric trench groove fill material portion 176, and each of the annular dielectric plate portions 174 may include a segment of the barrier dielectric layer 52 and a segment of the dielectric trench groove fill material portion 176.

[0297] In one embodiment, each of the annular dielectric plate portions 174 includes a continuous inner sidewall and a continuous outer sidewall, the continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other, and the continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other. Each laterally protruding surface is a surface having a protruding profile in a horizontal plane.

[0298] In one embodiment, each perforated dielectric trench structure (52, 176) includes a row of dielectric column portions 172 at each level of the insulating layers (132, 232). Each of the continuous inner sidewall and the continuous outer sidewall is laterally offset from the corresponding overlying row of dielectric column portions 172 by a uniform lateral offset distance, which may be a lateral recess distance, and the sidewalls of the sacrificial material layers (142, 242) are laterally recessed by this lateral recess distance relative to the sidewalls of the insulating layers (132, 232) at the processing step of Figure 35A and Figure 35B ..

[0299] Subsequently, the sacrificial fill material portion 369 in the memory opening 49 can be selectively removed with respect to the materials of the insulating layers (132, 232) and the sacrificial material layers (142, 242). For example, if the sacrificial fill material portion 369 in the memory opening 49 comprises a photoresist fill material, an ashing process can be performed to remove the photoresist fill material from inside the memory opening 49. If the sacrificial fill material portion comprises amorphous silicon or polysilicon, a wet etching process (which uses hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH)) can be employed to selectively remove the sacrificial fill material portion 359 with respect to the materials of the insulating layers (132, 232) and the sacrificial material layers (142, 242). Each memory opening 49 becomes empty.

[0300] Generally, the perforated dielectric trench structures (52, 176) and the finned dielectric pillar structures (52, 276) can be formed at the same processing step by filling the trench grooves 679 and the extended connection via region openings 379 (i.e., in the connection via region openings 329) with a dielectric fill material after laterally expanding the connection via region openings 329 by forming the fin-shaped lateral recesses 379F.

[0301] Each perforated dielectric trench structure (52, 176) includes an annular dielectric plate portion 174 formed at the level of the sacrificial material layers (142, 242). Each annular dielectric plate portion in the annular dielectric plate portion 174 includes a continuous inner sidewall and a continuous outer sidewall, the continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other, and the continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other. Each finned dielectric pillar structure (52, 276) includes a vertical stack of dielectric material fins 276F that are vertically interconnected with each other by at least one dielectric core pillar 276C.

[0302] In one embodiment, each dielectric material fin 276F within the vertical stack of dielectric material fins 276F contacts a respective one of the dielectric material plates (142’, 242’) and is laterally surrounded by the respective one of the dielectric material plates. In one embodiment, each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has the same height as a respective one of the dielectric material plates (142’, 242’). In one embodiment, each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has at least one convex cylindrical surface that contacts at least one concave cylindrical surface of a respective one of the dielectric material plates (142’, 242’).

[0303] A finned dielectric column structure (52, 276) can be provided in various configurations. Figure 41A and Figure 42A FIG. shows a first configuration in which the finned dielectric column structure 276 does not have any area overlap with an adjacent finned dielectric column structure 276. Figure 41B and Figure 42B FIG. shows a second configuration in which three finned dielectric column structures 276 are merged with each other, and at each level of the sacrificial material layer (142, 242) (i.e., at each level of the dielectric material plate (142’, 242’)), three dielectric material fins 276F are merged to form a merged dielectric material fin 276F that laterally surrounds three dielectric core columns 276C. Figure 41C and Figure 42C FIG. shows a third configuration in which four finned dielectric column structures 276 are merged with each other, and at each level of the sacrificial material layer (142, 242) (i.e., at each level of the dielectric material plate (142’, 242’)), four dielectric material fins 276F are merged to form a merged dielectric material fin 276F that laterally surrounds four dielectric core columns 276C. Configurations in which two finned dielectric column structures 276 are merged or five or more finned dielectric column structures 276 are merged are explicitly contemplated herein.

[0304] In some configurations (such as Figure 41A and Figure 42A the first configuration shown), each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has a single convex cylindrical surface that contacts the entire single concave cylindrical surface of a corresponding one of the dielectric material plates (142’, 242’).

[0305] In some configurations (such as Figure 41B and Figure 42B the second configuration shown or Figure 41C and Figure 42C the third configuration shown), each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has a plurality of convex cylindrical surfaces that are adjacent to each other at vertically extending edges, and the plurality of convex cylindrical surfaces contact a plurality of concave cylindrical surfaces of a corresponding one of the dielectric material plates (142’, 242’).

[0306] In each configuration of the finned dielectric pillar structure 276, the dielectric material fins 276F overlap each other in area in a plan view along the vertical direction and are vertically interconnected to each other by at least one dielectric core pillar 276C, which vertically extends through each layer within the alternating stack {(132, 142), (232, 242)}. The at least one dielectric core pillar 276C can be a single dielectric core pillar 276C as shown in Figure 41A or can be multiple dielectric core pillars 276C as shown in Figure 41B and Figure 41C . In one embodiment shown in Figure 41B and Figure 41C , the dielectric material fins 276F are vertically interconnected to each other by multiple dielectric core pillars 276C, which vertically extend through each layer within the alternating stack {(132, 142), (232, 242)}.

[0307] Referring to Figure 43A and Figure 43B , the processing steps of Figure 20B , Figure 20C and Figure 20D can be performed to form a memory opening fill structure 58 within each memory opening 49.

[0308] Referring to Figure 44A and Figure 44B , the processing steps of Figure 22A , Figure 22B and Figure 23A can be performed to form a first contact level dielectric layer 280 above the second layer structure (232, 242, 242’, 270, 265) and to form a backside trench 79 that vertically extends through the second layer structure (232, 242, 242’, 270, 265), the interlayer dielectric layer 180, and the first layer structure (132, 142, 142’, 170, 165). The alternating stack {(132, 232), (142, 242)} can be divided into multiple alternating stacks {(132, 232), (142, 242)} of a corresponding insulating layer (132, 232) and a corresponding sacrificial material layer (142, 242) by the backside trench 79. Optionally, the drain select level isolation structure can be formed in the same manner as in the first embodiment.

[0309] Referring to Figure 45A and Figure 45B , the processing steps of Figure 23B , Figure 23C and Figure 23D can be performed to replace the source level material layer 10’ in the process with the source level material layer 10. Subsequently, Figure 23EThe processing steps are to form the dielectric semiconductor oxide plate 122 and the annular dielectric semiconductor oxide spacer 124. For clarity, the dielectric semiconductor oxide plate 122 and the annular dielectric semiconductor oxide spacer 124 are not explicitly shown in Figure 45A and Figure 45B .

[0310] Referring to Figure 46A and Figure 46B , the processing steps of Figure 24A and Figure 24B can be performed, and Figure 25A and Figure 25B processing steps to replace each first sacrificial material layer 142 with the first conductive layer 146 and each second sacrificial material layer 242 with the second conductive layer 246. Replace the first alternating stack of the first insulating layer 132 and the first layer of the first sacrificial material layer 142 with the first alternating stack of the first insulating layer 132 and the first layer of the first conductive layer 146. Replace the second alternating stack of the second insulating layer 232 and the second layer of the second sacrificial material layer 242 with the second alternating stack of the second insulating layer 232 and the second layer of the second conductive layer 246. Replace the alternating stack {(132, 142), (232, 242)} of the insulating layers (132, 232) and the sacrificial material layers (142, 242) with the alternating stack {(132, 146), (232, 246)} of the insulating layers (132, 232) and the conductive layers (146, 246).

[0311] Referring to Figure 47A and Figure 47B , insulating spacers 674 can be formed around each perimeter of the backside trench 79. For example, a dielectric material (such as undoped silicate glass or doped silicate glass) can be conformally deposited on the physically exposed sidewalls of the alternating stack {(132, 146), (232, 246)}, deposited on the bottom surface of each backside trench 79 (which may include the dielectric semiconductor oxide plate 122), and deposited above the first contact level dielectric layer 280. An anisotropic etching process can be performed to remove the horizontal portions of the conformally deposited dielectric layer. The dielectric semiconductor oxide plate 122 can be etched through at the bottom of each backside trench 79 by an anisotropic etching process, and the top surface of the source contact layer 114 can be physically exposed at the bottom of each backside trench 79. Each remaining tubular portion of the conformally deposited material at the perimeter of the backside trench 79 constitutes the insulating spacer 674. A backside cavity 79' in the form of a void volume can be present inside each insulating spacer 674.

[0312] Referring to Figure 48A and Figure 48B , an optional hard mask (e.g., Carbon Advanced Patterning Film tm(not shown explicitly)) and a photoresist layer 287, and it can be lithographically patterned to form various openings therethrough. The openings in the photoresist layer include openings for subsequently forming word line layer contact via structures 86, peripheral direct memory level interconnect via structures 488, and array region direct memory level interconnect via structures 588. When the patterned film and / or the photoresist layer 287 do not fill the voids in the backside trench 79, a backside cavity 79' may exist in the backside trench 79.

[0313] The pattern of the openings in the photoresist layer can be transferred through the first contact level dielectric layer 280, the backside stepped dielectric material portion 65, and the finned dielectric pillar structures (52, 276) by performing an anisotropic etching process. The word line layer contact via cavity 85 is formed in the staircase region 200 through the first contact level dielectric layer 280 and at least one backside stepped dielectric material portion (165, 265) on a corresponding one of the conductive layers (146, 246). The horizontal surface of the conductive layer (146, 246) can be used as an etching stop structure for the anisotropic etching process. The peripheral direct memory level interconnect via cavity 487 can be formed through the first contact level dielectric layer 280, the second backside stepped dielectric material portion 265, and the first backside stepped dielectric material portion 165 to a corresponding one of the landing pad level metal line structures 788 in the landing pad level metal line structures. The landing pad level metal line structures 788 can be used as an etching stop structure for the anisotropic etching process.

[0314] According to an aspect of the present disclosure, an array region direct memory level interconnect via cavity 587 is formed through a portion 768' of the finned dielectric pillar structures (52, 276) and at least one second dielectric layer 768. The portion 768' and the finned dielectric fill material portion 276 can be substantially composed of a silicon oxide-based dielectric material (such as undoped silicate glass or doped silicate glass), and the first insulating layer 132 and the second insulating layer 232 can be substantially composed of another silicon oxide-based dielectric material (such as undoped silicate glass or doped silicate glass). The barrier dielectric layer 52 can include silicon oxide and / or dielectric metal oxides. The total thickness of the barrier dielectric layer 52 within the region of the dielectric core pillar 276C can be negligible. Thus, the anisotropic etching process etches through the silicon oxide-based material without hindrance during the formation of the array region direct memory level interconnect via cavity 587. The landing pad level metal line structure 788 located below the array region direct memory level interconnect via cavity 587 can be used as an etching stop structure, and the array region direct memory level interconnect via cavity 587 can extend vertically through the portion 768' to the top surface of a corresponding one of the landing pad level metal line structures 788.

[0315] In one embodiment, the array region direct memory tier through-viacavity 587 is formed entirely within the region of a corresponding opening in the dielectric material slab (142’, 242’). Thus, in the case where the dielectric material slab (142’, 242’) comprises silicon nitride, the array region direct memory tier through-viacavity 587 can be formed within a region filled with a silica-based dielectric material such as undoped silicate glass or doped silicate glass. In the case where the barrier dielectric layer 52 is not present in each finned dielectric pillar structure (52, 276) or in the case where the barrier dielectric layer 52 consists essentially of silica, the finned dielectric pillar structure (52, 276) can consist essentially of a silica-based material such as undoped silicate glass or doped silicate glass. The entire volume of each array region direct memory tier through-viacavity 587 can be formed by removing the silica-based material. Thus, an anisotropic etching process can form the various through-viacavities (85, 487, 587) by etching only the silica-based material or the silica-based material and a minimal amount of dielectric metal oxide (which can be disposed in the horizontal portion of the barrier dielectric layer 52 at the bottom of the finned dielectric pillar structure (52, 276)) primarily. The anisotropic etching process can be stopped by a metal material portion such as a conductive layer (146, 246) or a landing pad tier metal wire structure 788, which can provide a high etch selectivity to the oxide etch chemistry employed by the anisotropic etching process. Thus, the various through-viacavities (85, 487, 587) can be formed simultaneously with a wide range of depths. This simplifies the process and reduces the number of process steps.

[0316] Generally, a through-viacavity such as the array region direct memory tier through-viacavity 587 can be formed through the finned dielectric pillar structure (52, 276). At least a portion of at least one dielectric core pillar 276C of the finned dielectric pillar structure (52, 276) is removed during the formation of the through-viacavity. The Figure 41A Percentage of the volume of at least one dielectric core pillar 276C in the configuration shown that is removed prior to the anisotropic etching process can be in the range of 25% to 100% (such as 50% to 100%) of the initial volume of the at least one dielectric core pillar 276C. In one embodiment, a major portion (i.e., at least 50%) of at least one dielectric core pillar 276C can be removed during the formation of the array region direct memory tier through-viacavity 587 therethrough.

[0317] The remainder of the finned dielectric pillar structure (52, 276) includes a vertical stack of dielectric material fins 276F that laterally surrounds a corresponding one of the array region direct access memory level interconnect vias cavities 587 in the array region. In other words, each vertical stack of dielectric material fins 276F includes the remainder of the vertical stack in the process of the dielectric material fins 276F. The photoresist layer 287 and an optional hard mask can then be removed, for example, by ashing.

[0318] Reference Figure 49A and Figure 49B 、 Figures 50A to 50C and Figures 51A to 51C and, at least one conductive material can be deposited in various via cavities (85, 487, 587). The at least one conductive material can include, for example, a metal nitride barrier material (such as TiN, TaN, and / or WN) and a metal fill material (such as W, Cu, Mo, Ru, Co, another transition metal, and / or a combination thereof). The excess of the at least one conductive material can be removed from above a horizontal plane including the top surface of the first contact level dielectric layer 280 by a planarization process. The planarization process can employ, for example, chemical mechanical planarization and / or recess etching processes. The word line layer contact via structure 86 is formed in the word line layer contact via cavity 85 that is directly located on a corresponding one of the conductive layers (146, 246). The peripheral direct access memory level interconnect via structure 488 is formed in the peripheral direct access memory level interconnect via cavity 487 that is directly located on the top surface of a corresponding one of the landing pad level metal line structures 788 in the peripheral region. The array region direct access memory level interconnect via structure 588 is formed within the array region direct access memory level interconnect via cavity 587 in a corresponding one of the perforated dielectric trench structures (52, 176) in the memory array region 100. Each array region direct access memory level interconnect via structure 588 can be laterally surrounded by a corresponding vertical stack of dielectric material plates (142’, 242’) and can be laterally spaced apart from the corresponding vertical stack. The source line 676 is formed in the backside trench 79.

[0319] The finned dielectric pillar structure (52, 276) and the array region direct access memory level interconnect via structure 588 can be provided in various configurations. Figure 50A and Figure 51AShows a first configuration in which the finned dielectric pillar structure 276 does not have any area overlap with adjacent finned dielectric pillar structures 276. The dielectric core pillar 276C can be completely removed during the formation of the array region direct access memory level via cavity 587, and the array region direct access memory level via structure 588 can contact the entire inner perimeter of each dielectric material fin 276F within the vertical stack of dielectric material fins 276F. Figure 50B and Figure 51B Shows a second configuration in which three finned dielectric pillar structures 276 are merged with each other, and at each level of the sacrificial material layer (142, 242) (i.e., at each level of the dielectric material plate (142’, 242’)), three dielectric material fins 276F are merged to form a merged dielectric material fin 276F that laterally surrounds the three dielectric core pillars 276C. Each dielectric core pillar 276C can be only partially removed during the formation of the array region direct access memory level via cavity 587, and the array region direct access memory level via structure 588 can contact a plurality of dielectric core pillars 276C. Figure 50C and Figure 51C Shows a third configuration in which four finned dielectric pillar structures 276 are merged with each other, and at each level of the sacrificial material layer (142, 242) (i.e., at each level of the dielectric material plate (142’, 242’)), four dielectric material fins 276F are merged to form a merged dielectric material fin 276F that laterally surrounds the four dielectric core pillars 276C. Each dielectric core pillar 276C can be only partially removed or not removed at all during the formation of the array region direct access memory level via cavity 587, and the array region direct access memory level via structure 588 can contact a plurality of dielectric core pillars 276C. Configurations in which two finned dielectric pillar structures 276 are merged or five or more finned dielectric pillar structures 276 are merged are explicitly contemplated herein.

[0320] Generally, a via structure (such as the array region direct access memory level via structure 588) can vertically extend through at least one finned dielectric pillar structure (52, 276). The via structure can contact the sidewalls of the vertical stack of dielectric material fins 276F, which have a dielectric material composition and are laterally spaced apart from the perforated dielectric trench structure (52, 176).

[0321] Referring to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, which includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the alternating stack being positioned above a substrate 8; a memory stack structure 55 that extends vertically through the alternating stack {(132, 146), (232, 246)}, wherein each memory stack structure in the memory stack structure 55 includes a vertical semiconductor channel 60 and a vertical stack of memory elements located at the levels of the conductive layers (146, 246); a perforated dielectric trench structure (52, 176) that extends vertically through the alternating stack {(132, 146), (232, 246)} and includes a plurality of lateral openings at each level of the insulating layer (132, 232) and does not include any openings at the levels of the conductive layers (146, 246); and an interconnection via structure (such as an array region through-memory-level interconnection via structure 588), the interconnection via structure being laterally surrounded by the perforated dielectric trench structure (52, 176) and extending vertically through each insulating layer (132, 232) within the alternating stack {(132, 146), (232, 246)} and contacting the top surface of the underlying metal interconnect structure 788.

[0322] In one embodiment, the perforated dielectric trench structure (52, 176) is a continuous monolithic structure having a dielectric material composition, and the interconnection via structure (such as an array region through-memory-level interconnection via structure 588) contacts the sidewalls of a vertical stack of dielectric material fins 276F having a dielectric material composition and being laterally spaced apart from the perforated dielectric trench structure (52, 176).

[0323] In one embodiment, the perforated dielectric trench structure (52, 176) laterally surrounds a dielectric material plate (142’, 242’) at each level of the conductive layer (146, 246); and each dielectric material fin 276F within the vertical stack of dielectric material fins 276F contacts and is laterally surrounded by a corresponding one of the dielectric material plates (142’, 242’).

[0324] In one embodiment, each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has the same height as a corresponding one of the dielectric material plates (142’, 242’); and each dielectric material fin 276F within the vertical stack of dielectric material fins 276F has at least one convex cylindrical or cylindrical-sector surface that contacts at least one concave cylindrical surface of a corresponding one of the dielectric material plates (142’, 242’).

[0325] In one embodiment, each dielectric fin 276F within the vertical stack of dielectric fins 276F has a single convex cylindrical surface that contacts the entire single concave cylindrical surface of a corresponding one of the dielectric plates (142’, 242’). In one embodiment, each dielectric fin 276F within the vertical stack of dielectric fins 276F has a plurality of convex cylindrical sector surfaces that are adjacent to each other at vertically extending edges, and the plurality of convex cylindrical surfaces contact a plurality of concave cylindrical surfaces of a corresponding one of the dielectric plates 276F.

[0326] In one embodiment, the dielectric fins 276F have an area overlap with each other in a plan view along the vertical direction and are vertically interconnected with each other by at least one dielectric core column 276C that vertically extends through each layer within the alternating stack {(132, 146), (232, 246)}. In one embodiment, at least one dielectric core column 276C contacts a segment of the sidewall of an interconnection via structure (such as the array region through memory level interconnection via structure 588); and each of the insulating layers (132, 232) contacts a corresponding segment of the sidewall of the interconnection via structure. In one embodiment, the dielectric fins 276F are vertically interconnected with each other by a plurality of dielectric core columns 276C that vertically extend through each layer within the alternating stack {(132, 146), (232, 246)}.

[0327] In one embodiment, the perforated dielectric trench structure (52, 176) includes rows of dielectric column portions 172 at each level of the insulating layers (132, 232); and each of the insulating layers (132, 232) laterally extends from outside the perforated dielectric trench structure (52, 176) to inside the perforated dielectric trench structure (52, 176) between adjacent pairs of dielectric column portions 172. In one embodiment, each row of dielectric column portions 172 is arranged along the perimeter of the perforated dielectric trench structure (52, 176) at a level of one of the insulating layers (132, 232). In one embodiment, there is an area overlap between rows of dielectric column portions 172 located at different levels of the insulating layers (132, 232). In one embodiment, the perforated dielectric trench structure (52, 276) includes annular dielectric plate portions 174 at each level of the conductive layers (146, 246), and the annular dielectric plate portions laterally surround the corresponding dielectric plates (142’, 242’).

[0328] In one embodiment, a three-dimensional memory device may include: a lower-level dielectric material layer 760 disposed between a substrate 8 and an alternating stack {(132, 146), (232, 246)}; and a lower-level metal interconnect structure 780 embedded within the lower-level dielectric material layer 760, wherein a lower-level metal interconnect 788 is one of the lower-level metal interconnects in the lower-level metal interconnect structure 780.

[0329] Various embodiments of the present disclosure can be used to simultaneously form a word line layer contact via structure 86, a peripheral direct memory level interconnect via structure 488, and an array region direct memory level interconnect via structure 588 by employing the same anisotropic etching process, the same conductive material deposition process, and the same planarization process. The number of processing steps for forming a three-dimensional memory device can be reduced by simultaneously forming a plurality of conductive via structures having different height ranges, and the processing cost and turnaround time can be reduced accordingly. Finally, the embodiment structure is more compact and requires a smaller critical diameter for an opening 587, which reduces the overall chip size.

[0330] Although specific embodiments have been mentioned previously, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". In embodiments of the present disclosure that show the use of a specific structure and / or configuration, it should be understood that the present disclosure can be practiced with any other functionally equivalent compatible structure and / or configuration, provided that such substitution is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: An alternating stack of insulating layers and conductive layers, the alternating stack being positioned above a substrate; A memory stack structure, the memory stack structure extending vertically through the alternating stack, wherein each memory stack structure in the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements located at a level of the conductive layer; A perforated dielectric trench structure, the perforated dielectric trench structure extending vertically through the alternating stack, and including a plurality of lateral openings at each level of the insulating layer and not including any openings at the level of the conductive layer; And An interconnection via structure, the interconnection via structure being laterally surrounded by the perforated dielectric trench structure and extending vertically through each insulating layer within the alternating stack.

2. The three-dimensional memory device according to claim 1, wherein: The perforated dielectric trench structure includes a row of dielectric column portions at each level of the insulating layer; and Each insulating layer in the insulating layers extends laterally from outside the perforated dielectric trench structure to inside the perforated dielectric trench structure between adjacent pairs of dielectric column portions.

3. The three-dimensional memory device according to claim 2, wherein the row of each dielectric column portion is arranged along the perimeter of the perforated dielectric trench structure at a level of one of the insulating layers.

4. The three-dimensional memory device according to claim 2, wherein there is an area overlap between the rows of the dielectric column portions located at different levels of the insulating layer.

5. The three-dimensional memory device according to claim 2, wherein the perforated dielectric trench structure includes an annular dielectric plate portion at each level of the conductive layer, the annular dielectric plate portion laterally surrounding a corresponding dielectric material plate.

6. The three-dimensional memory device according to claim 5, wherein: The dielectric material plate contains a material different from the insulating layer; and The interconnection via structure extends vertically through the vertical stack of the dielectric material plate and the insulating layer in the area surrounded by the perforated dielectric trench structure.

7. The three-dimensional memory device according to claim 6, wherein: The insulating layer contains a silicon oxide material; and The dielectric material plate contains silicon nitride.

8. The three-dimensional memory device according to claim 5, wherein each dielectric material plate in the dielectric material plates always has a corresponding uniform thickness, and contacts the planar bottom surface of the corresponding overlying insulating layer in the insulating layer and contacts the planar top surface of the corresponding underlying insulating layer in the insulating layer.

9. The three-dimensional memory device according to claim 5, wherein each annular dielectric plate portion in the annular dielectric plate portions includes: A continuous inner sidewall, the continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other; And A continuous outer sidewall, the continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other.

10. The three-dimensional memory device according to claim 9, wherein each of the continuous inner sidewalls and the continuous outer sidewalls is laterally offset from a corresponding overlying row of dielectric pillar portions by a uniform lateral offset distance.

11. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising: a lower-level dielectric material layer disposed between the substrate and the alternating stack; and a lower-level metal interconnect structure embedded within the lower-level dielectric material layer, wherein the via interconnect structure contacts a top surface of one of the lower-level metal interconnect structures within the lower-level metal interconnect structure.

12. The three-dimensional memory device according to claim 11, the three-dimensional memory device further comprising a field effect transistor located above the substrate and including a node electrically connected to the via interconnect structure through a subset of the lower-level metal interconnect structures.

13. The three-dimensional memory device according to claim 11, the three-dimensional memory device further comprising: an upper-level dielectric material layer located above the alternating stack; and an upper-level metal interconnect structure embedded within the upper-level dielectric material layer, wherein the via interconnect structure contacts a bottom surface of one of the upper-level metal interconnect structures within the upper-level metal interconnect structure.

14. The three-dimensional memory device according to claim 1, wherein the vertical stack of memory elements includes portions of a charge storage layer located at each level of the conductive layer and laterally spaced from a corresponding one of the vertical semiconductor channels by a tunneling dielectric layer.

15. A method for forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer above a substrate, wherein the sacrificial material layer comprises a dielectric material; forming rows of trench region openings through the alternating stack, wherein the rows of trench region openings are arranged in a pattern surrounding regions within the alternating stack; forming trench grooves by laterally expanding each trench region opening within the rows of trench region openings at levels of the sacrificial material layer, wherein the trench grooves have a continuously extending volume that laterally surrounds patterned portions of the corresponding sacrificial material layer at each level of the sacrificial material layer; forming a perforated dielectric trench structure by filling the trench grooves with a dielectric fill material, the perforated dielectric trench structure extending vertically through the alternating stack; and forming a memory stack structure through the alternating stack, wherein each memory stack structure within the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements located at a level of a conductive layer.

16. The method according to claim 15, the method further comprising forming a via interconnect structure laterally surrounded by the perforated dielectric trench structure.

17. The method according to claim 16, wherein each trench region opening in a row of the trench region openings is laterally extended at the level of the sacrificial material layer by performing an isotropic etching process that selectively etches the material of the sacrificial material layer with respect to the material of the insulating layer.

18. The method according to claim 17, wherein: a remaining portion of the sacrificial material layer after the isotropic etching process includes a vertical stack of dielectric material plates laterally surrounded by the trench grooves; and the interconnect via structure vertically extends through each insulating layer within the alternating stack and through the vertical stack of dielectric material plates.

19. The method according to claim 18, wherein: the perforated dielectric trench structure includes an annular dielectric plate portion formed at the level of the sacrificial material layer; and each annular dielectric plate portion in the annular dielectric plate portions includes: a continuous inner sidewall including a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other, and a continuous outer sidewall including a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other.

20. The method according to claim 15, the method further comprising forming a lower-level metal interconnect structure embedded in a lower-level dielectric material layer above the substrate, wherein: the alternating stack is subsequently formed above the lower-level dielectric material layer; and the interconnect via structure is formed on a top surface of one of the lower-level metal interconnect structures in the lower-level metal interconnect structure.

21. A three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers, the alternating stack positioned above a substrate; a memory stack structure vertically extending through the alternating stack, wherein each memory stack structure in the memory stack structure includes a vertical semiconductor channel and a vertical stack of memory elements at the level of the conductive layer; a perforated dielectric trench structure vertically extending through the alternating stack as a single continuous dielectric structure, the dielectric structure including a dielectric fill material and including a plurality of lateral openings at each level of the insulating layer and not including any openings at the level of the conductive layer; wherein each of the plurality of lateral openings laterally extends through a single continuous dielectric structure between an outer sidewall and an inner sidewall of the perforated dielectric trench structure to define a corresponding volume group of the dielectric fill material without the single continuous dielectric structure; and An interconnected via structure, the interconnected via structure being laterally surrounded by the perforated dielectric trench structure and vertically extending through each insulating layer within the alternating stack and contacting the top surface of the underlying metal interconnect structure, wherein the perforated dielectric trench structure includes rows of dielectric pillar portions and the rows of dielectric pillar portions are in direct contact with sidewall segments of corresponding insulating layers within each level of the insulating layer, and each insulating layer extends laterally between adjacent pairs of dielectric pillar portions and extends from the exterior of the region defined by the outer sidewalls of the perforated dielectric trench structure in a plan view to the interior of the region defined by the inner sidewalls of the perforated dielectric trench structure in the plan view along a direction perpendicular to the top surface of the substrate.

22. The three-dimensional memory device according to claim 21, wherein: The perforated dielectric trench structure is a continuous integral structure having a dielectric material composition; and The interconnected via structure contacts sidewalls of a vertical stack of dielectric material fins, the dielectric material fins having the dielectric material composition and being laterally spaced apart from the perforated dielectric trench structure.

23. The three-dimensional memory device according to claim 22, wherein: The perforated dielectric trench structure laterally surrounds a dielectric material plate at each level of the conductive layer; and Each dielectric material fin within the vertical stack of dielectric material fins contacts a corresponding one of the dielectric material plates and is laterally surrounded by the corresponding one of the dielectric material plates.

24. The three-dimensional memory device according to claim 23, wherein: Each dielectric material fin within the vertical stack of dielectric material fins has the same height as the corresponding one of the dielectric material plates; and Each dielectric material fin within the vertical stack of dielectric material fins has at least one convex cylindrical or cylindrical sector surface that contacts at least one concave cylindrical surface of the corresponding one of the dielectric material plates.

25. The three-dimensional memory device according to claim 21, wherein the perforated dielectric trench structure includes undoped silicate glass or doped silicate glass.

26. The three-dimensional memory device according to claim 24, wherein each dielectric material fin within the vertical stack of dielectric material fins has a single convex cylindrical surface that contacts the entire single concave cylindrical surface of the corresponding one of the dielectric material plates.

27. The three-dimensional memory device according to claim 24, wherein: Each dielectric material fin within the vertical stack of dielectric material fins has a plurality of convex cylindrical sector surfaces that are adjacent to each other at vertically extending edges; and The plurality of convex cylindrical surfaces contact a plurality of concave cylindrical surfaces of the corresponding one of the dielectric material plates.

28. The three-dimensional memory device according to claim 22, wherein the dielectric material fins overlap with each other in a planar view along a vertical direction and are vertically interconnected with each other by at least one dielectric core column, and the at least one dielectric core column extends vertically through each layer within the alternating stack.

29. The three-dimensional memory device according to claim 28, wherein: each dielectric core column among the at least one dielectric core column contacts a segment of the sidewall of the through-interconnection hole structure; and and each insulating layer among the insulating layers contacts a corresponding segment of the sidewall of the through-interconnection hole structure.

30. The three-dimensional memory device according to claim 28, wherein the dielectric material fins are vertically interconnected with each other by a plurality of dielectric core columns, and the plurality of dielectric core columns extend vertically through each layer within the alternating stack.

31. The three-dimensional memory device according to claim 21, wherein: the perforated dielectric trench structure includes rows of dielectric column portions at each level of the insulating layer; and each insulating layer among the insulating layers extends laterally from outside the perforated dielectric trench structure to inside the perforated dielectric trench structure between adjacent pairs of dielectric column portions.

32. The three-dimensional memory device according to claim 31, wherein each row of dielectric column portions is arranged along the perimeter of the perforated dielectric trench structure at a level of one of the insulating layers.

33. The three-dimensional memory device according to claim 31, wherein there is an area overlap between the rows of dielectric column portions located at different levels of the insulating layer.

34. The three-dimensional memory device according to claim 31, wherein the perforated dielectric trench structure includes annular dielectric plate portions at each level of the conductive layer, and the annular dielectric plate portions laterally surround corresponding dielectric material plates.

35. The three-dimensional memory device according to claim 31, wherein each insulating layer continuously extends laterally from outside the perforated dielectric trench structure to inside the perforated dielectric trench structure through a plurality of lateral openings in the perforated dielectric trench structure.

36. The three-dimensional memory device according to claim 31, wherein the perforated dielectric trench structure includes a dielectric trench groove filling material portion composed of undoped silicate glass or doped silicate glass; and the perforated dielectric trench structure includes a barrier dielectric layer that laterally surrounds the dielectric trench groove filling material portion.

37. The three-dimensional memory device according to claim 36, wherein each memory stack structure includes respective memory membranes; and each memory membrane includes a vertical stack of respective memory elements and respective additional barrier dielectric layers, and the additional barrier dielectric layers have the same material composition and the same thickness as the barrier dielectric layer within the perforated dielectric trench structure.

38. The three-dimensional memory device according to claim 31, wherein a semiconductor package is located on a substrate semiconductor layer; and A lower-level metal interconnect structure, the lower-level metal interconnect structure being embedded within a lower-level dielectric material layer and electrically connected to corresponding nodes of the semiconductor package, wherein, the alternating stack is located above the lower-level metal interconnection structure.

39. The three-dimensional memory device according to claim 38, wherein the through-interconnection via structure contacts a top surface of one of the lower-level metal interconnection structures in the lower-level metal interconnection structure.

40. The three-dimensional memory device according to claim 39, further comprising a source-level material layer, the source-level material layer including a doped semiconductor material located between the lower-level dielectric material layer and the alternating stack, Among them, the source-level material layer including an opening therethrough, and the through-interconnection via structure extending vertically through the opening in the source-level material layer and contacting a dielectric material portion located within the opening in the source-level material layer.

41. A method for forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate, wherein the sacrificial material layer comprises a dielectric material; forming a row of trench region openings through the alternating stack, wherein the row of trench region openings is arranged to surround a pattern of a region within the alternating stack; forming at least one connecting via region opening through the alternating stack within the region surrounded by the row of trench region openings; forming a trench groove by laterally expanding each trench region opening within the row of trench region openings until the trench region openings merge at the level of the sacrificial material layer; forming a perforated dielectric trench structure by filling the trench groove with a dielectric filling material, the perforated dielectric trench structure extending vertically through the alternating stack; forming a finned dielectric pillar structure by filling the at least one connecting via region opening with the dielectric filling material; forming a memory stack structure through the alternating stack; and forming a through-interconnection via structure that extends vertically through the finned dielectric pillar structure, wherein a remaining portion of the finned dielectric pillar structure comprises a vertical stack of dielectric material fins that laterally surround and contact the through-interconnection via structure.

42. The method according to claim 41, wherein the trench groove has a continuously extending volume that laterally surrounds a patterned portion of the corresponding sacrificial material layer at each level of the sacrificial material layer, and wherein the at least one connecting via region opening is laterally expanded to form a fin-shaped lateral recess at the level of the sacrificial material layer.

43. The method according to claim 41, wherein the row of trench region openings and the at least one connecting via region opening are formed in the same processing step by performing an anisotropic etching process using a patterned etch mask.

44. The method according to claim 41, wherein the perforated dielectric trench structure and the finned dielectric pillar structure are formed in the same processing step by filling the trench groove and the at least one connecting via region opening with the dielectric filling material after laterally expanding the at least one connecting via region opening.

45. The method according to claim 41, wherein: The finned dielectric pillar structure includes a vertical stack in the process of dielectric material fins, and the dielectric material fins are vertically interconnected with each other through at least one dielectric core pillar; An interconnected via cavity is formed through the finned dielectric pillar structure, wherein at least a part of the at least one dielectric core pillar is removed; and The vertical stack of dielectric material fins includes the remaining part of the vertical stack in the process of dielectric material fins.

46. The method according to claim 45, wherein the interconnected via cavity is formed by performing an anisotropic etching process that etches a major part of the at least one dielectric core pillar.

47. The method according to claim 41, wherein: The perforated dielectric trench structure includes an annular dielectric plate portion formed at the level of the sacrificial material layer; and Each annular dielectric plate portion in the annular dielectric plate portion includes: A continuous inner sidewall, the continuous inner sidewall includes a plurality of laterally protruding and vertically planar inner sidewall segments adjacent to each other; and A continuous outer sidewall, the continuous outer sidewall includes a plurality of laterally protruding and vertically planar outer sidewall segments adjacent to each other.

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