Three-dimensional memory devices including multi-layer trench isolation structures and methods of manufacturing the same

Abstract

The present disclosure provides a method of forming a three-dimensional memory device including: forming a first tier-alternating stack of first insulating layers and first sacrificial material layers; forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step; forming first dielectric moat structures in the first moat layer trenches and first support pillar structures in the first-tier support openings during a same deposition step; forming memory stack structures in the first-tier memory openings; forming backside trenches through the first tier-alternating stack after forming the first dielectric moat structures; replacing portions of the first sacrificial material layers with first conductive layers through the backside trenches; and forming at least one through-memory-level interconnect via structure through a first vertical alternating sequence of first insulating slabs and first dielectric material slabs surrounded by the first dielectric moat structures.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application serial number 16 / 900,060, filed June 12, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more specifically to three-dimensional memory devices including multi-layer trench isolation structures and methods for manufacturing the same. Background Technology

[0004] Three-dimensional memory devices may include memory stack structures. The memory stack structure covers a substrate and extends through alternating stacks of insulating and conductive layers. The memory stack structure includes a vertical stack of memory elements disposed at levels of the conductive layers. Peripheral devices may be disposed on the substrate below the alternating stacks and the memory stack structure. Summary of the Invention

[0005] According to one aspect of this disclosure, a three-dimensional memory device is provided, comprising: a first alternating stack of a first insulating layer and a first conductive layer, the first alternating stack being positioned above a semiconductor material layer; a second alternating stack of a second insulating layer and a second conductive layer, the second alternating stack being positioned above the first alternating stack; memory stack structures extending vertically through the second alternating stack and the first alternating stack; a first dielectric trench structure extending vertically through the first alternating stack and laterally around a first vertical alternating sequence of a first insulating plate and a first dielectric material plate; a plurality of dielectric pillar structures extending vertically through the second alternating stack and contacting the top surface of the first dielectric trench structure; and at least one through-memory level interconnect via structure extending vertically from at least a horizontal plane including the top surface of the second alternating stack, through the first vertical alternating sequence of the first insulating plate and the first dielectric material plate, until extending to a corresponding metal interconnect structure below a horizontal plane including the bottom surface of the semiconductor material layer.

[0006] According to another aspect of this disclosure, a method for forming a three-dimensional memory device includes: forming a first alternating stack of a first insulating layer and a first sacrificial material layer; forming a first layer memory opening, a first layer support opening, and a first layer trench through the first alternating stack using the same etching steps; forming a first dielectric trench structure in the first trench trenches and a first support pillar structure in the first layer support openings during the same deposition steps; forming a memory stack structure in the first layer memory openings; forming a back-side trench through the first alternating stack after forming the first dielectric trench structure; replacing portions of the first sacrificial material layers through the back-side trench with a first conductive layer, wherein the remaining portions of the first insulating layer and the first sacrificial material layer within the first dielectric trench trench structure comprise a first vertical alternating sequence of a first insulating plate and a first dielectric material plate; and forming at least one through-memory level interconnect via structure through the first vertical alternating sequence of the first insulating plate and the first dielectric material plate. Attached Figure Description

[0007] Figure 1A This is a vertical cross-sectional view of an exemplary structure following the formation of a semiconductor device, a lower-level dielectric layer, a lower-level metal interconnect structure, and a source-level material layer on a semiconductor substrate according to a first embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A A top view of an exemplary structure. The hinged vertical plane A-A' is... Figure 1A The vertical cross-sectional view of the plane.

[0009] Figure 1C It is along Figure 1B An enlarged view of the source layer material layer during the vertical plane C-C' interception process.

[0010] Figure 2 This is a vertical cross-sectional view of an exemplary structure following the alternating stacking of a first insulating layer and a first spacer material layer, according to an embodiment of the present disclosure.

[0011] Figure 3 This is a vertical cross-sectional view of an exemplary structure following a patterned first stepped region, a first backward stepped dielectric material portion, and an interlayer dielectric layer, according to an embodiment of the present disclosure.

[0012] Figure 4A This is a vertical cross-sectional view of an exemplary structure after the formation of the first layer memory opening, the first layer support opening, the first layer isolation opening, and the first layer trench, according to an embodiment of the present disclosure.

[0013] Figure 4B yes Figure 4AA top view of an exemplary structure. The hinged vertical plane A-A' corresponds to... Figure 4A The vertical cross-sectional view of the plane.

[0014] Figure 4C yes Figure 4A A top view of another area of ​​the exemplary structure.

[0015] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the formation of various sacrificial infill structures, according to embodiments of this disclosure.

[0016] Figure 6A This is a vertical cross-sectional view of an exemplary structure following the formation of a second alternating stack of a second insulating layer and a second spacer material layer, a second stepped surface, and a second backward stepped dielectric material portion, according to an embodiment of this disclosure.

[0017] Figure 6B yes Figure 6A A top view of an exemplary structure. The hinged vertical plane A-A' corresponds to... Figure 6A The vertical cross-sectional view of the plane.

[0018] Figure 7A This is a vertical cross-sectional view of an exemplary structure after the formation of the second-layer memory opening, the second-layer support opening, the column cavity, and the second-layer trench, according to an embodiment of the present disclosure.

[0019] Figure 7B It is intercepted along plane B-B'. Figure 7A A horizontal cross-sectional view of an exemplary structure. The hinged vertical plane A-A' corresponds to... Figure 7A The vertical cross-sectional view of the plane.

[0020] Figure 7C yes Figure 7A and Figure 7B Another vertical cross-sectional view of the exemplary structure.

[0021] Figure 7D yes Figure 7A Another region of the exemplary structure is shown in a horizontal cross-sectional view at height B-B' in the horizontal plane. The hinged vertical plane C-C' corresponds to... Figure 7C The vertical cross-sectional view of the plane.

[0022] Figure 8A This is a vertical cross-sectional view of an exemplary structure after forming an interlayer memory opening, an interlayer support opening, and an embedded trench connected to the column cavity, according to an embodiment of the present disclosure.

[0023] Figure 8B It is intercepted along plane B-B'. Figure 8AA horizontal cross-sectional view of an exemplary structure. The hinged vertical plane A-A' corresponds to... Figure 8A The vertical cross-sectional view of the plane.

[0024] Figure 8C yes Figure 8A and Figure 8B Another vertical cross-sectional view of the exemplary structure.

[0025] Figure 8D yes Figure 8A Another region of the exemplary structure is shown in a horizontal cross-sectional view at height B-B' in the horizontal plane. The hinged vertical plane C-C' corresponds to... Figure 8C The vertical cross-sectional view of the plane.

[0026] Figure 9A This is a vertical cross-sectional view of an exemplary structure after the formation of the sacrificial memory opening filling material portion, according to an embodiment of the present disclosure.

[0027] Figure 9B It is along Figure 9A A horizontal cross-sectional view of an exemplary structure taken by plane B-B'.

[0028] Figure 10A This is a vertical cross-sectional view of a region of an exemplary structure after the formation of the dielectric filling material portion, according to an embodiment of the present disclosure.

[0029] Figure 10B It is along Figure 10A A horizontal cross-sectional view of an exemplary structure taken by plane B-B'.

[0030] Figure 11A This is a vertical cross-sectional view of a region of an exemplary structure after the removal of the sacrificial memory opening filler material portion, according to an embodiment of this disclosure.

[0031] Figure 11B It is along Figure 11A A horizontal cross-sectional view of an exemplary structure taken by plane B-B'.

[0032] Figures 12A to 12D A sequential vertical cross-sectional view of the memory openings during the formation of the memory opening filling structure according to an embodiment of the present disclosure is shown.

[0033] Figure 13A This is a vertical cross-sectional view of an exemplary structure after the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0034] Figure 13B yes Figure 8A and Figure 8B Another vertical cross-sectional view of the exemplary structure.

[0035] Figure 13C It is along Figure 13B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 13B The vertical cross-sectional view of the plane.

[0036] Figure 14A This is a vertical cross-sectional view of an exemplary structure after the formation of the back-side groove, according to an embodiment of the present disclosure.

[0037] Figure 14B yes Figure 14A Another vertical cross-sectional view of the exemplary structure.

[0038] Figure 14C It is along Figure 14B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 14B The vertical cross-sectional view of the plane.

[0039] Figure 14D It is along Figure 14C A vertical cross-sectional view of a region of an exemplary structure taken by a vertical plane D-D'.

[0040] Figures 15A to 15C A sequential vertical cross-sectional view of the memory opening-filling structure and back-side trench during the formation of the source-level material layer, according to an embodiment of the present disclosure, is shown.

[0041] Figure 16A This is a vertical cross-sectional view of an exemplary structure after the formation of the dielectric semiconductor oxide material portion, according to an embodiment of the present disclosure.

[0042] Figure 16B yes Figure 16A Another vertical cross-sectional view of the exemplary structure.

[0043] Figure 16C It is along Figure 16B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 16B The vertical cross-sectional view of the plane.

[0044] Figure 16D It is along Figure 16C A vertical cross-sectional view of the region of the illustrative structure, taken by the vertical plane D-D'.

[0045] Figure 17A This is a vertical cross-sectional view of an exemplary structure after the formation of the back recess according to an embodiment of the present disclosure.

[0046] Figure 17B yes Figure 17A Another vertical cross-sectional view of the exemplary structure.

[0047] Figure 17C It is along Figure 17B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 17B The vertical cross-sectional view of the plane.

[0048] Figure 17D It is along Figure 17C A vertical cross-sectional view of a region of an exemplary structure taken by a vertical plane D-D'.

[0049] Figure 18A This is a vertical cross-sectional view of an exemplary structure after the formation of a conductive layer, according to an embodiment of the present disclosure.

[0050] Figure 18B yes Figure 18A Another vertical cross-sectional view of the exemplary structure.

[0051] Figure 18C It is along Figure 18B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 18B The vertical cross-sectional view of the plane.

[0052] Figure 18D It is along Figure 18C A vertical cross-sectional view of a region of an exemplary structure taken by a vertical plane D-D'.

[0053] Figure 18E It is along Figure 18B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 18B The vertical cross-sectional view of the plane.

[0054] Figure 19A This is a vertical cross-sectional view of an exemplary structure after a dielectric wall structure has been formed in a back trench according to an embodiment of the present disclosure.

[0055] Figure 19B yes Figure 19A A vertical cross-sectional view of a region of an exemplary structure.

[0056] Figure 20A This is a vertical cross-sectional view of an exemplary structure after the formation of a higher-level dielectric material layer and a higher-level metal interconnect structure, according to an embodiment of this disclosure.

[0057] Figure 20B yes Figure 20A Another vertical cross-sectional view of the exemplary structure.

[0058] Figure 20C It is along Figure 20B The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane C-C'. The hinged vertical plane B-B' corresponds to... Figure 20B The vertical cross-sectional view of the plane.

[0059] Figure 20D It is along Figure 20C A vertical cross-sectional view of a region of an exemplary structure taken by a vertical plane D-D'.

[0060] Figure 20E It is along Figure 20B A horizontal cross-sectional view of an exemplary structure taken by the horizontal plane E-E'. The hinged vertical plane B-B' corresponds to... Figure 20B The vertical cross-sectional view of the plane. Detailed Implementation

[0061] The embodiments disclosed herein provide a three-dimensional memory device including a multi-layer trench isolation structure with contact via structure and a method for manufacturing the same, various embodiments of which are described in detail herein.

[0062] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0063] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0064] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0065] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0066] A monolithic three-dimensional memory array is a memory array in which multiple memory stages are formed on a single substrate, such as a semiconductor wafer, without having an intermediate substrate. The term "monolithic" refers to the fact that the layers of each stage of the array are deposited directly on the layers of each lower stage of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory stages on separate substrates and vertically stacking the memory stages. The substrate may be thinned or removed from the memory stages prior to bonding, but since the memory stages are initially formed on separate substrates, such a memory is not a true monolithic three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0067] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are joined therein, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") that are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages that are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0068] refer to Figures 1A to 1C An exemplary structure according to a first embodiment of this disclosure is shown. Figure 1C yes Figure 1A and Figure 1BThe diagram shows an enlarged view of the source-level material layer 10' during the process. This exemplary structure includes a semiconductor substrate 8 and a semiconductor device 710 formed thereon. The semiconductor substrate 8 may include a substrate semiconductor layer 9 at least in its upper portion. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between the semiconductor devices 710. The semiconductor device 710 may include, for example, field-effect transistors (FETs) including corresponding transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The FETs may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device 710 may include any semiconductor circuitry to support the operation of a subsequently formed memory structure; this semiconductor circuitry is generally referred to as driver circuitry, and also as peripheral circuitry. As used herein, peripheral circuitry refers to any, each, or all of the word line decoder circuitry, word line switching circuitry, bit line decoder circuitry, bit line sensing and / or switching circuitry, power supply / distribution circuitry, data buffers, and / or latches, or may be any other semiconductor circuitry that can be implemented outside the memory array structure of the memory device. For example, the semiconductor device may include word line switching devices for electrically biasing word lines of the three-dimensional memory structure to be formed.

[0069] A dielectric layer, referred to herein as a lower-level dielectric layer 760, may be formed over the semiconductor device. The lower-level dielectric layer 760 may include, for example, a dielectric pad 762 (such as a silicon nitride pad that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric layer 764 overlying the dielectric pad 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 overlying the first dielectric layer 764, and at least one second dielectric layer 768. A dielectric layer stack (including the lower-level dielectric layer 760) may be used as a matrix of lower-level metal interconnect structures 780, which provide electrical wiring to and from the landing pads of the semiconductor device and subsequently formed through-memory interconnect via structures. The lower-level metal interconnect structures 780 may be formed within the dielectric layer stack of the lower-level dielectric layer 760 and overlying a field-effect transistor. The lower-level metal interconnect structure 780 may include a lower-level metal line structure positioned below and optionally in contact with the bottom surface of the silicon nitride layer 766.

[0070] For example, a lower-level metal interconnect structure 780 may be formed within a first dielectric layer 764. The first dielectric layer 764 may be a plurality of dielectric layers in which various elements of the lower-level metal interconnect structure 780 are sequentially formed. Each dielectric layer selected from the first dielectric layer 764 may include any of doped silicate glass, undoped silicate glass, organosilicon glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric layer 764 may comprise or consist substantially of a dielectric layer with a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide). The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes of corresponding source and drain nodes or gate electrode contacts of devices), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing pad level metal line structures 788, which are configured to serve as landing pads for subsequent through-memory level interconnect via structures to be formed.

[0071] A landing pad-level metal wire structure 788 can be formed within the topmost dielectric layer of the first dielectric layer 764 (which may be multiple dielectric layers). Each of the lower-level metal interconnect structures 780 can include a metal nitride pad and a metal filler structure. The top surface of the landing pad-level metal wire structure 788 and the topmost surface of the first dielectric layer 764 can be planarized using a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 can be formed directly on the top surface of the landing pad-level metal wire structure 788 and the topmost surface of the first dielectric layer 764.

[0072] At least one second dielectric layer 768 may comprise a single dielectric layer or multiple dielectric layers. Each dielectric layer selected from at least one second dielectric layer 768 may comprise any of doped silicate glass, undoped silicate glass, and organosilicon glass. In one embodiment, at least one second dielectric layer 768 may comprise or be substantially composed of a dielectric layer with a dielectric constant not exceeding 3.9 of undoped silicate glass (silicon oxide).

[0073] Optional layers of metallic and semiconductor materials may be deposited over or within patterned recesses of at least one second dielectric material layer 768 and photolithographically patterned to provide an optional conductive platen layer 6 and a process source-level material layer 10'. The optional conductive platen layer 6, if present, provides a highly conductive conduction path for current flowing into or out of the process source-level material layer 10'. The optional conductive platen layer 6 comprises conductive materials such as metals or heavily doped semiconductor materials. The optional conductive platen layer 6 may, for example, comprise a tungsten layer having a thickness in the range of 3 nm to 100 nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the conductive platen layer 6 as a diffusion barrier layer. The conductive platen layer 6 can be used as a special source line in the finished device. Furthermore, the conductive platen layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor, or insulating layer. The optional conductive platen layer 6 may include a metal compound material, such as a conductive metal nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive layer 6 can range from 5 nm to 100 nm, but smaller and larger thicknesses can also be used.

[0074] The source-level material layer 10' during the process may include various layers that are subsequently modified to form the source-level material layer. The source-level material layer includes a source contact layer during formation, which serves as a common source region for the vertical field-effect transistors of the three-dimensional memory device. In one embodiment, the source-level material layer 10' during the process may include, from bottom to top, a lower source-level semiconductor layer 112, a lower sacrificial pad 103, a source-level sacrificial layer 104, a higher sacrificial pad 105, a higher source-level semiconductor layer 116, a source-level insulating layer 117, and an optional source-selective conductive layer 118.

[0075] The lower source layer semiconductor layer 112 and the higher source layer semiconductor layer 116 may contain doped semiconductor materials, such as doped polycrystalline silicon or doped amorphous silicon. The conductivity type of the lower source layer semiconductor layer 112 and the higher source layer semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a first conductivity type of doping, then the lower source layer semiconductor layer 112 and the higher source layer semiconductor layer 116 have a second conductivity type of doping opposite to the first conductivity type. The thickness of each of the lower source layer semiconductor layer 112 and the higher source layer semiconductor layer 116 may be in the range of 20 nm to 150 nm, from 10 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0076] The source-level sacrificial layer 104 includes sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the higher sacrificial pad 105. In one embodiment, the source-level sacrificial layer 104 may comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration greater than 20%. The thickness of the source-level sacrificial layer 104 can range from 30 nm to 400 nm, such as from 60 nm to 200 nm, but smaller and larger thicknesses are also possible.

[0077] The lower sacrificial pad 103 and the higher sacrificial pad 105 contain materials that can be used as etch-stop materials during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial pad 103 and the higher sacrificial pad 105 may contain silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial pad 103 and the higher sacrificial pad 105 may contain a silicon oxide layer with a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0078] The source-level insulating layer 117 may comprise a dielectric material, such as silicon oxide. The thickness of the source-level insulating layer 117 may range from 20 nm to 400 nm, such as 40 nm to 200 nm, but smaller and larger thicknesses are also possible. An optional source-selection layer conductive layer 118 may comprise a conductive material that can be used as a source-selection layer gate electrode. For example, the optional source-selection layer conductive layer 118 may comprise a doped semiconductor material, such as doped polycrystalline silicon or doped amorphous silicon, which may subsequently be converted to doped polycrystalline silicon by an annealing process. The thickness of the optional source-selection layer conductive layer 118 may range from 30 nm to 200 nm, such as 60 nm to 100 nm, but smaller and larger thicknesses are also possible.

[0079] During the process, the source layer 10' can be formed directly above a subset of semiconductor devices on the semiconductor substrate 8 (e.g., a silicon wafer). As used herein, the first element is positioned "directly above" the second element if the first element is positioned above a horizontal plane including the topmost surface of the second element and the region of the first element, and the region of the second element has regional overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the semiconductor substrate 8). In one embodiment, the source layer 10' may have openings in each region, where through-memory interconnect via structures will subsequently be formed. For example, the source layer 10' may have openings in the memory array region 100.

[0080] The optional conductive plate layer 6 and the in-process source layer material layer 10' can be patterned to provide openings in regions where through-memory level interconnect via structures and through-dielectric contact via structures will subsequently be formed. The patterned portion of the stack of conductive plate layer 6 and in-process source layer material layer 10' exists in each memory array region 100, in which a three-dimensional memory stack structure will subsequently be formed.

[0081] The optional conductive plate layer 6 and the in-process source level material layer 10' can be patterned such that openings extend above a stepped region 200 where a contact via structure for which a contact word line conductive layer will subsequently be formed. In one embodiment, the stepped region 200 can be laterally spaced from the memory array region 100 along a first horizontal direction hd1. A horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the in-process source level material layer 10' can be formed within a region of the memory array region 100, in which a three-dimensional memory array including a memory stack structure will subsequently be formed. A peripheral device region 400, which can subsequently be filled with a field dielectric material portion, can be provided adjacent to the stepped region 200.

[0082] The region comprising the semiconductor device 710, a lower-level dielectric layer 760, and a lower-level metal interconnect structure 780, referred herein as the lower peripheral device region 700, is located below the memory tier assembly to be formed and includes peripheral devices for the memory tier assembly. The lower-level metal interconnect structure 780 may be formed in the lower-level dielectric layer 760.

[0083] The lower-level metal interconnect structure 780 can be electrically connected to active nodes (e.g., transistor active regions 742 or gate electrodes 754) of the semiconductor device 710 (e.g., a CMOS device) and can be located at the level of the lower-level dielectric layer 760. Through-memory interconnect via structures can then be formed directly on the lower-level metal interconnect structure 780 to provide electrical connections to memory devices to be formed subsequently. In one embodiment, the pattern of the lower-level metal interconnect structure 780 can be selected such that a landing pad-level metal line structure 788 (which is a subset of the lower-level metal interconnect structures 780 located at the topmost portion of the lower-level metal interconnect structure 780) can provide a landing pad structure for the subsequently formed through-memory interconnect via structures.

[0084] refer to Figure 2Alternating stacks of first and second material layers can be formed. Each first material layer may contain a first material, and each second material layer may contain a second material different from the first material. In embodiments where at least another alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first layer alternating stack. The hierarchy of the first layer alternating stack is referred to herein as a first layer hierarchy, and the hierarchy of the alternating stack to be subsequently formed directly above the first layer hierarchy is referred to herein as a second layer hierarchy, and so on.

[0085] The first layer alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although this disclosure has been described using embodiments in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer are expressly contemplated herein (thereby eliminating the need to perform a replacement process).

[0086] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the source layer material layer 10' during the process. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

[0087] As used herein, alternating stacking of the first and second elements refers to a structure in which instances of the first element and instances of the second element alternate. In a plurality of elements that are not alternating, each instance of the first element is adjacent to two instances of the second element on both sides, and in a plurality of elements that are not alternating, each instance of the second element is adjacent to two instances of the first element at both ends. The first element may always have the same thickness or may have different thicknesses. The second element may always have the same thickness or may have different thicknesses.

[0088] Alternating multiple first and second material layers can begin with or end with an instance of a first material layer or an instance of a second material layer. In one embodiment, instances of the first element and instances of the second element can form a unit that repeats periodically within the alternating multiple elements.

[0089] The first alternating stack (132, 142) may include a first insulating layer 132 made of a first material and a first sacrificial material layer 142 made of a second material, which is different from the first material. The first material of the first insulating layer 132 may be at least one insulating material.

[0090] Insulating materials that can be used in the first insulating layer 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) commonly referred to as high dielectric constant (high k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0091] The second material of the first sacrificial material layer 142 may be a sacrificial material that can be selectively removed with respect to the first material of the first insulating layer 132. As used herein, the removal of the first material is "selective" with respect to the second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0092] The second material of the first sacrificial material layer 142 can then be replaced by a conductive electrode, which can be used as, for example, a control gate electrode for a vertical NAND device. According to one aspect of this disclosure, the first sacrificial material layer 142 comprises a dielectric material. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0093] In one embodiment, the first insulating layer 132 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. A second material may be formed of the first sacrificial material layer 142, for example, by CVD or atomic layer deposition (ALD).

[0094] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the alternating stack of first layers (132, 142) may have a substantially uniform thickness that remains constant within each respective first sacrificial material layer 142.

[0095] A first insulating cap layer 170 may then be formed over the alternating stack of first layers (132, 142). The first insulating cap layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may range from 20 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0096] refer to Figure 3 The first insulating cap layer 170 and the alternating stacks of the first layers (132, 142) can be patterned to form a first stepped surface in the stepped region 200. The stepped region 200 may include corresponding first stepped regions and second stepped regions, in which the first stepped surface is formed, and in the second stepped region, additional stepped surfaces are subsequently formed in a second layer structure (which is subsequently formed over the first layer structure) and / or an additional layer structure.

[0097] The cavity can be vertically recessed, forming a first stepped surface, for example, by forming a mask layer with openings therein, etching the cavity within the layers of the first insulating cap layer 170 and iteratively expanding the etched area, and by etching each pair of first insulating layers 132 and first sacrificial material layers 142 positioned directly below the bottom surface of the etched cavity within the etched area. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as the first stepped cavity.

[0098] A dielectric filler material (such as undoped or doped silicate glass) can be deposited to fill the first stepped cavity. Excess portions of the dielectric filler material can be removed from a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric filler material covering the area on the first stepped surface constitutes the first backward stepped dielectric portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the substrate to the top surface on which the element is situated. The alternating stack of the first layers (132, 142) and the first backward stepped dielectric portion 165 together constitute a first-layer structure, which is the structure subsequently modified in the process.

[0099] Interlayer dielectric layer 180 may optionally be deposited over the first layer structure (132, 142, 170, 165). Interlayer dielectric layer 180 comprises a dielectric material, such as silicon oxide. In one embodiment, interlayer dielectric layer 180 may comprise doped silicate glass having a higher etch rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, interlayer dielectric layer 180 may comprise phosphosilicate glass. The thickness of interlayer dielectric layer 180 may range from 30 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0100] refer to Figures 4A to 4C Various first-layer openings (149, 129, 179) can be formed to penetrate the interlayer dielectric layer 180 and the first-layer structure (132, 142, 170, 165) and enter the source layer material layer 10'. A photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form various openings therethrough.

[0101] The pattern of openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structures (132, 142, 170, 165) and into the source layer material layer 10' during the first anisotropic etching process to simultaneously (i.e., during the first isotropic etching process) form various first layer openings (149, 129, 179). The various first layer openings (149, 129, 179) may include a first layer memory opening 149, a first layer support opening 129, and a first layer trench 179. Figure 4B The position of step S in the first layer of alternating stacks (132, 142) is shown in dashed lines.

[0102] The first layer memory opening 149 may be an opening formed in the memory array region 100 through each layer within the first layer alternating stack (132, 142), and subsequently used to form a memory stack structure therein. The first layer memory opening 149 may be formed as a cluster 319 of the first layer memory openings 149 laterally spaced along the second horizontal direction hd2. Each cluster 319 of the first layer memory openings 149 may be formed as a two-dimensional array of the first layer memory openings 149.

[0103] A subset of the first layer support opening 129 may be formed in a segment of the memory array region 100 that is not filled with the first layer memory opening 149. The segments of the memory array region 100 that are not filled with the first layer memory opening 149 may be distributed over multiple regions within the memory array region 100. The first layer support opening 129 may include a first subset of the first layer support openings 129 formed in the stepped region 200, and a second subset of the first layer support openings 129 formed between groups 339 of clusters 319 of the first layer memory openings 149 laterally spaced along the first horizontal direction hd1 in the memory array region 100. The first subset of the first layer support openings 129 formed through the first backward stepped dielectric material portion 165 may be formed through a corresponding horizontal surface of the first stepped surface.

[0104] like Figure 4C As shown, a second subset of the first layer support openings 129 may be formed between groups 339 of clusters 319 of the first layer memory openings 149 that are laterally spaced along the first horizontal direction hd1. In one embodiment, some of the first layer support openings 129 within the second subset of the first layer support openings 129 may be arranged in a straight line extending along the first direction hd1. Additional first layer support openings 129 may be provided outside the straight line of the first layer support openings 129.

[0105] A first subset of the first layer memory openings 149 may be formed in a first portion of the memory array region 100, and a second subset of the first layer memory openings 149 may be formed in a second portion of the memory array region 100, the second portion being laterally spaced from the first portion of the memory array region 100 along a first horizontal direction hd1. A first layer trench 179 may be formed between the first subset and the second subset of the first layer memory openings 149. Each first layer trench 179 may have an inner sidewall laterally surrounding a patterned portion of alternating stacked (132, 142) first layer, an outer sidewall laterally offset outward from the inner sidewall, and a bottom surface connecting the inner sidewall to the outer sidewall. Each region containing the first layer trench 179 is referred to herein as a trench region MR.

[0106] Generally, the cell pattern UP of the combination of the first layer memory opening 149, the first layer support opening 129, and the first layer trench 179 can be repeated along the second horizontal direction hd2. Each cell pattern UP includes a group 339 of clusters 319 of the first layer memory openings 149 that are laterally spaced along the second horizontal direction hd2 and / or laterally spaced along the first horizontal direction hd1.

[0107] In one embodiment, the first anisotropic etching process may include an initial step in which the materials of the first alternating stacked layers (132, 142) are etched simultaneously with the material of the first backward-stepped dielectric portion 165. The chemistry of the initial etching step may be alternating to optimize the etching of the first and second materials in the first alternating stacked layers (132, 142) while providing an average etching rate comparable to that of the material of the first backward-stepped dielectric portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129, 179) may be substantially vertical or may be tapered.

[0108] After etching through alternating stacks (132, 142) and a first backward-stepped dielectric material portion 165, the chemical properties of the terminal portion of the first anisotropic etching process can be selected to etch one or more dielectric materials through at least one second dielectric layer 768 at an etch rate higher than the average etch rate of the source layer 10' during the process. For example, the terminal portion of the anisotropic etching process may include the step of selectively etching the dielectric material of the at least one second dielectric layer 768 for semiconductor materials within the component layer in the source layer 10' during the process. In one embodiment, the terminal portion of the first anisotropic etching process may etch through the source selective layer conductive layer 118, the source layer insulating layer 117, the higher source layer semiconductor layer 116, the higher sacrificial pad 105, the source layer sacrificial layer 104, and the lower sacrificial pad 103, and at least partially into the lower source layer semiconductor layer 112. The terminal portion of the first anisotropic etching process may include at least one etching chemical substance for etching various semiconductor materials of the source layer 10' in the process. The photoresist layer may then be removed, for example, by ashing.

[0109] Optionally, portions of the first layer memory opening 149, the first layer support opening 129, and the first layer trench 179 at the level of the interlayer dielectric layer 180 can be laterally extended by isotropic etching. In this case, the interlayer dielectric layer 180 may comprise a dielectric material (such as borosilicate glass) having a greater etch rate in dilute hydrofluoric acid than the first insulating layer 132 (which may comprise undoped silicate glass). Isotropic etching (such as wet etching using HF) can be used to extend the lateral dimension of the first layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first layer memory opening 149 located at the level of the interlayer dielectric layer 180 may optionally be widened to provide a larger landing pad for the second layer memory opening that will subsequently be formed through alternating stacks of second layers (formed subsequently before the formation of the second layer memory opening).

[0110] The first sacrificial material layer 142 may include a first dielectric material such as silicon nitride. A patterned portion of the first insulating layer 132, laterally surrounded by the first trench 179, includes a first insulating plate 132'. A patterned portion of the first sacrificial material layer 142, laterally surrounded by the first trench 179, includes a first dielectric material plate 142'. A patterned portion of the first insulating cap layer 170, laterally surrounded by the first trench 179, includes a first insulating cap plate 170'. A patterned portion of the interlayer dielectric layer 180, laterally surrounded by the first trench 179, includes an interlayer dielectric plate 180'. The patterned portion of the first insulating layer 132 and the first sacrificial material layer 142 within each first trench 179 includes a first vertical alternation sequence of the first insulating plate 132' and the first dielectric material plate 142'.

[0111] In one embodiment, each first-layer trench 179 may have a horizontal cross-sectional shape of a rectangular frame. In this case, the outer sidewalls of each first-layer trench 179 may include a pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along a second horizontal direction hd2. The inner sidewalls of each first-layer trench 179 may include a pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along the second horizontal direction hd2.

[0112] Each of the first insulating plates 132' is vertically spaced from the top surface of the source layer 10' in the process by the same vertical distance as the top surface of the source layer 10' to the corresponding first insulating layer 132 in the first alternating stack. Each of the first dielectric plates 142' is vertically spaced from the top surface of the source layer 10' in the process by the same vertical distance as the top surface of the source layer 10' to the corresponding first sacrificial layer 142 in the first alternating stack.

[0113] refer to Figure 5 Sacrificial first-layer opening fill portions (148, 128, 178) can be formed in various first-layer openings (149, 129, 179). For example, sacrificial first-layer fill material can be deposited simultaneously in each of the first-layer openings (149, 129, 179). The sacrificial first-layer fill material includes material that can be selectively removed from the materials of the first insulating layer 132 and the first sacrificial material layer 142.

[0114] In one embodiment, the sacrificial first layer filler material may include a semiconductor material, such as silicon (e.g., a-Si or polycrystalline silicon), silicon-germanium alloy, germanium, III-V compound semiconductor materials, or combinations thereof. Optionally, a thin etch stop pad (such as a silicon oxide layer or silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first layer filler material. The sacrificial first layer filler material can be formed by non-conformal deposition or conformal deposition methods.

[0115] In another embodiment, the sacrificial first filler material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating cap layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first filler material may include borosilicate glass or porous or non-porous organosilicon glass having an etch rate at least 100 times higher than that of dense TEOS oxide in 100:1 diluted hydrofluoric acid (i.e., silicon oxide formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying it in an annealing process). In this case, a thin etch stop pad (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first filler material. The sacrificial first filler material can be formed by non-conformal deposition or conformal deposition methods.

[0116] In yet another embodiment, the sacrifice of the first layer of filler material may include amorphous silicon or carbon-containing material (such as amorphous carbon or diamond-like carbon) that can subsequently be removed by ashing, or a silicon-based polymer that can be selectively removed from the material of the alternating stacks (132, 142) of the first layer.

[0117] Portions of the deposited sacrificial material can be removed from above the topmost layer of the alternating stack of first layers (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial first layer fill material can be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 can be used as an etch stop layer or a planarization stop layer.

[0118] The remaining portions of the sacrificial first layer fill material comprise sacrificial first layer opening fill portions (148, 128, 178). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening fill portion 128. Each remaining portion of the sacrificial material in the first layer trench 179 constitutes a sacrificial trench filling structure 178. The various sacrificial first layer opening fill portions (148, 128, 178) are formed simultaneously, i.e., formed during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the alternating stack of first layers (132, 142) (such as from above the top surface of the interlayer dielectric layer 180). The top surface of the sacrificial first layer opening fill portions (148, 128, 178) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the first layer of opening-filled portions (148, 128, 178) may or may not include the cavity therein.

[0119] refer to Figure 6A and Figure 6BA second layer structure can be formed over the first layer structure (132, 142, 170, 148). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack of material layers (232, 242) may subsequently be formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating third and fourth material layers. Each third material layer may contain a third material, and each fourth material layer may contain a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0120] In one embodiment, the third material layer may be the second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third and fourth material layers may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that can be selectively removed from the third material of the second insulating layer 232. According to one aspect of the present disclosure, the second sacrificial material layer 242 includes a dielectric material, which may be the same material as the dielectric material of the first sacrificial material layer 142. The fourth material of the second sacrificial material layer 242 may subsequently be replaced by a conductive electrode, which may be used as, for example, a control gate electrode for a vertical NAND device.

[0121] In one embodiment, each second insulating layer 232 may comprise a second insulating material, and each second sacrificial material layer 242 may comprise a second sacrificial material. In this case, the alternating stack of second layers (232, 242) may comprise alternating plurality of second insulating layers 232 and second sacrificial material layers 242. A third material for the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). A fourth material for the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0122] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that can be used in the second insulating layer 232 may be any material that can be used in the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed from the third material of the second insulating layer 232. The sacrificial material that can be used in the second sacrificial material layer 242 may be any material that can be used in the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material. In one embodiment, the first insulating layer 132 and the second insulating layer 232 may comprise silicon oxide, and the first sacrificial material layer 142 and the second sacrificial material layer 242 may comprise silicon nitride.

[0123] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the pair of second insulating layers 232 and second sacrificial material layers 242 can range from 2 to 1,024, and is typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the alternating stack of second layers (232, 242) can have a uniform thickness that remains substantially constant within each respective second sacrificial material layer 242.

[0124] The second stepped surface in the second stepped region can be formed in the stepped region 200 using the same set of processing steps as those used to form the first stepped surface in the first stepped region, wherein the pattern of at least one mask layer is appropriately adjusted. A second backward stepped dielectric material portion 265 may be formed above the second stepped surface in the stepped region 200.

[0125] A second insulating cap layer 270 may then be formed over the alternating stack of second layers (232, 242). The second insulating cap layer 270 contains a dielectric material different from that of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may contain silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may contain silicon nitride.

[0126] Generally, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source layer material layer 10' in the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the stepped region on at least one alternating stack (132, 142, 232, 242).

[0127] refer to Figures 7A to 7D Various second-layer openings (249, 229, 269, 279) can be formed through the second-layer structure (232, 242, 265, 270). A photoresist layer (not shown) can be applied over the second insulating cap layer 270 and can be photolithographically patterned to form various openings passing through it. The pattern of the openings in the photoresist layer may include the pattern of the first-layer memory opening 149 and the pattern of the first-layer support opening 129. Furthermore, the pattern of the openings in the photoresist layer may include a discrete array of openings located within a rectangular frame region of the corresponding underlying sacrificial trench filling structure 178. Additionally, the pattern of the openings in the photoresist layer may include a pattern of a rectangular frame nested within a region of a corresponding one of the sacrificial trench filling structures 178. In other words, each opening having a rectangular frame shape may be nested within a region of a corresponding one of the sacrificial trench filling structures 178.

[0128] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270) via a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings (249, 229, 269, 279). The various second layer openings (249, 229, 269, 279) may include a second layer memory opening 249, a second layer support opening 229, a pillar cavity 269, and a second layer trench 279.

[0129] The second-layer memory opening 249 can be formed directly on the top surface of a corresponding one of the first-layer memory opening filling portions 148. The second-layer support opening 229 can be formed directly on the top surface of a corresponding one of the first-layer support opening filling portions 128. The column cavity 269 can be formed directly on the top surface of a corresponding one of the first-layer trench filling portions 178. A plurality of discrete column cavities 269 having a cylindrical or rectangular horizontal cross-sectional shape can be formed on the top surface of each of the first-layer trench filling portions 178. The second-layer trench 279 can be formed within the top periphery of the inner sidewall of the correspondingly lower inner sidewall of the first-layer trench filling portion 178. A subset of the second-layer support openings 229 can be formed as horizontal surfaces passing through the second stepped surfaces, including the inter-face surfaces between the second alternating stack (232, 242) and the second backward stepped dielectric material portions 265. Figure 7B The dashed lines in the middle show the positions of the steps S in the first layer of alternating stacks (132, 142) and the second layer of alternating stacks (232, 242).

[0130] A subset of the second-layer support openings 229 may be formed in segments of the memory array region 100 that are not filled with the second-layer memory openings 249. These segments of the memory array region 100 that are not filled with the second-layer memory openings 249 may be distributed over multiple regions within the memory array region 100. The second-layer support openings 229 may include a first subset of the second-layer support openings 229 formed in the stepped region 200, and a second subset of the second-layer support openings 229 that may be formed between groups 439 of clusters 419 of the second-layer memory openings 249 laterally spaced along the first horizontal direction hd1 in the memory array region 100. The first subset of the second-layer support openings 229 formed through the second backward-stepped dielectric material portion 265 may be formed through the corresponding horizontal surface of the second stepped surface.

[0131] A second subset of the second-layer support openings 229 may be formed between groups 439 of clusters 419 of second-layer memory openings 249 laterally spaced along the first horizontal direction hd1. In one embodiment, some of the second-layer support openings 229 within the second subset of the second-layer support openings 229 may be arranged in a straight line extending along the first direction hd1. Additional second-layer support openings 229 may be provided outside the straight line of the second-layer support openings 229.

[0132] Generally, the cell pattern UP of the combination of the second layer memory opening 249, the second layer support opening 229, the column cavity 269, and the second layer trench 279 can be repeated along the second horizontal direction hd2. Each cell pattern UP includes a group 439 of clusters 419 of the first layer memory openings 149 that are laterally spaced along the second horizontal direction hd2 and / or laterally spaced along the first horizontal direction hd1.

[0133] The second anisotropic etching process may include an etching step in which the material of the second alternating stack (232, 242) is etched simultaneously with the material of the second backward-stepped dielectric portion 265. The chemical properties of the etching step may be alternating to optimize the etching of the material in the second alternating stack (232, 242) while providing an average etching rate comparable to that of the material in the second backward-stepped dielectric portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second-layer openings (249, 229, 269, 279) may be substantially vertical or may be tapered. The bottom periphery of each second-layer opening (249, 229, 269, 279) may be laterally offset and / or may be positioned entirely within the periphery of the top surface of the underlying sacrificial first-layer opening filling portion (148, 128, 178). The photoresist layer may then be removed, for example, by ashing.

[0134] Typically, multiple cylindrical cavities 269 may be formed through the second alternating stack (232, 242) and directly above each sacrificial trench trench filling structure 178. Each second-layer trench cavity 279 may be formed through the second alternating stack (232, 242). Each second-layer trench cavity 279 covers and is in contact with the first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142' (which includes the patterned portions of the first alternating stack (132, 142) and is laterally surrounded by the sacrificial trench trench filling structure 178). The bottom periphery of the outer sidewall of each second-layer trench cavity 279 may be laterally recessed inward relative to the top periphery of the inner sidewall of the corresponding underlying sacrificial trench trench filling structure 178.

[0135] The second sacrificial material layer 242 includes a second dielectric material such as silicon nitride. In one embodiment, the second sacrificial material layer 242 includes the same dielectric material as the first sacrificial material layer 142. The patterned portion of the second insulating layer 232, which is laterally surrounded by the second trench 279, includes a second insulating plate 232'. The patterned portion of the second sacrificial material layer 242, which is laterally surrounded by the second trench 279, includes a second dielectric material plate 242'. The patterned portion of the second insulating cap layer 270, which is laterally surrounded by the second trench 279, includes a second insulating cap plate. The patterned portion of the second insulating layer 232 and the second sacrificial material layer 242 within each second trench 279 includes a second vertical alternation sequence of the second insulating plate 232' and the second dielectric material plate 242'.

[0136] In one embodiment, each second-layer trench trough 279 may have a horizontal cross-sectional shape of a rectangular frame. In this case, the outer sidewalls of each second-layer trench trough 279 may include a pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along a second horizontal direction hd2. The inner sidewalls of each second-layer trench trough 279 may include a pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along the second horizontal direction hd2. Each second-layer trench cavity 279 laterally surrounds a second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242', and covers the first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142'. The sidewalls of the second insulating plate 232' and the second dielectric material plate 242' within the second vertical alternating sequence (232', 242') may be laterally offset inward relative to the sidewalls of the first insulating layer 132' and the first dielectric material plate 142' within the lower first vertical alternating sequence (132', 142'). The bottom periphery of the outer sidewall of the second trench trench 279 may be laterally recessed inward relative to the top periphery of the inner sidewall of the lower sacrificial trench trench filling structure 178.

[0137] Each of the second insulating plates 232' is vertically spaced from the top surface of the source layer material layer 10' during the process by the same vertical distance as the top surface of the source layer material layer 10' to the corresponding second insulating layer 232 in the alternating stack of second layers. Each of the second dielectric material plates 242' is vertically spaced from the top surface of the source layer material layer 10' during the process by the same vertical distance as the top surface of the source layer material layer 10' to the corresponding second sacrificial material layer 242 in the alternating stack of second layers.

[0138] refer to Figures 8A to 8DThe sacrificial first layer filler material of the sacrificial first layer opening filler portions (148, 128, 178) can be removed using an etching process. This etching process selectively etches the sacrificial first layer filler material onto the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating cap layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of the second layer memory opening 249 and the volume from which the sacrificial first layer memory opening filler portion 148 is removed. A support opening 19 (also referred to as an interlayer support opening 19) can be formed in each combination of the second layer support opening 229 and the volume from which the sacrificial first layer support opening filler portion 128 is removed. A continuous cavity comprising a first layer of trench 179 and a plurality of cylindrical cavities 269 can be formed by removing the sacrificial trench filling structure 178 through the plurality of cylindrical cavities 269 within each unit pattern UP. The sacrificial trench filling structure 178 can be selectively removed for the first alternating stack of the first layer (132, 142) and the first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142' by introducing an isotropic etchant through the plurality of cylindrical cavities 269.

[0139] refer to Figure 9A and Figure 9B Sacrificial filler material can be deposited into various openings (49, 19, 179, 269, 279). The sacrificial filler material includes materials that can be selectively removed subsequently from the materials of the first alternating stack (132, 142) and the second alternating stack (232, 242). In one embodiment, the sacrificial filler material may include amorphous carbon, diamond-like carbon (DLC), polymeric materials, germanium, or silicon-germanium alloys. In one embodiment, the sacrificial filler material may be deposited anisotropically to form voids at the bottom of each opening through the second alternating stack (232, 242) and the first alternating stack (132, 142). Excess portions of the sacrificial filler material can be removed from above a horizontal plane including the top surface of the second insulating cap layer 270 by a planarization process such as chemical mechanical planarization. Each remaining portion of the sacrificial filler material in the memory opening 49 constitutes a sacrificial memory opening filler material portion 359.

[0140] A photoresist layer (not shown) may be applied over the exemplary structure and may be photolithographically patterned to cover each of the sacrificial memory opening fill material portions 359 located within the memory opening 49, without covering the support opening 19, the pillar cavity 269, or the second trench 279. An etching process may be performed to selectively remove unmasked portions of the sacrificial fill material from within the support opening 19, the pillar cavity 269, the first trench 179, and the second trench 279 for the material of the alternating stacks of the first and second layers (132, 142). During the etching process, etchant may be provided into the volume of the first trench 179 through the pillar cavity 269. The etching process may include anisotropic etching or isotropic etching. The etching process removes portions of the sacrificial fill material in the support opening 19, the pillar cavity 269, the first trench 179, and the second trench 279. The photoresist layer can then be removed, for example, by ashing or by dissolving it in an organic solvent.

[0141] refer to Figure 10A and Figure 10B Dielectric filler materials, such as silicon oxide, can be conformally deposited in the support opening 19, the pillar cavity 269, the first trench 179, and the second trench 279. For example, a low-pressure chemical vapor deposition process can be performed to deposit dielectric filler materials in each of the support opening 19, the pillar cavity 269, the first trench 179, and the second trench 279. Excess dielectric filler material covering the top surface of the second insulating cap layer 270 can be removed by planarization processes such as recess etching and / or chemical mechanical planarization.

[0142] Each portion of the dielectric filler material filling the support opening 19 constitutes a support pillar structure 20. Each portion of the dielectric filler material filling the first trench 179 constitutes a first dielectric trench structure 176. Each portion of the dielectric filler material filling the pillar cavity 269 constitutes a dielectric pillar structure 266. Each portion of the dielectric filler material filling the second trench 279 constitutes a second dielectric trench structure 276. The combination of the first dielectric trench structure 176 and the plurality of dielectric pillar structures 266 can be formed within each continuously extending volume including the first trench 179 and the plurality of pillar cavities 169. Each first dielectric trench structure 176 fills the volume of the first trench 179, which is the volume formed by removing the sacrificial trench filler structure. The plurality of dielectric pillar structures 266 fill the plurality of pillar cavities 269. The support pillar structure 20, the first dielectric trench structure 176, the dielectric pillar structure 266, and the second dielectric trench structure 276 may contain the same dielectric material such as silicon oxide (which may be, for example, undoped silicate glass or doped silicate glass) and / or may be substantially composed of it.

[0143] Within each cell pattern UP, a first dielectric trench structure 176 extends vertically through a first alternating stack (132, 142) and laterally around a corresponding first vertical alternating sequence of a first insulating plate 132' and a first dielectric material plate 142'. A plurality of dielectric pillar structures 266 extend vertically through a second alternating stack (232, 242) and contact the top surface of the first dielectric trench structure 176. In one embodiment, the combination of the first dielectric trench structure 176 and the plurality of dielectric pillar structures 266 consists of a single, continuously extending dielectric material portion having a uniform material composition.

[0144] Within each cell pattern UP, a second dielectric trench structure 276 extends vertically through the second alternating stack (232, 242) and laterally around the second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242', and covers the first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142'. In one embodiment, the bottom periphery of the outer sidewall of the second dielectric trench structure 276 is laterally recessed inward relative to the top periphery of the inner sidewall of the first dielectric trench structure 176. The outer sidewall of the first dielectric trench structure 176 contacts the first insulating layer 132 and the first sacrificial material layer 142 of the first alternating stack (132, 142), while the outer sidewall of the second dielectric trench structure 276 contacts the second insulating layer 232 and the second sacrificial material layer 242 of the second alternating stack (232, 242). The bottom surface of the second dielectric trench structure 276 may be positioned above or at a horizontal plane including the topmost surface of the first alternating stack (132, 142), or extend into the first alternating stack (132, 142) and be positioned above at least one layer within the first alternating stack (132, 142). The total number of layers through which the second dielectric trench structure 276 extends vertically within the first alternating stack (132, 142) may be zero, or may be in the range of 1 to 10 (such as 1 to 4), and less than 10% of the total number of layers within the first alternating stack (132, 142).

[0145] refer to Figure 11A , Figure 11B and Figure 12AThe sacrificial memory opening fill material portion 359 can be selectively removed from the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), and various dielectric fill material portions (20, 266, 176, 276). For example, if the sacrificial memory opening fill material portion 359 contains a carbon-based material, it can be removed by ashing. If the sacrificial memory opening fill material portion 359 contains a silicon-germanium alloy or germanium, it can be removed by wet etching using a mixture of ammonium hydroxide and hydrogen peroxide. The memory opening 49 becomes empty after this step.

[0146] refer to Figure 12B A barrier dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L can be sequentially deposited in each memory opening 49. The barrier dielectric layer 52 can be deposited conformally using a conformal deposition process (such as low-pressure chemical vapor deposition) and can comprise a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer 52 may comprise a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the barrier dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can range from 1 nm to 20 nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can serve as a dielectric material portion, preventing the stored charge from leaking to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. Alternatively or otherwise, the barrier dielectric layer 52 may comprise a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

[0147] The charge storage layer 54 may be conformally deposited over the barrier dielectric layer 52. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge-trapping material including a dielectric charge-trapping material (e.g., silicon nitride). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) patterned, for example, by forming a sacrificial material layer (142, 242) within a lateral recess into multiple electrically isolated portions (e.g., floating gates). In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically overlapping sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers (142, 242) may be laterally recessed relative to the sidewalls of the insulating layers (132, 232), and a combination of deposition and anisotropic etching processes may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used.

[0148] A tunneling dielectric layer 56 may be formed over the charge storage layer 54. The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed via hot carrier injection or via Fowler-Nordheim tunneling-induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The stacking of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50 for storing memory bits. The combination of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50.

[0149] A semiconductor channel material layer 60L may be formed above the tunneling dielectric layer 56. The semiconductor channel material layer 60L may include a doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The conductivity type of the dopants in the semiconductor channel material layer 60L is referred to herein as a first conductivity type, which may be p-type or n-type. In one embodiment, the semiconductor channel material layer 60L has p-type doping, wherein the p-type dopant (such as boron atoms) is at a concentration of 1.0 × 10⁻⁶. 12 / cm 3 Up to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 Up to 1.0×10 17 / cm 3 The atomic concentration is present within a certain range. In one embodiment, the semiconductor channel material layer 60L comprises boron-doped amorphous silicon or boron-doped polycrystalline silicon and / or is substantially composed of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is at a concentration of 1.0 × 10⁻⁶. 12 / cm 3 Up to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 Up to 1.0×10 17 / cm 3 The atomic concentration is within a certain range. The semiconductor channel material layer 60L can be formed by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can range from 2 nm to 10 nm, but smaller and larger thicknesses can also be used. Cavities 49' are formed in the unfilled volumes of the deposited material layers (52, 54, 56, 60L) of each memory opening 49. Memory cavities 49' can exist within each unfilled volume of the memory opening 49.

[0150] refer to Figure 12CIn embodiments where the memory cavity 49' in each memory opening is not completely filled by the semiconductor channel material layer 60L, a dielectric core layer may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' in each memory opening. The dielectric core layer comprises a dielectric material, such as silicon oxide or organosilicon glass. The dielectric core layer may be deposited by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD) or by self-planarization deposition processes such as spin coating. The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 may be removed, for example, by recess etching. Recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to the height between the top surface and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0151] See Figure 12D A doped semiconductor material can be deposited in a cavity covering the dielectric core 62. The doped semiconductor material has a doping type opposite to that of the semiconductor channel material layer 60L. In one embodiment, the doped semiconductor material has n-type doping. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52, which cover a horizontal plane including the top surface of the second insulating cap layer 270, can be removed by a planarization process such as chemical mechanical planarization (CMP).

[0152] Each remaining portion of the doped semiconductor material constitutes the drain region 63. The dopant concentration in the drain region 63 can be 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 Within a certain range, but smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0153] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent barrier dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 collectively constitutes a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the barrier dielectric layer 52 may not be present in the memory film 50 at this step, and the back-side barrier dielectric layer may be formed subsequently after the formation of the back-side recess. As used herein, macroscopic retention time refers to the retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0154] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 may be a combination of the vertical semiconductor channel 60, a tunneling dielectric layer 56, multiple memory elements including portions of a charge storage layer 54, and an optional barrier dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each drain region 63 in the memory opening fill structure 58 is electrically connected to the upper end of a corresponding one of the vertical semiconductor channels 60. In the process, the source layer material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265), the interlayer dielectric layer 180, and the memory opening fill structure 58 together constitute a memory layer assembly.

[0155] The memory stack structure 55 is formed through alternating stacks {(132, 142), (232, 242)}. Each of the memory stack structures 55 includes a vertical semiconductor channel 60 and a vertical stack of memory elements positioned at the levels of the sacrificial material layers (142, 242) in the memory film 50. Each vertical stack of memory elements includes a charge storage material portion (i.e., a portion of the charge storage layer 54) positioned at each level of the sacrificial material layer 142 and laterally spaced from the vertical semiconductor channel 60 within the same memory opening 49 by a tunneling dielectric layer 56.

[0156] refer to Figures 13A to 13CThis illustrates an exemplary structure after the formation of the memory opening filling structure 58. Each of the alternating stacks {(132, 142), (232, 242)} includes a plateau region, wherein each sacrificial material layer (142, 242) within the alternating stacks {(132, 142) and / or (232, 242)}, except for the topmost sacrificial material layer (142, 242), extends laterally beyond any covering sacrificial material layer (142, 242) within the alternating stacks {(132, 142) and / or (232, 242)}. The plateau region includes stepped surfaces of the alternating stacks that extend continuously from the bottommost layer within the alternating stacks {(132, 142) or (232, 242)} to the topmost layer within the alternating stacks {(132, 142) or (232, 242)}. The support column structure 20 extends through the stepped surface and through the backward stepped dielectric material portion (165 or 265) covering the stepped surface.

[0157] A first subset of the memory stack structure 55 is located in a first portion of the memory array region 100, wherein each layer of a first alternating stack (132, 142) and each layer of a second alternating stack (232, 242) are present. A second subset of the memory stack structure 55 is located in a second portion of the memory array region 100, wherein each layer of the first alternating stack (132, 142) and each layer of the second alternating stack (232, 242) are present and laterally spaced from the first portion of the memory array region 100 along a first horizontal direction hd1.

[0158] refer to Figures 14A to 14D A first contact-level dielectric layer 280 can be formed over the second layer structure (232, 242, 270, 265). The first contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and can be formed by conformal or non-conformal deposition processes. For example, the first contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0159] A photoresist layer (not shown) may be applied over the first contact-level dielectric layer 280 and may be photolithographically patterned to form various openings in the memory array region 100 and the step region 200. The openings in the photoresist layer include a first elongated opening that extends laterally along a first horizontal direction hd1 through the entire lateral extent of the memory array region 100 and the step region 200 along the first horizontal direction hd1. This first elongated opening extends laterally between groups of memory opening-fill structures 58 and support pillar structures 20. Additionally, the openings in the photoresist layer may include second elongated openings that extend laterally along the first horizontal direction hd1 between clusters of memory opening-fill structures 58 spaced laterally along the first horizontal direction hd1 and positioned between adjacent pairs of first elongated openings. Each second elongated opening has a smaller lateral extent than the lateral extent of the memory array region 100 along the first horizontal direction hd1. Optionally, the openings in the photoresist layer may include discrete openings located between the end regions of an adjacent pair of second elongated openings.

[0160] Anisotropic etching can be performed to transfer a pattern in a photoresist layer through an underlying material portion comprising alternating stacks of {(132, 142), (232, 242)} and the upper portion of the in-process source-level material layer 10'. A back-side trench 79 can be formed beneath a first elongated opening in the photoresist layer, passing through a first contact-level dielectric layer 280, a second layer structure (232, 242, 270, 265), and a first layer structure (132, 142, 170, 165), and extending into the in-process source-level material layer 10'. The portion of the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the source-level material layer 10' below the first elongated opening in the photoresist layer can be removed to form a back-side trench 79. In one embodiment, the back-side trench 79 may be formed between groups of memory stack structures 55 laterally spaced along a second horizontal direction. The top surface of the source-level sacrificial layer 104 may be physically exposed at the bottom of each back-side trench 79. Since the back side trench 79 is formed separately from the trench trenches (179, 279), the portion of the alternating stack {(132, 232), (142, 242)} positioned between the trench trenches (179, 279) and the back side trench 79 does not have the opportunity to be laterally dumped into the back side trench 79, because the trench trenches (179, 279) are filled with dielectric trench structures (176, 276), which, together with the first contact level dielectric layer 280 covering it, hold the alternating stack {(132, 232), (142, 242)} in place after the formation of the back side trench 79.

[0161] Generally, alternating stacks {(132, 232), (142, 242)} of insulating layer 132 and sacrificial material layers (142, 242) can be formed over a semiconductor substrate 8 including a substrate semiconductor layer 9. The sacrificial material layers (142, 242) can include dielectric materials such as silicon nitride. The alternating stacks {(132, 232), (142, 242)} can be etched by performing an anisotropic etching process using a patterned mask layer, such as a photoresist layer. The alternating stacks {(132, 232), (142, 242)} can be divided by a back-side trench 79 into multiple alternating stacks {(132, 232), (142, 242)} of corresponding insulating layers (132, 232) and corresponding sacrificial material layers (142, 242).

[0162] A photoresist layer (not shown) may be applied over the exemplary structure and may be photolithographically patterned to form laterally extending linear openings that extend laterally along a first horizontal direction hd1 between adjacent clusters of the memory aperture filling structure 58. The patterning of the laterally extending linear openings may be passed through higher layers, including at least one insulating layer 232 and at least one sacrificial material layer 242, to form drain selection level trenches. The photoresist layer may be removed, for example, by ashing.

[0163] Dielectric filler material (such as undoped or doped silicate glass) can be deposited in the drain select level trench. Excess dielectric filler material can be removed from above the first contact level dielectric layer 280 using a planarization process. The portion of dielectric filler material filling the drain select level trench constitutes a drain select level isolation structure 72, which will be separated from the drain select electrode to be formed in a later step to replace one or more higher sacrificial material layers 242.

[0164] refer to Figure 15A In an isotropic etching process, an etchant is introduced into the back-side trench to selectively etch the material of the source-level sacrificial layer 104 for the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the first and second insulating cap layers (170, 270), the first contact-level dielectric layer 280, the higher sacrificial pad 105, and the lower sacrificial pad 103. For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or undoped amorphous silicon-germanium alloy, and if the higher and lower sacrificial pads (105, 103) comprise silicon oxide, a wet etching process (which uses thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH)) can be used to selectively remove the source-level sacrificial layer 104 for the higher and lower sacrificial pads (105, 103). A source cavity 109 can be formed in the volume from which the source-level sacrificial layer 104 is removed.

[0165] Wet etching chemicals such as thermal TMY and TMAH are selective for the doped semiconductor materials of the higher source layer semiconductor layer 116 and the lower source layer semiconductor layer 112. Therefore, using selective wet etching chemicals such as thermal TMY and TMAH in the wet etching process for forming the source cavity 109 provides a larger process window to resist variations in etching depth during the formation of the back-side trench 79. Specifically, in embodiments where the sidewalls of the higher source layer semiconductor layer 116 are physically exposed or where the surface of the lower source layer semiconductor layer 112 is physically exposed during the formation of the source cavity 109, incidental etching of the higher source layer semiconductor layer 116 and / or the lower source layer semiconductor layer 112 is minimized, and structural changes in the exemplary structure caused by unintended physical exposure of the surfaces of the higher source layer semiconductor layer 116 and / or the lower source layer semiconductor layer 112 during fabrication steps do not lead to device failure. Each of the memory aperture filling structures 58 may be physically exposed to the source cavity 109. Specifically, each of the memory opening filling structures 58 may include sidewalls and bottom surfaces physically exposed to the source cavity 109.

[0166] refer to Figure 15B A sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the layer level of the source cavity 109. Higher and lower sacrificial pads (105, 103) can be etched incidentally during the removal of portions of the memory film 50 positioned at the layer level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the layer levels of the source cavity 109 and the higher and lower sacrificial pads (105, 103). The top surface of the lower source layer semiconductor layer 112 and the bottom surface of the higher source layer semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 can be formed by selectively and isotropically etching the source sacrificial layer 104 and the bottom portion of each memory film 50 onto at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the higher source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0167] refer to Figure 15CA doped semiconductor material with a second conductivity type can be deposited on a physically exposed semiconductor surface around the source cavity 109. The second conductivity type is the opposite of a first conductivity type, which is the doped conductivity type of the vertical semiconductor channel 60. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surface of at least one source-level semiconductor layer (112, 116). For example, the physically exposed semiconductor surface may include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the higher source-level semiconductor layer 116.

[0168] In one embodiment, a second conductivity type doped semiconductor material can be deposited on a physically exposed semiconductor surface surrounding a source cavity 109 using a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas can simultaneously flow into a processing chamber including the exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the n-type dopant precursor gas may be phosphine, arsine, or antimony. In this case, the selective semiconductor deposition process grows in-situ doped semiconductor material from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114 that can contact the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the second conductivity type dopant in the deposited semiconductor material can be 1.0 × 10⁻⁶. 20 / cm 3 Up to 2.0×10 21 / cm 3 Such as 2.0×10 20 / cm 3 Up to 8.0×10 20 / cm 3 Within the range. The initially formed source contact layer 114 may consist essentially of semiconductor atoms of a second conductivity type and dopant atoms. Alternatively, the source contact layer 114 may be formed using at least one non-selective doping semiconductor material deposition process. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0169] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Therefore, the source-level sacrificial layer 104 can be replaced by the source contact layer 114.

[0170] A stack of layers including a lower source-level semiconductor layer 112, a source contact layer 114, and a higher source-level semiconductor layer 116 constitutes source regions (112, 114, 116). Source regions (112, 114, 116) are electrically connected to a first end (such as the bottom end) of each of the vertical semiconductor channels 60. A group of layers including source regions (112, 114, 116), a source-level insulating layer 117, and a source-selective conductive layer 118 constitutes source-level material layer 10, which is replaced by source-level material layer 10'.

[0171] refer to Figures 16A to 16D An oxidation process can be performed to convert physically exposed surface portions of a semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of the source contact layer 114 and the higher source level semiconductor layer 116 can be converted into a dielectric semiconductor oxide plate 122, and surface portions of the source selection level conductive layer 118 can be converted into annular dielectric semiconductor oxide spacers 124.

[0172] refer to Figures 17A to 17D The sacrificial material layers (142, 242) can be selectively removed from the insulating layers (132, 232), the first insulating cap layer 170 and the second insulating cap layer 270, the first contact-level dielectric layer 280, the source contact layer 114, the dielectric semiconductor oxide plate 122, and the annular dielectric semiconductor oxide spacer 124. For example, an isotropic etching process can be used to introduce an isotropic etchant into the back trench 79 to selectively etch the material of the sacrificial material layers (142, 242) for the insulating layers (132, 232), the first and second insulating cap layers (170, 270), the backward stepped dielectric material portions (165, 265), and the outermost layer of the memory film 50.

[0173] The isotropic etching process can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which the etchant is introduced in the vapor phase into the back-side trench 79. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. The duration of the isotropic etching process can be selected such that the entire sacrificial material layer (142, 242) is removed by the isotropic etching process.

[0174] Backside recesses (143, 243) can be formed in the volume from which sacrificial material layers (142, 242) are removed. The backside recesses (143, 243) include a first backside recess 143 that can be formed in the volume from which the first sacrificial material layer 142 is removed, and a second backside recess 243 that can be formed in the volume from which the second sacrificial material layer 242 is removed. Each backside recess (143, 243) can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess (143, 243) can be greater than the height of the corresponding backside recess (143, 243). Multiple backside recesses (143, 243) can be formed in the volume of material from which the sacrificial material layers (142, 242) are removed. Each of the back-side recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The back-side recesses (143, 243) may be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the back-side recesses (143, 243) may have a uniform height throughout.

[0175] The first lateral recess 143 may be laterally defined by the outer sidewall of the corresponding first dielectric trench structure 176. Therefore, the outer sidewall of the first dielectric trench structure 176 is physically exposed to the first lateral recess 143. The second lateral recess 243 may be laterally defined by the outer sidewall of the corresponding second dielectric trench structure 276. Therefore, the outer sidewall of the second dielectric trench structure 276 is physically exposed to the second lateral recess 243. The sidewall of the dielectric pillar structure 266 is physically exposed to the second lateral recess 243. A set of dielectric pillar structures 266 may laterally surround the second dielectric trench structure 276 and may be adjacent to the top portion of the underlying first dielectric trench structure 176.

[0176] refer to Figures 18A to 18EA back-side barrier dielectric layer (not shown) may optionally be deposited in the back-side recesses (143, 243) and the back-side trench 79, and over the first contact-level dielectric layer 280. The back-side barrier dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the back-side barrier dielectric layer may comprise aluminum oxide. The back-side barrier dielectric layer can be formed by conformal deposition processes such as atomic layer deposition or chemical vapor deposition. The thickness of the back-side barrier dielectric layer can range from 1 nm to 20 nm, such as from 2 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0177] At least one conductive material can be deposited in the plurality of back-side recesses (243, 243), on the sidewalls of the back-side trench 79, and over the first contact-level dielectric layer 280. The at least one conductive material can be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include elemental metals, intermetallic alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal-semiconductor alloys such as metal silicides, alloys thereof, and combinations or stacks thereof.

[0178] In one embodiment, at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or combinations thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, at least one conductive material for filling the backside recesses (143, 243) may be a combination of a titanium nitride layer and a tungsten filler material.

[0179] Conductive layers (146, 246) can be formed in the back-side recesses (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in a plurality of first back-side recesses 143, a plurality of second conductive layers 246 can be formed in a plurality of second back-side recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each back-side trench 79 and over the first contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 may include a corresponding conductive metal nitride pad and a corresponding conductive filler material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the back-side barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the back-side barrier dielectric layer and the second conductive layer 246. The dorsal cavity exists within the portion of each dorsal groove 79 that is not filled with a continuous layer of metallic material.

[0180] Residual conductive material can be removed from within the back trench 79. Specifically, the deposited metal material can be etched back from the sidewalls of each back trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first back trench 79 constitutes the first conductive layer 146. Each remaining portion of the deposited metal material in the second back trench 79 constitutes the second conductive layer 246. The sidewalls of the first conductive layer 146 and the second conductive layer can be physically exposed to the respective back trench 79.

[0181] Typically, the remainder of the first sacrificial material layer 142 located outside the first dielectric trench structure 176 is replaced by the first conductive layer 146, and the remainder of the second sacrificial material layer 242 located outside the second dielectric trench structure 276 is replaced by the second conductive layer 246. Each conductive layer (146, 246) may be a conductive sheet including an opening. A first subset of the openings through each conductive layer (146, 246) may be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) may be filled with a support pillar structure 20. Each of the memory stack structures 55 includes a vertically stacked memory elements located at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. Semiconductor devices in the underlying peripheral device region 700 may include word line switching devices configured to control a bias voltage to the corresponding word line. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory hierarchy component includes at least one alternating stack {(132, 146), (232, 246)} and a memory stack structure 55 extending vertically through the at least one alternating stack (132, 146, 232, 246).

[0182] refer to Figure 19A and Figure 19B Dielectric material can be deposited in the unfilled volume of the back-side trench 79. Excess dielectric material can be removed from above the top surface of the first contact-level dielectric layer 280 using a planarization process, which can employ a recess etching process or a chemical mechanical planarization process. Each remaining portion of the dielectric material filling the back-side trench 79 constitutes a dielectric wall structure 76. The dielectric wall structure 76 can extend laterally along a first horizontal direction hd1 and includes a dielectric material such as undoped silicate glass or doped silicate glass.

[0183] refer to Figures 20A to 20EThe through-memory interconnect via structures (588, 488) can be formed through a hierarchy of alternating first-layer stacks (132, 146) and alternating second-layer stacks (232, 246). The through-memory interconnect via structures (588, 488) include an array region through-memory interconnect via structure 588 and a peripheral through-memory interconnect via structure 488. In the region of each cell pattern UP, the array region through-memory interconnect via structure 588 can be formed through a first vertical stack of a first insulating plate 132' and a first dielectric material plate 142', and through a second vertical stack of a second insulating plate 232' and a second dielectric material plate 242'. The peripheral through-memory interconnect via structure 488 can be formed through a backward-stepped dielectric material portion (165, 265). Each of the array region through-memory level interconnect via structure 588 and the peripheral through-memory level interconnect via structure 488 may be formed on a corresponding one of the landing pad level metal wire structures 788, which are subsets of the lower-level metal interconnect structures 780 embedded in the lower-level dielectric material layer 760. Each array region through-memory level interconnect via structure 588 is laterally surrounded by a first dielectric trench structure 176 and a second dielectric trench structure 276, and may extend vertically through the vertical levels of each insulating layer (132, 232) and conductive layer (146, 246).

[0184] Subsequently, higher-level dielectric material layers (282, 290) and higher-level metal interconnect structures (88, 86, 286, 98, 96) can be formed. The higher-level dielectric material layers (282, 290) may include a second contact-level dielectric layer 282 and a first line-level dielectric layer 290. The higher-level metal interconnect structures (88, 86, 286, 98, 96) may include a drain contact via structure 88, a word line contact via structure 86, a connection via structure 286, a bit line 98, and a connection metal line 96. The drain contact via structure 88 extends through the first contact-level dielectric layer 280 and the second contact-level dielectric layer 282 and contacts a corresponding drain region 63. Word line layer contact via structure 86 extends through the first contact level dielectric layer 280, the second contact level dielectric layer 282, the second backward stepped dielectric portion 265, and optionally through the first backward stepped dielectric portion 165, and contacts a corresponding one of the conductive layers (e.g., word lines) (146, 246). Connection via structure 286 extends through the second contact level dielectric layer 282 and contacts the top surface of a corresponding one of the array region through-memory level interconnect via structure 588 and the peripheral through-memory level interconnect via structure 488. Therefore, each of the array region through-memory level interconnect via structure 588 and the peripheral through-memory level interconnect via structure 488 is electrically connectable to the bottom surface of a higher-level metal interconnect structure, such as the bottom surface of the connection metal line 96. Bit line 98 is embedded in the first line level dielectric layer 290 and contacts a corresponding subset of the drain contact via structure 88. Connecting metal lines 96 are embedded in the first-line level dielectric layer 290 and are corresponding subsets of contact via structures (such as word line layer contact via structure 86 and / or connecting via structure 286). Additional higher-level dielectric material layers (not shown) and additional higher-level metal interconnect structures (not shown) may be formed as needed.

[0185] Typically, at least one through-memory level interconnect via structure (such as at least one array region through-memory level interconnect via structure 588) may be formed through a first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142', and through a second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242' covering them. The at least one through-memory level interconnect via structure (such as at least one array region through-memory level interconnect via structure 588) may be formed through a volume laterally surrounded by a combination of the first dielectric trench structure 176 and the plurality of dielectric pillar structures 266 adjacent thereto, and directly positioned on a corresponding one of the lower-level metal interconnect structures 780 (such as the landing pad level metal wire structure 788). Each through-memory level interconnect via structure (588, 488) extends vertically from at least a horizontal plane of the top surface including the second layer of alternating stacks (232, 246) to a metal interconnect structure (such as landing pad level metal wire structure 788) below the horizontal plane of the bottom surface including semiconductor material layers (such as source contact layer 114).

[0186] Referring to all the accompanying drawings and various embodiments of the present disclosure, a three-dimensional memory device is provided, comprising: a first alternating stack of a first insulating layer 132 and a first conductive layer 146 positioned above a semiconductor material layer (such as a source contact layer 114); a second alternating stack of a second insulating layer 232 and a second conductive layer 246 positioned above the first alternating stack (132, 146); a memory stack structure 55 extending vertically through the second alternating stack (232, 246) and the first alternating stack (132, 146); a first dielectric trench structure 176 extending vertically through the first alternating stack (132, 146) and laterally around a first vertical alternating sequence of a first insulating plate 132' and a first dielectric material plate 142'; and a plurality of dielectric pillar structures 266 extending vertically through the second alternating stack (232, 146). 246) and contact the top surface of the first dielectric trench structure 176; and at least one through-memory level interconnect via structure (such as at least one array region through-memory level interconnect via structure 588), which at least one through-memory level interconnect via structure extends vertically from a horizontal plane including the top surface of the second alternating stack (232, 246), through a first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142', until it extends to a corresponding metal interconnect structure (such as a landing pad level metal wire structure 788) below the horizontal plane including the bottom surface of the semiconductor material layer (such as the source contact layer 114).

[0187] In one embodiment, the combination of the first dielectric trench structure 176 and the plurality of dielectric pillar structures 266 consists of a single, continuously extending dielectric material portion (such as an undoped silicate glass portion or a doped silicate glass portion) having a uniform material composition.

[0188] In one embodiment, the second dielectric trench structure 276 extends vertically through the second alternating stack (232, 246), laterally surrounds the second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242', and covers the first vertical alternating sequence of the first insulating plate 132' and the first dielectric material plate 142'. In one embodiment, the bottom periphery of the outer sidewall of the second dielectric trench structure 276 is laterally recessed inward relative to the top periphery of the inner sidewall of the first dielectric trench structure 176. In one embodiment, the at least one through-memory level interconnect structure (such as at least one array region through-memory level interconnect structure 588) extends vertically through and directly contacts the second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242'.

[0189] In one embodiment, the outer sidewall of the first dielectric trench structure 176 contacts the first insulating layer 132 and the first conductive layer 146 of the first alternating stacked layers (132, 146), or a back-side barrier dielectric layer embedded in the first conductive layer 146. The outer sidewall of the second dielectric trench structure 276 contacts the second insulating layer 232 and the second conductive layer 246 of the second alternating stacked layers (232, 246), or a back-side barrier dielectric layer embedded in the second conductive layer 246.

[0190] In one embodiment, each of the first insulating plates 132' is vertically spaced from the top surface of a semiconductor material layer (e.g., source contact layer 114), the vertical distance of which is the same as the vertical distance from the corresponding first insulating layer 132 in the alternating stack of first layers (132, 146) to the top surface of the semiconductor material layer; and each of the second insulating plates 232' is vertically spaced from the top surface of the semiconductor material layer, the vertical distance of which is the same as the vertical distance from the corresponding second insulating layer 232 in the alternating stack of second layers (232, 246) to the top surface of the semiconductor material layer.

[0191] In one embodiment, the bottom surface of the second dielectric trench structure 276 is located above or at a horizontal plane including the topmost surface of the first alternating stack (132, 246), or extends into the first alternating stack (132, 146) and is located above at least one layer within the first alternating stack (132, 146).

[0192] In one embodiment, a semiconductor substrate 8 is located beneath a semiconductor material layer (such as source contact layer 114), and a semiconductor device 710 is positioned on the semiconductor substrate 8. A lower-level dielectric material layer 760 covers the semiconductor device 710 and is located beneath the semiconductor material layer (such as source contact layer 114). A lower-level metal interconnect structure 780 may be embedded in the lower-level dielectric material layer 760. Each of the at least one through-memory interconnect via structure (such as at least one array region through-memory interconnect via structure 588) contacts a corresponding one of the lower-level metal interconnect structures 780. In one embodiment, the semiconductor material layer includes an opening in a region beneath a first vertical alternation sequence of the first insulating plate 132' and the first dielectric material plate 142', and the at least one through-memory interconnect via structure extends through the opening in the semiconductor material layer.

[0193] In one embodiment, the first alternating stack (132, 146) and the second alternating stack (232, 246) extend laterally along a first horizontal direction hd1 and have a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; and the three-dimensional memory device includes a pair of back-side trench-filled structures (such as dielectric wall structures 76) that extend laterally along the first horizontal direction hd1, are laterally spaced from each other along the second horizontal direction hd2, and contact the respective sidewalls of the first alternating stack (132, 146) and the second alternating stack (232, 246).

[0194] In one embodiment, each of the memory stack structure 55 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60; and each vertical semiconductor channel 60 contacts a semiconductor material layer (such as a source contact layer 114).

[0195] In one embodiment, the three-dimensional memory device may include a support pillar structure 20 comprising and / or substantially composed of the same dielectric material as the first dielectric trench structure 176 and the plurality of dielectric pillar structures 266. The support pillar structure 20 extends vertically through the first alternating stack (132, 146) and the second alternating stack (232, 246).

[0196] In one embodiment, a first subset of the memory stack structure 55 is located in a first portion of the memory array region 100, wherein each of a first alternating stack (132, 146) and each of a second alternating stack (232, 246) is present, and a second subset of the memory stack structure 55 is located in a second portion of the memory array region 100, wherein each of the first alternating stack (132, 146) and each of the second alternating stack (232, 246) is present. The second portion of the memory array region 100 is laterally spaced from the first portion of the memory array region 100 along a first horizontal direction hd1. In one embodiment, a first dielectric trench structure 176, the plurality of dielectric pillar structures 266, the at least one through-memory level interconnect structure (such as at least one array region through-memory level interconnect structure 588), and a support pillar structure 20 are located in the intermediate portion of the memory array region 100 between the first portion and the second portion of the memory array region 100.

[0197] Line trenches, such as first-layer trench 179 and second-layer trench 279, can be formed with lateral wobbling in a horizontal direction perpendicular to the longitudinal direction of the trench. This lateral wobbling can be caused by instability in anisotropic etching processes that etch through dielectric material layers, such as alternating stacks of a first insulating layer 132 and a first sacrificial material layer 142, and alternating stacks of a second insulating layer 232 and a second sacrificial material layer 242. In contrast, isolation cavities, such as pillar cavities 269, are formed with straight profiles. By employing pillar cavities 269 connected to the sacrificial trench fill structure 178, the sacrificial trench fill structure 178 is replaced by a corresponding first dielectric trench structure 176 with enhanced reliability. Lateral wobbling of the bottom portion of the second-layer trench 279 will not affect the function of the three-dimensional semiconductor device because the second-layer trench 279 is not required to expose the underlying sacrificial trench fill structure 178 for removal. The second dielectric trench structure 276 can laterally surround the corresponding second vertical alternating sequence of the second insulating plate 232' and the second dielectric material plate 242', regardless of any lateral swing therein.

[0198] In an alternative implementation, if there is no lateral swaying in the trenches (such as the first trench trench 179 and the second trench trench 279), it can be omitted. Figures 7A to 7C The formation of the column cavity 269, and the second layer of trench groove 279 can be directly formed on the underlying sacrificial trench groove filling structure 178, which fills the first layer of trench groove 179. Then... Figures 8A to 8DIn the illustrated step, the sacrificial trench filling structure 178 is removed via the second trench 279. The number of process steps is reduced by forming the first and second trenches (179, 279) and the support opening 19 in the same etching step, and by filling at least one of the first and second trenches (179, 279) and the support opening 19 with the same dielectric material during the same deposition step to form a dielectric trench structure and a support pillar structure 20. Furthermore, the possibility of alternating stackings dumping into the back trench 79 is reduced by forming the back trench 79 after forming the dielectric trench structure (176, 276).

[0199] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device comprising: a first alternating stack of first insulating layers and first conductive layers, the first alternating stack positioned above a layer of semiconductor material; a second alternating stack of second insulating layers and second conductive layers, the second alternating stack positioned above the first alternating stack; memory stack structures vertically extending through the second alternating stack and the first alternating stack; a first dielectric trench structure vertically extending through the first alternating stack and laterally surrounding a first vertically alternating sequence of first insulative plates and first dielectric material plates; a plurality of dielectric pillar structures vertically extending through the second alternating stack and contacting a top surface of the first dielectric trench structure; and at least one through-memory-level interconnect via structure vertically extending from at least a horizontal plane comprising a top surface of the second alternating stack, through the first vertically alternating sequence of first insulative plates and first dielectric material plates, to a respective metal interconnect structure extending below a horizontal plane comprising a bottom surface of the layer of semiconductor material.

2. The three-dimensional memory device of Claim 1, wherein a combination of the first dielectric trench structure and the plurality of dielectric pillar structures is comprised of a single continuously extending dielectric material portion having a uniform material composition throughout.

3. The three-dimensional memory device of Claim 1, further comprising a second dielectric trench structure vertically extending through the second alternating stack and laterally surrounding a second vertically alternating sequence of second insulative plates and second dielectric material plates, and overlying the first vertically alternating sequence of first insulative plates and first dielectric material plates.

4. The three-dimensional memory device of Claim 3, wherein a bottom periphery of an outer sidewall of the second dielectric trench structure is laterally recessed inward relative to a top periphery of an inner sidewall of the first dielectric trench structure.

5. The three-dimensional memory device of Claim 3, wherein the at least one through-memory-level interconnect via structure vertically extends through the second vertically alternating sequence of second insulative plates and second dielectric material plates.

6. The three-dimensional memory device of Claim 3, wherein: an outer sidewall of the first dielectric trench structure contacts the first insulating layers of the first alternating stack; and an outer sidewall of the second dielectric trench structure contacts the second insulating layers of the second alternating stack.

7. The three-dimensional memory device of Claim 3, wherein: each of the first insulative plates is vertically spaced apart from a top surface of the layer of semiconductor material by a vertical distance that is the same as a vertical distance of a respective first insulating layer in the first alternating stack to the top surface of the layer of semiconductor material; and ​ ​ each of the second insulative plates is vertically spaced apart from the top surface of the layer of semiconductor material by a vertical distance that is the same as a vertical distance of a respective second insulative layer in the second-tier alternating stack to the top surface of the layer of semiconductor material.

8. The three-dimensional memory device of claim 3, wherein a bottom surface of the second dielectric trench structure is positioned above a horizontal plane that includes a topmost surface of the first-tier alternating stack, or is positioned at the horizontal plane that includes the topmost surface of the first-tier alternating stack, or extends into the first-tier alternating stack and is positioned above at least one layer within the first-tier alternating stack.

9. The three-dimensional memory device of claim 1, further comprising: a semiconductor substrate that is located below the layer of semiconductor material; a semiconductor device that is positioned on the semiconductor substrate; a lower-level dielectric material layer that overlies the semiconductor device and is located below the layer of semiconductor material; and a lower-level metal interconnect structure that is embedded in the lower-level dielectric material layer, wherein each of the at least one through-memory-level interconnect via structure contacts a respective one of the lower-level metal interconnect structure.

10. The three-dimensional memory device of claim 9, wherein: the layer of semiconductor material includes an opening in an area below the first vertical alternating sequence of first insulative plates and first dielectric material plates; and the at least one through-memory-level interconnect via structure extends through the opening in the layer of semiconductor material.

11. The three-dimensional memory device of claim 1, wherein: the first-tier alternating stack and the second-tier alternating stack laterally extend along a first horizontal direction and have a uniform width along a second horizontal direction that is perpendicular to the first horizontal direction; and the three-dimensional memory device includes a pair of backside trench fill structures that laterally extend along the first horizontal direction, are laterally spaced apart from one another along the second horizontal direction, and contact respective sidewalls of the first-tier alternating stack and the second-tier alternating stack.

12. The three-dimensional memory device of claim 1, wherein: each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel; and each of the vertical semiconductor channels contacts the layer of semiconductor material.

13. The three-dimensional memory device of claim 1, further comprising a support pillar structure that includes the same dielectric material as the first dielectric trench structure and the plurality of dielectric pillar structures, and that vertically extends through the first-tier alternating stack and the second-tier alternating stack.

14. The three-dimensional memory device of claim 13, wherein: ​ a first subset of the memory stack structures is positioned in a first portion of the memory array region in which each layer of the first alternating stack of layers and each layer of the second alternating stack of layers is present; a second subset of the memory stack structures is positioned in a second portion of the memory array region in which each layer of the first alternating stack of layers and each layer of the second alternating stack of layers is present; the second portion of the memory array region is laterally spaced apart from the first portion of the memory array region along a first horizontal direction; and the first dielectric trench structure, the plurality of dielectric pillar structures, the at least one through-memory-level interconnect via structure, and the support pillar structure are positioned in an intermediate portion of the memory array region that is positioned between the first portion of the memory array region and the second portion of the memory array region.

15. A method of forming a three-dimensional memory device, comprising: forming a first alternating stack of a first insulating layer and a first sacrificial material layer over a semiconductor material layer; forming, using a same etching step, a first layer of memory openings, a first layer of support openings, and a first layer of trench trenches through the first alternating stack of layers; forming, during a same deposition step, a first dielectric trench structure in a first layer of trench trenches and a first support pillar structure in the first layer of support openings; forming memory stack structures in the first layer of memory openings; after forming the first dielectric trench structure, forming a backside trench through the first alternating stack of layers; replacing portions of the first sacrificial material layer with a first conductive layer through the backside trench, wherein remaining portions of the first insulating layer and the first sacrificial material layer within the first layer of trench trenches comprise a first vertically alternating sequence of first insulating slabs and first dielectric material slabs; and forming at least one through-memory-level interconnect via structure through the first vertically alternating sequence of first insulating slabs and first dielectric material slabs; and wherein the method further comprises: forming a sacrificial trench trench fill structure in the first layer of trench trenches; forming a second alternating stack of a second insulating layer and a second sacrificial material layer over the first alternating stack of layers; forming a plurality of pillar cavities through the second alternating stack of layers over the sacrificial trench trench fill structure; removing the sacrificial trench trench fill structure through the plurality of pillar cavities; forming a combination of the first dielectric trench structure and a plurality of dielectric pillar structures, wherein the first dielectric trench structure fills a volume formed by removing the sacrificial trench trench fill structure, and the plurality of dielectric pillar structures fill the plurality of pillar cavities.

16. The method of claim 15, wherein: the memory stack structures are formed through the second alternating stack of layers and the first alternating stack of layers; the first sacrificial material layer comprises a first dielectric material; the first insulating slabs comprise patterned portions of the first insulating layer; the first dielectric material slabs comprise patterned portions of the first sacrificial material layer; and the first dielectric material slabs comprise patterned portions of the first sacrificial material layer; and The at least one through-memory-level interconnect via structure extends vertically at least from a horizontal plane comprising a top surface of the second alternating stack down to a metal interconnect structure below a horizontal plane comprising a bottom surface of the layer of semiconductor material.

17. The method of claim 15, further comprising: forming a second-tier moat cavity through the second-tier alternating stack, wherein the second-tier moat cavity overlies the first vertical alternating sequence of first insulative plates and first dielectric material plates, and wherein a bottom periphery of an outer sidewall of the second-tier moat cavity is laterally recessed inward relative to a top periphery of an inner sidewall of the sacrificial moat trench fill structure; and forming a second dielectric moat structure in the second-tier moat cavity.

18. The method of claim 17, wherein: the second-tier moat cavity laterally surrounds a second vertical alternating sequence of second insulative plates and second dielectric material plates, and overlies the first vertical alternating sequence of first insulative plates and first dielectric material plates, and the at least one through-memory-level interconnect via structure extends through the first vertical alternating sequence of first insulative plates and first dielectric material plates, and through the second vertical alternating sequence of second insulative plates and the second dielectric material plates.

19. The method of claim 15, further comprising: forming a semiconductor device on a semiconductor substrate; and forming lower-level metal interconnect structures embedded in a lower-level dielectric material layer above the semiconductor device, wherein the layer of semiconductor material, the first-tier alternating stack, and the second-tier alternating stack are formed above the lower-level metal interconnect structures; wherein the at least one through-memory-level interconnect via structure passes through a volume laterally surrounded by the combination of the first dielectric moat structure and the plurality of dielectric pillar structures, wherein the at least one through-memory-level interconnect via structure is positioned directly on a respective one of the lower-level metal interconnect structures.

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