Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly having an active region including a semiconductor material. The active region includes a first, a second, and a third source / drain region within the semiconductor material, a first channel region within the semiconductor material and between the first source / drain region and the second source / drain region, and a second channel region within the semiconductor material and between the second source / drain region and the third source / drain region. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source / drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage element is electrically coupled with the first source / drain region. A second storage element is electrically coupled with the third source / drain region. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Related patent data

[0002] This application is related to U.S. Patent Application Serial No. 16 / 666,709, filed October 29, 2019, entitled “Integrated Assemblies, and Methods of Forming Integrated Assemblies,” which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Integrated assemblies (e.g., integrated memories) and methods of forming integrated assemblies. BACKGROUND

[0004] Semiconductor materials can be incorporated into integrated assemblies. For example, semiconductor materials can be used as active regions, including channel regions and / or source / drain regions of transistors. The transistors can be used as access devices in memory arrays or in other applications.

[0005] It would be desirable to develop improved active region arrangements suitable for utilization in integrated assemblies, and to develop integrated assemblies that utilize the improved arrangements. It would also be desirable to develop improved memory cell configurations and improved memory array configurations. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 and 1A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage of an example method for forming an example memory array. Figure 1A The cross-sectional view of Figure 1 is along line A-A of

[0007] Figure 2 and 2A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage following Figure 1 and 1A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage following Figure 1 and 1A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage following Figure 2A The cross-sectional view of Figure 2 is along line A-A of

[0008] Figure 3 and 3A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage following Figure 2 and 2A are diagrammatic top views and diagrammatic cross-sectional side views, respectively, of regions of an example integrated assembly at an example process stage following Figure 1 and 1AThe example integrates the area of ​​the assembly with a top view and a cross-sectional side view. Figure 3A The cross-sectional view is along Figure 3 Line AA.

[0009] Figure 4 and 4A They are respectively in the following Figure 3 and 3A Instances of process phases Figure 1 and 1A The example integrates the area of ​​the assembly with a top view and a cross-sectional side view. Figure 4A The cross-sectional view is along Figure 4 Line AA.

[0010] Figure 5 and 5A They are respectively in the following Figure 4 and 4A Instances of process phases Figure 1 and 1A The example integrates the area of ​​the assembly with a top view and a cross-sectional side view. Figure 5A The cross-sectional view is along Figure 5 Line AA.

[0011] Figure 6 and 6A They are respectively in the following Figure 5 and 5A Instances of process phases Figure 1 and 1A The example integrates the area of ​​the assembly with a top view and a cross-sectional side view. Figure 6A The cross-sectional view is along Figure 6 Line AA.

[0012] Figure 7 and 7A They are respectively in the following Figure 6 and 6A Instances of process phases Figure 1 and 1A The example integrates the area of ​​the assembly with a top view and a cross-sectional side view. Figure 7A The cross-sectional view is along Figure 7 Line AA.

[0013] Figure 8 , 8A And 8B is following Figure 7 and 7A Instances of process phases Figure 1 and 1A A top view of the area of ​​an example integrated assembly ( Figure 8 ) and solution cross-sectional side view (Figure 8A and 8B ). Figure 8A and 8B are cross-sectional views taken along lines A-A and B-B, respectively, of Figure 8 .

[0014] Figure 9 , 9A and 9B are example process stages following Figure 8 , 8A and 8B. Figure 1 and 1A are diagrammatic top views of a region of an example integrated assembly of Figure 9 ) and diagrammatic cross-sectional side views of Figure 9A and 9B . Figure 9A and 9B are cross-sectional views taken along lines A-A and B-B, respectively, of Figure 9 .

[0015] Figure 10 , 10A and 10B are example process stages following Figure 9 , 9A and 9B. Figure 1 and 1A are diagrammatic top views of a region of an example integrated assembly of Figure 10 ) and diagrammatic cross-sectional side views of Figure 10A and 10B . Figure 10A and 10B are cross-sectional views taken along lines A-A and B-B, respectively, of Figure 10 .

[0016] Figure 11 , 11A and 11C are example process stages following Figure 10 , 10A and 10B. Figure 1 and 1A are diagrammatic top views of a region of an example integrated assembly of Figure 11 ) and diagrammatic cross-sectional side views of Figure 11A , 11B and 11C. Figure 11A , 11B and 11C are cross-sectional views taken along lines A-A, B-B, and C-C, respectively, of Figure 11 . Figure 11C are to different scales than Figure 11 .

[0017] Figure 12 is a diagrammatic top view of a region of an example integrated assembly of Figure 11 incorporated into an example memory array.

[0018] Figure 13 is a replacement for Figure 11C diagrammatic cross-sectional side view of a region of an example integrated assembly of the region shown in

[0019] Figure 14 is a replacement for Figure 11A diagrammatic cross-sectional side view of a region of an example integrated assembly of the region shown in

[0020] Figure 15 is a diagrammatic cross-sectional side view of an assembly including a vertical stack of levels. DETAILED DESCRIPTION

[0021] Some embodiments include a memory architecture having memory active regions supported above digit lines (i.e., sense lines, bit lines, etc.) and having word lines (i.e., access lines, etc.) extending across the digit lines and the active regions. The memory active regions can be incorporated into memory cells, and each of the memory cells can be uniquely addressed with one of the digit lines and one of the word lines. Some embodiments include a memory architecture in which the memory active regions include a semiconductor material that includes at least one element selected from Group 13 of the Periodic Table (e.g., gallium (Ga), indium (In), thallium (Tl), etc.). The memory active regions can be above the digit lines. The digit lines can extend horizontally, and the memory active regions can also extend horizontally. Reference is made to Figures 1 to 15 Example embodiments are described.

[0022] Figures 1 to 12 An example method of forming an example memory array is described.

[0023] Reference is made to Figure 1 and 1A The integrated assembly 10 includes a block 14 above a support insulative structure 16.

[0024] The block 14 includes a material (block material) 15. This material can include any suitable composition; and in some embodiments can include one or more of silicon dioxide, low-k dielectric material, etc. The term "low-k" means a dielectric constant that is less than the dielectric constant typically associated with silicon dioxide (i.e., less than about 3.9). Example low-k materials are porous silicon dioxide, carbon-doped silicon dioxide, boron-doped silicon dioxide, etc.

[0025] The insulative structure 16 includes an insulative material 17. This insulative material can include any suitable composition; and in some embodiments can include one or more of silicon nitride, silicon dioxide, low-k dielectric material, high-k dielectric material, etc., consist essentially of or consist of one or more thereof.

[0026] The insulating structure 16 is supported by the underlying substrate 12. The substrate 12 may include semiconductor materials; and may include, for example, monocrystalline silicon, be substantially composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconducting materials, including (but not limited to) bulk semiconducting materials, such as semiconducting wafers (alone or in a combination including other materials) and layers of semiconducting materials (alone or in a combination including other materials). The term "substrate" refers to any support structure including (but not limited to) the semiconductor substrate described above. In some applications, the substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0027] A gap is provided between the substrate 12 and the insulating material 16 to indicate that other materials, components, etc., may be provided between the substrate 12 and the insulating material 16. In some embodiments, the insulating material 16 may be provided as the upper surface directly abutting the substrate 12.

[0028] refer to Figure 2 and 2A Block 14 ( Figure 1 and 1A The pattern is formed into a plurality of linear features 18, wherein such linear features are spaced apart from each other by intermediate gaps 20. The linear features extend along a first direction, which is relative to... Figure 2 The top view is indicated in the y-axis direction.

[0029] refer to Figure 3 and 3A Conductive digital line material 22 is provided within the gap 20. The digital line material within the gap is patterned into digital lines 24. Such digital lines extend along a first direction (y-axis direction) defined by the gap 20. In some embodiments, the digital line material 22 may be formed over material 15 and then removed from over material 15 using planarization (e.g., chemical mechanical treatment) or other suitable treatments. The process of forming trenches, subsequently forming material within the trenches to the level of overfilling the trenches, and then removing excess material using planarization or other suitable treatments, can be referred to as damascene processing.

[0030] The digital line 24 can be recessed into the gap 20 using any suitable process; including, for example, selective etching chemistry of the conductive material 22 relative to the material 15.

[0031] The number lines 24 are spaced apart from each other, and specifically along... Figure 3 The x-axis directions are spaced apart from each other.

[0032] The digit line material 22 can comprise any suitable electrically conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or electrically conductive doped semiconductor materials (e.g., electrically conductive doped silicon, electrically conductive doped germanium, etc.). In some embodiments, the digit line material 22 can be a metal-containing material. Such a metal-containing material can comprise any suitable composition; for example, one or more of titanium, tungsten, titanium nitride, tungsten nitride, tantalum nitride, etc.

[0033] Referring to Figure 4 and 4A , an electrically conductive interconnect material 26 is formed within the gap 20 (over the digit line 24). The electrically conductive interconnect material 26 can be formed within the gap 20 using a damascene process. Figure 3 and 3A The electrically conductive interconnect material 26 can be patterned to form an electrically conductive contact (interconnect) 28. The electrically conductive interconnect material 26 can be patterned using any suitable process. For example, a patterned mask (e.g., a photolithographically patterned photoresist mask) can be used to protect the material 26 within the location of the electrically conductive contact 28, and then an etch selective to the underlying digit line material 22 can be used to remove unprotected segments of the material 26. Subsequently, the protective mask can be removed to leave the electrically conductive contact 28.

[0034] The electrically conductive interconnect material 26 can comprise any suitable electrically conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or electrically conductive doped semiconductor materials (e.g., electrically conductive doped silicon, electrically conductive doped germanium, etc.). In some embodiments, the electrically conductive interconnect material 26 can be a metal-containing material. Such a metal-containing material can comprise any suitable composition; for example, one or more of titanium, tungsten, titanium nitride, tungsten nitride, tantalum nitride, etc.

[0035] The electrically conductive interconnect material 26 can comprise the same composition as the digit line material 22, or can comprise a different composition relative to the digit line material. In some embodiments, both the electrically conductive interconnect material 26 and the digit line material 22 can be metal-containing materials, but can be different compositions from one another. For example, the electrically conductive interconnect material 26 can comprise a metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), and the digit line material 22 can comprise, consist essentially of, or consist of tungsten. In some embodiments, the digit line material 22 can be referred to as a first electrically conductive material, and the interconnect material 26 can be referred to as a second electrically conductive material.

[0036] Referring to Figure 5 and 5A , a region of the electrically conductive interconnect material 26 is removed to pattern the remaining portion of the electrically conductive interconnect material 26 as the electrically conductive contact (interconnect) 28. The electrically conductive interconnect material 26 can be patterned using any suitable process. For example, a patterned mask (e.g., a photolithographically patterned photoresist mask) can be used to protect the material 26 within the location of the electrically conductive contact 28, and then an etch selective to the underlying digit line material 22 can be used to remove unprotected segments of the material 26. Subsequently, the protective mask can be removed to leave the electrically conductive contact 28. Figure 5 and5A The configuration shown in the figure. In some embodiments, the conductive interconnect material 26 may advantageously comprise a composition different from that of the digital line material 22, such that the conductive interconnect material 26 can be selectively removed relative to the digital line material 22.

[0037] Contacts 28 are spaced apart from each other and electrically coupled to digital lines 24. In the illustrated embodiment, contacts 28 directly abut against digital lines 24. In some embodiments, digital lines 24 may be considered to extend substantially horizontally, and contacts 28 may be considered to extend substantially vertically (i.e., upwardly) from digital lines. The term “substantially horizontal” means horizontal within reasonable manufacturing and measurement tolerances, and the term “substantially vertical” means vertical within reasonable manufacturing and measurement tolerances. In some embodiments, substrate 12 may have a flat, horizontal upper surface (as shown), the term “substantially horizontal” may mean within 10° parallel to the flat upper surface, and the term “substantially vertical” may mean within 10° orthogonal to the flat upper surface.

[0038] A segment of conductive material 26 is removed from above the digital line 24, leaving a gap 30 above the area of ​​the digital line.

[0039] refer to Figure 6 and 6A Insulating material 32 is formed in gap 30 ( Figure 5 and 5A The insulating material 32 may include any suitable composition; and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0040] The insulating material 32 may initially be formed to extend across material 15 and within gap 30; and may then be removed from above material 15 by a planarization process (e.g., chemical mechanical polishing). The planarization process forms a planarized surface 31 extending across materials 15, 26 and 32.

[0041] refer to Figure 7 and 7A Semiconductor material 34 is formed on the planarized surface 31, and specifically on the spaced-apart contacts 28.

[0042] Semiconductor material 34 may comprise any suitable composition; and in some embodiments, it may comprise a material comprising at least one element selected from Group 13 of the periodic table (e.g., one or more of aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), substantially composed of or composed of said material. Semiconductor material 34 may further comprise at least one element selected from Group 15 of the periodic table (e.g., one or more of phosphorus (P), arsenic (As), and antimony (Sb). For example, semiconductor material may comprise one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, and GaInP; wherein the chemical formula indicates the major component rather than a specific stoichiometry.

[0043] In some embodiments, the semiconductor material 34 may include at least one element selected from Group 13 of the periodic table, and at least one element selected from Group 16 of the periodic table (e.g., one or more of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). In some embodiments, the semiconductor material 34 may include one or more elements selected from Group 14 of the periodic table (e.g., one or more of silicon, germanium, etc.).

[0044] In some embodiments, semiconductor material 34 may include a combination of a metal selected from the group consisting of aluminum, gallium, indium, thallium, tin, cadmium, zinc and mixtures thereof, and one or more of oxygen, sulfur, selenium and tellurium.

[0045] refer to Figure 8 , 8A And 8B, semiconductor material 34 is patterned into active region 36. Such active region can be considered to extend horizontally (or at least substantially horizontally) along the planarized upper surface 31. Contact 28 in Figure 8 The image is shown in a dashed view to indicate that such contacts are located below the active area 36. The insulating material below the active area 36 is generally indicated as "15 / 32" to indicate that this insulating material includes both material 15 and material 32. Figure 8 The insulating material 32 is not explicitly shown in the figure, so the focus of this figure is on the active region 36 and the general layout of such active regions.

[0046] One of the active regions 36 is designated as 36a, so that it can be distinguished from the other active regions described below. All active regions are substantially identical to each other, where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances.

[0047] Active regions 36 correspond one-to-one with contacts 28. Each active region has a central region 38 above its counterpart in contact 28 and a pair of remote regions 40 and 42 horizontally offset from the central region. Regions 38, 40, and 42 are marked only relative to active regions 36a, but exist relative to all active regions 36. In some embodiments, regions 38, 40, and 42 may correspond to source / drain regions and are therefore doped with suitable conductivity-enhancing dopants. Doping of regions 38, 40, and 42 may be performed at any suitable process stage; including, for example, after patterning of the active regions 36 and / or during patterning of word lines (…). Figure 10 , 10A One or more implantations are performed after (and 10B). Suitable dopants may include one or both of sulfur and selenium in applications in which the semiconductor material 34 includes elements from Group 13 and Group 15 of the periodic table; and may include one or both of nitrogen and fluorine in applications in which the semiconductor material 34 includes elements from Group 13 and Group 16 of the periodic table.

[0048] In some embodiments, the central source / drain region 38 may be referred to as the internal source / drain region, and the remote source / drain regions 40 and 42 may be referred to as external source / drain regions. In some embodiments, the source / drain regions 40, 38, and 42 may be referred to as the first, second, and third source / drain regions, respectively.

[0049] The internal source / drain region 38 (or alternatively, the second source / drain region 38) is electrically coupled to the underlying digital line 24 via one of the conductive interconnects 28. In the illustrated embodiment, the conductive interconnect 28 directly contacts both the central source / drain region 38 and the digital line 24.

[0050] Region 44 is located between source / drain regions 38 and 40, and another region 46 is located between source / drain regions 38 and 42. Regions 44 and 46 ultimately correspond to the channel regions and can be doped to appropriate levels with suitable dopants to achieve the desired threshold voltage. Doping of regions 44 and 46, if any, can be performed at any suitable process stage. Regions 44 and 46 can be referred to as the first channel region and the second channel region, respectively.

[0051] refer to Figure 9 , 9A In 9B, a gate dielectric material (also referred to as dielectric material or insulating material) 48 is formed above and between the active regions 36, a conductive gate material 50 is formed above the gate dielectric material 48, and an insulating covering material 52 is formed above the gate material 50.

[0052] The gate dielectric material 48 may include any suitable composition; and in some embodiments may include silicon dioxide, consisting essentially of silicon dioxide or composed of silicon dioxide.

[0053] The conductive gate material 50 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive gate material 50 may include one or more metal-containing materials; for example, one or more of tungsten, titanium nitride, tantalum nitride, tungsten nitride, etc.

[0054] The insulating covering material 52 may include any suitable composition; and in some embodiments may include one or both of silicon dioxide and silicon nitride, substantially composed of one or both of them, or composed of one or both of them.

[0055] refer to Figure 10 , 10A And 10B, conductive material 50 is patterned into letter lines 54. The letter lines are along the second direction ( Figure 10 The second direction of the word line extends along the x-axis direction. The second direction of the word line intersects the first direction of the number line (where this first direction is along, for example, the x-axis direction). Figure 3 (The y-axis direction shown in the image). Figures 1 to 10 In the illustrated embodiment, the second direction of the word lines is substantially orthogonal to the first direction of the digital lines; wherein the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances. In other embodiments, the word lines may intersect the digital lines without being substantially orthogonal to such digital line extensions.

[0056] about Figure 10 The top view shows the active area 36 in a dashed (phantom) view to indicate that such an active area is below other materials.

[0057] The two word lines 54 are labeled 54a and 54b to distinguish them from other word lines. Word lines 54a and 54b run along channel regions 44 and 46 associated with active region 36a, as... Figure 10B As shown in the diagram. The regions of word lines 54a and 54b adjacent to the active region 36a can be considered to include transistor gates 56a and 56b. Each of the word lines 54 will include a transistor gate at its intersection with the active region, and transistor gates 56a and 56b are understood to represent such transistor gates.

[0058] Transistor 60a includes a transistor gate 56a, a channel region 44, and source / drain regions 38 and 40. The transistor gate 56a can be considered operatively adjacent to (operatively close to) the channel region 44 such that a sufficient voltage applied to the gate 56a will induce an electric field that allows current flowing through the channel region 44 to electrically couple the source / drain regions 38 and 40 to each other. If the voltage to the gate is below a threshold level, then current will not flow through the channel region 44, and the source / drain regions 38 and 40 will not be electrically coupled to each other. Selectively controlling the coupling / decoupling of the source / drain regions 38 and 40 by the level of voltage applied to the gate 56a is referred to as source / drain gated coupling. In other words, the source / drain regions 38 and 40 can be considered as gatedly coupled to each other through the channel region 44 during operation of transistor 60a. Similarly, gate 56b can be considered to be operatively adjacent to channel region 46 such that the source / drain regions 38 and 42 of the second transistor 60b can be gate-coupled to each other through operation of gate 56b. Gates 56a and 56b can be considered to represent a plurality of transistor gates formed across active region 36 and associated with word line 54.

[0059] refer to Figure 11 , 11A 11B and 11C, insulating material 62 is formed along the sidewalls of word lines 54 and along the edge of active regions 36. Material 62 may include any suitable composition; and in some embodiments may include one or both of silicon dioxide and silicon nitride, substantially composed of one or both, or composed of one or both. In some embodiments, insulating material 62 may be referred to as spacer material. Insulating material 62 may be formed using any suitable processing. For example, material 62 may be deposited as a layer across the surface of assembly 10 and then anisotropically etched to the illustrated configuration.

[0060] Figure 11A The cross-sectional view shows that the digital line 24 can be electrically coupled to a sense amplifier circuit system (SA), which can be supported by the substrate 12.

[0061] Figure 11B The cross-sectional view shows that word line 54 can be electrically coupled to a word line driver circuit system (DRIVER), which can be supported by substrate 12.

[0062] The word lines 54 and 24 described herein can represent a large number of word lines and 24 formed across a memory array. For example, a memory array may have hundreds, thousands, millions, or even millions of substantially identical word lines and substantially identical 24 digit lines. Word lines can be considered to extend along rows of the memory array, and 24 digit lines can be considered to extend along columns of the memory array.

[0063] Figure 11CShowing the cross-section through trench 44 (where Figure 11C It is different from Figure 11 The proportions are shown. The structure beneath the channel area is generally described as 15 / 32 / 22 / 26 to indicate that this structure may include one or more of materials 15, 32, 22, and 26. However, Figure 11C Materials 15, 32, 22, and 26 are not shown, so the focus of the drawings is on the channel region 44 and the word line 54a extending along this channel region. In the illustrated embodiment, the word line 54a includes a gate 56a, which extends along the top of the channel region 44 and along the sidewall of the channel region 44. However, the gate extends only partially around the channel region and does not extend completely around the channel region (specifically, it does not extend along the bottom of the channel region). In other embodiments (see below) Figure 13 In the description, the gate can extend completely around the channel region.

[0064] refer to Figure 12 The integrated assembly 10 is described as being able to continue Figure 11 The process phase of the process. Specifically, contacts 70 (some only) are formed to extend to remote (external) source / drain regions associated with active region 36 (e.g., source / drain regions 40 and 42 associated with active region 36a), and then storage elements 72 (some only) are formed above the active region and electrically coupled to the remote source / drain regions via contacts 70. The storage element can be any suitable device having at least two detectable states; and in some embodiments it can be, for example, a capacitor (as shown), a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc. In some embodiments, one or more of the contacts 70 can be spatially displaced using a redistribution layer to allow the storage elements to be densely packed.

[0065] In some embodiments, each of the active regions 36 may be considered as associated with two memory elements 72, wherein one of the memory elements is a first memory element and the other is a second memory element. For example, active region 36a is shown as associated with two memory elements 72a and 72b. Memory element 72a may be considered as a first memory element electrically coupled to a first source / drain region 40. Memory element 72b may be considered as a second memory element electrically coupled to a second source / drain region 42.

[0066] Memory cells 80 (some of which are labeled) may include storage elements 72. In some embodiments, transistors (e.g., 60a and 60b) may be considered as access transistors for memory cells 80. For example, transistor 60a may be considered as an access device for the memory cell labeled 80a, and transistor 60b may be considered as an access device for the memory cell labeled 80b.

[0067] The memory array 82 includes memory cells 80. The described memory cells may represent a large number of substantially identical memory cells formed across the memory array. Each of the memory cells can be uniquely addressed by one of the word lines 54 and one of the digital lines 24.

[0068] The above text is about Figure 11 and 12 The configuration of the described structure is an instance configuration, and other suitable configurations can be used in other embodiments. For example, Figure 13 The display is similar to the one above. Figure 11C A view of channel 44, describing the channel region. However, Figure 13 One embodiment has a transistor gate 56a that completely surrounds the periphery of the channel region 44.

[0069] As another example, Figure 14 The display is similar to Figure 11A The arrangement of the digital lines 24 is shown, but shielding lines 84 between the digital lines are also shown. Shielding lines 84 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). Shielding lines 84 may be electrically coupled to a reference voltage (e.g., ground, VCC / 2), may be electrically floating, or may be electrically coupled to an active circuit. Shielding lines help eliminate capacitive coupling (crosstalk) between adjacent digital lines during operation of the memory array.

[0070] In the embodiments described above (e.g., Figure 11 and 12 In the embodiment, compared to a conventional structure, the formation of the digital line 24 under the active region 36 provides additional space for the digital line. This allows for the use of a larger digital line while reducing the resistance along the digital line.

[0071] Low leakage (e.g., negligible gate-induced drain leakage (GIDL)) can be achieved by using semiconductor materials that include elements from Groups 13 and 15 of the periodic table, which improves device refresh compared to conventional configurations.

[0072] The configuration described above (e.g., Figure 11 and 12 The memory array configuration enables low coupling (crosstalk) between adjacent word lines, which can alleviate the so-called "row hammer" problem associated with conventional architectures.

[0073] In some embodiments, the memory arrays described herein (e.g., Figure 12The memory array 82 may be located within a memory layer (e.g., a memory hierarchy), said memory layer being within a vertically stacked arrangement of layers (or hierarchies). For example, Figure 15 This illustration shows a portion of an integrated assembly 100 comprising a vertically stacked arrangement of layers 110, 120, and 130. The vertically stacked arrangement may extend upward to include additional layers. Layers 110, 120, and 130 can be considered as instances of layers stacked on top of each other. The layers may be within different semiconductor dies, or at least two of the layers may be within the same semiconductor die.

[0074] The bottom layer (first layer) 110 may include a control circuitry and / or a sensing circuitry (e.g., word line driver circuitry, sense amplifier circuitry, etc.); and in some applications may include a CMOS circuitry. The upper layers (second and third layers) 120 and 130 may include a memory array, such as (for example) the one described above. Figure 12 The memory array 82 is described. The memory arrays within each layer may be identical to each other (e.g., all may be DRAM arrays) or may be different from each other (e.g., some may be DRAM arrays while others are NAND arrays). Moreover, one or more of the upper layers may contain control circuitry or other logic circuitry.

[0075] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layer, multi-chip modules. Electronic systems can be found in any of a wide range of systems, such as (for example) cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0076] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable methodology now known or developed in the past, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0077] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others provides a linguistic variation within this disclosure to simplify the pre-basis of the following claims and is not intended to indicate any significant chemical or electrical differences.

[0078] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. Using one term in some instances and another in others provides linguistic variation within this disclosure to simplify the pre-basis of the following claims.

[0079] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the shown orientation. The description provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in the specific orientation shown in the drawings or rotated relative to that orientation.

[0080] The accompanying cross-sectional views show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section (unless otherwise indicated) in order to simplify the illustration.

[0081] When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it may be directly on said other structure or there may be an intermediate structure present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there is no intermediate structure present. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0082] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure generally extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0083] Some embodiments include an integrated assembly having digital lines comprising a first conductive material and extending substantially horizontally. Interconnects extend upward from the digital lines and comprise a second conductive material. Active regions extend substantially horizontally above the interconnects. The active regions comprise semiconductor material. The active regions comprise first and second source / drain regions within the semiconductor material, and a channel region within the semiconductor material between the first and second source / drain regions. The interconnects electrically couple the second source / drain region to the digital lines. A transistor gate is operatively adjacent to the channel region. A memory element is electrically coupled to the first source / drain region.

[0084] Some embodiments include an integrated assembly having an active region containing a semiconductor material. The active region includes first, second, and third source / drain regions within the semiconductor material, a first channel region within the semiconductor material and between the first and second source / drain regions, and a second channel region within the semiconductor material and between the second and third source / drain regions. The semiconductor material contains at least one element selected from Group 13 of the periodic table. A digital line is electrically coupled to the second source / drain region. A first transistor gate is operatively adjacent to the first channel region. A second transistor gate is operatively adjacent to the second channel region. A first memory element is electrically coupled to the first source / drain region. A second memory element is electrically coupled to the third source / drain region.

[0085] Some embodiments include a method of forming an integrated assembly. Spaced-apart digital lines extending along a first direction are formed. A conductive interconnect material is formed above the digital lines. The conductive interconnect material is patterned into spaced-apart contacts electrically coupled to the digital lines. A semiconductor material is formed above the spaced-apart contacts. The semiconductor material is patterned into active regions. Each active region corresponds one-to-one with a contact. Each active region has a central region above its associated contact and a pair of remote regions horizontally offset from the central region. An external source / drain region is formed within the remote regions of the active regions. An internal source / drain region is formed within the central region of the active regions. A channel region is formed between the internal source / drain regions and the external source / drain regions. The internal source / drain regions are electrically coupled to the digital lines through the contacts. A word line extending along a second direction is formed. The second direction intersects the first direction. The word line includes a transistor gate along the channel region. A memory element electrically coupled to the external source / drain regions is formed.

[0086] In accordance with regulations, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the means disclosed herein include exemplary embodiments. Therefore, the claims should be given the full scope as literal and should be properly interpreted according to the doctrine of equivalence.

Claims

1. An integrated assembly comprising: a digit line comprising a first conductive material and extending substantially horizontally; an interconnect extending upwardly from the digit line and comprising a second conductive material; an active region over the interconnect and extending substantially horizontally; the active region comprising a semiconductor material, first and second source / drain regions included within the semiconductor material, and a channel region included within the semiconductor material and between the first and second source / drain regions; the interconnect electrically coupling the second source / drain region with the digit line; a transistor gate in operative proximity to the channel region, the transistor gate being disposed entirely over the interconnect; and a storage element electrically coupled with the first source / drain region.

2. The integrated assembly of claim 1 wherein the second conductive material is compositionally different than the first conductive material.

3. The integrated assembly of claim 2 wherein the first and second conductive materials are metal-containing materials.

4. The integrated assembly of claim 2 wherein the first conductive material comprises tungsten, and wherein the second conductive material comprises a metal nitride directly against the tungsten.

5. The integrated assembly of claim 1 wherein: the channel region is a first channel region, the transistor gate is a first transistor gate, and the storage element is a first storage element; the active region includes a second channel region on a side of the second source / drain region opposite the first channel region, and includes a third source / drain region on a side of the second channel region opposite the second source / drain region: wherein a second transistor gate is in operative proximity to the second channel region; and wherein a second storage element is electrically coupled with the third source / drain region.

6. The integrated assembly of claim 5 wherein the first and second storage elements include one or more of a capacitor, a resistive memory device, a conductive bridging device, a phase change memory device, and a programmable metallization cell.

7. The integrated assembly of claim 5 wherein the first and second storage elements are capacitors.

8. The integrated assembly of claim 1 wherein the semiconductor material comprises a combination of at least one element from Group 13 of the Periodic Table and at least one element from Group 15 of the Periodic Table.

9. The integrated assembly of claim 8 wherein the semiconductor material comprises one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, and GaInP; wherein the chemical formulas indicate the primary constituents rather than a specific stoichiometry.

10. The integrated assembly of claim 1 wherein the semiconductor material comprises a combination of a metal selected from the group consisting of aluminum, gallium, indium, thallium, tin, cadmium, zinc, and mixtures thereof, and one or more of oxygen, sulfur, selenium, and tellurium. ​ 11. The integrated assembly of claim 1, wherein the semiconductor material comprises a combination of at least one element from Group 13 of the Periodic Table and at least one element from Group 16 of the Periodic Table.

12. The integrated assembly of claim 11, wherein the semiconductor material comprises: at least one element selected from the group consisting of gallium, indium, and mixtures thereof; and at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium, and mixtures thereof.

13. The integrated assembly of claim 1, wherein the digit line is supported by a base having a planar, horizontal upper surface; and wherein the substantially horizontally extending digit line extends along a direction that is within 10° of parallel to the horizontal upper surface.

14. An integrated assembly comprising: an active region comprising a semiconductor material; the active region including a first, a second, and a third source / drain region included within the semiconductor material, a first channel region included within the semiconductor material and between the first source / drain region and the second source / drain region, and a second channel region included within the semiconductor material and between the second source / drain region and the third source / drain region; the semiconductor material including at least one element selected from Group 13 of the Periodic Table; a digit line disposed below a bottom surface of the active region and electrically coupled with the second source / drain region; a first transistor gate above the bottom surface of the active region and in operative proximity to the first channel region; a second transistor gate above the bottom surface of the active region and in operative proximity to the second channel region; a first storage element electrically coupled with the first source / drain region; and a second storage element electrically coupled with the third source / drain region.

15. The integrated assembly of claim 14, wherein the semiconductor material further includes at least one element selected from Group 15 of the Periodic Table.

16. The integrated assembly of claim 15, wherein the semiconductor material comprises one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, and GaInP; wherein the chemical formula indicates a primary constituent rather than a specific stoichiometry.

17. The integrated assembly of claim 14, wherein the semiconductor material further includes at least one element selected from Group 16 of the Periodic Table.

18. The integrated assembly of claim 17, wherein the semiconductor material comprises: at least one element selected from the group consisting of gallium, indium, and mixtures thereof; and at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium, and mixtures thereof.

19. The integrated assembly of claim 14, wherein: the digit line is below the second source / drain region; the digit line is electrically coupled with a sense amplifier circuitry; the first and second transistor gates are electrically coupled with first and second word lines, respectively; the word lines are electrically coupled with a word line driver circuitry; and the first and second storage elements are within first and second memory cells of a memory array. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 20. The integrated assembly of claim 19, wherein: the first and second word lines are two of a number of substantially identical word lines; the digit line is one of a number of substantially identical digit lines; the first and second memory cells are two of a number of substantially identical memory cells, wherein each of the memory cells is uniquely addressed by a combination of one of the digit lines and one of the word lines; and a conductive shield line is between the digit lines.

21. The integrated assembly of claim 19, wherein the first and second storage elements are capacitors.

22. The integrated assembly of claim 19, wherein: the sense amplifier circuitry and the word line driver circuitry are within a first level of a vertically-stacked arrangement of levels; the memory array is within a second level of the vertically-stacked arrangement of levels; and the second level is above the first level.

23. The integrated assembly of claim 14, wherein the first and second transistor gates completely enclose a periphery of the first and second channel regions.

24. The integrated assembly of claim 14, wherein the first and second transistor gates do not completely enclose a periphery of the first and second channel regions.

25. A method of forming an integrated assembly, comprising: forming spaced-apart digit lines extending along a first direction; forming conductive interconnect material over the digit lines; patterning the conductive interconnect material into spaced-apart contacts electrically coupled with the digit lines; forming semiconductor material over the spaced-apart contacts; patterning the semiconductor material into active regions, the active regions in one-to-one correspondence with the contacts; each active region having a central region over an associated one of the contacts, and having a pair of remote regions horizontally offset from the central region; forming an outer source / drain region within the remote regions of the active regions, and forming an inner source / drain region within the central regions of the active regions; a channel region between the inner source / drain region and the outer source / drain region; the inner source / drain regions electrically coupled with the digit lines through the contacts; forming word lines extending along a second direction, the second direction intersecting the first direction; the word lines comprising transistor gates along the channel regions, wherein an entirety of the transistor gates is disposed over the conductive interconnect material; and forming storage elements electrically coupled with the outer source / drain regions.

26. The method of claim 25, wherein the digit lines comprise a first metal- containing material; wherein the conductive interconnect material comprises a second metal- containing material; and wherein the second metal-containing material is compositionally different from the first metal-containing material.

27. The method of claim 25, wherein the second direction is substantially orthogonal to the first direction.

28. The method of claim 25, wherein the forming of the spaced-apart digit lines utilizes a damascene process.

29. The method of claim 25, wherein the semiconductor material includes at least one element selected from Group 13 of the Periodic Table.

30. The method of claim 29, wherein the semiconductor material further comprises at least one element selected from Group 15 of the Periodic Table.

31. The method of claim 30, wherein the semiconductor material comprises one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, and GaInP; wherein the chemical formula indicates the primary constituent, not the specific stoichiometry.

32. The method of claim 29, wherein the semiconductor material further comprises at least one element selected from Group 16 of the Periodic Table.

33. The method of claim 32, wherein the semiconductor material comprises: at least one element selected from the group consisting of gallium, indium, and mixtures thereof; and at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium, and mixtures thereof. ​ ​ ​

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