Multilayer three-dimensional memory device including dielectric well structure for contacting through-hole structure and method for forming the same

Abstract

A first vertical alternating sequence of a first insulating layer and a first spacer material layer and a first layer of backward-stepped dielectric material portion are formed above the substrate. The first spacer material layer is formed into a first conductive layer or is subsequently replaced by the first conductive layer. A second vertical alternating sequence of a second insulating layer and a second spacer material layer and a second layer of backward-stepped dielectric material portion are formed above the first vertical alternating sequence and the first layer of backward-stepped dielectric material portion. The second spacer material layer is formed into a second conductive layer or is subsequently replaced by the second conductive layer. An opening is formed above the first layer of backward-stepped dielectric material portion through the second vertical alternating sequence and is filled with a dielectric well structure. A contact via structure can be formed on the first conductive layer through the dielectric well structure and the first layer of backward-stepped dielectric material portion.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 16 / 827,990, filed on March 24, 2020, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular, to a multi-layer three-dimensional memory device including a dielectric well structure for contacting a via structure and a method of forming the same. Background Art

[0004] A three-dimensional semiconductor device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell," IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a three-dimensional memory device is provided, comprising: a first layer of an alternating stack of first insulating layers and first conductive layers, the first layer of the alternating stack being positioned above a substrate; a first layer of a backward-stepped dielectric material portion, the first layer of the backward-stepped dielectric material portion overlying a first stepped surface of the first layer of the alternating stack; a second layer of an alternating stack of second insulating layers and second conductive layers, wherein the second layer of the alternating stack overlying the first layer of the alternating stack and overlying a horizontal plane including a flat top surface of the first layer of the backward-stepped dielectric material portion; and memory opening filling structures. The memory opening filling structure is positioned within the first memory array region and extends vertically through each layer within the first layer alternating stack and the second layer alternating stack, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding memory film and a corresponding vertical semiconductor channel; a second layer backward stepped dielectric material portion, which covers the second stepped surface of the second layer alternating stack and extends through the first lateral recessed portion region of the second layer alternating stack; and a dielectric well structure, which contacts the top surface of the first layer backward stepped dielectric material portion and extends through the second lateral recessed portion region of the second layer alternating stack.

[0006] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming a first vertical alternating sequence of a first insulating layer and a first spacer material layer over a substrate and a first backward-stepped dielectric material portion overlying a first stepped surface of the first vertical alternating sequence, wherein the first spacer material layer is formed into a first conductive layer or is subsequently replaced by the first conductive layer; forming a second vertical alternating sequence of a second insulating layer and a second spacer material layer over the first vertical alternating sequence and the first backward-stepped dielectric material portion, wherein the second spacer material layer is formed into a second conductive layer or is subsequently replaced by the second conductive layer; forming a second stepped surface through the second alternating stack within a first opening by patterning the second alternating stack; forming a second backward-stepped dielectric material portion in the first opening through the second vertical alternating sequence above the second stepped surface; forming a second opening through the second vertical alternating sequence above the first backward-stepped dielectric material portion; and forming a dielectric well structure on a top surface of the first backward-stepped dielectric material portion through the second vertical alternating sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a plan view of a semiconductor die including multiple three-dimensional memory array regions according to an embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A Schematic perspective top view of the region M1 of FIG.

[0009] Figure 1C It is along Figure 1B Schematic vertical cross-sectional view of a region of a semiconductor die taken along a vertical plane CC'.

[0010] Figure 1D It is along Figure 1B Schematic vertical cross-sectional view of a region of a semiconductor die taken along a vertical plane DD′.

[0011] Figure 1E It is along Figure 1B Schematic vertical cross-sectional view of a region of the semiconductor die along the vertical plane EE′.

[0012] Figure 1F It is along Figure 1B Schematic vertical cross-sectional view of a region of a semiconductor die taken along a vertical plane FF′.

[0013] Figure 1G It is along Figure 1B Schematic vertical cross-sectional view of a region of a semiconductor die along a vertical plane GG'.

[0014] Figure 2is a vertical cross-sectional view of an exemplary structure for forming a semiconductor die after forming an optional semiconductor device, an optional lower level dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, and a first vertical alternating sequence of first insulating and first spacer material layers in accordance with an embodiment of the present disclosure.

[0015] Figure 3A is a vertical cross-sectional view of an exemplary structure after forming a first stepped surface in the inter-array region according to an embodiment of the present disclosure.

[0016] Figure 3B yes Figure 3A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 3A A vertical section of a plane.

[0017] Figure 4A is a vertical cross-sectional view of an exemplary structure after forming a first level back stepped dielectric material portion, a first level opening, and a sacrificial first level opening fill portion according to an embodiment of the present disclosure.

[0018] Figure 4B yes Figure 4A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 4A A vertical section of a plane.

[0019] Figure 5 is a vertical cross-sectional view of the exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers according to an embodiment of the present disclosure.

[0020] Figure 6A is a vertical cross-sectional view of an exemplary structure after forming a second level rearward stepped dielectric material portion according to an embodiment of the present disclosure.

[0021] Figure 6B yes Figure 6A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 6A A vertical section of a plane.

[0022] Figure 7A is a vertical cross-sectional view of an exemplary structure after forming a dielectric well structure according to an embodiment of the present disclosure.

[0023] Figure 7B yes Figure 7A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 7A A vertical section of a plane.

[0024] Figure 8is a vertical cross-sectional view of an exemplary structure after forming second-level openings according to an embodiment of the present disclosure.

[0025] 9A to 9D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure are shown according to an embodiment of the present disclosure.

[0026] Figure 10 is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0027] Figure 11 is a vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer according to an embodiment of the present disclosure.

[0028] Figure 12A is a vertical cross-sectional view of an exemplary structure after forming backside trenches according to an embodiment of the present disclosure.

[0029] Figure 12B yes Figure 12A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 12A A vertical section of a plane.

[0030] Figure 13A is a vertical cross-sectional view of an exemplary structure after forming a conductive layer and a backside trench fill structure according to an embodiment of the present disclosure.

[0031] Figure 13B yes Figure 13A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 13A A vertical section of a plane.

[0032] Figure 14A is a vertical cross-sectional view of an exemplary structure after forming various contact via structures according to an embodiment of the present disclosure.

[0033] Figure 14B yes Figure 14A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 14A A vertical section of a plane. DETAILED DESCRIPTION

[0034] As described above, embodiments of the present disclosure relate to a multi-layer three-dimensional memory device including a dielectric well structure for contacting a via structure and a method of forming the same, various aspects of which are now described in detail.

[0035] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0036] The same reference numerals represent the same or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0037] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of a first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0038] As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from vertical by an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0039] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the memory element array and a second horizontal plane including the bottommost surface of the memory element array. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0040] As used herein, "semiconductor material" refers to a material having a -5 S / m to 1.0×10 5 As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to become conductive (i.e., provide a conductivity greater than 1.0×10 5 S / m) of semiconductor material. "Doped semiconductor material" may be a heavily doped semiconductor material, or may include a material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m) in the range of 100 Å / s. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0041] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for the memory device.

[0042] Various three-dimensional memory devices disclosed herein include single-unit three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. A single-unit three-dimensional NAND string is positioned in a single-unit three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0043] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded together, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming and the smallest units that can be selected for read operations.

[0044] See also Figures 1A to 1G, a semiconductor die 1000 including multiple three-dimensional memory array regions and inter-array regions is shown in various views. The semiconductor die 1000 may include multiple planes, each plane including two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B, laterally separated by a corresponding inter-array region 200. Generally speaking, the semiconductor die 1000 may include a single plane or multiple planes. The total number of planes in the semiconductor die 1000 may be selected based on the performance requirements of the semiconductor die 1000. A pair of memory array regions 100 within a plane may be laterally separated along a first horizontal direction hd1 (which may be a wordline direction). A second horizontal direction hd2 (which may be a bitline direction) may be perpendicular to the first horizontal direction hd1.

[0045] Each memory array region 100 includes a first alternating stack of a first insulating layer 132 and a first conductive layer 146 (the first conductive layer serving as a first word line), and a second alternating stack of a second insulating layer 232 and a second conductive layer 246 (the second conductive layer serving as a second word line). Each second alternating stack (232, 246) overlies a corresponding first alternating stack (132, 246), and each first alternating stack (132, 146) underlies a corresponding second alternating stack (232, 246). Each combination of a first alternating stack (132, 146) and an overlying second alternating stack (232, 246) can be laterally separated from an adjacent combination of a corresponding first alternating stack (132, 146) and a corresponding second alternating stack (232, 246) by a backside trench fill structure 76 extending laterally along a first horizontal direction hd1.

[0046] The exemplary structure may include an optional semiconductor material layer 110 comprising a single crystal or polycrystalline semiconductor material, such as single crystal silicon or polycrystalline silicon. In one embodiment, the semiconductor material layer 110 may be a substrate. Optionally, an underlying dielectric material layer may be provided below the semiconductor material layer 110. In this case, the underlying dielectric material layer is referred to as a lower level dielectric material layer 760.

[0047] A first alternating stack of first insulating layers 132 and first conductive layers 146 is positioned above a substrate (which may include semiconductor material layer 110 or another structure underlying semiconductor material layer 110, such as a silicon wafer) between each adjacent pair of backside trench fill structures 76. A first layer of backward-stepped dielectric material portions 165 overlie and contact a first stepped surface of the first alternating stack (132, 146). A second layer of alternating stack of second insulating layers 232 and second conductive layers 246 overlie the first alternating stack (132, 146) and overlie a horizontal plane including a flat top surface of the first layer of backward-stepped dielectric material portions 165 between each adjacent pair of backside trench fill structures 76. A second layer of backward-stepped dielectric material portions 265 overlie and contact a second stepped surface of the second alternating stack (132, 146). The vertical steps S of the first and second stepped surfaces extend laterally in a second horizontal direction hd2 (e.g., a bitline direction).

[0048] A memory opening filling structure 58 may be positioned within each memory array region 100 (each memory array region including a first memory array region 100A and a second memory array region 100B) between each adjacent pair of backside trench fill structures 76. The memory opening filling structure 58 may be positioned within memory openings that extend vertically through each of the first and second alternating stacks (132, 146) positioned between the respective adjacent pairs of backside trench fill structures 76. Each of the memory opening filling structures 58 includes a respective memory film and a respective vertical semiconductor channel, as will be described in greater detail below.

[0049] A second layer of backward stepped dielectric material portions 265 overlies the second stepped surface of the second layer of alternating stacks (232, 246) and extends through the first lateral recessed region of the second layer of alternating stacks (232, 246) positioned between each adjacent pair of backside trench fill structures 76. A dielectric well structure 365 comprising and / or consisting essentially of at least one dielectric material contacts the top surface of the first layer of backward stepped dielectric material portions 165 and extends through the second lateral recessed region of the second layer of alternating stacks (232, 246) positioned between each adjacent pair of backside trench fill structures 76. As used herein, a "lateral recessed region" of a structure refers to a region in which a non-horizontal sidewall of the structure is laterally recessed relative to an additional sidewall of the structure.

[0050] A contact-level dielectric layer 280 may be provided above each second-layer alternating stack (232, 246). In one embodiment, a first contact via structure 86A extends vertically through the dielectric well structure 365 and the first-layer backward stepped dielectric material portion 165 and contacts a corresponding one of the first conductive layers 146. A second contact via structure 86B extends vertically through the second-layer backward stepped dielectric material portion 265 and contacts a corresponding one of the second conductive layers 246.

[0051] For each combination of a first layer of alternating stacks (132, 146) and an overlying second layer of alternating stacks (232, 246), a corresponding first backside trench filling structure 76 extends laterally along a first horizontal direction hd1 (e.g., a word line direction) and contacts a first sidewall of the first layer of alternating stacks (132, 146) and a first sidewall of the second layer of alternating stacks (232, 246), and a second backside trench filling structure 76 extends laterally along the first horizontal direction hd1 and contacts a second sidewall of the first layer of alternating stacks (132, 146) and a second sidewall of the second layer of alternating stacks (232, 246).

[0052] In one embodiment, each dielectric well structure 365 can be positioned between a laterally adjacent pair of backside trench fill structures 76, referred to herein as a respective first backside trench fill structure 76 and a respective second backside trench fill structure 76. Each dielectric well structure 365 includes a first tapered sidewall extending laterally along a first horizontal direction hd1 and positioned between and laterally spaced apart from each of the respective first backside trench fill structure 76 and the respective second backside trench fill structure 76.

[0053] In one embodiment, each dielectric well structure 365 positioned between a corresponding laterally adjacent pair of backside trench fill structures 76 may include a pair of second tapered sidewalls extending laterally along a second horizontal direction hd2. The entirety of each of the second tapered sidewalls of the dielectric well structure 365 contacts a corresponding sidewall of the second layer of alternating stacks (232, 246). The first tapered sidewall and the pair of second tapered sidewalls of the dielectric well structure 365 define the lateral extent of the second lateral recess region of the second layer of alternating stacks (232, 246).

[0054] In one embodiment, the entirety of the bottom surface of each dielectric well structure 365 can be in contact with the top surface of the underlying first layer of backward stepped dielectric material portion 165. A first portion of the perimeter of the bottom surface of each dielectric well structure 365 can be laterally offset inward from a first portion of the perimeter of the top surface of the corresponding underlying first layer of backward stepped dielectric material portion 165. A second portion of the perimeter of the bottom surface of each dielectric well structure 365 can coincide with a second portion of the perimeter of the top surface of the corresponding underlying first layer of backward stepped dielectric material portion 165.

[0055] The additional memory opening filling structure 58 can be positioned within the second memory array region 100B, which is laterally offset from the first memory array region 100A along the first horizontal direction hd1 by the second layer of backward stepped dielectric material portion 265 and the dielectric well structure 365. Each layer of the first layer alternating stack (132, 246) and each layer of the second layer alternating stack (232, 246) are present within the second memory array region 100B. Figure 1B As shown, at least a portion of the first conductive layer 146 and at least a portion of the second conductive layer 246 extend continuously from the first memory array region 100A to the second memory array region 100B through the array interconnect region (e.g., a "bridge" region) 220, which is positioned between the backside trench fill structure 76 of each of the second level backward stepped dielectric material portion 265 and the dielectric well structure 365. At least a portion of the first conductive layer 146 and at least a portion of the second conductive layer 246 contact the second level backward stepped dielectric material portion 265 and the dielectric well structure 365.

[0056] In one embodiment, the second layer backward stepped dielectric material portion 265 and the dielectric well structure 365 include the same dielectric material and are laterally spaced apart from each other along the first horizontal direction by a portion of the second layer alternating stack (232, 246) extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0057] Each combination of a first layer alternating stack (132, 146) and an overlying second layer alternating stack (232, 246) may be positioned between corresponding adjacent pairs of backside trench fill structures 76. Thus, for each combination of a first layer alternating stack (132, 146) and an overlying second layer alternating stack (232, 246), an adjacent combination of an additional first layer alternating stack (132, 146) and an additional second layer alternating stack (232, 246) may be provided. The structure adjacent to each combination of the first layer alternating stack (132, 146) and the overlying second layer alternating stack (232, 246) may include: an additional first layer alternating stack of an additional first insulating layer 132 and an additional first conductive layer 146 positioned above the substrate; an additional first layer backward stepped dielectric material portion 165 overlying the additional first stepped surface of the additional first layer alternating stack (132, 146); an additional second layer alternating stack of an additional second insulating layer 232 and an additional second conductive layer 246; an additional memory opening filling structure 58 positioned within the additional memory array region 100B and extending vertically through each layer within the additional first layer alternating stack (132, 146) and the additional second layer alternating stack (232, 246); and an additional second layer alternating stack overlying the additional second layer alternating stack (232, 246). 2,246) and extending through the additional lateral recessed portion area in the additional second layer alternating stack (232,246); an additional dielectric well structure 365 contacting the top surface of the additional first layer backward stepped dielectric material portion 165 and extending through the additional second lateral recessed portion area in the additional second layer alternating stack (232,246); and a backside trench filling structure 76, which extends laterally along the first horizontal direction hd1 and contacts the sidewalls of the first layer alternating stack (132,146), the sidewalls of the second layer alternating stack (232,246), the sidewalls of the additional first layer alternating stack (132,146) and the sidewalls of the additional second layer alternating stack (232,246). The additional second layer alternating stack (232, 246) overlies the additional first layer alternating stack (132, 146) and overlies a horizontal plane including the flat top surface of the first layer rear stepped dielectric material portion 165.

[0058] The dielectric well structure 365 and the additional dielectric well structure 365 can be diagonally spaced apart from each other with a backside trench fill structure 76 therebetween, and the second layer backward stepped dielectric material portion 265 and the additional second layer backward stepped dielectric material portion 265 can be diagonally spaced apart from each other with a backside trench fill structure 76 therebetween. In one embodiment, the lateral offset distance between the dielectric well structure 365 and the additional second layer backward stepped dielectric material portion 265 (which can be the same as the width of the backside trench fill structure 76 along the second horizontal direction hd2) is less than the lateral offset distance between the dielectric well structure 365 and the additional dielectric well structure 365. Similarly, the lateral offset distance between the second layer backward stepped dielectric material portion 265 and the additional dielectric well structure 365 (which lateral offset distance may be the same as the width of the backside trench filling structure 76 along the second horizontal direction hd2) is smaller than the lateral offset distance between the second layer backward stepped dielectric material portion 265 and the additional second layer backward stepped dielectric material portion 265.

[0059] The steps of the first stepped surface and the second stepped surface, comprising a combination of first-layer alternating stacks (132, 146) and overlying second-layer alternating stacks (232, 246), may rise from the substrate in a first horizontal direction hd1 or in a direction opposite to the first horizontal direction hd1. In one embodiment, the direction of rise of the steps may change for every other pair of the combination of respective first-layer alternating stacks (132, 146) and respective second-layer alternating stacks (232, 246). In other words, the direction of rise is staggered in adjacent alternating stacks separated along the second horizontal direction. For example, when each combination of the corresponding first layer alternating stacking (132, 146) and the corresponding second layer alternating stacking (232, 246) is sequentially numbered with a positive integer N starting from 1, each (4N+1)th combination and each (4N+2)th combination of the corresponding first layer alternating stacking (132, 146) and the corresponding second layer alternating stacking (232, 246) may have a step ascending along the first horizontal direction hd1, and each (4N+3)th combination and each (4N+4)th combination of the corresponding first layer alternating stacking (132, 146) and the corresponding second layer alternating stacking (232, 246) may have a step ascending in a direction opposite to the first horizontal direction hd1.

[0060] In one embodiment, the vertical distance between the first stepped surface and the substrate increases along the first horizontal direction hd1, the vertical distance between the second stepped surface and the substrate increases along the first horizontal direction hd1, the vertical distance between the additional first stepped surface and the substrate decreases along the first horizontal direction hd1, and the vertical distance between the additional second stepped surface and the substrate decreases along the first horizontal direction hd1.

[0061] A bridging region 240 comprising strips of the first insulating layer 132, the first conductive layer 146, the second insulating layer 232, and the second conductive layer 246 can be positioned between laterally adjacent pairs of the backside trench fill structures 76 and adjacent to respective combinations of the first layer backward stepped dielectric material portion 165, the dielectric well structure 365, and the second layer backward stepped dielectric material portion 265. Each strip of the first insulating layer 132, the first conductive layer 146, the second insulating layer 232, and the second conductive layer 246 can extend continuously from the first memory array region 100A to the second memory array region 100B.

[0062] Laterally isolated vertical interconnect structures (484, 486) may be formed across the bridge region 240. Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure 486 and a tubular insulating spacer 484 that laterally surrounds the conductive via structure 486. Each through-memory level conductive via structure 486 may contact a lower level metal interconnect structure 780 positioned in the lower level dielectric material layer 760, as shown. Figure 1E Drain contact through hole structure ( Figure 14A 1000) may extend through the contact-level dielectric layer 280 and may contact upper portions of corresponding memory opening fill structures 58 (such as drain regions within corresponding memory opening fill structures 58). Bit lines (not shown) may extend laterally along a second horizontal direction hd2 and may contact top surfaces of corresponding subsets of drain contact via structures. Additional metal interconnect structures embedded in an overlying dielectric material layer (not shown) may be employed to provide electrical connections between various nodes of the three-dimensional memory device positioned in semiconductor die 1000.

[0063] Can be manufactured using a sequence of processing steps Figures 1A to 1G See the example structure of Figure 2 , a vertical cross-sectional view along a first horizontal direction (eg, word line direction) hd1 shows a method for forming a Figures 1A to 1G An exemplary structure of a structure is provided after forming a first vertical alternating sequence of semiconductor devices 720 disposed on a substrate semiconductor layer 9 at least within an upper portion of a substrate 8, a lower-level dielectric layer 760, a lower-level metal interconnect structure 780 embedded in the lower-level dielectric layer 760 (schematically represented by a dashed area including a physical implementation of the lower-level metal interconnect structure), a semiconductor material layer 110, and a first insulating layer 132 and a first spacer material layer (the first spacer material layer may include a first sacrificial material layer 142). Figure 2The structure shown. The substrate semiconductor layer 9 may include a top portion (e.g., a doped well) of a semiconductor substrate 8 (such as a silicon wafer) or a semiconductor layer positioned above a substrate (such as a silicon-on-insulator substrate or a semiconductor substrate). The semiconductor device 720 may include a field effect transistor formed above the top surface of the substrate 8. The lower level dielectric layer 760 may be an interconnect-level dielectric material layer embedded in the lower level metal interconnect structure 780.

[0064] As used herein, a vertical alternating sequence refers to a sequence of multiple instances of a first element and multiple instances of a second element, arranged such that an instance of the second element is positioned between each vertically adjacent pair of instances of the first element, and an instance of the first element is positioned between each vertically adjacent pair of instances of the second element. Generally speaking, the spacer material layer within each alternating stack is formed as a conductive layer or is subsequently replaced with a conductive layer. Thus, the first spacer material layer can be formed as the first conductive layer 146 or can be subsequently replaced with such first conductive layers.

[0065] The first insulating layer 132 may be composed of a first material, and the first sacrificial material layer 142 may be composed of a second material different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0066] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively with respect to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0067] The first spacer material layer may be formed as a first conductive layer (which may include TiN, TaN, WN, W, Ru, Co, Mo, Cu, or a combination thereof), or may be formed as a first sacrificial material layer that is subsequently replaced within the first conductive layer. In the case where the first spacer material layer is formed as a first spacer material layer, the first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride. Although the present disclosure is described using an embodiment in which the first spacer material layer is formed as a first sacrificial material layer 142, embodiments in which the first spacer material layer is formed as a first conductive layer are explicitly contemplated herein. In this case, the processing step for replacing the first sacrificial material layer 142 with the first conductive layer may be omitted.

[0068] See also Figure 3A and Figure 3B , a first stepped surface can be simultaneously formed within the inter-array region 200. A hard mask layer (not shown), such as a metal or dielectric mask material layer, can be formed above the first vertical alternating sequence and can be patterned to form a plurality of rectangular openings. The area of ​​the openings within the hard mask layer corresponds to the area where the first stepped surface will subsequently be formed. Each opening through the hard mask layer can be rectangular and can have a pair of sides parallel to the first horizontal direction hd1 and a pair of sides parallel to the second horizontal direction hd2. The rectangular openings through the hard mask layer can be arranged along the second horizontal direction hd2 and can alternatively be staggered along the first horizontal direction hd1. Therefore, when the rectangular openings are numbered sequentially along the second horizontal direction hd2, each odd-numbered rectangular opening passing through the hard mask layer can be formed into a first one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1 (i.e., having the same lateral extent along the first horizontal direction), and each even-numbered rectangular opening passing through the hard mask layer can be formed into a second one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1.

[0069] A fine-tunable mask layer (not shown) may be applied over the first vertical alternating sequence. The fine-tunable mask layer may include a fine-tunable photoresist layer that can be controllably fine-tuned by a timed ashing process. The fine-tunable mask layer may be patterned with an initial pattern such that the section of the hard mask layer closest to each rectangular opening in the memory array region 100 is not masked by the fine-tunable mask layer, while the remainder of each rectangular opening is covered by the fine-tunable mask layer. For example, the fine-tunable mask layer may have a rectangular shape having straight edges parallel to the second horizontal direction hd2, such that these straight edges are positioned above the vertical steps S of the corresponding first stepped surface closest to one of the memory array regions in the memory array region 100. The location of the initial fine-tunable mask edge ITME of the fine-tunable mask layer is marked with a dotted line.

[0070] The first stepped surface can be formed within the rectangular opening in the hard mask layer by repeatedly performing a set of layer patterning steps, the number of which is equal to the total number of first spacer material layers in the first vertical alternating sequence minus one. The set of layer patterning steps includes an anisotropic etching process that etches unmasked portions of a pair of first insulating layers 132 and a first spacer material layer (such as first sacrificial material layer 142); and a mask trimming process in which the tunable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 100. The location of the final tunable mask edge (FTME) of the tunable mask layer is marked by a dashed line. The general direction of movement of the edges of the tunable mask layer is indicated by arrows A1 and A2. A final anisotropic etching process can be performed after the final mask trimming process, and the tunable mask layer can be removed, for example, by ashing. The hard mask layer may be removed selectively to the material of the first vertical alternating sequence (132, 142), for example, by an isotropic etching process, such as a wet etching process.

[0071] A first stepped cavity 163 may be formed within each region of the rectangular opening in the hard mask layer. Each first stepped cavity 163 may include a steep-walled region in which the tapered sidewalls of the first vertical alternating sequence vertically extend from the bottommost layer of the first vertical alternating sequence (132, 142) to the topmost layer of the first vertical alternating sequence (132, 142). Each first stepped cavity 163 has a corresponding first stepped surface as a stepped bottom surface. Each first stepped cavity 163 has a pair of stepped sidewalls extending laterally along a first horizontal direction hd1. Each stepped sidewall of the first stepped cavity abuts the first stepped surface at a bottom edge and extends to the top surface of the topmost layer of the first vertical alternating sequence (132, 142).

[0072] The array of first stepped regions can be arranged along the second horizontal direction hd2 with alternating lateral offsets along the first horizontal direction hd1 to provide the first stepped regions with a staggered configuration. In other words, after the first stepped regions are numerically labeled sequentially along the second horizontal direction hd2 with positive integers starting from 1, each odd-numbered first stepped region can be closer to the first memory array region 100A than to the second memory array region 100B, and each even-numbered first stepped region can be closer to the second memory array region 100B than to the second memory array region 100A.

[0073] See also Figure 4A and Figure 4B A first dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each first stepped cavity 163. The first dielectric fill material may be planarized to remove excess portions of the first dielectric fill material above a horizontal plane including the topmost surface of the first vertical alternating sequence (132, 142). Each remaining portion of the first dielectric fill material filling the corresponding first stepped cavity constitutes a first layer of backward stepped dielectric material portion 165.

[0074] Various first-level openings may be formed in the semiconductor material layer 110 through the first vertical alternating sequence (132, 142). A photoresist layer (not shown) may be applied over the first vertical alternating sequence (132, 142) and photolithographically patterned to form the various openings therethrough. The pattern of openings in the photoresist layer may be transferred through the first vertical alternating sequence (132, 142) into the semiconductor material layer 110 through a first anisotropic etching process to simultaneously form the various first-level openings (i.e., during the first isotropic etching process). The various first-level openings may include first-level memory openings formed in the memory array region 100 and first-level support openings formed in the inter-array region 200. Each cluster of first-level memory openings may be formed as a two-dimensional array of first-level memory openings. The first-level support openings are openings formed in the inter-array region 200 and are subsequently used to form support pillar structures. A subset of the first-level support openings may be formed through corresponding horizontal surfaces of the first stepped surface.

[0075] A sacrificial first layer opening fill portion (148, 128) may be formed in the various first layer openings. For example, a sacrificial first layer fill material may be deposited simultaneously in each of the first layer openings. The sacrificial first layer fill material may include a material that may be selectively removed from the first insulating layer 132 and the first sacrificial material layer 142.

[0076] In one embodiment, the sacrificial first layer fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0077] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the material of the first insulating layer 132. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0078] In yet another embodiment, the sacrificial first layer filler material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selectively to the material of the first alternating stack (132, 142).

[0079] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the topmost first insulating layer 132. For example, the sacrificial first layer fill material may be recessed to the top surface of the topmost first insulating layer 132 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the topmost first insulating layer 132 may serve as an etch stop or a planarization stop.

[0080] The remaining portions of the sacrificial first layer fill material comprise sacrificial first layer opening fill portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory openings constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support openings constitutes a sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148, 128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142), such as from above the top surface of the topmost first insulating layer 132. The top surface of the sacrificial first layer opening fill portions (148, 128) may be coplanar with the top surface of the topmost first insulating layer 132. Each of the sacrificial first layer opening fill portions (148, 128) may or may not include a cavity therein. The collection of all structures positioned between the bottommost surface of the first vertical alternating sequence (132, 142) and the topmost surface of the first vertical alternating sequence (132, 142) or embedded within the first vertical alternating sequence (132, 142) constitutes a first layer of structure.

[0081] See also Figure 5 , a second vertical alternating sequence of second insulating layers 232 and second spacer material layers may be formed. The second spacer material layer may be formed as a second conductive layer, or as a second sacrificial material layer 242 that is subsequently replaced with a second conductive layer. The second insulating layer 232 may have the same material composition and thickness as the first insulating layer 132. The second spacer material layer may have the same material composition and thickness as the second spacer material layer.

[0082] In general, at least one additional vertical alternating sequence of additional insulating layers and additional spacer material layers may optionally be formed over the first vertical alternating sequence (132, 142) and the first layer of rear stepped dielectric material portion 165. The additional spacer material layers may be formed as additional conductive layers or subsequently replaced with additional conductive layers.

[0083] See also Figure 6A and Figure 6B, a second stepped surface can be simultaneously formed within the inter-array region 200. The area of ​​the second stepped surface is laterally offset from the corresponding proximal first stepped surface along the first horizontal direction hd1, so that a set of first stepped surfaces and a set of second stepped surfaces that are laterally spaced apart along the first horizontal direction hd1 and not offset along the second horizontal direction hd2 can provide a continuously ascending step or a continuously descending step. For example, a hard mask layer (not shown), such as a metal or dielectric mask material layer, can be formed over the second vertical alternating sequence and can be patterned to form a plurality of rectangular openings that are laterally offset from the corresponding first layer rearward stepped dielectric material portion 165 along the first horizontal direction hd1 and aligned with (i.e., not laterally offset from) the corresponding first layer rearward stepped dielectric material portion 165 along the second horizontal direction hd2. The area of ​​the openings within the hard mask layer corresponds to the area where the second stepped surface will subsequently be formed. Each opening through the hard mask layer can be rectangular and can have a pair of sides parallel to a first horizontal direction hd1 and a pair of sides parallel to a second horizontal direction hd2. The rectangular openings through the hard mask layer can be arranged along the second horizontal direction hd1 and can alternatively be staggered along the second horizontal direction hd2. Thus, when the rectangular openings are sequentially numbered along the second horizontal direction hd2, each odd-numbered rectangular opening through the hard mask layer can form a first one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1 (i.e., having the same lateral extent along the first horizontal direction), and each even-numbered rectangular opening through the hard mask layer can form a second one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1.

[0084] A fine-tunable mask layer (not shown) may be applied over the second vertical alternating sequence. The fine-tunable mask layer may include a fine-tunable photoresist layer that can be controllably fine-tuned by a timed ashing process. The fine-tunable mask layer may be patterned with an initial pattern such that a portion of each rectangular opening in the hard mask layer farthest from the memory array region 100 is not masked by the fine-tunable mask layer, while the remainder of each rectangular opening is covered by the fine-tunable mask layer. For example, the fine-tunable mask layer may have a rectangular shape with straight edges parallel to the second horizontal direction hd2, such that these straight edges are positioned above the vertical steps S of the corresponding second stepped surface farthest from one of the memory array regions 100. The location of an initial fine-tunable mask edge ITME of the fine-tunable mask layer is marked with a dotted line.

[0085] A second stepped surface can be formed within the rectangular opening in the hard mask layer by repeatedly performing a set of layer patterning steps, the number of which is equal to the total number of second spacer material layers in the second vertical alternating sequence minus one. The set of layer patterning steps includes an anisotropic etching process that etches unmasked portions of a pair of second insulating layers 232 and a second spacer material layer (such as second sacrificial material layer 242); and a mask trimming process in which the tunable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 100. The location of the final tunable mask edge FTME of the tunable mask layer is marked by a dashed line. The general direction of movement of the edges of the tunable mask layer is indicated by arrows B1 and B2. A final anisotropic etching process can be performed after the final mask trimming process, and the tunable mask layer can be removed, for example, by ashing. The hard mask layer may be removed selectively to the material of the second vertical alternating sequence (132, 142), for example, by an isotropic etching process, such as a wet etching process.

[0086] A second stepped cavity 263 may be formed within each region of the rectangular opening in the hard mask layer. Each second stepped cavity 263 may include a steep wall region in which the tapered sidewalls of the second vertical alternating sequence extend vertically from the bottommost layer of the second vertical alternating sequence (232, 242) to the topmost layer of the second vertical alternating sequence (232, 242). Each second stepped cavity 263 has a corresponding second stepped surface as a stepped bottom surface. Each second stepped cavity 263 has a pair of stepped sidewalls extending laterally along the first horizontal direction hd1. Each stepped sidewall of the second stepped cavity 263 abuts the second stepped surface at a bottom edge and extends to the top surface of the topmost layer of the second vertical alternating sequence (232, 242). Each second stepped cavity 263 defines the lateral extent of the corresponding second stepped surface.

[0087] The array of second stepped regions can be arranged along a second horizontal direction hd2 with alternating lateral offsets along the first horizontal direction hd1 to provide a staggered configuration for the second stepped regions. In other words, after numerically labeling the second stepped regions sequentially with positive integers starting from 1 along the second horizontal direction hd2, each even-numbered second stepped region can be closer to the second memory array region 100A than to the second memory array region 100B, and each odd-numbered second stepped region can be closer to the second memory array region 100B than to the second memory array region 100A. The second stepped cavity can be a first opening extending through each layer within the second vertical alternating sequence (232, 242).

[0088] See also Figure 7A and Figure 7B, a photoresist layer can be applied over the second vertical alternating sequence (232, 242) and the second stepped cavity 263 and can be photolithographically patterned to form openings in areas overlying the first layer backward stepped dielectric material portion 165 and not overlapping the second stepped cavity 263. In one embodiment, the edges of the openings in the photoresist layer can coincide with the edges of the top surface of the corresponding underlying first layer backward stepped dielectric material portion 165, or can be laterally offset from these edges. In one embodiment, the edges of the openings in the photoresist layer can be positioned so that the bottom perimeter of each opening (also referred to as a well) that will subsequently be formed through the second vertical alternating sequence (232, 242) is positioned completely within the perimeter of the top surface of a corresponding one of the first layer backward stepped dielectric material portions 165.

[0089] An anisotropic etching process can be performed using a photoresist layer as an etching mask. The unmasked portion of the second vertical alternating sequence (232, 242) is etched by the anisotropic etching process, and a second opening is formed in the vertical alternating sequence (232, 242). The second opening is referred to herein as a well. Each well can be formed above a corresponding one of the first layer backward stepped dielectric material portions 165, and the top surface of the first layer backward stepped dielectric material portion 165 is physically exposed to the bottom of each well. Each well is a second opening through the second vertical alternating sequence (232, 242) and is laterally offset from the second stepped cavity 263, which is the first opening through the second vertical alternating sequence (232, 242). In one embodiment, each well can be aligned with a corresponding second stepped cavity 263 along a second horizontal direction hd2 and can be laterally spaced apart from the corresponding second stepped cavity 263 along the first horizontal direction hd1 by a stripe portion of a second vertical alternating sequence (232, 242) extending along the second horizontal direction hd2. The bottom perimeter of each well can be laterally offset inward from the top perimeter of the top surface of the corresponding underlying first layer back-stepped dielectric material portion 165.

[0090] A second dielectric fill material (such as undoped silicate glass or doped silicate glass) can be deposited in each second stepped cavity 263 and in each well. The second dielectric fill material can be planarized to remove excess portions of the second dielectric fill material above a horizontal plane including the topmost surface of the second vertical alternating sequence (232, 242). Each remaining portion of the second dielectric fill material filling the corresponding second stepped cavity 263 constitutes a second layer of backward-stepped dielectric material portion 265. Each remaining portion of the second dielectric fill material filling the corresponding well constitutes a dielectric well structure 365. Thus, a second layer of backward-stepped dielectric material portion 265 is formed in the first opening through the second vertical alternating sequence (232, 242), and a dielectric well structure 365 is formed in the second opening through the second vertical alternating sequence (232, 242). Each dielectric well structure 365 is formed on the top surface of the corresponding first layer of backward-stepped dielectric material portion 165 through the second vertical alternating sequence (232, 242). Each dielectric well structure 365 is laterally spaced apart from the second level backward stepped dielectric material portion 265 by a patterned portion of the second vertical alternating sequence ( 232 , 242 ).

[0091] See also Figure 8 Various second layer openings (249, 229) may be formed through the second vertical alternating sequence (132, 142) and over the sacrificial first layer opening-filling portions (148, 128). A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232, 242) and may be photolithographically patterned to form the various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the second vertical alternating sequence (232, 242) to simultaneously (i.e., during the second isotropic etching process) form the various second layer openings (249, 229).

[0092] The various second-layer openings (249, 229) may include second-layer memory openings 249 formed in the memory array region 100 and second-layer support openings 229 formed in the inter-array region 200. Each second-layer opening (249, 229) may be formed within the region of a corresponding one of the sacrificial first-layer opening-filling portions (148, 128). Thus, the top surface of the sacrificial first-layer opening-filling portion (148, 128) may be physically exposed to the bottom of each second-layer opening (249, 229). Specifically, each second-layer memory opening 249 may be formed directly above a corresponding sacrificial first-layer memory opening-filling portion 148, and each second-layer support opening 229 may be formed directly above a corresponding sacrificial first-layer support opening-filling portion 128. Each cluster of second-layer memory openings 249 may be formed as a two-dimensional array of second-layer memory openings 249. The second-layer support openings 229 are openings formed in the inter-array region 200 and are subsequently used to form a support pillar structure. A subset of second-layer support openings can be formed through corresponding horizontal surfaces of the second stepped surface. The photoresist layer can then be removed, for example, by ashing. The collection of all structures positioned between the bottommost surface of the second vertical alternating sequence (232, 242) and the topmost surface of the second vertical alternating sequence (232, 242) or embedded within the second vertical alternating sequence (232, 242) constitutes a second-layer structure.

[0093] See also Figure 9A The sacrificial first layer fill material of the sacrificial first layer opening filling portion (148, 128) can be removed using an etching process that selectively etches the sacrificial first layer fill material with respect to the material of the first and second insulating layers (132, 232) and the first and second sacrificial material layers (142, 242). A memory opening (also referred to as an interlayer memory opening 49) is formed in each combination of a second layer memory opening and a volume from which the sacrificial first layer memory opening filling portion 148 is removed. A support opening (also referred to as an interlayer support opening) is formed in each combination of a second layer support opening and a volume from which the sacrificial first layer support opening filling portion 128 is removed. The interlayer memory opening 49 extends through the first and second layer structures. Generally speaking, the memory opening 49 can be formed within each memory array region 100 where there is each layer of the first vertical alternating sequence (132, 142) and each layer of the second vertical alternating sequence (232, 242).

[0094] See also Figure 9B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the interlayer memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0095] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and an anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, although lesser and greater thicknesses can also be used.

[0096] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52 , the charge storage layer 54 , and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

[0097] The semiconductor channel material layer 60L comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has p-type doping, wherein the p-type dopant (such as boron atoms) is present at a concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polysilicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3The semiconductor channel material layer 60L exists at an atomic concentration within a range of 100 nm to 100 nm. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be used. A cavity 49 ′ is formed in the volume of each interlayer memory opening 49 that is not filled with the deposited material layer ( 52 , 54 , 56 , 60L).

[0098] See also Figure 9C In the event that the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer may be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer comprises a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self-planarization deposition process, such as spin coating. The horizontal portion of the dielectric core layer overlying the top second insulating layer 232 may be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the top second insulating cap layer 232. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0099] See also Figure 9D and Figure 10 A doped semiconductor material having a second conductivity type can be deposited in the cavity overlying the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and portions of blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the top second insulating layer 232) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0100] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0101] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0102] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the interlayer memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed across the memory array region 100 of the first and second vertical alternating sequences, wherein all layers of the first and second vertical alternating sequences are present. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the interlayer memory opening 49 constitutes a memory opening filling structure 58. Generally speaking, the memory opening filling structure 58 is formed within the memory opening 49. Each of the memory opening filling structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0103] Each interlayer support opening may be filled with a corresponding set of material portions having the same material composition as the corresponding components in the memory opening filling structure 58. Each set of material portions filling the interlayer support opening is referred to herein as a support post structure 20. It should be noted that Figures 1B to 1E The memory opening fill structure 58 positioned in the memory array region 100 is shown in FIG. 1 and is not shown in FIG. 1 for clarity. Figures 1A to 1G The support pillar structure 20 is shown in FIG. The semiconductor material layer 110 , the first layer structure ( 132 , 142 , 165 ), the second layer structure ( 232 , 242 , 265 ), the memory opening filling structure 58 and the support pillar structure 20 together constitute a memory level assembly.

[0104] Generally speaking, the support post structure 20 is formed in the inter-array region 200. The support post structure 20 includes a first support post structure 20 and a second support post structure 20, wherein the first support post structure vertically extends through the dielectric well structure 365, the first layer of the backward stepped dielectric material portion 165, and a portion of the first layer of the alternating stack (132, 142) below the first layer of the backward stepped dielectric material portion 165, and the second support post structure vertically extends through the second layer of the backward stepped dielectric material portion 265, a portion of the second layer of the alternating stack (232, 242) below the second layer of the backward stepped dielectric material portion 265, and each layer within the first layer of the alternating stack (132, 142).

[0105] See also Figure 11 A contact-level dielectric layer 280 may be formed over the second vertical alternating sequence (232, 242). The contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be used.

[0106] See also Figure 12A and Figure 12B A photoresist layer (not shown) may be applied over the contact-level dielectric layer 280 and may be photolithographically patterned to form linear openings extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The pattern of the linear openings in the photoresist layer may be similar to Figures 1B to 1G The same pattern is shown for backside trench 79 fill structure 76. Linear openings in the photoresist layer may be formed in areas where memory opening fill structure 58 or support post structure 20 are not present.

[0107] The backside trenches 79 may be formed by transferring a pattern in a photoresist layer (not shown) through the contact level dielectric layer 280, the second layer structure (232, 242, 265, 365) and the first layer structure (132, 142, 165) into the semiconductor material layer 110. The pattern of the backside trenches 79 may be similar to that of the first layer structure (132, 142, 165). Figures 1B to 1G The backside trenches 79 shown have the same pattern as the fill structure 76. The contact-level dielectric layer 280, the second layer structures (232, 242, 265, 365), the first layer structures (132, 142, 165), and the portion below the linear opening in the photoresist layer of the semiconductor material layer 110 can be removed by an anisotropic etching process to form the backside trenches 79. In one embodiment, the backside trenches 79 can be formed between clusters of the memory stack structures 55. The clusters of the memory stack structures 55 can be laterally separated by the backside trenches 79 along the second horizontal direction hd2.

[0108] The backside trenches 79 may be formed as a periodic one-dimensional array having a periodicity along the second horizontal direction hd2. The backside trenches 79 may be numerically numbered sequentially from one side to the other along the second horizontal direction hd2 using positive integers. In one embodiment, each odd-numbered backside trench 79 may extend through the second vertical alternating sequence (232, 242) and the first vertical alternating sequence (132, 142) without etching through the first layer of backward stepped dielectric material portion 165, the second layer of backward stepped dielectric material portion 265, and the dielectric well structure 365. Each even-numbered backside trench 79 may extend through the second vertical alternating sequence (232, 242) and the first vertical alternating sequence (132, 142) and cut through the corresponding first layer of backward stepped dielectric material portion 165, the corresponding second layer of backward stepped dielectric material portion 265, and the corresponding dielectric well structure 365.

[0109] Each vertical alternating sequence {(132, 142), (232, 242)} is divided into a plurality of alternating stacks of insulating layers (132 or 232) and spacer material layers (such as sacrificial material layers (142, 242)) (e.g., memory blocks) by backside trenches 79. Each backside trench 79 can extend laterally along a first horizontal direction hd1 through the inter-array region 200 and a pair of memory array regions 100 adjacent to the inter-array region 200. Furthermore, each backside trench 79 can extend vertically through the entire thickness of the vertical alternating sequence {(132, 142), (232, 242)}. Each patterned portion of the first vertical alternating sequence (132, 142) positioned between adjacent pairs of backside trenches 79 constitutes a first alternating stack of first insulating layers 132 and first spacer material layers (such as first sacrificial material layers 142). Each patterned portion of the second vertical alternating sequence positioned between adjacent pairs of backside trenches 79 constitutes a second alternating stack of a second insulating layer 232 and a second spacer material layer, such as a second sacrificial material layer 242. Multiple alternating stacks of insulating layers (132 or 232) and spacer material layers (which may be the first sacrificial material layer 142 or the second sacrificial material layer 242) may be formed.

[0110] Each first-layer backward stepped dielectric material portion 165 is divided into two separate first-layer backward stepped dielectric material portions 165 by a backside trench 79. Each second-layer backward stepped dielectric material portion 265 is divided into two separate second-layer backward stepped dielectric material portions 265 by a backside trench 79. Each dielectric well structure 365 is divided into two separate dielectric well structures 365 by a backside trench 79.

[0111] See also Figure 13A and Figure 13BIf the spacer material layer includes a sacrificial material layer (142, 242), the sacrificial material layer (142, 242) is removed selectively to the insulating layer (132, 232), the contact-level dielectric layer 280, and the semiconductor material layer 110. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the material of the backward stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242) can include silicon nitride, and the material of the insulating layer (132, 232), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50 can include a silicon oxide material.

[0112] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0113] A backside recess is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess includes a first backside recess formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses can be greater than the height of the corresponding backside recess. Multiple backside recesses can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses can extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recess can be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the back-side recesses may have a uniform height throughout.

[0114] An optional backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses and backside trenches 79, and over the contact-level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide (e.g., aluminum oxide), silicon oxide, or combinations thereof.

[0115] At least one conductive material may be deposited in the plurality of backside recesses, on the sidewalls of the backside trenches 79, and over the contact-level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0116] In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess may be a combination of a titanium nitride layer and a tungsten filler material.

[0117] A conductive layer (146, 246) can be formed in the backside recess by depositing the at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses, a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses, and a continuous metal material layer (not shown) can be formed on the sidewalls of each backside trench 79 and above the contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a corresponding conductive metal nitride liner and a corresponding conductive filler material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0118] Residual conductive material can be removed from the interior of the backside trenches 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first conductive material layer 146 and the second conductive layer can be physically exposed to the corresponding backside trench 79. The backside trench 79 can have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a nonlinear width variation along the vertical direction.

[0119] Each conductive layer (146, 246) may be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) may be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) may be filled with a support pillar structure 20.

[0120] A subset of the conductive layers (146, 246) may include word lines for memory elements. The semiconductor devices in the semiconductor device 720 below may include word line switching devices (the word line switching devices are configured to control the bias voltage to the corresponding word lines) and / or bit line driver devices, such as sense amplifiers. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 vertically extending through the at least one alternating stack (132, 146, 232, 246). Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246).

[0121] In one embodiment, the semiconductor material layer 110 may have a doping of the same conductivity type as the vertical semiconductor channel 60 (i.e., the first conductivity type), and a source region 61 having a doping of the second conductivity type (the same conductivity type as the doping of the drain region 63) may be formed below each backside trench 79 by implanting a dopant of the second conductivity type. A dielectric liner comprising a dielectric material (such as silicon oxide) may be conformally deposited around the perimeter of each backside trench 79 and anisotropically etched to form dielectric spacers 76A within each backside trench 79. At least one conductive material may be deposited in the remaining volume of the backside trench 79, and excess portions of the at least one conductive material may be removed from above the top surface of the contact-level dielectric layer 280 by a planarization process. Each remaining portion of the at least one conductive material in contact with the source region 61 and laterally surrounded by a corresponding dielectric spacer 76A constitutes a backside contact via structure 76B extending laterally along a first horizontal direction hd1. Each continuous combination of the dielectric spacer 76A and the backside contact via structure 76B filling the backside trench 79 constitutes a backside trench filling structure 76 .

[0122] Alternatively, at least one dielectric material, such as silicon oxide, can be conformally deposited in the backside trench 79 by a conformal deposition process. Each portion of the deposited dielectric material that fills the backside trench 79 constitutes a backside trench fill structure 76. In this case, each backside trench fill structure can fill the entire volume of the backside trench 79 and can be essentially composed of at least one dielectric material. In this alternative embodiment, the source region 61 can be omitted, and the horizontal source line (e.g., a direct stripe contact) can contact the side of the lower portion of the semiconductor channel 60.

[0123] The backside trench filling structure 76 may be Figures 1B to 1G In one embodiment, each first-level backward stepped dielectric material portion 165, each second-level backward stepped dielectric material portion 265, and each dielectric well structure 365 is positioned between adjacent pairs of backside trench fill structures 76 and is laterally spaced apart from one backside trench fill structure 76 in the adjacent pair of backside trench fill structures.

[0124] See also Figure 14A and Figure 14B Various contact via structures (88, 86, 486) may be formed through the contact-level dielectric layer 280 and, optionally, through portions of the underlying material on corresponding underlying conductive structures. The various contact via structures (88, 86, 486) may include drain contact via structures (e.g., drain electrodes) 88 formed through the contact-level dielectric layer 280 on the top surfaces of corresponding drain regions 63 in the memory array region 100.

[0125] The various contact via structures (88, 86, 486) may include layer contact via structures 86 formed on a corresponding one of the conductive layers (146, 246) through the contact-level dielectric layer 280 and at least one backward stepped dielectric material portion (165, 265) in the inter-array region 200. The layer contact via structures 86 may include a first contact via structure 86A and a second contact via structure 86B, the first contact via structure being formed directly on a corresponding one of the first conductive layers 146 through a corresponding dielectric well structure 365 and a corresponding first-level backward stepped dielectric material portion 165, and the second contact via structure being formed directly on a corresponding one of the second conductive layers 246 through a second-level backward stepped dielectric material portion 265.

[0126] Additionally, laterally isolated vertical interconnect structures (484, 486) may be formed through the alternating stacks (132, 146, 232, 246) in the vertical interconnect via region 240. Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure 486 and a tubular insulating spacer 484 that laterally surrounds the conductive via structure 486. Each through-memory level conductive via structure 486 may contact a respective one of the lower-level metal interconnect structures 780 embedded within the lower-level dielectric material layer 760.

[0127] Bit lines (not shown) are then formed in a manner that provides electrical contact to the drain contact via structures 88. The bit lines may directly contact the top surfaces of the corresponding subset of the drain contact via structures 88, or an intermediate contact via structure (not shown) may be employed between the drain contact via structures 88 and the bit lines.

[0128] Embodiments of the present disclosure can be used to provide a staircase structure adjacent to one another along a direction (such as a second horizontal direction hd2, such as a bitline direction) perpendicular to a lateral separation direction (such as a first horizontal direction hd1, such as a wordline direction) between a pair of memory array regions (100A, 100B). The anisotropic etching process for forming wells through the second vertical alternating sequence (232, 242) etches only through the second vertical alternating sequence (232, 242) and not through the first vertical alternating sequence (132, 142). Furthermore, the openings in the photoresist layer for forming wells through the second vertical alternating sequence (232, 242) are staggered along the second horizontal direction hd2. Thus, the openings in the photoresist layer are laterally spaced apart along the second horizontal direction by at least the spacing of the backside trenches 79 along the second horizontal direction hd2. Thus, high aspect ratio openings in the photoresist layer used to pattern the wells can be avoided, and wells passing through the second vertical alternating sequence (232, 242) can be formed with high pattern fidelity. This high pattern fidelity ensures that the strip portions of the first conductive layer 146 and the second conductive layer 246 in the interlayer region 200 have sufficiently uniform widths along the second horizontal direction hd2 and do not produce electrical opens or high resistances. Therefore, by using the methods and structures of the embodiments of the present disclosure, the reliability of the electrical connection between the first conductive layer 146 and the second conductive layer 246 in the interlayer region 200 can be enhanced. In addition, by staggering adjacent steps in opposite directions (i.e., adjacent steps along the second horizontal direction hd2), such steps do not have to be offset from each other along the first horizontal direction hd1 to avoid high aspect ratio photoresist layer patterns. This reduces the size of the memory device and the semiconductor chip containing the memory device.

[0129] Although specific embodiments have been mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments using specific structures and / or configurations are shown in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, characterized in that: The three-dimensional memory device comprises: a first layer of a first insulating layer and a first conductive layer alternately stacked, the first layer alternately stacked being positioned above the substrate; a first layer of backward stepped dielectric material portion, the first layer of backward stepped dielectric material portion overlying the first layer of alternatingly stacked first stepped surfaces; a second layer alternating stack of a second insulating layer and a second layer of a second conductive layer, wherein the second layer alternating stack overlies the first layer alternating stack and overlies a horizontal plane including a flat top surface of a rearward stepped dielectric material portion of the first layer; a memory opening filling structure positioned within the first memory array region and extending vertically through each layer within the first alternating stack and the second alternating stack, wherein each of the memory opening filling structures includes a corresponding memory film and a corresponding vertical semiconductor channel; a second layer of rearwardly stepped dielectric material portion overlying the second stepped surface of the second layer of alternating stack and extending through the first lateral recessed region of the second layer of alternating stack; and A dielectric well structure contacts a top surface of the first layer of the rearward stepped dielectric material portion and extends through the second layer of the alternating stack of second lateral recessed portions.

2. The three-dimensional memory device of claim 1 , further comprising a first contact via structure extending vertically through the dielectric well structure and the first layer of backward stepped dielectric material portion and contacting a corresponding one of the first conductive layers. 3 . The three-dimensional memory device of claim 2 , further comprising a second contact via structure extending vertically through the second layer of backward stepped dielectric material portion and contacting a corresponding one of the second conductive layers.

4. The three-dimensional memory device according to claim 1 , further comprising: a first backside trench filling structure extending laterally along a first horizontal direction and contacting a first sidewall of the first layer of alternating stacks and a first sidewall of the second layer of alternating stacks; as well as A second backside trench filling structure extends laterally along the first horizontal direction and contacts a second sidewall of the first alternating stack and a second sidewall of the second alternating stack.

5. The three-dimensional memory device of claim 4 , wherein the dielectric well structure comprises a first tapered sidewall extending laterally along the first horizontal direction and positioned between and laterally spaced apart from each of the first and second backside trench filling structures.

6. The three-dimensional memory device according to claim 5, wherein: The dielectric well structure includes a pair of second tapered sidewalls extending laterally along a second horizontal direction; and An entirety of each of the second tapered sidewalls of the dielectric well structure contacts a corresponding sidewall of the alternating stack of second layers. 7 . The three-dimensional memory device of claim 1 , wherein an entire bottom surface of the dielectric well structure contacts a top surface of the first layer of backward stepped dielectric material.

8. The three-dimensional memory device of claim 7, wherein a first portion of a perimeter of the bottom surface of the dielectric well structure is laterally offset inward from a first portion of a perimeter of a top surface of the first layer of rearward stepped dielectric material portion.

9. The three-dimensional memory device of claim 1 , further comprising a second memory opening filling structure positioned within a second memory array region, the second memory array region being laterally offset from the first memory array region along a first horizontal direction by the second layer of the backward stepped dielectric material portion and the dielectric well structure, wherein each layer of the first alternating stack and each layer of the second alternating stack are present within the second memory array region.

10. The three-dimensional memory device of claim 9 , wherein at least some of the first conductive layers and at least some of the second conductive layers continuously extend from the first memory array region to the second memory array region through a bridge region and contact each of the second layer backward stepped dielectric material portion and the dielectric well structure.

11. The three-dimensional memory device of claim 1 , wherein the second layer of backward stepped dielectric material portion and the dielectric well structure comprise the same dielectric material and are laterally spaced apart from each other along the first horizontal direction by a portion of the second layer of alternating stacks extending laterally along a second horizontal direction perpendicular to the first horizontal direction.

12. The three-dimensional memory device according to claim 1 , further comprising: a first support post structure extending vertically through the dielectric well structure, the first layer of the backward stepped dielectric material portion, and a portion of the first layer of the alternating stack below the first layer of the backward stepped dielectric material portion; as well as A second support post structure extends vertically through the second layer of the back stepped dielectric material portion, a portion of the second layer of the alternating stack below the second layer of the back stepped dielectric material portion, and each layer in the first layer of the alternating stack.

13. The three-dimensional memory device according to claim 9, further comprising: an additional first layer alternating stack of additional first insulating layers and additional first conductive layers, the additional first layer alternating stack being positioned above the substrate; an additional first layer of rearwardly stepped dielectric material portions, the additional first layer of rearwardly stepped dielectric material portions overlying the additional first layer of alternately stacked additional first stepped surfaces; an additional second layer alternating stack of additional second insulating layers and additional second conductive layers, wherein the additional second layer alternating stack overlies the additional first layer alternating stack and overlies the horizontal plane including the flat top surface of the first layer rearward stepped dielectric material portion; an additional memory opening filling structure positioned within the additional memory array region and extending vertically through each layer within the additional first layer alternating stack and the additional second layer alternating stack; an additional second layer rearwardly stepped dielectric material portion overlying the additional second stepped surface of the additional second layer alternating stack and extending through the additional first lateral recessed portion region in the additional second layer alternating stack; an additional dielectric well structure contacting a top surface of the additional first layer rearward stepped dielectric material portion and extending through an additional second lateral recess region in the additional second layer alternating stack; as well as A backside trench filling structure extends laterally along a first horizontal direction and contacts the sidewalls of the first layer of alternating stacking, the sidewalls of the second layer of alternating stacking, the sidewalls of the additional first layer of alternating stacking, and the sidewalls of the additional second layer of alternating stacking.

14. The three-dimensional memory device according to claim 13, wherein: a lateral offset distance between the dielectric well structure and the additional second layer backward stepped dielectric material portion being smaller than a lateral offset distance between the dielectric well structure and the additional dielectric well structure; and A lateral offset distance between the second layer of backward stepped dielectric material portion and the additional dielectric well structure is smaller than a lateral offset distance between the second layer of backward stepped dielectric material portion and the additional second layer of backward stepped dielectric material portion.

15. The three-dimensional memory device according to claim 13, wherein: a vertical distance between the first stepped surface and the substrate increasing along a first horizontal direction; a vertical distance between the second stepped surface and the substrate increases along the first horizontal direction; a vertical distance between the additional first stepped surface and the substrate decreases along the first horizontal direction; and A vertical distance between the additional second stepped surface and the substrate decreases along the first horizontal direction.

16. A method for forming a three-dimensional memory device, characterized in that: The method comprises: forming a first vertically alternating sequence of a first insulating layer and a first spacer material layer over a substrate and a first layer of backward stepped dielectric material portion overlying a first stepped surface of the first vertically alternating sequence, wherein the first spacer material layer is formed as a first conductive layer or is subsequently replaced by the first conductive layer; forming a second vertical alternating sequence of a second insulating layer and a second spacer material layer over the first vertical alternating sequence and the first layer of backward stepped dielectric material portion, wherein the second spacer material layer is formed as a second conductive layer or is subsequently replaced by the second conductive layer; forming a second stepped surface through the second alternating stack by patterning the second alternating stack within the first opening; forming a second layer of backward stepped dielectric material portion in the first openings through the second vertical alternating sequence above the second stepped surface; forming a second opening above the first layer of backward stepped dielectric material portion through the second vertical alternating sequence; and A dielectric well structure is formed on a top surface of the first layer of backward stepped dielectric material portion through the second vertical alternating sequence.

17. The method according to claim 16, wherein: the second openings through the second vertical alternating sequence are laterally spaced from the first openings through the second vertical alternating sequence; and The dielectric well structure is laterally spaced apart from the second layer of backward stepped dielectric material portion by the patterned portion of the second vertical alternating sequence.

18. The method according to claim 16, further comprising: forming a first contact via structure directly on a corresponding one of the first conductive layers through the dielectric well structure and the first layer of backward stepped dielectric material portion; as well as A second contact via structure is formed through the second layer of backward stepped dielectric material portion directly on a corresponding one of the second conductive layers.

19. The method according to claim 16, further comprising: forming a memory opening in a first memory array area wherein each layer of the first vertical alternating sequence and each layer of the second vertical alternating sequence exists; as well as Memory opening filling structures are formed in the memory openings, wherein each of the memory opening filling structures includes a corresponding memory film and a corresponding vertical semiconductor channel.

20. The method of claim 16, further comprising: forming backside grooves through the second vertical alternating sequence and the first vertical alternating sequence, wherein each of the backside grooves extends laterally in a first horizontal direction; as well as A backside trench filling structure is formed in the backside trench, wherein each of the first layer of backward stepped dielectric material portion, the second layer of backward stepped dielectric material portion, and the dielectric well structure is positioned between adjacent pairs in the backside trench filling structure and is laterally spaced apart from each of the adjacent pairs in the backside trench filling structure.

Images