A conversion device, method and integrated circuit

Abstract

The present application provides a conversion device, method and integrated circuit, the device includes: a bus and interface standard PCIE message scheduling module, a first PCIE message conversion module and a second PCIE message conversion module, a PCIE message scheduling module, which is used to receive the first PCIE message and the second PCIE message, and send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel according to the scheduling strategy; the first PCIE message conversion module is used to obtain a first local bus message according to the first PCIE message; the second PCIE message conversion module is used to obtain a second local bus message according to the second PCIE message. The above-mentioned conversion device can perform pipeline processing on multiple PCIE messages in parallel, so that the access bandwidth is larger and the efficiency of data transmission is improved.

Description

Technical Field

[0001] The present application relates to the field of network communications, and more specifically, to a conversion device, a conversion method and an integrated circuit. Background Art

[0002] With the continuous development of the Internet Protocol (IP), a master device can access a slave device and exchange data with the slave device. As an example, a processor (e.g., a central processing unit (CPU)) as a master device can exchange data with an external device (e.g., a chip or a single board) as a slave device. In the above data exchange process, the bandwidth requirements and cost requirements need to be met between the master device and the slave device.

[0003] In order to meet the cost requirement of CPU access to external devices, in the related technical solution, the CPU can access the local bus of the external device through the PCIE protocol. In this technical solution, the external device can only support access to a single local bus interface and does not support concurrent processing of multiple data packets, so that the access bandwidth is limited and the data transmission efficiency is reduced. Summary of the invention

[0004] The present application provides a conversion device, a conversion method and an integrated circuit, which can perform pipeline processing on multiple PCIE messages in parallel, so that the access bandwidth is larger and the efficiency of data transmission is improved.

[0005] In a first aspect, a conversion device is provided, comprising: a bus and interface standard PCIE message scheduling module, a first PCIE message conversion module and a second PCIE message conversion module,

[0006] The PCIE message scheduling module is used to receive the first PCIE message and the second PCIE message, and send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel according to the scheduling strategy;

[0007] The first PCIE message conversion module is used to obtain a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface;

[0008] The second PCIE message conversion module is used to obtain a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

[0009] The conversion device can concurrently perform pipeline processing on multiple PCIE messages, thereby increasing the access bandwidth and improving the efficiency of data transmission.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the PCIE message scheduling module is specifically used to: send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel according to access addresses of the first PCIE message and the second PCIE message.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the PCIE message scheduling module is further used to send the first PCIE message to the first PCIE message conversion module according to the cache of the first PCIE message conversion module, and to send the second PCIE message to the second PCIE message conversion module according to the cache of the second PCIE message conversion module.

[0012] In combination with the first aspect, in some implementations of the first aspect, the device further includes: a PCIE collection module,

[0013] The first PCIE message conversion module is further used to receive a first local bus response message sent by the first local bus interface, obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message to the PCIE collection module;

[0014] The second PCIE message conversion module is further used to receive a second local bus response message sent by the second local bus interface, obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message to the PCIE collection module;

[0015] The PCIE collection module is used to obtain and send the first PCIE response message and the second PCIE response message.

[0016] In combination with the first aspect, in certain implementations of the first aspect, the first PCIE message conversion module is further used to send the first PCIE response message to the PCIE collection module according to the cache of the PCIE collection module; the second PCIE message conversion module is further used to send the second PCIE response message to the PCIE collection module according to the cache of the PCIE collection module.

[0017] In a second aspect, a conversion method is provided, including: a bus and interface standard PCIE message scheduling module receives a first PCIE message and a second PCIE message; the PCIE message scheduling module sends the first PCIE message to a first PCIE message conversion module and sends the second PCIE message to a second PCIE message conversion module in parallel according to a scheduling strategy; the first PCIE message conversion module obtains a first local bus message according to the first PCIE message, and the first local bus message is a message that can be recognized by the first local bus interface; the second PCIE message conversion module obtains a second local bus message according to the second PCIE message, and the second local bus message is a message that can be recognized by the second local bus interface.

[0018] In combination with the second aspect, in certain implementations of the second aspect, the PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module and sends the second PCIE message to the second PCIE message conversion module in parallel based on access addresses of the first PCIE message and the second PCIE message.

[0019] In combination with the second aspect, in some implementations of the second aspect, the method also includes: the PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module according to the cache of the first PCIE message conversion module, and sends the second PCIE message to the second PCIE message conversion module according to the cache of the second PCIE message conversion module.

[0020] In combination with the second aspect, in some implementations of the second aspect, the method also includes: the first PCIE message conversion module receives a first local bus response message sent by the first local bus interface, obtains a first PCIE response message based on the first local bus response message, and sends the first PCIE response message to the PCIE collection module; the second PCIE message conversion module receives a second local bus response message sent by the second local bus interface, obtains a second PCIE response message based on the second local bus response message, and sends the second PCIE response message to the PCIE collection module; the PCIE collection module obtains and sends the first PCIE response message and the second PCIE response message.

[0021] In combination with the second aspect, in some implementations of the second aspect, the method also includes: the first PCIE message conversion module sends the first PCIE response message to the PCIE collection module according to the cache of the PCIE collection module; the second PCIE message conversion module sends the second PCIE response message to the PCIE collection module according to the cache of the PCIE collection module.

[0022] In a third aspect, an integrated circuit is provided, comprising: a bus and interface standard PCIE message scheduling circuit, a first PCIE message conversion circuit and a second PCIE message conversion circuit,

[0023] The PCIE message scheduling circuit is used to receive a first PCIE message and a second PCIE message, and send the first PCIE message to the first PCIE message conversion circuit and send the second PCIE message to the second PCIE message conversion circuit in parallel according to a scheduling strategy;

[0024] The first PCIE message conversion circuit is used to obtain a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface;

[0025] The second PCIE message conversion circuit is used to obtain a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

[0026] In combination with the third aspect, in certain implementations of the third aspect, the PCIE message scheduling circuit is specifically used to: send the first PCIE message to the first PCIE message conversion circuit and send the second PCIE message to the second PCIE message conversion circuit in parallel according to access addresses of the first PCIE message and the second PCIE message.

[0027] In combination with the third aspect, in certain implementations of the third aspect, the PCIE message scheduling circuit is further used to send the first PCIE message to the first PCIE message conversion circuit according to the cache of the first PCIE message conversion circuit, and to send the second PCIE message to the second PCIE message conversion circuit according to the cache of the second PCIE message conversion circuit.

[0028] In combination with the third aspect, in some implementations of the third aspect, the integrated circuit further includes: a PCIE collection circuit,

[0029] The first PCIE message conversion circuit is further used to receive a first local bus response message sent by the first local bus interface, obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message to the PCIE collection circuit;

[0030] The second PCIE message conversion circuit is further used to receive a second local bus response message sent by the second local bus interface, obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message to the PCIE collection circuit;

[0031] The PCIE collection circuit is used to obtain and send the first PCIE response message and the second PCIE response message.

[0032] In combination with the third aspect, in certain implementations of the third aspect, the first PCIE message conversion circuit is further used to send the first PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit; the second PCIE message conversion circuit is further used to send the second PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit.

[0033] In combination with the third aspect, in some implementations of the third aspect, the integrated circuit further includes: a PCIE interface circuit, a first local bus interface circuit, a second local bus interface circuit,

[0034] The PCIE interface circuit is used to send the first PCIE message and the second PCIE message to the PCIE message scheduling circuit;

[0035] The first local bus interface circuit is used to receive the first local bus message;

[0036] The second local bus interface circuit is used to receive the second local bus message.

[0037] Optionally, the integrated circuit may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0038] In a fourth aspect, a conversion device is provided, comprising an input / output interface, a processor and a memory, wherein the processor is used to control the input / output interface to send and receive information, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the conversion device executes the method described in the second aspect or any possible implementation method of the second aspect.

[0039] Optionally, the processor may be a general-purpose processor, which may be implemented by hardware or software. When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor may be a general-purpose processor implemented by reading software code stored in a memory, which may be integrated in the processor or located outside the processor and exist independently.

[0040] In a fifth aspect, a computer program product is provided, comprising: a computer program code, which, when executed on a computer, enables the computer to execute the method described in the second aspect or any possible implementation of the second aspect.

[0041] In a sixth aspect, a computer readable and writable medium is provided, wherein the computer readable and writable medium stores program code, data to be processed, etc. When the computer program code is executed on a computer, the computer executes the method described in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic block diagram of a conversion device 100 provided in an embodiment of the present application.

[0043] Figure 2 It is a schematic flow chart of a conversion method provided in an embodiment of the present application.

[0044] Figure 3It is a schematic block diagram of another conversion device 300 provided in an embodiment of the present application.

[0045] Figure 4 It is a schematic block diagram of another conversion device 400 provided in an embodiment of the present application.

[0046] Figure 5 It is a schematic block diagram of an integrated circuit 500 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0048] With the continuous development of the Internet Protocol (IP), a master device can access a slave device and exchange data with the slave device. As an example, a processor (e.g., a central processing unit (CPU)) as a master device can exchange data with an external device (e.g., a chip or a single board) as a slave device. In the above data exchange process, the bandwidth requirements and cost requirements need to be met between the master device and the slave device.

[0049] For ease of description, the following explanation is given by taking the master device as a CPU and the slave device as an external device as an example.

[0050] Taking the CPU's read-write interface as a local bus standard interface as an example, the CPU can access external devices through a local bus interface. If the CPU needs to access multiple external devices, whether the CPU is a single-core CPU or a multi-core CPU, since there is only one local bus interface, the CPU can only access multiple external devices through the local bus interface in a time-division multiplexing manner. In this way, the bus access cycle is long, and the local bus bandwidth cannot meet the system's external device access bandwidth requirements. Taking the CPU's read-write interface as a bus and interface standard (Peripheral Component Interface Express, PCIE) as an example, the CPU can access external devices through PCIE. PCIE is a high-speed serial interface protocol, which is characterized by high-speed serial point-to-point transmission and has a high bandwidth. In this implementation method, external devices need to support the PCIE interface, and the implementation cost is relatively high.

[0051] In order to meet the cost requirement of CPU access to external devices, in the related technical solution, the CPU can access the local bus of the external device through the PCIE protocol. In this technical solution, the external device can only support access to a single local bus interface and does not support concurrent processing of multiple data packets, so that the access bandwidth is limited and the data transmission efficiency is reduced.

[0052] In view of this, the embodiment of the present application provides a conversion device that can simultaneously meet the implementation cost requirements and bandwidth requirements of the master device accessing the slave device. Figure 1 , the conversion device provided in the embodiment of the present application is described in detail.

[0053] Figure 1 is a schematic block diagram of a conversion device 100 provided in an embodiment of the present application. Figure 1 As shown, the conversion device 100 may include a PCIE message scheduling module 110 , a first PCIE message conversion module 120 and a second PCIE message conversion module 130 .

[0054] The PCIE message scheduling module 110 is used to obtain the first PCIE message and the second PCIE message, and send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel based on the scheduling strategy. In one example, the PCIE message scheduling module 110 can send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel based on the access addresses of the first PCIE message and the second PCIE message. In another example, the PCIE message scheduling module 110 can also perform fair parallel scheduling of the first PCIE message and the second PCIE message between the ports of the first PCIE message conversion module 120 and the second PCIE message conversion module 130 based on the scheduling strategy of weighted round robin (WRR), without priority. In another example, the PCIE message scheduling module 110 can also distinguish the priorities of the first PCIE message conversion module 120 and the second PCIE message conversion module 130 based on a strict prior (SP) scheduling strategy, and the priority of the first PCIE message conversion module 120 with a higher real-time requirement is higher than the priority of the second PCIE message conversion module 130 with a lower real-time requirement. In another example, the PCIE message scheduling module 110 can also schedule the first PCIE message and the second PCIE message fairly and in parallel between the ports of the first PCIE message conversion module 120 and the second PCIE message conversion module 130 based on the WRR+SP scheduling strategy, and can also solve the real-time problem.

[0055] Optionally, the PCIE message scheduling module 110 may also send the first PCIE message to the first PCIE message conversion module according to the cache of the first PCIE message conversion module. Send the second PCIE message to the second PCIE message conversion module according to the cache of the second PCIE message conversion module. Such an upper module (e.g., PCIE message scheduling module 110) controls whether to send a message to a lower module according to the cache of a lower module (e.g., the first PCIE message conversion module 120 and / or the second PCIE message conversion module 130), which can maximize the PCIE capability.

[0056] The first PCIE message conversion module 120 can process the received PCIE message in parallel with the second PCIE message conversion module 130. In the sending direction of the PCIE message, after receiving the first PCIE message, it is used to cache the first PCIE message, convert the first PCIE message into a first local bus message that can be recognized by the first local bus interface, and send the first local bus message to the first local bus interface. For example, the first PCIE message conversion module 120 can obtain the key access information of the first PCIE message based on the PCIE protocol, and the key access information may include but is not limited to: the starting address of the master device accessing the slave device, the access length, the read and write command type, the First DW BE / Last DW BE and other key information of PCIE access. And convert the key access information of the first PCIE message into the format required for the first local bus access (first local bus message), for example, the access start address and end address, the byte / word / double word access attribute, the access data length, the number of local bus accesses, the read and write commands and other key information. In the receiving direction of the PCIE message, the first PCIE message conversion module 120 is also used to cache the first local bus response message received from the first local bus interface. The first local bus response message includes data read by the first local bus interface, PCIE access status, and the corresponding PCIE message return required 3DW / 4DW and other information. The first PCIE message conversion module 120 can also obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message.

[0057] The second PCIE message conversion module 130 can process the received PCIE message in parallel with the first PCIE message conversion module 120. For example, in the sending direction of the PCIE message, after receiving the second PCIE message, it is used to cache the second PCIE message and convert the second PCIE message into a second local bus message that can be recognized by the first local bus interface, and send the second local bus message to the second local bus interface. In the receiving direction of the PCIE message, the second PCIE message conversion module 130 is also used to cache the second local bus response message received from the second local bus interface. The second local bus response message includes data read by the second local bus interface, PCIE access status, and the corresponding PCIE message return required 3DW / 4DW and other information. The second PCIE message conversion module 130 can also obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message.

[0058] Optionally, the above-mentioned conversion device 100 also includes: a PCIE collection module 140, which is used to obtain a first PCIE response message from the first PCIE message conversion module 120, obtain a second PCIE response message from the second PCIE message conversion module 130, and send the first PCIE response message and the second PCIE response message to the PCIE interface.

[0059] Optionally, in the PCIE message receiving direction, the first PCIE message conversion module 120 is further configured to send the first PCIE response message to the PCIE collection module according to the cache of the PCIE collection module 140 .

[0060] Optionally, in the PCIE message receiving direction, the second PCIE message conversion module 130 is further configured to send the second PCIE response message to the PCIE collection module 140 according to the cache of the PCIE collection module.

[0061] Combine the following Figure 2 , a conversion method provided in an embodiment of the present application is described in detail. Figure 2 As shown, the method may include steps 210-240, and steps 210-240 are described in detail below.

[0062] Step 210: The bus and interface standard PCIE message scheduling module 110 receives the first PCIE message and the second PCIE message.

[0063] The PCIE message scheduling module 110 may receive a first PCIE message and a second PCIE message from a PCIE slave standard interface. As an example, the first PCIE message and the second PCIE message may be sent by a master device to the PCIE slave standard interface.

[0064] It should be understood that the PCIE slave standard interface is a standard part of the PCIE interface, which is used to implement the PCIE underlying protocol so that the conversion device 100 can work as a PCIE slave device. Specifically, the first PCIE message and the second PCIE message sent by the master device can be received. It should be understood that the first PCIE message and the second PCIE message can be PCIE write messages, or can also be PCIE read messages, and this application does not make specific limitations on this. Among them, the PCIE write message indicates that data needs to be written to the slave device, and the PCIE read message indicates that data stored in the slave device needs to be read.

[0065] Step 220: the PCIE message scheduling module 110 sends the first PCIE message to the first PCIE message conversion module 120 and sends the second PCIE message to the second PCIE message conversion module 130 in parallel according to the scheduling strategy.

[0066] After the PCIE message scheduling module 110 obtains the first PCIE message and the second PCIE message, it can send the first PCIE message to the first PCIE message conversion module 120 and send the second PCIE message to the second PCIE message conversion module 130 in parallel based on the scheduling strategy. In one example, the PCIE message scheduling module 110 can send the first PCIE message to the first PCIE message conversion module 120 and send the second PCIE message to the second PCIE message conversion module 130 in parallel based on the access addresses of the first PCIE message and the second PCIE message. For other scheduling strategies, please refer to the description of the PCIE message scheduling module 110 above, which will not be repeated here.

[0067] Step 230: The first PCIE message conversion module 120 obtains a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface.

[0068] After the first PCIE message conversion module 120 obtains the first PCIE message, the first PCIE message can be cached. The first PCIE message is converted into a first local bus message that can be recognized by the first local bus interface, and the first local bus message is sent to the first local bus interface. For the specific implementation method of obtaining the first local bus message according to the first PCIE message, please refer to the description of the first PCIE message conversion module 120 above, which will not be repeated here.

[0069] It should be understood that after the first local bus interface obtains the first local bus message, it can determine the information required for each local bus write operation (or each timing), for example, the access start address and end address corresponding to each timing, byte / word / double word access attributes, access data length, read and write commands and other key information, so as to perform local bus access of arbitrary length of byte / word / double word. And based on the above information required for each timing, the local bus write operation is completed until all write data of the first PCIE message is processed.

[0070] Step 240: the second PCIE message conversion module 130 obtains a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

[0071] The second PCIE message conversion module 130 and the first PCIE message conversion module 120 process the received PCIE message in parallel. The method by which the second PCIE message conversion module 130 processes the second PCIE message is similar to the method by which the first PCIE message conversion module 130 processes the first PCIE message. For details, please refer to the method by which the first PCIE message conversion module 130 processes the first PCIE message in step 230, which will not be repeated here.

[0072] The forwarding device and conversion method provided above can perform pipeline processing on multiple PCIE messages in parallel, so that the access bandwidth is larger and the efficiency of data transmission is improved.

[0073] Optionally, in the receiving direction of the PCIE message, the first PCIE message conversion module 120 is also used to cache the first local bus response message received from the first local bus interface. The first PCIE response message is obtained according to the first local bus response message, and the first PCIE response message is sent to the PCIE collection module 140. Similarly, the second PCIE message conversion module 130 is also used to cache the second local bus response message received from the second local bus interface. The second PCIE response message is obtained according to the second local bus response message, and the second PCIE response message is sent to the PCIE collection module 140. After the PCIE collection module obtains the first PCIE response message and the second PCIE response message from the first PCIE message conversion module 120 and the second PCIE response message from the second PCIE message conversion module 130 respectively, the first PCIE response message and the second PCIE response message are sent to the PCIE slave standard interface, thereby completing the return processing of the PCIE message.

[0074] Optionally, the embodiment of the present application also supports a back pressure mechanism. It should be understood that the back pressure mechanism can be that the upstream module schedules / stops scheduling packets according to the bandwidth of the downstream module. In this way, the cache of the downstream module can be controlled by the back pressure mechanism, and the message is sent down and the data is sent up based on the empty and full state, so that the cache capacity is maximized and the operation efficiency and bandwidth are improved. As an example, if the bandwidth of the downstream module is less than the bandwidth of the upstream module, the upstream module can stop scheduling data packets to the downstream module; if the bandwidth of the downstream module is greater than the bandwidth of the upstream module, the upstream module can schedule data packets to the downstream module.

[0075] In the sending direction of the above PCIE message, for example, if the bandwidth of the first PCIE message conversion module 120 is smaller than the bandwidth of the PCIE message scheduling module 110, the PCIE message scheduling module 110 may stop scheduling the first PCIE message to the first PCIE message conversion module 120. For another example, if the bandwidth of the second PCIE message conversion module 130 is smaller than the bandwidth of the PCIE message scheduling module 110, the PCIE message scheduling module 110 may stop scheduling the first PCIE message to the second PCIE message conversion module 130.

[0076] In the receiving direction of the above PCIE message, for example, the bandwidth of the PCIE collection module 140 is less than the bandwidth of the first PCIE message conversion module 120, and the first PCIE message conversion module 120 can stop scheduling the first PCIE response message to the PCIE collection module 140. For another example, the second PCIE message conversion module 130 can stop scheduling the second PCIE response message to the PCIE collection module 140.

[0077] Figure 3 is a schematic block diagram of another conversion device 300 provided in an embodiment of the present application. Figure 3 As shown, the conversion device 300 includes: a sender (transport, TX) multi-port polling scheduling module 320, a receiver (receive, RX) multi-port polling scheduling module 330, 1 to N PCIE TX packet caching and parsing modules 340, 1 to N PCIE TX message conversion preprocessing modules 350, 1 to N PCIE RX message conversion preprocessing modules 360, 1 to N PCIE RX packet caching and encapsulation modules 370, and an abnormal packet processing module 390.

[0078] The TX multi-port polling scheduling module 320 is used to complete the message scheduling in the TX direction between 1 to N PCIE TX packet buffers and parsing modules 340. For example, based on the access address of the PCIE message, multiple PCIE messages can be respectively scheduled and cached in the corresponding 1 to N PCIE TX packet buffers and parsing modules 340.

[0079] The RX multi-port polling scheduling module 330 is used to complete the message scheduling in the RX direction between 1 to N PCIE RX packet buffers and encapsulation modules 370. For example, based on the empty or full state of the 1 to N PCIE RX packet buffers and encapsulation modules 370, the PCIE RX message can be sent to the PCIE slave standard interface module 310 according to a certain scheduling strategy.

[0080] The PCIE TX packet buffering and parsing module 340 is used to buffer multiple received PCIE TX messages, parse and buffer the key information of each PCIE TX message accessing the PCIE, and output it to 1 to N PCIE TX message conversion preprocessing modules 350. The key information may include but is not limited to: the starting address of the master device accessing the slave device, the access length, the read and write command type, the First DW BE / Last DW BE and other key information of PCIE access.

[0081] The PCIE TX message conversion preprocessing module 350 is used to obtain the key information of the PCIE TX message accessing the PCIE from the corresponding PCIE TX packet buffering and parsing module 340, and convert the key information of the PCIE accessing into the format required for the local bus access, for example, the access start address and end address, byte / word / double word access attributes, access data length, local bus access times, read and write commands and other key information.

[0082] The PCIE RX message conversion preprocessing module 360 ​​caches the data and status information returned from the local bus interface, and the information related to the PCIE message header 3DW / 4DW, so as to perform subsequent encapsulation processing.

[0083] The PCIE RX packet buffering and encapsulation module 370 is used to obtain the above-mentioned related information from the corresponding PCIE RX message conversion preprocessing module 360, encapsulate the data into a PCIE message according to the information, and send it to the RX multi-port polling scheduling module 330.

[0084] The abnormal packet processing module 390 mainly caches packets that do not meet expectations and returns corresponding information so that the host device can release PCIE resources as soon as possible, provide opportunities and resources for other accesses, and improve access efficiency and bandwidth under abnormal circumstances.

[0085] Take the write process as an example. The TX multi-port polling scheduling module 320 receives multiple PCIE write messages, and sends the cached multiple PCIE write messages to the corresponding 1 to N PCIE TX packet cache and parsing modules 340 based on the scheduling strategy. After obtaining the corresponding multiple PCIE write messages, each PCIE TX packet cache and parsing module 340 can obtain the key access information of the PCIE write message based on the PCIE protocol, and send it to the corresponding PCIE TX message conversion preprocessing module 350. Each PCIETX message conversion preprocessing module 350 is used to obtain the key information of the PCIE TX message accessing the PCIE from the corresponding PCIE TX packet cache and parsing module 340, and convert the key information of the PCIE access to the format required for the local bus access and send it to the local bus interface connected thereto. For example, access start address and end address, byte / word / double word access attributes, access data length, number of local bus accesses, read and write commands and other key information.

[0086] Take the reading process as an example. The PCIE RX message conversion preprocessing module 360 ​​receives the data and status information returned by the local bus interface, as well as the information related to the PCIE message header 3DW / 4DW, so as to perform subsequent encapsulation processing. The PCIE RX packet buffer and encapsulation module 370 obtains the above information from the corresponding PCIE RX message conversion preprocessing module 360, encapsulates the data into a PCIE message according to the information, and sends it to the RX multi-port polling scheduling module 330. The RX multi-port polling scheduling module 330 can obtain PCIE messages from 1 to N PCIE RX packet buffers and encapsulation modules 370 based on the fullness of 1 to N PCIE RX packet buffers and encapsulation modules 370, according to a certain scheduling strategy, and send the PCIE RX message to the PCIE slave standard interface. The PCIE slave standard interface obtains the PCIE RX message and sends it to the master device, thereby completing the return processing of the PCIE message.

[0087] Figure 4 is a schematic block diagram of another conversion device 400 provided in an embodiment of the present application. Figure 4 As shown, the conversion device 400 includes: a PCIE TX message buffer module 420, a TX multi-port polling scheduling module 430, a PCIE TX message parsing module 440, 1 to N PCIE TX message conversion preprocessing modules 450, 1 to N PCIE RX message conversion preprocessing modules 470, an RX multi-port polling scheduling module 480, a PCIE RX packet module 490, and an abnormal packet processing module 495.

[0088] It should be understood that Figure 4 The conversion device 400 converts the TX direction message cache and parsing by Figure 3Change the distributed mode in the RX direction to centralized mode. Figure 3 In other words, Figure 4 In Figure 3 1 to N PCIE TX packet buffering and parsing modules 340 are deleted, and a PCIE TX message buffering module 420 and a PCIE TX message parsing module 440 are newly added. Figure 3 The 1 to N PCIE RX packet buffering and encapsulation modules 370 are deleted, and a new PCIE RX encapsulation module 490 is added. Such a centralized deployment can save the number of modules, thereby further reducing the volume of the conversion device 400 and saving production costs.

[0089] The PCIE TX message buffer module 420 is used to buffer all PCIE TX messages.

[0090] The PCIE TX message parsing module 440 is used to parse the PCIE TX message, obtain key information for each PCIE TX message to access the PCIE, and send 1 to N PCIE TX message conversion preprocessing modules 450 respectively.

[0091] The PCIE RX packetization module 490 is used to perform unified packetization processing on all data read and returned from the local bus interface based on the relevant information required for PCIE encapsulation sent by 1 to N PCIE RX message conversion preprocessing modules 470 to obtain multiple encapsulated PCIE messages.

[0092] Other modules’ functions and Figure 3 The functions are the same as in, please refer to Figure 3 The description in will not be repeated here.

[0093] Take the writing process as an example. The PCIE TX message buffer module 420 receives multiple PCIE write messages and sends the cached multiple PCIE write messages to the TX multi-port polling scheduling module 430. The TX multi-port polling scheduling module 430 can send the cached multiple PCIE write messages to the PCIE TX message parsing module 440 based on the scheduling strategy (for example, the access address of the PCIE write message). As an example, the PCIE write message may include the port number sent to the corresponding 1 to N PCIE TX message conversion preprocessing modules 450. The PCIE RX message parsing module 440 can obtain the key access information of the PCIE write message based on the PCIE protocol, and send the key access information of the PCIE write message to the corresponding PCIE TX message conversion preprocessing module 450 based on the port number in the PCIE write message. Each PCIE TX message conversion preprocessing module 450 is used to obtain the key information of the PCIE TX message accessing the PCIE, convert the key information of the PCIE accessing into the format required for the local bus access and send it to the corresponding local bus interface. The local bus interface obtains the access information corresponding to each PCIE write message, such as the access start address, byte / word / double word access attribute, access data length, read / write command and other key information, and adapts based on the local bus width, converting it into the information required for each local bus write operation (or each timing sequence), including: access start and end address, access byte / word / double word attribute, local bus access times, read / write command, etc. The local bus interface can complete the local bus write operation based on the above information required for each timing sequence until all write data of the PCIE write message is processed.

[0094] Take the reading process as an example. Each PCIE RX message conversion preprocessing module 470 receives and caches the data and status information returned by the corresponding local bus interface, and the information related to the PCIE message header 3DW / 4DW, so as to perform subsequent encapsulation processing. The RX multi-port polling scheduling module 480 can send the data and status information cached by each PCIE RX message conversion preprocessing module 470, and the information related to the PCIE message header 3DW / 4DW to the PCIE RX packetization module 490 based on the scheduling strategy. The PCIERX packetization module 490 performs unified packetization processing on all data read from the local bus interface based on the relevant information required for encapsulating PCIE obtained from 1 to N PCIE RX message conversion preprocessing modules 470, obtains multiple encapsulated PCIE messages, and sends them to the host device, thereby completing the return processing of the PCIE message.

[0095] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] Figure 5 1 is a schematic block diagram of an integrated circuit 500 provided in an embodiment of the present application. The integrated circuit 500 includes: a bus and interface standard PCIE message scheduling circuit 510, a first PCIE message conversion circuit 520 and a second PCIE message conversion circuit 530,

[0097] The PCIE message scheduling circuit 510 is used to receive a first PCIE message and a second PCIE message, and send the first PCIE message to the first PCIE message conversion circuit 520 and send the second PCIE message to the second PCIE message conversion circuit 530 in parallel according to a scheduling strategy;

[0098] The first PCIE message conversion circuit 520 is used to obtain a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface;

[0099] The second PCIE message conversion circuit 530 is used to obtain a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

[0100] Optionally, the PCIE message scheduling circuit 510 is specifically used to: send the first PCIE message to the first PCIE message conversion circuit and send the second PCIE message to the second PCIE message conversion circuit in parallel according to access addresses of the first PCIE message and the second PCIE message.

[0101] Optionally, the PCIE message scheduling circuit 510 is further used to send the first PCIE message to the first PCIE message conversion circuit according to the cache of the first PCIE message conversion circuit, and to send the second PCIE message to the second PCIE message conversion circuit according to the cache of the second PCIE message conversion circuit.

[0102] Optionally, the integrated circuit 500 further includes: a PCIE collection circuit 540,

[0103] The first PCIE message conversion circuit 520 is further configured to receive a first local bus response message sent by the first local bus interface, obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message to the PCIE collection circuit;

[0104] The second PCIE message conversion circuit 530 is further configured to receive a second local bus response message sent by the second local bus interface, obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message to the PCIE collection circuit;

[0105] The PCIE collection circuit 540 is used to obtain and send the first PCIE response message and the second PCIE response message.

[0106] Optionally, the first PCIE message conversion circuit 520 is further used to send the first PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit; the second PCIE message conversion circuit 530 is further used to send the second PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit.

[0107] Optionally, the integrated circuit 500 further includes: a PCIE interface circuit 550, a first local bus interface circuit 560, a second local bus interface circuit 570,

[0108] The PCIE interface circuit 550 is used to send the first PCIE message and the second PCIE message to the PCIE message scheduling circuit 510;

[0109] The first local bus interface circuit 560 is used to receive the first local bus message;

[0110] The second local bus interface circuit 570 is used to receive the second local bus message.

[0111] The integrated circuit 500 may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0112] An embodiment of the present application also provides a computer-readable and writable storage medium, in which readable instructions and writable data to be processed are stored, and the instructions and data are used in the method in the above method embodiment.

[0113] The embodiment of the present application also provides a computer program product including instructions, wherein the instructions are used to implement the method in the above method embodiment.

[0114] In one implementation example, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0115] In one implementation example, the memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0116] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable and writable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0122] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A conversion device, characterized in that: include: Bus and interface standard PCIE message scheduling module, first PCIE message conversion module and second PCIE message conversion module, The PCIE message scheduling module is used to receive the first PCIE message and the second PCIE message, and send the first PCIE message to the first PCIE message conversion module and send the second PCIE message to the second PCIE message conversion module in parallel according to the scheduling strategy; The first PCIE message conversion module is used to obtain a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface; The second PCIE message conversion module is used to obtain a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

2. The device according to claim 1, characterized in that The PCIE message scheduling module is specifically used for: According to the access addresses of the first PCIE message and the second PCIE message, the first PCIE message is sent to the first PCIE message conversion module and the second PCIE message is sent to the second PCIE message conversion module in parallel.

3. The device according to claim 1, characterized in that The PCIE message scheduling module is further used to send the first PCIE message to the first PCIE message conversion module according to the cache of the first PCIE message conversion module, and send the second PCIE message to the second PCIE message conversion module according to the cache of the second PCIE message conversion module.

4. The device according to any one of claims 1 to 3, characterized in that The device also includes: a PCIE collection module, The first PCIE message conversion module is further used to receive a first local bus response message sent by the first local bus interface, obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message to the PCIE collection module; The second PCIE message conversion module is further used to receive a second local bus response message sent by the second local bus interface, obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message to the PCIE collection module; The PCIE collection module is used to obtain and send the first PCIE response message and the second PCIE response message.

5. The device according to claim 4, characterized in that The first PCIE message conversion module is further configured to send the first PCIE response message to the PCIE collection module according to the cache of the PCIE collection module; The second PCIE message conversion module is further used to send the second PCIE response message to the PCIE collection module according to the cache of the PCIE collection module.

6. A conversion method, characterized in that: The method comprises: The bus and interface standard PCIE message scheduling module receives the first PCIE message and the second PCIE message; The PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module and sends the second PCIE message to the second PCIE message conversion module in parallel according to the scheduling strategy; The first PCIE message conversion module obtains a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface; The second PCIE message conversion module obtains a second local bus message according to the second PCIE message, where the second local bus message is a message that can be identified by the second local bus interface.

7. The method according to claim 6, characterized in that The PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module and sends the second PCIE message to the second PCIE message conversion module in parallel according to the scheduling strategy, including: The PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module and sends the second PCIE message to the second PCIE message conversion module in parallel according to the access addresses of the first PCIE message and the second PCIE message.

8. The method according to claim 6, characterized in that The method further comprises: The PCIE message scheduling module sends the first PCIE message to the first PCIE message conversion module according to the cache of the first PCIE message conversion module, and sends the second PCIE message to the second PCIE message conversion module according to the cache of the second PCIE message conversion module.

9. The method according to any one of claims 6 to 8, characterized in that The method further comprises: The first PCIE message conversion module receives the first local bus response message sent by the first local bus interface, obtains a first PCIE response message according to the first local bus response message, and sends the first PCIE response message to the PCIE collection module; The second PCIE message conversion module receives the second local bus response message sent by the second local bus interface, obtains a second PCIE response message according to the second local bus response message, and sends the second PCIE response message to the PCIE collection module; The PCIE collection module obtains and sends the first PCIE response message and the second PCIE response message.

10. The method according to any one of claims 6 to 8, characterized in that The method further comprises: The first PCIE message conversion module sends the first PCIE response message to the PCIE collection module according to the cache of the PCIE collection module; The second PCIE message conversion module sends the second PCIE response message to the PCIE collection module according to the cache of the PCIE collection module.

11. An integrated circuit, characterized in that: include: bus and interface standard PCIE message dispatching circuit, first PCIE message conversion circuit and second PCIE message conversion circuit, The PCIE message scheduling circuit is used to receive a first PCIE message and a second PCIE message, and send the first PCIE message to the first PCIE message conversion circuit and send the second PCIE message to the second PCIE message conversion circuit in parallel according to a scheduling strategy; The first PCIE message conversion circuit is used to obtain a first local bus message according to the first PCIE message, where the first local bus message is a message that can be recognized by the first local bus interface; The second PCIE message conversion circuit is used to obtain a second local bus message according to the second PCIE message, where the second local bus message is a message that can be recognized by the second local bus interface.

12. The integrated circuit according to claim 11, characterized in that The PCIE message scheduling circuit is specifically used for: According to the access addresses of the first PCIE message and the second PCIE message, the first PCIE message is sent to the first PCIE message conversion circuit and the second PCIE message is sent to the second PCIE message conversion circuit in parallel.

13. The integrated circuit according to claim 11, characterized in that The PCIE message scheduling circuit is further used to send the first PCIE message to the first PCIE message conversion circuit according to the cache of the first PCIE message conversion circuit, and to send the second PCIE message to the second PCIE message conversion circuit according to the cache of the second PCIE message conversion circuit.

14. The integrated circuit according to any one of claims 11 to 13, characterized in that The integrated circuit also includes: a PCIE collection circuit, The first PCIE message conversion circuit is further used to receive a first local bus response message sent by the first local bus interface, obtain a first PCIE response message according to the first local bus response message, and send the first PCIE response message to the PCIE collection circuit; The second PCIE message conversion circuit is further used to receive a second local bus response message sent by the second local bus interface, obtain a second PCIE response message according to the second local bus response message, and send the second PCIE response message to the PCIE collection circuit; The PCIE collection circuit is used to obtain and send the first PCIE response message and the second PCIE response message.

15. The integrated circuit according to claim 14, characterized in that The first PCIE message conversion circuit is further used to send the first PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit; The second PCIE message conversion circuit is further configured to send the second PCIE response message to the PCIE collection circuit according to the cache of the PCIE collection circuit.

16. The integrated circuit according to any one of claims 11 to 13, characterized in that The integrated circuit further comprises: a PCIE interface circuit, a first local bus interface circuit, a second local bus interface circuit, The PCIE interface circuit is used to send the first PCIE message and the second PCIE message to the PCIE message scheduling circuit; The first local bus interface circuit is used to receive the first local bus message; The second local bus interface circuit is used to receive the second local bus message.

17. A conversion device, characterized in that: include: Processor and memory; The processor executes the instructions in the memory so that the conversion device performs the method according to any one of claims 6 to 10.

18. A computer readable and writable storage medium, characterized in that: The method comprises instructions and data; the instructions and data are used to implement the method according to any one of claims 6 to 10.

Images