A neuron information processing method, device, chip and storage medium

Abstract

The application provides a neuron information processing method and device, a chip and a storage medium. The method is applied to the chip. The chip simulates at least one neuron through at least one computing core included by the chip. The method can comprise: acquiring a current membrane potential of each neuron in the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing the current membrane potential and neuron information of the neuron; and in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a neuron information processing method and device, a chip and a storage medium. BACKGROUND

[0002] Some chips (for example, neuromorphic chips) can be used to build a neural network. The neural network can include a plurality of neurons. The computing cores in such chips can be used to simulate neurons in the neural network. At least some of the plurality of neurons can communicate with each other through synapses.

[0003] In such chips, neuron information of neurons needs to be stored, and the neurons can perform processing actions according to the neuron information. Currently, the neuron information of each neuron is usually stored to facilitate each neuron to make corresponding processing according to the neuron information. However, this can occupy too much storage space of the chip. SUMMARY

[0004] Therefore, the present application discloses a neuron information processing method. The method is applied to a chip. The chip simulates at least one neuron through at least one computing core included in the chip. The method can include: obtaining a current membrane potential of each neuron in the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing the current membrane potential and neuron information of the neuron; and in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.

[0005] In some embodiments, the neuron information includes at least one of the following: a release threshold, a leakage value, and a resting potential.

[0006] In some embodiments, the neuron information of the at least one neuron is pre-stored in the chip according to a neuron type; the associatively storing the current membrane potential and the neuron information of the neuron in response to the current membrane potential being different from the resting potential of the neuron includes: in response to the current membrane potential being different from the resting potential of the neuron, associatively storing the current membrane potential and a neuron type identifier corresponding to the neuron; and the discarding the current membrane potential in response to the current membrane potential being the same as the resting potential includes: in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential and storing the neuron type identifier corresponding to the neuron.

[0007] In some embodiments, the method further comprises: in response to storing the membrane potential of a target neuron, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron; in response to not storing the membrane potential of a target neuron, determining a corresponding resting potential of the target neuron as the current membrane potential of the target neuron.

[0008] In some embodiments, the neuron information of the at least one neuron is pre-stored in the chip according to neuron types; the chip stores a neuron type identifier of the at least one neuron; and the associatively storing the current membrane potential and the neuron information of the neuron in response to the current membrane potential being different from the resting potential of the neuron comprises: in response to the current membrane potential being different from the resting potential of the neuron, storing a number identifier of the neuron and the current membrane potential, and associating the stored number identifier and the current membrane potential with the neuron type identifier of the neuron.

[0009] In some embodiments, the method further comprises: in response to storing a number identifier of a target neuron, determining a membrane potential associated with the number of the target neuron as a current membrane potential of the target neuron; in response to not storing a number identifier of a target neuron, determining a corresponding resting potential of the target neuron as the current membrane potential of the target neuron.

[0010] In some embodiments, the associatively storing the current membrane potential and the neuron information of the neuron comprises: sequentially associatively storing the current membrane potential and the neuron information of the neuron based on a pre-set neuron number identifier.

[0011] In some embodiments, the chip comprises a many-core chip; and the neuron comprises a neuron in a spiking neural network.

[0012] The present application also provides a neuron information processing apparatus. The apparatus is applied to a chip. The chip simulates at least one neuron through at least one computing core included therein; and the apparatus comprises: an acquisition module configured to acquire a current membrane potential of each of the at least one neuron; a storage module configured to, in response to the current membrane potential being different from a resting potential of the neuron, associatively store the current membrane potential and neuron information of the neuron; and in response to the current membrane potential being the same as the resting potential, discard the current membrane potential.

[0013] The application further provides a chip, which simulates at least one neuron through at least one computing core included by the chip; wherein the computing core is configured to acquire a current membrane potential of each of the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, store the current membrane potential in association with neuron information of the neuron; and in response to the current membrane potential being the same as the resting potential, discard the current membrane potential.

[0014] The application further provides a storage medium, which stores a program for causing a computing core of a chip to execute the neuron information processing method according to any one of the preceding embodiments.

[0015] In the scheme according to any one of the preceding embodiments, by storing the current membrane potential in association with the neuron information of the neuron in response to the current membrane potential being different from the resting potential of the neuron, and discarding the current membrane potential in response to the current membrane potential being the same as the resting potential, the membrane potential of the neuron in the working state can be stored only, and the membrane potential of the neuron in the non-working state does not need to be stored, thereby saving the storage space of the chip.

[0016] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the application. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the one or more embodiments of the application or the related art, the drawings needed to be used in the embodiment or related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the one or more embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor under the premise of these drawings.

[0018] Figure 1 A method flowchart of a neuron information processing method according to an embodiment of the application is shown in the figure;

[0019] Figure 2 A method schematic diagram of acquiring a resting potential according to an embodiment of the application is shown in the figure;

[0020] Figure 3 A method flowchart of acquiring a current membrane potential according to an embodiment of the application is shown in the figure;

[0021] Figure 4 A method flowchart of acquiring a current membrane potential according to an embodiment of the application is shown in the figure;

[0022] Figure 5Fig. 1 shows a schematic diagram of a neuron information processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The exemplary embodiments will be described in detail below with reference to the accompanying drawings. In the following description, unless otherwise indicated, like numbers in the different drawings represent similar or analogous elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0024] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the present application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be further understood that the term "if', depending on the context, can be interpreted either as meaning "when" or "responsive to the determination of" or both.

[0025] The present application proposes a neuron information processing method. In the method, only the membrane potential of a neuron in an active state can be stored, and the membrane potential of a neuron in an inactive state does not need to be stored, thereby saving storage space. The method can be applied to a chip. The chip can simulate at least one neuron through at least one computing core included in the chip.

[0026] In some embodiments, the chip can be an AI chip. The AI chip can be a neuromorphic chip (brain-like chip). The chip can be a many-core chip. Each computing core in the many-core chip can simulate one or more neurons.

[0027] Please refer to Figure 1 , Figure 1 A method flowchart of a neuron information processing method according to an embodiment of the present application is shown in Fig. 2. As shown in Fig. 2, the method can include S102-S106. Figure 1

[0028] S102, obtaining a current membrane potential of each neuron in the at least one neuron.

[0029] The current membrane potential refers to a voltage value generated by a neuron stimulated by other neurons. The neuron can be a neuron in an artificial neural network or a spiking neural network.

[0030] ​In some embodiments, the current membrane potential is calculated according to stimulation signals sent by other neurons connected to the neuron.

[0031] In some embodiments, obtaining the current membrane potential can include obtaining multiple stimulation signals received by the neuron at the current time, then performing weighted processing on the multiple stimulation signals according to weights corresponding to each stimulation signal to obtain an input potential, and then summing the input potential with a leakage voltage of the neuron, a membrane potential at a previous time to obtain the membrane potential.

[0032] For example, neuron A is connected to neurons B, C, and D through synapses 1, 2, and 3. When obtaining the membrane potential corresponding to neuron A, the stimulation signals (which can also be processed signals) sent by neurons B, C, and D at the current time can be weighted and summed according to the weights set for synapses 1, 2, and 3 to obtain an input potential. Then, the input voltage is summed with the membrane potential of neuron A at the previous time, and the difference with the leakage potential of neuron A is obtained to obtain the membrane potential corresponding to neuron A.

[0033] S104, in response to the current membrane potential being different from the resting potential of the neuron, associatively storing the current membrane potential and neuron information of the neuron.

[0034] The resting potential refers to the potential of the neuron when it is not stimulated by other neurons. If the membrane potential of the neuron is equal to the resting potential, it can be considered that the neuron is not stimulated, i.e., in a non-working state; if the membrane potential of the neuron is not equal to the resting potential, it can be considered that the neuron is stimulated, i.e., in a working state.

[0035] In some embodiments, the chip can be pre-allocated a storage space for storing neuron information of each neuron included in the chip. The neuron information can include the resting potential of the neuron, release threshold information, etc.

[0036] Obtaining the resting potential can include obtaining neuron information corresponding to the neuron from the pre-allocated storage space, and obtaining the resting potential of the neuron from the neuron information.

[0037] The neuron information includes at least one of the following: release threshold, leakage value, and resting potential.

[0038] In some embodiments, the neuron information can be pre-stored in the chip, and in S104, the associatively storing can be achieved by storing an identifier indicating the neuron information together with the obtained current membrane potential.

[0039] For example, the identifier can be a storage address indicating the neuron information, and the storage of the storage address together with the obtained current membrane potential can realize the associated storage. For another example, the identifier can be a neuron type number. The neuron corresponding to the type number has the same neuron information. The storage of the neuron type number together with the obtained current membrane potential can also realize the associated storage.

[0040] In some embodiments, the neurons simulated by the chip can be numbered in advance. In S104, the current membrane potential and the neuron information of the neuron can be sequentially associated and stored based on the pre-set neuron number identifier.

[0041] For example, the chip can simulate 100 neurons numbered from 1 to 100. The current membrane potential and the neuron information can be sequentially associated and stored for each neuron in the order of the number from small to large.

[0042] In S106, the current membrane potential is discarded in response to the current membrane potential being the same as the resting potential.

[0043] In some embodiments, after the current membrane potential and the resting potential of the neuron are obtained, the sizes of the two can be compared. If the two are not the same, it can be indicated that the neuron is stimulated by other neurons and is in a working state, and the membrane potential can be associated and stored. If the two are the same, it can be indicated that the neuron is not stimulated by other neurons and is in a non-working state, and the membrane potential can be discarded.

[0044] For example, in a sparse network, most of the neurons will not work, i.e., will not be stimulated by other neurons, and only a small part of the neurons will work. Through the steps of S102-S106, only the membrane potentials of the small part of the neurons will be recorded, and thus a large amount of storage space can be saved.

[0045] The technical solution recorded by S102-S106 can save storage space. Since the membrane potential of the neuron is equal to the resting potential of the neuron, it can be indicated that the neuron is in a non-working state, and the membrane potential is not equal to the resting potential, which can indicate that the neuron is in a working state. Therefore, in the method, the current membrane potential and the neuron information of the neuron are associated and stored in response to the current membrane potential being different from the resting potential of the neuron, and the current membrane potential is discarded in response to the current membrane potential being the same as the resting potential, so that only the membrane potential of the neuron in the working state is stored, and the membrane potential of the neuron in the non-working state does not need to be stored, thereby saving storage space.

[0046] In some embodiments, neurons of the same type have at least partially same neuron information, and the chip can store only one copy of the same neuron information for neurons of the same type, without storing the same neuron information (e.g., the same resting potential) for each neuron, thereby further saving storage space. It can be understood that the neuron information in this example does not change due to whether the neuron receives external stimulation. For example, the neuron information can include a resting potential, a release threshold, a leakage value, etc.

[0047] In some embodiments, the neuron information of the at least one neuron can be pre-stored in the chip according to the neuron type.

[0048] See Figure 2 , Figure 2 A schematic diagram of a method for obtaining a resting potential according to an embodiment of the present application is shown. Figure 2 A detailed description of the method for obtaining a resting potential is shown. As Figure 2 shown, the method can include S202-S204.

[0049] S202, obtain a neuron type identifier of the neuron.

[0050] The chip shown can include neurons of multiple types. The neuron type identifier shown can be a type identifier pre-maintained for each neuron of the chip. In some embodiments, a storage space can be pre-allocated for each neuron type in the chip, and the neuron information corresponding to each neuron type can be stored in the storage space.

[0051] S204, obtain a resting potential included in the neuron information corresponding to the neuron type identifier.

[0052] After S202 obtains the neuron type of the neuron, a storage space corresponding to the neuron type can be found, and then the neuron information of neurons of this type can be read from the storage space, and the resting potential can be obtained.

[0053] For example, the neuron type can include two types A and B, where the resting potential of A is -70mv, and the release threshold is 0.7V. The resting potential of B is -70mv, and the release threshold is 0.9V. The chip can maintain a storage space for types A and B respectively. Each storage space can store corresponding neuron information (including the resting potential and the release threshold). Assuming that S202 knows that the neuron is a neuron of type B, through S204, the resting potential can be obtained from the storage space corresponding to type B, i.e., the resting potential of the neuron is -70mv.

[0054] Thus, only one copy of the same neuron information needs to be stored for the same type of neuron, and neuron information does not need to be stored for each neuron, further saving storage space.

[0055] In some embodiments, the neuron information of the at least one neuron can be pre-stored in the chip according to the neuron type. For example, a storage space can be pre-allocated in the chip for each neuron type, and the neuron information corresponding to each neuron type can be stored in the storage space.

[0056] In S104, the current membrane potential can be associatedly stored with the neuron type identifier corresponding to the neuron in response to the current membrane potential being different from the resting potential of the neuron.

[0057] In S106, the current membrane potential can be discarded, and the neuron type identifier corresponding to the neuron can be stored in response to the current membrane potential being the same as the resting potential.

[0058] Thus, the neuron information can be associated with the current membrane potential by the neuron type, and the associated storage can be implemented, so that in addition to only recording the membrane potential of the neuron in the working state, the neuron type identifier of the neuron can be associatedly stored with the membrane potential in the same storage space, which can facilitate the query of other neuron information of the neuron when the membrane potential of the neuron is updated, and improve the storage efficiency and storage space utilization.

[0059] In some embodiments, different methods can be used to obtain the current membrane potential of the target neuron according to whether the membrane potential of the target neuron is stored.

[0060] See Figure 3 , Figure 3 A method flow diagram for obtaining a current membrane potential is shown in the embodiments of the present application. As shown in Figure 3 , the method can include S302-S304.

[0061] S302, in response to storing the membrane potential of the target neuron, determining the stored membrane potential of the target neuron as the current membrane potential of the target neuron.

[0062] The target neuron is any neuron in the at least one neuron simulated by the chip. In some embodiments, each neuron included in the chip can be sequentially determined as the target neuron according to the neuron number.

[0063] If the membrane potential of the target neuron is stored, it means that the target neuron is in the working state and has been stimulated by the outside world, and the stored membrane potential of the target neuron can be used as the current membrane potential of the target neuron.

[0064] S304, in response to not storing the membrane potential of the target neuron, determining the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

[0065] If the membrane potential of the target neuron is not stored, it indicates that the target neuron is in a non-working state, i.e., not stimulated by the outside world, and the resting potential of the target neuron can be used as the current membrane potential.

[0066] In some embodiments, the neuron information of the at least one neuron can be pre-stored in the chip according to the neuron type. In S304, the neuron type of the target neuron can be obtained, and then the neuron information of the target neuron can be queried based on the neuron type. Thereafter, the resting potential included in the neuron information of the target neuron can be used as the current membrane potential of the target neuron.

[0067] Through the steps of S302-S304, the current membrane potential of the target neuron can be accurately determined even in the case of only recording the membrane potential of the neuron in the working state.

[0068] In some embodiments, after determining the current membrane potential of the target neuron, the current membrane potential can be compared with the release threshold of the target neuron. If the current membrane potential reaches the release threshold, the target neuron can be caused to send a pulse signal to the neurons connected thereto.

[0069] In some embodiments, the neuron type identifier can be stored only once for neurons of the same type, thereby further reducing the storage space.

[0070] In this example, the neuron information of the at least one neuron can be pre-stored in the chip according to the neuron type; and the chip stores the neuron type identifier of the at least one neuron.

[0071] In S104, in response to the current membrane potential being different from the resting potential of the neuron, the number identifier of the neuron and the current membrane potential can be stored, and the stored number identifier and the current membrane potential can be associated with the neuron type identifier of the neuron.

[0072] The number identifier can be a number ID pre-assigned to each neuron included in the chip. In some embodiments, each number identifier can indicate a unique neuron. In some embodiments, a mapping relationship between the number identifier and the neuron type can be maintained. Through the mapping relationship and the number of the neuron, the neuron type of the neuron can be obtained. For example, the chip can maintain that numbers 1-100 are mapped to type A, and numbers 101-200 are mapped to type B. If the number of the neuron is 50, it can be determined that the neuron type is A.

[0073] The number identifier can also represent the neuron type of the neuron. The neuron type of the neuron can be known by the number identifier of the neuron. For example, the number of the neuron is B1, which can indicate that the neuron is a B-type neuron, numbered 1. For another example, the number of the neuron is A10, which can indicate that the neuron is an A-type neuron, numbered 10.

[0074] In S104, in response to the current membrane potential being different from the resting potential of the neuron, it can be determined whether the type identifier of the neuron is stored in the chip. If the type identifier of the neuron is stored in the chip, the number identifier of the neuron and the obtained current membrane potential can be stored in association with the type identifier.

[0075] If the type identifier of the neuron is not stored in the chip, the type identifier of the neuron can be stored first, and then the number identifier of the neuron and the obtained current membrane potential can be stored in association with the type identifier.

[0076] For example, a storage space can be allocated for each type of neuron. After the type of the neuron is obtained in S104, it can be determined whether a storage space is allocated for the type in the chip. If yes, the number identifier of the neuron and the obtained current membrane potential can be stored in association in the storage space corresponding to the type. If no, a storage space can be allocated for the type of neuron first, and then the number identifier of the neuron and the obtained current membrane potential can be stored in association in the storage space corresponding to the type.

[0077] Thus, the current membrane potential of the neuron of the same type is stored in the storage space corresponding to the type, so that the neuron type identifier does not need to be stored for each neuron, and the storage space is further saved.

[0078] In some embodiments, the following method can be used to obtain the current membrane potential of the target neuron for the above association storage method.

[0079] Please refer to Figure 4 , Figure 4 A method flow diagram for obtaining a current membrane potential is shown in an embodiment of the present application. As shown in Figure 4 , the method can include S402-S404.

[0080] S402, in response to storing the number identifier of the target neuron, determining the membrane potential stored in association with the number of the target neuron as the current membrane potential of the target neuron.

[0081] The target neuron is any neuron in the at least one neuron simulated by the chip. In some embodiments, each neuron included in the chip can be sequentially determined as the target neuron according to a neuron number.

[0082] If the number identifier of the target neuron is stored and indicates that the target neuron is in an active state and has been stimulated by an external stimulus, the membrane potential associated with the number of the target neuron can be stored as the current membrane potential.

[0083] S404, in response to not storing the number identifier of the target neuron, determining the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

[0084] If the number identifier of the target neuron is not stored, it indicates that the target neuron is in an inactive state, i.e., not stimulated by an external stimulus, and the resting potential of the target neuron can be used as the current membrane potential.

[0085] In some embodiments, the neuron information of the at least one neuron can be pre-stored in the chip according to the neuron type. In S404, the neuron type of the target neuron can be obtained, and then the neuron information of the target neuron can be queried based on the neuron type. Thereafter, the resting potential included in the neuron information of the target neuron can be used as the current membrane potential of the target neuron.

[0086] Through the steps of S402-S404, the current membrane potential of the target neuron can be accurately determined in the case of storing the type identifier only once for the same type of neuron.

[0087] In some embodiments, after determining the current membrane potential of the target neuron, the current membrane potential can be compared with a release threshold of the target neuron. If the current membrane potential reaches the release threshold, the target neuron can be caused to send a pulse signal to the neurons connected thereto.

[0088] In some embodiments, in order to facilitate the management (including updating and reading) of the membrane potential of the neuron, the storage space can be divided according to the neural network layer of the neuron, and the neuron information of the neuron can be stored in the storage space corresponding to the network layer to which the neuron belongs. Thus, the membrane potential of the neuron can be managed layer by layer and neuron by neuron.

[0089] The following is an exemplary description in combination with the scenario of managing the neuron information of the brain-like chip.

[0090] The brain type chip can include one or more computing kernels. Each computing kernel can simulate one or more neurons, or multiple computing kernels can simulate one neuron, and the embodiments of the present disclosure are not limited thereto. The neurons can be neurons in a spiking neural network. Each neuron can be numbered and the neuron type can be determined in advance, and then a mapping relationship between the neuron number and the neuron type can be stored in the chip. Each neuron type corresponds to some static neuron information (i.e., information that does not change regardless of whether the neuron is stimulated, which can include a resting potential). The chip can store the static neuron information according to the neuron type. The chip can also allocate storage space for storing the current membrane potential according to the neuron type.

[0091] In S102, the current membrane potential of the neuron can be determined according to the stimulated information of the neuron, and the neuron type of the neuron can be determined according to the number of the neuron and the mapping relationship, and the resting potential of the neuron can be obtained.

[0092] In S104, if the membrane potential is different from the resting potential, it means that the neuron is stimulated, and it can be determined whether the storage space for the neuron type is allocated in the chip. If yes, the number of the neuron and the membrane potential are stored in the allocated storage space. If not, the storage space for the neuron type can be allocated first, and then the number of the neuron and the membrane potential are stored in the allocated storage space.

[0093] In S106, if the membrane potential is the same as the resting potential, it means that the neuron is in a non-working state, and the membrane potential can be discarded without storage.

[0094] Through the foregoing steps in the brain type chip, on the one hand, a storage space is allocated for the same type of neuron, i.e., the neurons in the same storage space have the same neuron type, so there is no need to record the neuron type information of each neuron, further saving storage space. On the other hand, only the number of the neuron and the membrane potential of the neuron in the working state are recorded in the same storage space, and there is no need to record the related information of the neuron in the non-working state, so there is no need to allocate storage space for the neuron in the non-working state, further saving storage space. On the other hand, the neuron information of the same type of neuron is allocated in the same storage space, which is convenient for querying the membrane potential of the neuron.

[0095] When querying the current membrane potential of the neuron in the brain type chip, the target neuron can be determined in order according to the neuron number from small to large, and S402-S404 can be executed, so that the current membrane potential of the target neuron can be accurately determined.

[0096] Corresponding to the foregoing embodiments, the present application proposes a neuron information processing apparatus. The apparatus can be applied to a chip, which simulates at least one neuron through at least one computing core included in the chip.

[0097] Please refer to Figure 5 , Figure 5 A structural schematic diagram of a neuron information processing apparatus shown in an embodiment of the present application is shown.

[0098] As Figure 5 shown, the apparatus 500 can include:

[0099] The acquisition module 510 is configured to acquire a current membrane potential of each of the at least one neuron.

[0100] The storage module 520 is configured to, in response to the current membrane potential being different from a resting potential of the neuron, store the current membrane potential in association with neuron information of the neuron.

[0101] In response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded.

[0102] In some embodiments, the neuron information includes at least one of the following: a release threshold, a leakage value, and a resting potential.

[0103] In some embodiments, the neuron information of the at least one neuron is pre-stored in the chip according to a neuron type; and the storage module 520 is specifically configured to:

[0104] In response to the current membrane potential being different from a resting potential of the neuron, the current membrane potential is stored in association with a neuron type identifier corresponding to the neuron.

[0105] In response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded, and the method includes:

[0106] In response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded, and the neuron type identifier corresponding to the neuron is stored.

[0107] In some embodiments, the apparatus 500 further includes:

[0108] The first determination module is configured to, in response to a membrane potential of a target neuron being stored, determine the stored membrane potential of the target neuron as a current membrane potential of the target neuron.

[0109] The second determination module is configured to, in response to a membrane potential of a target neuron not being stored, determine a resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

[0110] In some embodiments, the neuron information of the at least one neuron is pre-stored in the chip according to neuron types; the chip stores neuron type identifiers of the at least one neuron;

[0111] The storage module 520 is specifically configured to:

[0112] In response to the current membrane potential being different from the resting potential of the neuron, store the number identifier of the neuron and the current membrane potential, and associate the stored number identifier and the current membrane potential with the neuron type identifier of the neuron.

[0113] In some embodiments, the method further comprises:

[0114] The third determination module is configured to, in response to storing the number identifier of a target neuron, determine the membrane potential associated with the number of the target neuron as the current membrane potential of the target neuron;

[0115] The fourth determination module is configured to, in response to not storing the number identifier of a target neuron, determine the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

[0116] In some embodiments, the storage module 520 is specifically configured to:

[0117] Based on pre-set neuron number identifiers, sequentially store the current membrane potential and the neuron information of the neuron.

[0118] In some embodiments, the chip comprises a many-core chip; and the neuron comprises a neuron in a spiking neural network.

[0119] The present application also proposes a chip. The chip simulates at least one neuron through at least one computing core included in the chip; wherein the computing core is configured to acquire a current membrane potential of each of the at least one neuron;

[0120] In response to the current membrane potential being different from the resting potential of the neuron, store the current membrane potential and the neuron information of the neuron in association;

[0121] In response to the current membrane potential being the same as the resting potential, discard the current membrane potential.

[0122] In the foregoing scheme, the current membrane potential is associatedly stored with neuron information of the neuron in response to the current membrane potential being different from a resting potential of the neuron, and the current membrane potential is discarded in response to the current membrane potential being the same as the resting potential, so that only the membrane potential of the neuron in a working state can be stored, and the membrane potential of the neuron in a non-working state does not need to be stored, thereby saving the storage space of the chip.

[0123] The computing core can also perform the neuron information processing method shown in any of the foregoing embodiments, which will not be described in detail here.

[0124] The application also discloses an electronic device. The electronic device comprises a chip. The chip simulates at least one neuron through at least one computing core comprised by the chip; the computing core is configured to acquire a current membrane potential of each of the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, the current membrane potential is associatedly stored with neuron information of the neuron; and in response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded.

[0125] The application provides a computer-readable storage medium, which stores a computer program. The computer program can be used to make a processor perform the neuron information processing method shown in any of the foregoing embodiments.

[0126] Those skilled in the art should understand that one or more embodiments of the application can be provided as a method, a system or a computer program product. Therefore, one or more embodiments of the application can adopt a completely hardware embodiment, a completely software embodiment or an embodiment combining software and hardware aspects. Moreover, one or more embodiments of the application can adopt a computer program product in the form of being implemented on one or more computer usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer usable program codes.

[0127] In the application, "and / or" means at least one of two, for example, "A and / or B" includes three schemes: A, B and "A and B".

[0128] Each embodiment in the application is described in a progressive manner, and the same and similar parts of each embodiment can be referred to each other. Each embodiment mainly describes the difference from other embodiments. Especially, the data processing device embodiment is basically similar to the method embodiment, so the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0129] The particular embodiments described herein describe the present application. Other embodiments are within the scope of the following claims. In some cases, an act or step recited in the claims can be performed in a different order than that described in the embodiments, and still achieve desirable results. Additionally, the process depicted in the figures does not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0130] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0131] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), and the apparatus can be implemented as special purpose logic circuitry. Devices of the sort

[0132] Computers suitable for the execution of a computer program include, by way of example, general and / or special purpose microprocessors, or any other kind of central processing system. Generally, a central processing unit will receive instructions and data from a read-only memory and / or a random access memory. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0133] Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0134] While this application contains many specific embodiments, these should not be construed as limiting the scope or range of any disclosures or embodiments, but merely as accurately describing particular ones. Certain features that are, both separately described and / or in various combinations and / or permutations of features, can be selected, either individually or collectively, for the application of a set of embodiments. Conversely, certain features that are, in single embodiments, sub-combinations of features, can be separated from that single embodiment into separate embodiments. In addition, while features can be described above as acting in certain combinations and / or initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or variation of a sub-combination.

[0135] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor that all illustrated operations be performed, to implement and / or form desired results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0136] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0137] The above descriptions are merely some preferred embodiments of the one or more embodiments of the present application, and are not intended to limit the one or more embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the one or more embodiments of the present application shall be included in the scope of protection of the one or more embodiments of the present application.

Claims

1. A method for processing information of neurons, applied to a chip, characterized in that, The chip simulates at least one neuron through at least one computing core included by the chip, and neuron information of the at least one neuron is pre-stored in the chip according to neuron types; the method comprises: obtaining a current membrane potential of each of the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing the current membrane potential and neuron information of the neuron, comprising: in response to the current membrane potential being different from the resting potential of the neuron, storing a neuron type identifier indicating the neuron information of the neuron in association with the current membrane potential in a same storage space, wherein each neuron type identifier corresponds to a neuron having the same neuron information; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.

2. The method of claim 1, wherein, The neuron information comprises at least one of a release threshold, a leakage value, and a resting potential.

3. The method of claim 1, wherein, in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential, the method comprising: in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential, and storing a neuron type identifier corresponding to the neuron.

4. The method of claim 1, wherein, Further comprising: in response to a membrane potential of a target neuron being stored, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron; in response to a membrane potential of a target neuron not being stored, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.

5. The method of claim 1, wherein, The chip stores neuron type identifiers of the at least one neuron; in response to the current membrane potential being different from the resting potential of the neuron, storing a neuron type identifier indicating the neuron information of the neuron in association with the current membrane potential in a same storage space, comprising: in response to the current membrane potential being different from the resting potential of the neuron, storing a number identifier of the neuron and the current membrane potential, and associating the stored number identifier and the current membrane potential with the neuron type identifier of the neuron.

6. The method of claim 5, wherein, Further comprising: in response to a number identifier of a target neuron being stored, determining a membrane potential stored in association with the number of the target neuron as a current membrane potential of the target neuron; in response to a number identifier of a target neuron not being stored, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.

7. The method according to any of claims 1 to 6, characterized in that The associatively storing the current membrane potential and the neuron information of the neuron comprises: sequentially associatively storing the current membrane potential and the neuron information of the neuron based on a pre-set neuron number identifier.

8. The method of claim 1, wherein, The chip comprises a many-core chip; and the neuron comprises a neuron in a spiking neural network.

9. A neuron information processing device applied to a chip, characterized by, The chip simulates at least one neuron through at least one computing core included by the chip, and neuron information of the at least one neuron is pre-stored in the chip according to neuron types; the device comprises: an obtaining module, configured to obtain a current membrane potential of each of the at least one neuron; The storage module is configured to, in response to the current membrane potential being different from the resting potential of the neuron, store the current membrane potential in association with neuron information of the neuron, including: in response to the current membrane potential being different from the resting potential of the neuron, storing a neuron type identifier indicating the neuron information of the neuron in association with the current membrane potential in the same storage space, wherein each neuron type identifier corresponds to a neuron having the same neuron information; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.

10. A chip, characterized by The chip simulates at least one neuron through at least one computing core included in the chip, and neuron information of the at least one neuron is pre-stored in the chip according to neuron types; wherein, the computing core is configured to acquire a current membrane potential of each of the at least one neuron; in response to the current membrane potential being different from the resting potential of the neuron, store the current membrane potential in association with neuron information of the neuron, including: in response to the current membrane potential being different from the resting potential of the neuron, storing a neuron type identifier indicating the neuron information of the neuron in association with the current membrane potential in the same storage space, wherein each neuron type identifier corresponds to a neuron having the same neuron information; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.

11. A storage medium, characterized by The storage medium stores a program for causing a chip computing core to execute the neuron information processing method according to any one of claims 1-8.

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