An exposure area-based chip packaging processing method

Abstract

The disclosure provides a chip packaging processing method based on exposure area, the packaging processing method comprising: firstly determining each exposure area of a target wafer by using prior photolithography process data, the target wafer can be one or more. Taking each exposure area as the cutting unit of the current process, the target wafer is cut and processed to divide the target wafer into multiple device units. For the device unit containing defective dies, the device unit is directly cut and processed with the die as the cutting unit and then bonded. The qualified device units are integrally bonded, and then the device units after the bonding process are cut and processed with the die as the cutting unit of the current process. The disclosure innovatively uses the known exposure area as the basis for the first cutting wafer, and the qualified device units are bonded between the two cutting processing processes, which can improve the yield of semiconductor devices and improve the packaging efficiency. The process of the disclosure is simpler and has high alignment accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and more specifically, this disclosure provides a chip packaging processing method based on the exposed area. Background Technology

[0002] In the field of semiconductor technology, chip packaging technology plays a crucial role. Currently, wafer-level device bonding or chip-level device bonding is frequently used in chip packaging processes.

[0003] For wafer-level device bonding, multiple wafers to be diced are first bonded together, and then the resulting multilayer wafer is diced as a whole. The biggest problem with this method is the low device yield. If any layer of the wafer has a faulty die, all the multilayer dies bonded to that faulty die will be unusable. Obviously, as the number of wafer layers increases, this method leads to a significant decrease in device yield. For example, if the yield of a single-layer wafer is 90%, then the yield of a two-layer wafer is 90% × 90% = 81%.

[0004] For chip-level device bonding solutions, all wafers are first diced, and then the individual dies are bonded. The problems with this approach are poor die alignment and low device packaging efficiency. Misalignment issues often arise when multiple dies are stacked. As semiconductor device integration increases, the number of dies on a given wafer size tends to increase. Therefore, chip-level device bonding solutions become increasingly time-consuming and costly, making it difficult to meet the evolving needs of semiconductor devices. Summary of the Invention

[0005] To address the problems of low device yield or low packaging efficiency in existing chip packaging technologies, this disclosure provides a chip packaging processing method based on the exposure area, in order to achieve at least one of the following objectives: improving the yield of semiconductor device packaging, improving packaging efficiency, and reducing packaging costs.

[0006] To achieve the above technical objectives, this disclosure specifically provides a chip packaging method based on exposure regions. This packaging method may include, but is not limited to, at least one of the following steps: First, using prior photolithography process data, determine each exposure region of a target wafer; the target wafer may be one or more. Using each exposure region as the dicing unit for the current process, dice the target wafer into multiple device units. Then, perform bonding processing on the qualified device units. Finally, using a bare die as the dicing unit for the current process, dice the bonded device units.

[0007] The beneficial effects of this disclosure are as follows: This disclosure uses the known exposure area as the basis for the first wafer dicing. Between the two dicing processes, it can perform a bonding process on the qualified device units formed by dicing and perform overall dicing on the bonded device units. Alternatively, it can first dicing unqualified device units into bare dies and then bonding them in bare die units. It can be seen that this disclosure can not only greatly improve the alignment accuracy during bonding, but also improve the yield of semiconductor devices and improve packaging efficiency.

[0008] This disclosure does not require separate alignment or overlay marks as in conventional processes. Instead, alignment between upper and lower wafers or between a wafer and a substrate can be achieved based on the exposure area in the preceding process. Therefore, the process disclosed in this disclosure is simpler and has higher alignment accuracy. Attached Figure Description

[0009] Figure 1 This diagram illustrates the state of packaging a multilayer device unit using the exposed area as the cutting unit (in this case, there are no defective dies).

[0010] Figure 2 This diagram illustrates the state of packaging a single-layer device unit with the exposed area as the cutting unit (in this case, there are defective dies; for example, two defective dies). Detailed Implementation

[0011] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0012] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0013] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0014] Example 1: All dies on the device unit are qualified

[0015] This embodiment specifically provides a chip packaging processing method based on the exposure area, which can be used to cut multilayer wafers. The packaging processing method may include, but is not limited to, at least one of the following steps.

[0016] At least one through-silicon via (TSV) is formed on the target wafer using a through-silicon via (TSV) process, and at least one TSV is filled with a conductive material. The conductive material can be, for example, copper, tungsten, or polysilicon. Vertical electrical interconnection of the TSV is achieved by filling it with at least one conductive material. New bonding pads are formed on the target wafer using a re-distribution layer (RDL) process, thereby achieving pad repositioning and improving the reliability of the semiconductor device.

[0017] Bump process: This step forms metal balls on the target wafer for conductive connections. The metal balls can be gold balls or solder balls. Each metal ball is formed one-to-one on a corresponding solder pad.

[0018] This embodiment can perform back-side grinding and back-side etching on the target wafer, which is a thinning process to make the thickness of the target wafer reach a preset thickness.

[0019] Before dicing the target wafer, wafer-level chip scale packages are performed to obtain the test results of each die on the target wafer. This embodiment can utilize prior lithography process data to determine each exposure shot on the target wafer. Prior lithography process data may include, but is not limited to, exposure area size data and exposure area coordinate data.

[0020] Understandably, in the photolithography process, the exposure area of ​​the photolithography machine is adjusted according to the chip size. First, the wafer surface is divided into several rectangular grids of the same size according to the set exposure area, each grid covering multiple bare wafers. Then, exposure areas are set in the areas of each grid; specifically, the exposure areas are areas on the wafer set on each grid and are slightly smaller than the grid size. The photolithography machine mentioned in the embodiments of this disclosure may include, but is not limited to, stepper lithography machines, scanning lithography machines, etc.

[0021] like Figure 1As shown, the exposed area is used as the cutting unit for the current process to perform a sawing process on the multilayer target wafer, dividing the target wafer into multiple device units. The multilayer target wafer may include a target wafer at the top and a target wafer at the bottom. In this embodiment, during the initial sawing process of the multilayer target wafer, it is possible to determine whether all the dies on each device unit have passed the test based on the test results of the dies on the wafer, that is, to determine whether the entire device unit (all the dies on a certain device unit) is qualified.

[0022] Next, the qualified device units are bonded. During the bonding process, qualified device units are selected for bonding based on the test results of each die. All dies on a qualified device unit must meet the set conditions. In this embodiment, the set condition is "qualified," meaning that at least two dies to be bonded have passed the test during the bonding process. Specifically, this embodiment has two bonding scenarios: the first is bonding between device units. Bonding qualified device units includes aligning at least two device units to be bonded. In this embodiment, innovatively, exposure marks formed on the scribe line of the device unit are used as alignment marks. Figure 1 Alignment is performed using the dashed lines shown in the diagram, without the need for additional alignment marks. In this embodiment, at least two device units are stacked, and bonding processing is performed on the at least two device units based on the alignment results. The second type is bonding between a device unit and a substrate. Bonding processing for qualified device units may further include: aligning the device unit with the substrate, and also utilizing the exposure marks on the dicing groove of the device unit as alignment marks; and performing bonding processing between the device unit and the substrate based on the alignment results between the device unit and the substrate.

[0023] After the qualified device units are bonded, the bare die is used as the cutting unit of the current process to cut the device units after the above bonding process, which is actually equivalent to the second cutting of the wafer.

[0024] It is understood that the chip packaging processing method based on the exposure area provided in this disclosure can be specifically used in packaging processes such as flip chip packaging.

[0025] Example 2: Case where defective bare dies exist on the device unit

[0026] This embodiment also provides a chip packaging method based on the exposed area, which can be used to dicing a single-layer wafer. This packaging method may include, but is not limited to, at least one of the following steps.

[0027] At least one via is formed on the target wafer using a through-silicon via (TSV) process, and the via is filled with a conductive material, such as copper, tungsten, or polysilicon, to achieve vertical electrical interconnection through the TSV. A redistribution process is then used to form new bonding pads on the target wafer, thereby repositioning the pads and improving the reliability of the semiconductor device. Metal balls, which can be gold or solder balls, are then formed on the target wafer for conductive connections. Each metal ball is formed one-to-one with each bonding pad.

[0028] This embodiment can perform back-side grinding on the target wafer to achieve a preset thickness for the target wafer.

[0029] Before dicing the target wafer, this embodiment performs wafer-level testing to obtain the test results of each die on the target wafer. The wafer-level testing method in this embodiment may include, but is not limited to, testing schemes such as energy dispersive spectroscopy (EDS). In this embodiment, prior lithography process data is used to determine each exposure region of the target wafer. Prior lithography process data may include, but is not limited to, exposure region size data and exposure region coordinate data. In the lithography process, the wafer surface is first divided into several rectangular grids of the same size according to the set exposure regions. Each grid can cover multiple dies. Then, exposure regions are set in the areas where each grid is located. The exposure regions are areas on the wafer that are set on each grid and are slightly smaller than the grid size.

[0030] like Figure 2 As shown, the exposed area is used as the cutting unit of the current process to cut the current target wafer into multiple device units.

[0031] For device units containing defective bare dies, the device unit is cut directly using the bare die as the cutting unit; the cut-off qualified bare dies are then bonded.

[0032] Specifically, in this embodiment, when faced with a device unit containing defective dies, the die is used as the cutting unit of the current process, and the device unit is directly cut. Then, the qualified dies selected from all the cut dies are joined one by one.

[0033] Based on the technical solutions provided in the various embodiments of this disclosure, this disclosure utilizes known exposure areas as the basis for the first wafer dicing, performing a bonding process between two dicing processes. This not only greatly improves the alignment accuracy during bonding but also significantly enhances semiconductor device yield and packaging efficiency. The technical solutions provided by this disclosure can screen the device units obtained after the first dicing while considering die yield, and can then perform subsequent packaging on qualified or partially qualified device units respectively. Therefore, this disclosure can further improve semiconductor device yield. This disclosure does not require separately set alignment or overlay marks as in conventional processes; instead, alignment between the upper and lower wafers or between the wafer and the substrate can be achieved based on the exposure areas in the preceding processes.

[0034] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0035] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A chip packaging processing method based on an exposed area, characterized in that, include: Wafer-level testing is performed on the target wafer to obtain the test results of each bare die on the target wafer; The exposure areas of the target wafer are determined using prior lithography process data; Using the exposed area as the cutting unit of the current process, the target wafer is cut into multiple device units. Qualified device units are then bonded together. During the bonding process of qualified device units, qualified device units are selected for bonding based on the test results of each die, and the test results of all dies on the qualified device units meet the set conditions. Using the bare die as the cutting unit for the current process, the device unit after bonding is cut. For device units containing defective bare dies, the device unit is cut directly using the bare die as the cutting unit; The cut, qualified blanks are then joined together.

2. The chip packaging method based on the exposure area according to claim 1, characterized in that, The bonding process for qualified device units includes: Align at least two device units to be joined, wherein the at least two device units are arranged in a stacked relationship; The joining process of the at least two device units is performed based on the alignment results between the device units.

3. The chip packaging method based on the exposure area according to claim 2, characterized in that, The alignment of at least two device units to be joined includes: Alignment is performed using the exposure marks formed on the dicing grooves of the device unit as alignment marks.

4. The chip packaging processing method based on the exposure area according to claim 1, characterized in that, The bonding process for qualified device units includes: Align the device unit with the substrate; The bonding process between the device unit and the substrate is performed based on the alignment results between the device unit and the substrate.

5. The chip packaging method based on the exposed area according to claim 1, characterized in that, Before dicing the target wafer, the process also includes: The target wafer is subjected to back-side grinding to achieve a preset thickness.

6. The chip packaging method based on the exposure area according to claim 5, characterized in that, Before performing back-side grinding on the target wafer, the process also includes: At least one through-hole is formed on the target wafer based on the through-silicon via (TSV) process and the at least one through-hole is filled with a conductive material. New pads are formed on the target wafer using a rewiring process.

7. The chip packaging method based on the exposure area according to claim 1, characterized in that, Before dicing the target wafer, the process also includes: Metal balls for conductive connections are formed on the target wafer.

8. The chip packaging processing method based on the exposure area according to claim 1, characterized in that, The prior lithography process data includes exposure area size data and exposure area coordinate data.

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