Stacked semiconductor chip and method of manufacturing the same, repair method of through hole

Abstract

The application provides a stacked semiconductor chip, a preparation method thereof and a repair method of a through hole. The stacked semiconductor chip comprises at least two layers of dies, a repair layer and a conductor which are stacked, wherein at least one of the at least two layers of dies has a through hole; the repair layer is adhered to the inner side wall of the through hole to smooth the inner side wall, and the repair layer comprises conductive particles which are physically aggregated; and the conductor is formed in a space outside the repair layer of the through hole to electrically connect the at least two layers of dies. The stacked semiconductor chip has good conductive performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a stacked semiconductor chip, a preparation method thereof and a repair method of a through hole. BACKGROUND

[0002] In the manufacturing process of 3D-IC (three-dimensional integrated circuit), the through silicon via (TSV) technology gradually becomes an indispensable link. It has stronger space utilization than traditional wafer stacking and external wire bonding.

[0003] The core of the TSV technology is to process a through hole. At present, the through hole processing technology mainly includes dry etching, wet etching, laser drilling and photo-assisted electrochemical etching. Among them, laser drilling and deep reactive etching are the mainstream processes at present. However, the existing processing technology of the through hole will leave scallop-shaped undulations and other defects on the inner side wall of the through hole, thereby affecting the filling of the metal in the through hole and the conductivity of the TSV. SUMMARY

[0004] The stacked semiconductor chip, the preparation method thereof and the repair method of the through hole provided by the present application aim to solve the problem that the existing processing technology of the through hole will leave scallop-shaped undulations and other defects on the inner side wall of the through hole, thereby affecting the filling of the metal in the through hole and the conductivity of the TSV.

[0005] To solve the above technical problems, one technical scheme adopted by the present application is to provide a stacked semiconductor chip. The stacked semiconductor chip comprises: at least two layers of dies which are stacked, a repair layer and a conductor; wherein at least one of the at least two layers of dies has a through hole; the repair layer is adhered to the inner side wall of the through hole to flatten the inner side wall, and the repair layer comprises conductive particles which are physically agglomerated; and the conductor is formed in the space outside the repair layer of the through hole to electrically connect the at least two layers of dies.

[0006] The material of the repair layer comprises an adhesive and the conductive particles mixed together.

[0007] The conductive particles comprise silver nanoparticles and / or metal particles.

[0008] The conductive particles comprise the silver nanoparticles and the metal particles; and the ratio of the adhesive, the silver nanoparticles and the metal particles is 1:1:(9-11).

[0009] The ratio of the adhesive, the silver nanoparticles and the metal particles is 1:1:10.

[0010] To solve the above technical problems, another technical solution adopted by the present application is to provide a preparation method of a chip stack semiconductor chip. The method comprises: providing at least two wafers; wherein at least one of the wafers has a through hole; adhering a repair layer to the inner sidewall of the through hole to smooth the inner sidewall; and forming a conductor in the space outside the repair layer of the through hole.

[0011] The step of adhering the repair layer to the inner sidewall of the through hole comprises: flowing a fluid mixed with conductive particles through the inner sidewall of the through hole, so that at least part of the conductive particles are adsorbed to the inner sidewall of the through hole; and curing the conductive particles adsorbed to the inner sidewall of the through hole to form the repair layer.

[0012] The conductive particles comprise silver nanoparticles and / or metal particles.

[0013] The fluid is mixed with an adhesive and a fluid medium; the conductive particles comprise the silver nanoparticles and the metal particles; and the proportions of the adhesive, the silver nanoparticles, the metal particles, and the fluid medium are 1:1:(9-11):(9-11).

[0014] To solve the above technical problems, another technical solution adopted by the present application is to provide a repair method of a through hole. The method comprises: providing a semiconductor sheet having a through hole; flowing a fluid mixed with conductive particles through the inner sidewall of the through hole, so that at least part of the conductive particles are adsorbed to the inner sidewall of the through hole; and curing the conductive particles adsorbed to the inner sidewall of the through hole to form a repair layer.

[0015] The stack semiconductor chip provided by the embodiments of the present application and the preparation method thereof and the repair method of the through hole, the stack semiconductor chip is provided by arranging at least two layers of crystal grains in a stacked manner, at least one of the at least two layers of crystal grains has a through hole; at the same time, by arranging a repair layer and a conductor, the repair layer is adhered to the inner sidewall of the through hole to smooth the inner sidewall, so that the defects of the through hole are repaired, and the influence of the defects of the through hole on the subsequent filling of the metal to form the conductor and the conductivity of the conductor is avoided. In addition, the conductor is formed in the space outside the repair layer of the through hole, so as to electrically connect the at least two layers of crystal grains. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A structure diagram of a stacked semiconductor chip provided by an embodiment of the present application;

[0018] Figure 2 A flow chart of a preparation method of a stacked semiconductor chip provided by an embodiment of the present application;

[0019] Figure 3 A structure diagram of a structure in which a through hole is provided through at least two wafers;

[0020] Figure 4 A diagram of a fluid flowing through an inner sidewall of a through hole;

[0021] Figure 5 A diagram of curing conductive particles on an inner sidewall of a through hole;

[0022] Figure 6 A structure diagram of forming a repair layer on an inner sidewall of a through hole;

[0023] Figure 7 A structure diagram of forming a conductor in a through hole;

[0024] Figure 8 A flow chart of a repair method of a through hole provided by an embodiment of the present application.

[0025] Marking description

[0026] Die 11, repair layer 12, conductor 13, wafer 14, through hole 141, conductive particle 15. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0028] The terms "first", "second", "third", etc. are used only for descriptive purposes and do not connote or imply relative importance or a number of the indicated technical features. Thus, features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. In the embodiments of the present application, all directional indications (such as up, down, left, right, front, back, etc.) are used only for the purpose of explanation of relative positional relationships, movement conditions, etc. between components, and if the specific posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0029] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor does it necessarily refer to a separate or alternative embodiment, which is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0031] Please refer to Figure 1 , Figure 1 A schematic structural diagram of a stacked semiconductor chip is provided for an embodiment of the present application; in the embodiment, a stacked semiconductor chip is provided, which includes at least two layers of dies 11, a repair layer 12 and a conductor 13 arranged in layers.

[0032] At least one of the at least two layers of dies 11 has a through hole; the present application takes the example of a through hole penetrating the at least two layers of dies 11. The repair layer 12 adheres to the inner side wall of the through hole to smooth the inner side wall, thereby repairing the defects of the through hole by the repair layer 12, avoiding the influence of the defects of the through hole on the formation of the conductor 13 and the conductive performance of the conductor 13, so that the through hole and the conductor 13 define a through silicon via with good conductive performance. It can be understood that the repair layer 12 defines a hollow.

[0033] In an embodiment, the at least two layers of dies 11 include a memory die and a logic die, and the memory die and the logic die are connected by a three-dimensional heterogeneous integration of hybrid bonding and TSV technology.

[0034] Specifically, the repair layer 12 includes conductive particles 15 (see below Figure 4 ) that are physically agglomerated. The material of the repair layer 12 includes a binder and the conductive particles 15 mixed together. The conductive particles 15 include silver nanoparticles and / or metal particles. The metal particles can be copper metal particles or aluminum metal particles, etc. In some embodiments, the conductive particles 15 include silver nanoparticles and metal particles, because silver has strong conductivity and copper has relatively large resistance. Thus, the resistance value of the corresponding repair layer 12 can be adjusted by adjusting the proportion of silver nanoparticles and metal particles according to actual needs. In this embodiment, the proportion of the binder, silver nanoparticles, and metal particles is 1:1:(9-11). In a preferred embodiment, the proportion of the binder, silver nanoparticles, and metal particles is 1:1:10. Of course, in other embodiments, the repair layer 12 can also include residual fluid medium.

[0035] The conductor 13 is formed in the space outside the repair layer 12 of the through hole, i.e., the conductor 13 is formed in the hollow to electrically connect the at least two layers of dies 11. One conductor 13 is arranged in one through hole. Those skilled in the art can understand that the through hole and the conductor 13 form a through silicon via on the chip to interconnect the two adjacent layers of dies 11 through the through silicon via.

[0036] Specifically, the material of the conductor 13 can include graphene and / or carbon nanotubes and agglomerates, and the agglomerates are filled between the graphene and / or carbon nanotubes. The agglomerates arranged between the graphene and / or carbon nanotubes are conducive to the agglomeration and stabilization of the graphene and / or carbon nanotubes, which not only improves the density of the conductor 13 to improve the conductivity of the through silicon via, but also speeds up the filling process during the formation of the conductor 13 to improve the preparation efficiency.

[0037] The stacked semiconductor chip provided in the embodiment includes the at least two layers of dies 11 arranged in layers. At least one of the at least two layers of dies 11 has a through hole. The repair layer 12 is arranged to adhere to the inner side wall of the through hole to smooth the inner side wall, so as to repair the defects of the through hole through the repair layer 12, thereby avoiding the influence of the defects of the through hole on the formation of the conductor 13 and the conductivity of the conductor 13. In addition, the conductor 13 is formed in the space outside the repair layer 12 of the through hole to electrically connect the at least two layers of dies 11.

[0038] The stacked semiconductor chip can be prepared by the preparation method of the stacked semiconductor chip provided in the following embodiments.

[0039] Specifically, refer to Figure 2 , Figure 2 The flowchart of the preparation method of the chip stacked semiconductor chip provided in an embodiment of the present application; in the embodiment, a preparation method of a chip stacked semiconductor chip is provided, which comprises the following steps:

[0040] Step S11: providing at least two wafers; wherein at least one of the wafers has a through hole.

[0041] In a specific embodiment, refer to Figure 3 , Figure 3 The structural diagram of the at least two wafers provided with the through hole; the through hole 141 penetrates at least two wafers 14, which is taken as an example in the following embodiments. In specific embodiments, ion etching technology or laser drilling technology can be used to form the through hole 141 on the wafer 14. The specific diameter, position and other process parameters of the through hole 141 can be set according to actual conditions, and the present application does not limit them. The specific process can refer to the process of forming a through hole in the existing through silicon via forming process.

[0042] Step S12: adhering a repair layer to the inner side wall of the through hole to smooth the inner side wall.

[0043] Wherein, during the process of forming the through hole 141, scallop-shaped defects and the like will be left on the inner side wall of the through hole 141, which will affect the subsequent filling of the conductive metal and further affect the conductive performance of the formed through silicon via. Therefore, in the specific implementation process, the repair layer 12 can be adhered to the inner side wall of the through hole 141 to smooth the inner side wall of the through hole 141, so as to repair the defects of the through hole 141. In the specific implementation process, step S2 specifically comprises:

[0044] Step S121: flowing the fluid mixed with the conductive particles 15 through the inner side wall of the through hole 141, so that at least part of the conductive particles 15 are adsorbed to the inner side wall of the through hole 141.

[0045] Wherein, step S121 further comprises: preparing the fluid mixed with the conductive particles 15.

[0046] Specifically, the fluid of the adhesive, the conductive particles 15 and the fluid medium is prepared according to a predetermined proportion.

[0047] The adhesive can be silver amalgam or copper amalgam, etc. The conductive particles 15 include silver nanoparticles and / or metal particles. The metal particles can be copper metal or aluminum metal, etc. In some embodiments, the conductive particles 15 include silver nanoparticles and metal particles; in this way, the resistance value of the corresponding repair layer 12 can be adjusted by adjusting the proportion of silver nanoparticles and metal particles according to actual needs. The fluid medium can be a silicone oil substance, such as methyl silicone oil, ethyl silicone oil, phenyl silicone oil, methyl hydrogen-containing silicone oil, methyl phenyl silicone oil, ethyl hydrogen-containing silicone oil, hydroxyl hydrogen-containing silicone oil, etc. Of course, the fluid medium can also be a sodium chloride solution, a potassium hydroxide and sodium carbonate solution.

[0048] In the implementation process, the adhesive, silver nanoparticles, metal particles and fluid medium can be mixed in a predetermined proportion, then stirred for a certain time, and then ultrasonically treated for a certain time to prepare a uniformly mixed fluid. The stirring time and ultrasonic time can be set according to actual conditions. It can be understood that in this embodiment, the fluid medium is used to assist the flow of the fluid.

[0049] In some embodiments, the proportion of the adhesive, silver nanoparticles, metal particles and fluid medium is 1:1:(9-11):(9-11). Preferably, the proportion of the adhesive, silver nanoparticles, metal particles and fluid medium is 1:1:10:10.

[0050] Referring to Figure 4 , Figure 4 is a schematic view of the fluid flowing through the inner side wall of the through hole; since the fluid includes a fluid medium; therefore, in the implementation process of step S121, the fluid can flow directly through the through hole 141; of course, the fluid can also be loaded into a liquid pressurizing tool, and the fluid can be forced into the through hole 141 by the liquid pressurizing tool to flow through the through hole 141. The injection pressure of the liquid pressurizing tool is approximately the same as the normal water flow pressure, and can be 0.1-0.4 Mpa. The time for the fluid to flow through the through hole 141 is positively correlated with the size of the aperture of the through hole 141, and can be set according to actual conditions.

[0051] In the process of flowing through the through hole 141, the fluid generates slight electric charge by rubbing against the inner side wall of the through hole 141, and the electric charge adsorbs the conductive particles 15 mixed with the adhesive, so that the conductive particles 15 accumulate in large quantities at the defects of the through hole 141, and then the defects of the through hole 141 are repaired by the adsorbed conductive particles 15. The process is relatively simple and convenient, and the ability to fill metal in the through hole 141 to form the conductor 13 is stronger. In the position where the defects of the through hole 141 are obvious, the flow rate of the fluid will increase, the electric charge generated by the fluid rubbing against the inner side wall of the through hole 141 will increase, and more conductive particles 15 will be adsorbed under the adsorption of the electric charge, so that the defects of the inner side wall of the through hole 141 are repaired to different degrees.

[0052] Step S122: The conductive particles 15 adsorbed on the inner side wall of the through hole 141 are solidified to form a repair layer 12.

[0053] Specifically, referring to Figure 5 , Figure 5 is a schematic view of solidifying the conductive particles on the inner side wall of the through hole. Since the silver amalgam adhesive can be solidified after ultraviolet light treatment, in specific embodiments, ultraviolet light can be used to irradiate the inner side wall of the through hole 141 for a predetermined time, so as to solidify the conductive particles 15 adsorbed on the inner side wall of the through hole 141, ensure the stability of the conductive particles 15 on the inner side wall of the through hole 141, and then form a stable repair layer 12. The structure of the formed repair layer 12 can be specifically referred to Figure 6 , Figure 6 is a structural schematic view of forming the repair layer 12 on the inner side wall of the through hole 141. The predetermined time can be 1-5 min.

[0054] Step S13: Forming a conductor in the space outside the repair layer of the through hole.

[0055] The structure of the formed conductor can be specifically referred to Figure 7 , Figure 7 is a structural schematic view of forming a conductor in the through hole. Specifically, a metal can be filled in the through hole 141 by using a magnetron sputtering or electroplating method, so as to form a conductor 13 placed in the through hole 141, and then a silicon through hole with more excellent and stable conductive performance is obtained. The specific process flow of filling metal in the through hole 141 is the same as or similar to that of the prior art, and the same or similar technical effects can be achieved. For details, please refer to the prior art.

[0056] Of course, in other embodiments, a repair layer 12 can also be formed on the inner side wall of the through hole 141 by using electroplating or deposition, etc. The formation method of the repair layer 12 is not limited in the application, as long as the inner side wall of the through hole 141 can be repaired.

[0057] Of course, in the specific implementation process, the preparation method of the stacked semiconductor chip further includes other steps for preparing the stacked semiconductor chip, such as packaging and cutting at least two layers of stacked wafers 14, and the specific implementation process is the same as or similar to the prior art, and the same or similar technical effects can be achieved, and details can be referred to the prior art, which will not be repeated here.

[0058] The preparation method of the stacked semiconductor chip provided in the embodiment can prepare a fluid that can flow, so that the conductive particles 15 in the fluid are adsorbed on the inner side wall of the through hole 141 in the case of natural flow of the fluid, and then the conductive particles 15 adsorbed on the inner side wall of the through hole 141 are solidified to form a repair layer 12 on the inner side wall of the through hole 141. In turn, the repair layer 12 is used to repair the defects on the inner side wall of the through hole 141. The process of repairing the through hole 141 is simple and convenient, and the filling capacity of the through hole 141 is enhanced. At the same time, the conductor 13 is formed in the space outside the repair layer 12 of the through hole 141 to obtain a through silicon via with more excellent and stable conductive performance, and the at least two dies 11 are electrically connected.

[0059] Referring to Figure 8 , Figure 8 The flow chart of the through hole repair method provided in an embodiment of the present application; at present, in the opening process of the through silicon via, the existing through hole processing process will leave scallop-shaped undulations and other defects on the inner side wall of the through hole 141. These defects will affect the filling of the subsequent conductive metal, and in turn affect the conductive performance of the formed through silicon via. Therefore, in the present embodiment, a through hole repair method is provided, which can repair the defect position of the through hole 141, and in turn improve the filling performance of the through hole 141 and the conductive performance of the formed through silicon via. Specifically, the through hole repair method comprises:

[0060] Step S21: providing a semiconductor sheet; wherein the semiconductor sheet has a through hole.

[0061] The semiconductor sheet can be a wafer or a die. In an embodiment, the semiconductor sheet includes at least two layers of wafers 14, and at least one of the at least two layers of wafers 14 has a through hole 141. In specific embodiments, ion etching technology or laser drilling technology can be used to open the through hole 141 on the semiconductor sheet. The specific diameter, position and other process parameters of the through hole 141 can be set according to the actual situation, and the present application does not limit this, and the specific process can be referred to the existing through hole opening process.

[0062] Step S22: flowing the fluid mixed with conductive particles through the inner side wall of the through hole, so that at least part of the conductive particles are adsorbed on the inner side wall of the through hole.

[0063] Step S23: solidifying the conductive particles adsorbed on the inner side wall of the through hole to form a repair layer.

[0064] The specific implementation process of steps S22 to S23 is the same as or similar to the specific implementation process of steps S121 to S122 in the method for preparing a stacked semiconductor chip, and can achieve the same or similar technical effects. For details, refer to the relevant description above, which will not be repeated here.

[0065] The repair method for the through hole provided in this embodiment can prepare a fluid that can flow, so that the conductive particles 15 in the fluid are adsorbed on the inner side wall of the through hole 141 under the condition that the fluid naturally flows, and then the conductive particles 15 adsorbed on the inner side wall of the through hole 141 are solidified to form a repair layer 12 on the inner side wall of the through hole 141. The repair layer 12 is used to repair defects on the inner side wall of the through hole 141. The process of repairing the through hole 141 is simple and convenient, and the filling capacity of the through hole 141 is enhanced, which can effectively improve the conductive performance of the through silicon via.

[0066] In this embodiment, a composite material for repairing a through hole is also provided, which can be used to repair defects of the through hole 141. The composite material mainly consists of an adhesive, conductive particles 15, and a fluid medium. The adhesive is used to bond with the through silicon via after solidification, and the fluid medium is used to generate charges by friction with the inner side wall of the through hole 141 in the process of injecting the through hole 141 in a flowing manner, so that the conductive particles 15 of the composite material are adsorbed on the inner side wall of the through hole 141. The conductive particles 15 include silver nanoparticles and / or metal particles. The metal particles can be copper metal particles or aluminum metal particles, etc. In some specific embodiments, the conductive particles 15 include silver nanoparticles and metal particles. The silver nanoparticles and metal particles are used to fill the defect position of the through hole 141 after the composite material is adsorbed on the inner side wall of the through hole 141, so as to repair the defect position and realize the conductive function.

[0067] Specifically, the ratio of the adhesive, silver nanoparticles, metal particles, and fluid medium is 1:1:(9-11):(9-11). In a preferred embodiment, the ratio of the adhesive, silver nanoparticles, metal particles, and fluid medium is 1:1:10:10.

[0068] The composite material for repairing the through hole 141 provided by the embodiment can have the performance of flowing liquid by adding a fluid medium, so that the composite material can generate electric charges by rubbing with the inner side wall of the through hole 141 during the process of repairing the through hole 141, the metal particles mixed with the adhesive are adsorbed by the electric charges, the metal particles are accumulated in a large amount at the defects of the through hole 141, and then the defects of the through hole 141 are repaired by the adsorbed metal particles, the process is relatively simple and convenient, and the ability of filling metal in the through hole 141 is stronger.

[0069] The above is only the embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A stacked semiconductor chip, characterized by, The semiconductor structure comprises: at least two layers of crystal grains arranged in a stack; at least one of the layers of crystal grains has a through-hole; a repair layer adhered to an inner sidewall of the through-hole to smooth the inner sidewall, the repair layer comprising electrically conductive particles physically agglomerated together, the repair layer forming a hollow in the through-hole; a conductor formed in the hollow to electrically connect the at least two layers of crystal grains.

2. The stacked semiconductor chip of claim 1, wherein, The repair layer comprises an adhesive mixed together with the electrically conductive particles.

3. The stacked semiconductor chip of claim 2, wherein, The electrically conductive particles comprise silver nanoparticles and / or metal particles.

4. The stacked semiconductor chip of claim 3, wherein, The electrically conductive particles comprise the silver nanoparticles and the metal particles; and the adhesive, the silver nanoparticles, and the metal particles are in a ratio of 1:1:(9-11).

5. The stacked semiconductor chip of claim 4, wherein, The adhesive, the silver nanoparticles, and the metal particles are in a ratio of 1:1:

10.

6. A method of fabricating a stack of semiconductor chips, comprising: The semiconductor structure comprises: providing at least two layers of wafers; at least one of the layers of wafers has a through-hole; adhering a repair layer to an inner sidewall of the through-hole to smooth the inner sidewall; the repair layer forming a hollow in the through-hole; forming a conductor in the hollow.

7. The method of claim 6, wherein the step of forming the stack of semiconductor chips is performed by a method comprising: The step of adhering the repair layer to the inner sidewall of the through-hole comprises: flowing a fluid mixed with electrically conductive particles through the inner sidewall of the through-hole to cause at least some of the electrically conductive particles to adhere to the inner sidewall of the through-hole; solidifying the electrically conductive particles adhered to the inner sidewall of the through-hole to form the repair layer.

8. The method of claim 7, wherein the step of forming the stack of semiconductor chips is performed by a method comprising: The electrically conductive particles comprise silver nanoparticles and / or metal particles.

9. The method for fabricating a stacked semiconductor chip according to claim 8, characterized in that, The fluid is mixed with an adhesive and a fluid medium; the electrically conductive particles comprise the silver nanoparticles and the metal particles; and the adhesive, the silver nanoparticles, the metal particles, and the fluid medium are in a ratio of 1:1:(9-11):(9-11).

10. A method of repairing a through hole, characterized by, The semiconductor structure comprises: providing a semiconductor sheet having a through-hole; flowing a fluid mixed with electrically conductive particles through an inner sidewall of the through-hole to cause at least some of the electrically conductive particles to adhere to the inner sidewall of the through-hole; solidifying the electrically conductive particles adhered to the inner sidewall of the through-hole to form a repair layer; the repair layer forming a hollow in the through-hole; the hollow for disposing a conductor.

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