Reconfigurable complementary metal-oxide-semiconductor devices and methods

Abstract

The present application relates to reconfigurable complementary metal-oxide semiconductor devices and methods, and discloses reconfigurable complementary metal-oxide semiconductor devices having multiple modes of operation, such as frequency doubling mode and the like. The devices include N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs) that are threshold voltage programmable, connected in parallel, and have electrically connected gates. The threshold voltages of the NFETs and PFETs can be programmed simultaneously, and the mode of operation of the device can be set according to a particular combination of threshold voltages achieved in the NFETs and PFETs. Alternatively, the threshold voltages of the NFETs and PFETs can be reprogrammed simultaneously to switch the mode of operation. Such devices are small and achieve frequency doubling and other functions with minimal power consumption. The present application also discloses methods for forming the devices and for reconfiguring the devices (i.e., for simultaneously programming the NFETs and PFETs to set or switch the mode of operation).

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to threshold voltage programmable field effect transistors (e.g., ferroelectric field effect transistors (FeFETs) and the like), and more particularly, to reconfigurable complementary metal oxide semiconductor (CMOS) devices, methods of forming the devices, and methods of reconfiguring (i.e., programming) the devices. BACKGROUND

[0002] Frequency multipliers are basic components of wireless communication systems where stable high frequency oscillations are required. Current state-of-the-art frequency multipliers include filtering and amplification circuits. Unfortunately, such filtering and amplification circuits consume a large amount of chip area and power. SUMMARY

[0003] Embodiments of a reconfigurable complementary metal oxide semiconductor (CMOS) device are disclosed herein. The device includes a plurality of field effect transistors (FETs), particularly N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). Both the NFETs and the PFETs can be threshold voltage programmable FETs. Moreover, the NFETs and the PFETs can be electrically connected in parallel and can have electrically connected gates. With this configuration, the threshold voltages of the NFETs and the PFETs can be simultaneously programmed (as discussed further in the DETAILED DESCRIPTION section) by applying a particular set of voltage conditions. As a result of applying the particular set of voltage conditions, a particular threshold voltage combination of a plurality of possible threshold voltage combinations can be achieved in the two FETs, such that the device is operable in a particular operating mode of a plurality of possible operating modes (e.g., a frequency multiplication operating mode, a positive signal transmission mode, a signal blocking mode, etc.). With this configuration, the threshold voltages of the NFETs and the PFETs can be optionally reprogrammed (e.g., in the field) by applying a different set of voltage conditions to achieve a different particular threshold voltage combination in the two FETs and thus switch the device to a different operating mode of the plurality of possible operating modes.

[0004] Embodiments of methods of forming the reconfigurable complementary metal-oxide-semiconductor (CMOS) devices described above are also disclosed herein. The methods can include providing a substrate, and forming the reconfigurable CMOS device on the substrate. In particular, the methods can include forming a complementary pair of field effect transistors (FETs), specifically an N-type FET (NFET) and a P-type FET (PFET), on the substrate. The NFET and PFET can be formed such that they are threshold voltage programmable FETs. Further, the NFET and the PFET can be formed such that they are electrically connected in parallel and have electrically connected gates.

[0005] Embodiments of methods for reconfiguring (also referred to herein as programming) the reconfigurable complementary metal-oxide-semiconductor (CMOS) devices described above are also disclosed herein. In particular, the methods can include providing such a reconfigurable CMOS device. The methods can also include simultaneously programming the threshold voltages of the NFET and the PFET. In particular, the threshold voltages of the NFET and the PFET can be simultaneously programmed by applying a particular set of voltage conditions (as discussed further in the DETAILED DESCRIPTION section). As a result of said applying the particular set of voltage conditions, a particular threshold voltage combination of a plurality of possible threshold voltage combinations can be reached in the two FETs, such that the device is operable in a particular operational mode of a plurality of possible operational modes (e.g., a frequency doubling operational mode, a positive signal transmission mode, a signal blocking mode, etc.). Alternatively, the methods can also include simultaneously reprogramming the threshold voltages of the NFET and the PFET (e.g., in the field) by applying a different set of voltage conditions to reach a different particular threshold voltage combination in the two FETs, and thus switch the device to a different operational mode of the plurality of possible operational modes. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present application will be better understood from the following detailed description taken in conjunction with the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0007] Figure 1 is a schematic diagram showing an embodiment of the disclosed reconfigurable complementary metal-oxide-semiconductor (CMOS) device;

[0008] Figure 2A shows an example layout of an embodiment of the reconfigurable CMOS device, and Figure 2B and 2C shows a cross-sectional view of an example threshold voltage programmable FET (e.g., an N-type and a P-type ferroelectric field effect transistor (FeFET)) that can be included in an embodiment of the reconfigurable CMOS device;

[0009] Figure 3 is a table showing example set voltage conditions that can be used to reconfigure an embodiment of the reconfigurable CMOS device including N-type and P-type FeFETs;

[0010] Figure 4A-1 is a graph showing negative and positive threshold voltage curves for a first device state, and Figure 4A-2 shows graphs including drain current - gate voltage curves, input voltage signals, and output current signals for Figure 3 the modes listed in the table and related to the first device state;

[0011] Figure 4B-1 is a graph showing negative and positive threshold voltage curves for a second device state, and Figure 4B-2 shows graphs including drain current - gate voltage curves, input voltage signals, and output current signals for Figure 3 the positive signal transmission mode listed in the table and related to the second device state;

[0012] Figure 4C-1 is a graph showing negative and positive threshold voltage curves for a third device state, and Figure 4C-2 shows graphs including drain current - gate voltage curves, input voltage signals, and output current signals for Figure 3 the signal blocking mode listed in the table and related to the third device state;

[0013] Figure 4D-1 is a graph showing negative and positive threshold voltage curves for a fourth device state, and Figure 4D-2 shows graphs including drain current - gate voltage curves, input voltage signals, and output current signals for Figure 3 the negative signal transmission mode listed in the table and related to the fourth device state;

[0014] Figure 4E-1 is a graph showing negative and positive threshold voltage curves for a fifth device state, and Figure 4E-2 shows graphs including drain current - gate voltage curves, input voltage signals, and output current signals for Figure 3 the alternative transmission mode listed in the table and related to the fifth device state;

[0015] Figure 5 is a flowchart showing an embodiment of a method for forming the reconfigurable CMOS device; and

[0016] Figure 6 is a flowchart showing an embodiment of a method for reconfiguring the reconfigurable CMOS device. DETAILED DESCRIPTION

[0017] As mentioned above, frequency multipliers are essential components of wireless communication systems where stable high frequency oscillations are required. Current state-of-the-art frequency multipliers include filtering and amplification circuits. Unfortunately, such filtering and amplification circuits consume a large amount of chip area and power.

[0018] In view of the above, embodiments of a reconfigurable complementary metal-oxide-semiconductor (CMOS) device having a plurality of different modes of operation, including but not limited to a frequency multiplication mode, are disclosed herein. The device can include an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) that are threshold voltage programmable, connected in parallel, and have electrically connected gates. With this configuration, the threshold voltages of the NFET and PFET can be programmed simultaneously, and the mode of operation of the device can be set according to a particular combination of threshold voltages achieved in the NFET and PFET during programming. For example, if the NFET has a low positive threshold voltage and the PFET has a low negative threshold voltage, the device can operate in a frequency multiplication mode. Furthermore, the threshold voltages of the NFET and PFET can be reprogrammed (e.g., in the field) simultaneously as needed to switch the mode of operation of the device. Such a device can be small (i.e., can consume a minimum amount of chip area) and can achieve frequency multiplication and other functions with minimal power consumption. Embodiments of methods for forming the device and embodiments of methods for reconfiguring the device (i.e., for simultaneously programming the NFET and PFET to set or switch the mode of operation) are also disclosed herein.

[0019] Figure 1 FIG. 1 is a schematic diagram showing an embodiment of a reconfigurable complementary metal-oxide-semiconductor (CMOS) device 100. Figures 2A-2C FIG. 2 is a top view layout and two cross-sectional views (discussed in more detail below) showing an example embodiment of the device 100.

[0020] Referring to FIGS. 1-2 together, Figure 1 and 2A -2C, the reconfigurable CMOS device 100 can include a pair of complementary field effect transistors (FETs), specifically an N-type FET 110 (NFET) and a P-type FET 120 (PFET). The NFET 110 and PFET 120 can be electrically connected in parallel and can have electrically connected gates.

[0021] For purposes of illustration, the NFET 110 and PFET 120 of the device 100 are described below and shown in the figures as planar FETs located on a bulk semiconductor substrate (e.g., a bulk silicon substrate). However, it should be understood that the figures are not intended to be limiting. Instead, the NFET and PFET can be non-planar FETs and / or located on a semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) substrate.

[0022] Embodiments of the disclosed device 100 can include a NFET 110. The NFET 110 can have a first body region (Bl) (e.g., a P-body region) (e.g., defined by a shallow trench isolation (STI) region 205), and in the first body region (Bl), a first channel region (Cl) (e.g., a P- channel region) laterally between a first source region (Sl) (e.g., an N+ source region) and a first drain region (Dl) (e.g., an N+ drain region). Optionally, the NFET 110 can also have a first body contact region (BC1) (e.g., a P+ region) in the first body region (Bl) electrically isolated (e.g., by the STI region 205) from the first source region (Sl) and the first drain region (Dl). The first body contact region (BC1) can facilitate contacting the first body region (Bl) during device programming, as discussed in more detail below. The NFET 110 can also have a first gate (Gl) adjacent to the first channel region (Cl).

[0023] Embodiments of the disclosed device 100 can also include a PFET 120. The PFET 120 can have a second body region (B2) (e.g., an N-body region) (e.g., defined by the STI region 205), and in the second body region (B2), a second channel region (C2) (e.g., an N- channel region) laterally between a second source region (S2) (e.g., a P+ source region) and a second drain region (D2) (e.g., a P+ drain region). Optionally, the PFET 120 can also have a second body contact region (BC2) (e.g., an N+ region) in the second body region (B2) electrically isolated (e.g., by the STI region 205) from the second source region (S2) and the second drain region (D2). The second body contact region (BC2) can facilitate contacting the second body region (B2) during device programming, as discussed in more detail below. The PFET 120 can also have a second gate (G2) adjacent to the second channel region (C2).

[0024] NFET 110 and PFET 120 can be electrically connected in parallel. That is, a first drain region (Dl) of NFET 110 can be electrically connected with a second source region (S2) of PFET 120 (e.g., through local interconnects or through a combination of contacts and back-end-of-line (BEOL) lines). Also, a first source region (Sl) of NFET 110 can be electrically connected with a second drain region (D2) of PFET 120 (e.g., through local interconnects or through a combination of contacts and BEOL lines). Furthermore, the gates of NFET 110 and PFET 120 (i.e., a first gate (Gl) and a second gate (G2)) can also be electrically connected.

[0025] In particular, NFET 110 and PFET 120 can be threshold voltage programmable FETs. That is, NFET 110 can be a threshold voltage programmable NFET, and PFET 120 can be a threshold voltage programmable PFET. Those skilled in the art will appreciate that a threshold voltage programmable FET refers to a FET whose threshold voltage can be programmed (i.e., selectively changed, adjusted, etc.) in response to a particular set of voltage conditions applied to the gate and source / drain regions of the FET and / or the body region of the FET. That is, different sets of voltage conditions applied to the gate and source / drain regions and / or the body region can cause the FET to exhibit different threshold voltages, respectively. In particular, each threshold voltage programmable NFET will have two or more different programmable positive threshold voltages, and each threshold voltage programmable PFET will have two or more different programmable negative threshold voltages. Example voltage programmable FETs that can be included in device 100 include, but are not limited to, ferroelectric field effect transistors (FeFETs), floating gate field effect transistors (FGFETs), and charge-trap field effect transistors (CTFETs). Those skilled in the art will also appreciate that the number of different programmable threshold voltages can vary depending on the type of threshold voltage programmable FET (e.g., FeFET, FGFET, CTFET, etc.). Those skilled in the art will also appreciate that the different sets of voltage conditions applied to the gate and source / drain regions and / or the body region of a threshold voltage programmable FET for programming purposes will vary depending on the type of threshold voltage programmable FET (e.g., FeFET, FGFET, CTFET, etc.) and the conductivity type of the FET (e.g., N-type or P-type) (as discussed in more detail below with respect to method embodiments for reconfiguring device 100).

[0026] For illustrative purposes, device 100 is described in more detail below and illustrated in Figures 2A-2CThe device 100 is shown to include an N-type FeFET 110 and a P-type FeFET 120. That is, Figure 2A is a top view showing an example layout that can be used for such a device 100, and Figure 2B and 2C are cross-sectional views of the N-type FeFET 110 and the P-type FeFET 120, respectively, which are connected in parallel and have electrically connected gates as shown in the layout of Figure 2A .

[0027] It should be understood that the configuration of the first and second gates (G1 / G2) of the NFET 110 and the PFET 120 will depend on what type of threshold voltage programmable FET they are, respectively. For example, in the example embodiment shown in Figures 2A-2C , where the NFET 110 and the PFET 120 are both FeFETs, each gate structure G1, G2 can be a multi-layer gate structure including at least: a ferroelectric layer 147 (e.g., a hafnium oxide layer or some other suitable ferroelectric layer) adjacent to the channel region; and a metal gate layer 148 on the ferroelectric layer 147. Optionally, each gate structure G1, G2 can include a thinner gate insulator layer 146 (e.g., a silicon dioxide layer or other suitable insulator layer) stacked between the channel region and the ferroelectric layer 147 (as shown). Optionally, each gate structure G1, G2 can also include an additional metal gate layer, such that the ferroelectric layer 147 is sandwiched between two metal gate layers (not shown).

[0028] In alternative embodiments (not shown) where the NFET 110 and the PFET 120 are different types of threshold voltage programmable FETs (e.g., FGFETs or CTFETs), the gate structures will be different. For example, the gate structure of an FGFET can be a multi-layer gate structure including: a gate dielectric layer adjacent to the channel region; a floating gate layer (e.g., a polysilicon layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the floating gate layer. The gate structure of a CTFET can be a multi-layer gate structure including: a gate dielectric layer adjacent to the channel region; a charge trapping layer (e.g., a silicon nitride layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the charge trapping layer.

[0029] In any case, within the device 100, the NFET 110 and the PFET 120 can have separate first and second gates G1 and G2, respectively, which are electrically connected (e.g., by local interconnects or by a combination of contacts and back-end-of-line routing). Alternatively, as shown in Figures 2A-2CAs shown in the middle, the device 100 can include a single gate structure 145 (referred to herein as a common gate structure for the NFET and the PFET). This single gate structure 145 (including the aforementioned gate layers) can traverse the first channel region (Cl) of the NFET 110 and the second channel region (C2) of the PFET 120, such that the first gate (Gl) of the NFET 110 and the second gate (G2) of the PFET 120 are merely different portions of the same gate structure.

[0030] Referring also to Figure 1 and Figures 2A-2C The disclosed embodiments of the device 100 can also include an input node 140, an output node 132, a ground node 131, a first programming node 151 (also referred to herein as an NFET programming node), and a second programming node 152 (also referred to herein as a PFET programming node). The input node 140 can be located at the junction between the electrically connected (e.g., on the single gate structure 145, if applicable) first gate (Gl) and the second gate (G2). The output node 132 can be located at the junction between the first drain region (Dl) of the NFET 110 and the second source region (S2) of the PFET 120. The ground node (i.e., the connection to ground) can be located at the junction between the first source region (Sl) of the NFET 110 and the second drain region (D2) of the PFET 120. The NFET programming node 151 can be located at the first body (Bl) of the NFET 110 (e.g., via BC1), and the PFET programming node 152 can be located at the second body (B2) of the PFET (e.g., via BC2).

[0031] In device 100, as described above, the threshold voltages of NFET 110 and PFET 120 can be programmed simultaneously by applying a particular set of voltage conditions to input node 140 (i.e., to gates (Gl) and (G2) of NFET 110 and PFET 120), to NFET programming node 151 (i.e., to first body (Bl) of NFET 110), and to PFET programming node 152 (i.e., to second body (B2) of PFET 120). As a result of the application of this particular set of voltage conditions, device 100 will be programmed (e.g., configured, set, etc.) to operate in one of a plurality of different operating modes. That is, as a result of the application of this particular set of voltage conditions, NFET 110 and PFET 120 will be programmed to collectively have one particular threshold voltage combination of a plurality of possible threshold voltage combinations. Depending on this particular threshold voltage combination, device 100 will operate in a particular operating mode of a plurality of possible operating modes (e.g., a frequency doubling operating mode, a positive signal transmission mode, a signal blocking mode, a negative signal transmission mode, etc.). With this configuration, the threshold voltages of NFET 110 and PFET 120 can be selectively reprogrammed (e.g., in the field) by applying a different set of voltage conditions to achieve a different particular threshold voltage combination in the two FETs and thus switch the device to a different one of the plurality of possible operating modes. In any case, when device 100 operates in a particular one of the plurality of different operating modes, device 100 exhibits a particular one of a plurality of different drain current-gate voltage curves. That is, in various different operating modes, the device exhibits different drain current-gate voltage curves. Thus, device 100 can be reconfigured for different functions.

[0032] For example, NFET 110 can be programmable to have a low positive threshold voltage (low positive Vt) or a high positive threshold voltage (high positive Vt) that is higher than the low positive threshold voltage. PFET 120 can be programmable to have a low negative threshold voltage (low negative Vt) or a high negative threshold voltage (high negative Vt) that is higher than the low negative threshold voltage. It should be understood that one negative threshold voltage is higher than the other when the absolute value of the voltage quantity is higher; one negative threshold voltage is lower than the other when the absolute value of the voltage quantity is lower. If NFET 110 and PFET 120 each have two programmable threshold voltages (as described above), then simultaneous programming of the threshold voltages of the two FETs can be employed to reconfigure device 100 to be in a selected one of four different states, thereby operating in a selected one of four different operating modes. The four different device states can include: a first state in which NFET 110 has the low positive threshold voltage and PFET 120 has the low negative threshold voltage (e.g., for a frequency doubling mode); a second state in which NFET 110 has the low positive threshold voltage and PFET 120 has the high negative threshold voltage (e.g., for a positive signal transmission mode); a third state in which NFET 110 has the high positive threshold voltage and PFET 120 has the high negative threshold voltage (e.g., for a signal blocking mode); and a fourth state in which NFET 110 has the high positive threshold voltage and PFET 120 has the low negative threshold voltage (e.g., for a negative signal transmission mode).

[0033] It should be understood that if NFET 110 and PFET 120 have more than two programmable threshold voltages, then device 100 can be reconfigured to be in any one of more than four different states for more than four different operating modes. For example, NFET 110 can also have an ultra-low positive threshold voltage and PFET 120 can have an ultra-low negative threshold voltage. In this case, additional states of device 100 can include: a fifth state in which NFET 110 has the ultra-low positive threshold voltage and PFET 120 has the ultra-low negative threshold voltage (e.g., for an alternative signal transmission mode); a sixth state in which NFET 110 has the ultra-low positive threshold voltage and PFET 120 has the low negative threshold voltage; and so on.

[0034] Figure 3is a table showing example set voltage conditions that can be used to reconfigure the device 100, which includes an N-type FeFET 110 and a P-type FeFET 120 that are electrically connected in parallel and have electrically connected gates. Specifically, this table shows example voltage conditions that can be applied to the input node 140 (i.e., the gate (G1 / G2)), the NFET programming node 151 (i.e., the first body (B1) of the N-type FeFET 110), and the PFET programming node 152 (i.e., the second body (B2) of the P-type FeFET (120)) to achieve the above-described device states and operating modes.

[0035] For example, to reconfigure the device 100 so that it is in the first device state for the double frequency mode, the input node 140 can be discharged to ground, a particular negative voltage (e.g., -4V) can be applied to the NFET programming node 151, and a corresponding positive voltage (e.g., +4V) can be applied to the PFET programming node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (G1) will force electrons into the first channel region (C1) to ensure that the N-type FeFET 110 has a low positive threshold voltage. In addition, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes into the second channel region (C2) to ensure that the P-type FeFET 120 has a low negative threshold voltage. Figure 4A-1 is a graph showing the negative and positive threshold voltage curves for the first device state, and Figure 4A-2 is a table including the drain current-gate voltage curves, input voltage signals, and output current signals for the double frequency mode that are listed in Figure 3 and are related to the third device state. As shown in Figure 4A-2 this first device state doubles the parabolic portion of the drain current-gate voltage curves twice. This example specifically illustrates how the disclosed device 100 can achieve double frequency without requiring a large amount of chip space or power. As a result, such a device 100 can be the best solution for use in wireless communication systems that require stable high frequency oscillation.

[0036] To reconfigure the device 100 so that it is in the second device state for the positive signal transmission mode, the input node 140 can be discharged to ground, a particular negative voltage (e.g., -4V) can be applied to the NFET programming node 151, and the same negative voltage (e.g., -4V) can be applied to the PFET programming node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (G1) will force electrons into the first channel region (C1) to ensure that the N-type FeFET 110 has a low positive threshold voltage. However, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes away from the second channel region (C2) to ensure that the P-type FeFET 120 has a high negative threshold voltage.Figure 4B-1 is a graph showing the negative and positive threshold voltage curves of this second device state, and Figure 4B-2 is a graph including the drain current-gate voltage curves, input voltage signal, and output current signal for the positive signal transmission mode listed in the table for Figure 3 and associated with this second device state. As shown, this second device state helps block the negative signal portion and only transmit the positive signal portion.

[0037] To reconfigure the device 100 to be in a third device state for a signal blocking mode, the input node 140 can be discharged to ground, a particular positive voltage (e.g., +4V) can be applied to the NFET program node 151, and a corresponding negative voltage (e.g., -4V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons out of the first channel region (Cl) to ensure that the N-type FeFET 110 has a high positive threshold voltage. The direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes out of the second channel region (C2) to ensure that the P-type FeFET 120 has a high negative threshold voltage. Figure 4C-1 is a graph showing the negative and positive threshold voltage curves of this third device state, and Figure 4C-2 is a graph including the drain current-gate voltage curves, input voltage signal, and output current signal for the signal blocking mode listed in the table for Figure 3 and associated with this third device state. As shown, this third device state helps block both the positive and negative signal portions.

[0038] To reconfigure the device 100 to be in a fourth device state for a negative signal transmission mode, the input node 140 can be discharged to ground, a particular positive voltage (e.g., +4V) can be applied to the NFET program node 151, and the same positive voltage (e.g., +4V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons out of the first channel region (Cl) to ensure that the N-type FeFET 110 has a high positive threshold voltage. However, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes into the second channel region (C2) to ensure that the P-type FeFET 120 has a low negative threshold voltage. Figure 4D-1 is a graph showing the negative and positive threshold voltage curves of this fourth device state, and Figure 4D-2 is a graph including the drain current-gate voltage curves, input voltage signal, and output current signal for the negative signal transmission mode listed in the table for Figure 3 and associated with this fourth device state. As shown, this fourth device state helps block the positive signal portion and only transmit the negative signal portion.

[0039] As mentioned above, the N-type FeFET 110 and the P-type FeFET 120 can have two or more possible programmable threshold voltages. For example, the N-type FeFET can also have an ultra-low positive threshold voltage and the P-type FeFET can also have an ultra-low negative threshold voltage. In this case, to reconfigure the device 100 to be in a fifth device state for an alternative transmission mode, the input node 140 can be discharged to ground, a particular high negative voltage (i.e., a higher negative voltage than the negative voltage used for the first state, e.g., -5V) can be applied to the NFET program node 151, and a corresponding high positive voltage (e.g., +5V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons into the first channel region (Cl) to ensure that the N-type FeFET 110 has an ultra-low positive threshold voltage. In addition, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes into the second channel region (C2) to ensure that the P-type FeFET 120 has an ultra-low negative threshold voltage. Figure 4E-1 is a graph showing the negative and positive threshold voltage curves of the fifth device state, and Figure 4E-2 is a table including the alternative transmission mode's drain current-gate voltage curves, input voltage signals, and output current signals listed in Figure 3 and related to the fifth device state. As shown, this fifth state supports signal transmission along the linear portion of the drain current-gate voltage curves. This example specifically illustrates that different portions of the drain current-gate voltage curves can be accessed by different programming / erasing voltages.

[0040] It should be appreciated that for embodiments in which the device 100 includes different types of threshold voltage programmable FETs (e.g., FGFETs or CTFETs, instead of FeFETs), a different set of voltage conditions will be employed to simultaneously program the NFET 110 and the PFET 120 to reconfigure the device 100. This is because the mechanisms for implementing threshold voltage programming in FGFETs and CTFETs are different from the mechanisms for implementing threshold voltage programming in FeFETs.

[0041] Referring to the flowchart of Figure 5 embodiments of a method of forming a reconfigurable complementary metal-oxide-semiconductor (CMOS) device are also disclosed herein. The method can include providing a semiconductor substrate (see process step 502). The semiconductor substrate can be a bulk semiconductor substrate (e.g., a bulk silicon substrate). Alternatively, the semiconductor substrate can be a semiconductor-on-insulator (e.g., a silicon-on-insulator (SOI) substrate).

[0042] The method can also include forming a reconfigurable complementary metal-oxide-semiconductor (CMOS) device on the semiconductor substrate (see process step 504). In particular, the reconfigurable CMOS device 100 can be formed at process step 504 using conventional CMOS processing techniques, except that particular front-end-of-the-line (FEOL), middle-of-the-line (MOL), and back-end-of-the-line (BEOL) CMOS processing steps should be performed at process step 504 to form, for example Figure 1 and 2A a novel reconfigurable CMOS device 100 as shown in -2C and including a complementary pair of field effect transistors (FETs) (i.e., an N-type FET 110 (NFET) and a P-type FET 120 (PFET)), which are threshold voltage programmable FETs, are connected in parallel, and have electrically connected gates.

[0043] More particularly, the NFET 110 can be formed to have a first body region (Bl) (e.g., a P-body region) (e.g., defined by a shallow trench isolation (STI) region 205), and in the first body region (Bl), a first channel region (Cl) (e.g., a P- channel region) laterally between a first source region (Sl) (e.g., an N+ source region) and a first drain region (Dl) (e.g., an N+ drain region). Optionally, the NFET 110 can be formed to also have, in the first body region (Bl), a first body contact region (BCl) (e.g., a P+ region) electrically isolated (e.g., by the STI region 205) from the first source region (Sl) and the first drain region (Dl). The first body contact region (BCl) can facilitate contacting the first body region (Bl) during device programming, as discussed in more detail below. A first gate (Gl) can be formed adjacent the first channel region (Cl). Meanwhile, the PFET 120 can be formed to have a second body region (B2) (e.g., an N- body region), and in the second body region (B2), a second channel region (C2) (e.g., an N- channel region) laterally between a second source region (S2) (e.g., a P+ source region) and a second drain region (D2) (e.g., a P+ drain region). Optionally, the PFET 120 can also be formed to have, in the second body region (B2), a second body contact region (BC2) (e.g., an N+ region) electrically isolated (e.g., by the STI region 205) from the second source region (S2) and the second drain region (D2). The second body contact region (BC2) can facilitate contacting the second body region (B2) during device programming, as discussed in more detail below. A second gate (G2) can be formed adjacent the second channel region (C2).

[0044] As shown, NFET 110 and PFET 120 can be formed as planar FETs. Alternatively, NFET 110 and PFET 120 can be formed as non-planar FETs (not shown).

[0045] NFET 110 and PFET 120 can also be formed such that they are threshold voltage programmable FETs. Those skilled in the art will appreciate that the configuration of the first and second gates (Gl / G2) of NFET 110 and PFET 120 will depend on the type of threshold voltage programmable FET that is formed. For example, the gate structure of a FeFET can be formed to include at least: a ferroelectric layer 147 (e.g., a hafnium oxide layer or some other suitable ferroelectric layer) adjacent to the channel region; and a metal gate layer 148 (e.g., as shown in FIGS. 1A and IB) on the ferroelectric layer 147. Optionally, the gate structure of a FeFET can be formed to also include a thinner gate insulator layer 146 (e.g., a silicon dioxide layer or other suitable insulator layer) stacked between the channel region and the ferroelectric layer 147 (as shown), and / or an additional metal gate layer such that the ferroelectric layer 147 is sandwiched between two metal gate layers (not shown). In alternative embodiments (not shown) where different types of threshold voltage programmable FETs (e.g., FGFETs or CTFETs) are formed, the gate structure will be different. For example, the gate structure of an FGFET can be formed to include: a gate dielectric layer adjacent to the channel region; a floating gate layer (e.g., a polysilicon layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the floating gate layer. The gate structure of a CTFET can be formed to include: a gate dielectric layer adjacent to the channel region; a charge trapping layer (e.g., a silicon nitride layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the charge trapping layer. Figure 2B and 2C As shown, the gate structure of a FeFET can be formed to include at least: a ferroelectric layer 147 (e.g., a hafnium oxide layer or some other suitable ferroelectric layer) adjacent to the channel region; and a metal gate layer 148 (e.g., as shown in FIGS. 1A and IB) on the ferroelectric layer 147. Optionally, the gate structure of a FeFET can be formed to also include a thinner gate insulator layer 146 (e.g., a silicon dioxide layer or other suitable insulator layer) stacked between the channel region and the ferroelectric layer 147 (as shown), and / or an additional metal gate layer such that the ferroelectric layer 147 is sandwiched between two metal gate layers (not shown). In alternative embodiments (not shown) where different types of threshold voltage programmable FETs (e.g., FGFETs or CTFETs) are formed, the gate structure will be different. For example, the gate structure of an FGFET can be formed to include: a gate dielectric layer adjacent to the channel region; a floating gate layer (e.g., a polysilicon layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the floating gate layer. The gate structure of a CTFET can be formed to include: a gate dielectric layer adjacent to the channel region; a charge trapping layer (e.g., a silicon nitride layer) adjacent to the gate dielectric layer; and a control gate layer (e.g., a metal gate layer) adjacent to the charge trapping layer.

[0046] It should be noted that the first and second gates Gl and G2 can be formed as separate gates and then electrically connected (e.g., by local interconnects or by a combination of contacts and back-end-of-line routing). Alternatively, as shown in FIGS. 1A and IB, a single gate structure spans the first channel region (Cl) of NFET 110 and the second channel region (C2) of PFET 120 such that the first gate (Gl) of NFET 110 and the second gate (G2) of PFET 120 are just different parts of the same gate structure. Figures 2A-2C

[0047] ​Finally, local interconnects and / or contacts in combination with back-end-of-the-line (BEOL) lines can be formed to electrically connect NFET 110 and PFET 120 in parallel, and to electrically connect the gates if necessary. That is, first drain region (Dl) of NFET 110 can be electrically connected to second source region (S2) of PFET 120 (e.g., by local interconnects or by contacts in combination with BEOL lines). Also, first source region (Sl) of NFET 110 can be electrically connected to second drain region (D2) of PFET 120 (e.g., by local interconnects or by contacts in combination with BEOL lines). Additional contacts and BEOL lines can be formed to facilitate access to the following nodes: input node 140 at the junction between the first gate (Gl) and the second gate (G2); output node 132 at the junction between first drain region (Dl) of NFET 110 and second source region (S2) of PFET 120; ground node (i.e., connected to ground) at the junction between first source region (Sl) of NFET 110 and second drain region (D2) of PFET 120; NFET programming node 151 at first body (Bl) of NFET 110; and PFET programming node 152 at second body (B2) of PFET 120.

[0048] Referring to the flowchart of Figure 6 Embodiments of a method for reconfiguring (also referred to herein as programming) a reconfigurable complementary metal-oxide-semiconductor (CMOS) device 100 as described in detail above are also disclosed herein. The method can include providing a reconfigurable CMOS device 100 (see process step 602). This reconfigurable CMOS device 100 can be, for example, on an integrated circuit (IC) chip for a wireless communication system or some other IC chip. The method can also include simultaneously programming threshold voltages of NFET 110 and PFET 120 of device 100 to reconfigure device 100, particularly to initially set up or subsequently switch the device to a particular one of a plurality of possible modes of operation (see process step 604).

[0049] More specifically, as described above and as Figure 1 and 2AAs shown in FIG. 2C, the device 100 can include an input node 140 at the junction between the first gate (Gl) and the second gate (G2) of the electrical connection (e.g., on the single gate structure 145, if applicable). The device 100 can also include an NFET programming node 151 at the first body (Bl) of the NFET 110 and a PFET programming node 152 at the second body (B2) of the PFET. At process step 604, the threshold voltages of the NFET 110 and the PFET 120 can be simultaneously programmed by applying a particular set of voltage conditions to the input node 140 (i.e., to the gates (Gl) and (G2) of the NFET 110 and the PFET 120), to the NFET programming node 151 (i.e., to the first body (Bl) of the NFET 110), and to the PFET programming node 152 (i.e., to the second body (B2) of the PFET 120). As a result of the application of the particular set of voltage conditions, the device 100 will be programmed (e.g., reconfigured, set, etc.) to operate in a selected one of a plurality of different operating modes. That is, as a result of the application of the particular set of voltage conditions, the NFET 110 and the PFET 120 will be programmed to collectively have a particular threshold voltage combination of a plurality of possible threshold voltage combinations. Depending on this particular threshold voltage combination in the FETs 110 and 120, the device 100 will operate in a particular one of a plurality of possible operating modes (e.g., a frequency doubling operating mode, a positive signal transmission mode, a signal blocking mode, a negative signal transmission mode, etc.).

[0050] For example, the NFET 110 can be programmable to have a low positive threshold voltage (low positive Vt) or a high positive threshold voltage (high positive Vt). The PFET 120 can be programmable to have a low negative threshold voltage (low negative Vt) or a high negative threshold voltage (high negative Vt). In this case, the device 100 can be reconfigured at process step 604 to have a selected one of four different device states, thereby operating in a selected one of four different operating modes. The four different device states can include: a first state in which the NFET 110 has the low positive threshold voltage and the PFET 120 has the low negative threshold voltage (e.g., for a frequency doubling mode); a second state in which the NFET 110 has the low positive threshold voltage and the PFET 120 has the high negative threshold voltage (e.g., for a positive signal transmission mode); a third state in which the NFET 110 has the high positive threshold voltage and the PFET 120 has the high negative threshold voltage (e.g., for a signal blocking mode); and a fourth state in which the NFET 110 has the high positive threshold voltage and the PFET 120 has the low negative threshold voltage (e.g., for a negative signal transmission mode).

[0051] It should be understood that if the NFET 110 and the PFET 120 have more than two programmable threshold voltages, the device 100 can have more than four different device states, and thus more than four different operating modes. For example, the NFET 110 can also have an ultra-low positive threshold voltage and the PFET 120 can have an ultra-low negative threshold voltage. In this case, additional device states can include a fifth state in which the NFET 110 has the ultra-low positive threshold voltage and the PFET 120 has the ultra-low negative threshold voltage (e.g., for a replacement signaling mode), a sixth state in which the NFET 110 has the ultra-low positive threshold voltage and the PFET 120 has a low negative threshold voltage, and so on.

[0052] Figure 3 is a table showing example set voltage conditions that can be used to reconfigure the device 100, which includes an N-type FeFET 110 and a P-type FeFET 120 that are electrically connected in parallel and have electrically connected gates. Specifically, this table shows example voltage conditions that can be applied to the input node 140 (i.e., the gate (Gl / G2)), the NFET programming node 151 (i.e., the first body (Bl) of the N-type FeFET 110), and the PFET programming node 152 (i.e., the second body (B2) of the P-type FeFET (120)) to achieve the above-described device states and operating modes.

[0053] For example, at process step 604, to reconfigure the device 100 so that it is in the first device state for the frequency doubling mode, the input node 140 can be discharged to ground, a particular negative voltage (e.g., -4V) can be applied to the NFET programming node 151, and a corresponding positive voltage (e.g., +4V) can be applied to the PFET programming node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons into the first channel region (Cl) to ensure that the N-type FeFET 110 has a low positive threshold voltage. In addition, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes into the second channel region (C2) to ensure that the P-type FeFET 120 has a low negative threshold voltage. As shown in FIG. 6B, this first device state doubles the frequency of the parabolic portion of the drain current-gate voltage curve. Figure 4A-1 and 4A-2 As shown in FIG. 6B, this first device state doubles the frequency of the parabolic portion of the drain current-gate voltage curve. This example specifically illustrates how the disclosed method can achieve frequency doubling without requiring a large amount of chip space or power.

[0054] At process step 604, to reconfigure the device 100 to be in a second device state for a positive signal transmission mode, the input node 140 can be discharged to ground, a specific negative voltage (e.g., -4V) can be applied to the NFET program node 151, and the same negative voltage (e.g., -4V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons into the first channel region (Cl) to ensure that the N-type FeFET 110 has a low positive threshold voltage. However, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes out of the second channel region (C2) to ensure that the P-type FeFET 120 has a high negative threshold voltage. As shown in FIG. 6B, this second device state helps to block the negative signal portion and only transmit the positive signal portion. Figure 4B-1 and 4B-2 As shown in FIG. 6B, this second device state helps to block the negative signal portion and only transmit the positive signal portion.

[0055] At process step 604, to reconfigure the device 100 to be in a third device state for a signal blocking mode, the input node 140 can be discharged to ground, a specific positive voltage (e.g., +4V) can be applied to the NFET program node 151, and a corresponding negative voltage (e.g., -4V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons out of the first channel region (Cl) to ensure that the N-type FeFET 110 has a high positive threshold voltage. The direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes out of the second channel region (C2) to ensure that the P-type FeFET 120 has a high negative threshold voltage. As shown in FIG. 6C, this third device state helps to block both the positive and negative signal portions. Figure 4C-1 and 4C-2 As shown in FIG. 6C, this third device state helps to block both the positive and negative signal portions.

[0056] At process step 604, to reconfigure the device 100 to be in a fourth device state for a negative signal transmission mode, the input node 140 can be discharged to ground, a specific positive voltage (e.g., +4V) can be applied to the NFET program node 151, and the same positive voltage (e.g., +4V) can be applied to the PFET program node 152. As a result, the direction of the polarization vector in the ferroelectric layer of the first gate (Gl) will force electrons out of the first channel region (Cl) to ensure that the N-type FeFET 110 has a high positive threshold voltage. However, the direction of the polarization vector in the ferroelectric layer of the second gate (G2) will force holes into the second channel region (C2) to ensure that the P-type FeFET 120 has a low negative threshold voltage. As shown in FIG. 6D, this fourth device state helps to block the positive signal portion and only transmit the negative signal portion. Figure 4D-1 and 4D-2 As shown in FIG. 6D, this fourth device state helps to block the positive signal portion and only transmit the negative signal portion.

[0057] As mentioned above, the N-type FeFET 110 and the P-type FeFET 120 can have more than two possible programmable threshold voltages. For example, the N-type FeFET can also have an ultra-low positive threshold voltage and the P-type FeFET can also have an ultra-low negative threshold voltage. In this case, at process step 604, to reconfigure the device 100 so that it is in a fifth device state (e.g., for an alternative transmission mode), the input node 140 can be discharged to ground, a specific high negative voltage (i.e., a higher negative voltage than the negative voltage used for this first state, e.g., -5V) can be applied to the NFET program node 151, and a corresponding high positive voltage (e.g., +5V) can be applied to the PFET program node 152. Thus, the direction of the polarization vector in the ferroelectric layer of this first gate (Gl) will force electrons into this first channel region (Cl) to ensure that the N-type FeFET 110 has an ultra-low positive threshold voltage. Furthermore, the direction of the polarization vector in the ferroelectric layer of this second gate (G2) will force holes into this second channel region (C2) to ensure that the P-type FeFET 120 has an ultra-low negative threshold voltage. As Figure 4E-1 and 4E-2 This fifth device state supports signal transmission along the linear portion of the drain current-gate voltage curve, as shown. This example illustrates that different portions of the drain current-gate voltage curve can be accessed by different programming / erasing voltages.

[0058] Optionally, the method can also include reprogramming the threshold voltages of the NFET 110 and the PFET 120 simultaneously (e.g., at any time in the field, if necessary) by applying a different set of voltage conditions to achieve a different specific threshold voltage combination in the two FETs 110, 120, and thus switch the device 100 to a different one of the multiple possible operating modes.

[0059] Furthermore, it should be appreciated that in the above-described methods and structures, the semiconductor material is a material whose electrical properties can be changed by doping with impurities. Example semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and Group III-V compound semiconductors (i.e., compounds obtained by combining a Group III element such as aluminum (Al), gallium (Ga), indium (In) with a Group V element such as nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, particularly semiconductor materials that are not doped with impurities to increase electrical conductivity (i.e., undoped semiconductor materials), are referred to in the art as intrinsic semiconductors. Semiconductor materials that are doped with impurities to increase electrical conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors, and will be more electrically conductive than intrinsic semiconductors made of the same base material. That is, an extrinsic silicon will be more electrically conductive than an intrinsic silicon; an extrinsic silicon germanium will be more electrically conductive than an intrinsic silicon germanium, and so on. Moreover, it should be appreciated that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with a Group III dopant such as boron (B) or indium (In) to achieve P-type conductivity, and typically doped with a Group V dopant such as arsenic (As), phosphorous (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity, or with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also appreciate that different levels of conductivity will depend on the relative concentration levels of the dopants in a given semiconductor region.

[0060] The above-described methods are used in the fabrication of integrated circuit chips. The resulting integrated circuits are distributed in raw wafer form (e.g., as single pieces, bulk "real estate" of a single wafer), as bare dies, or in packaged forms. In the latter case the chip is mounted in a single package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier, with or without a bare die in addition to mounting leads). In any case the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer

[0061] It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, unless specifically stated otherwise, as used herein, the singular "a" and "the" include plural referents. Also, as used herein, the term "including" means including but not limited to, the meaning of the term "comprising" is inclusive (meaning that the compositions, methods, acts and / or elements include other unspecified items), but also means merely including, i.e. comprising. Moreover, specific terminology used herein is to be construed as meaning, unless otherwise specifically stated, relative positions when they are oriented and shown in the drawings, and terms such as "touching", "directly touching", "adjacent", "directly adjacent", "immediately adjacent" and the like are intended to mean that at least one element is in physical contact with another element (without other elements interposed between the elements). As used herein, the term "laterally" is intended to mean relative positions of elements when they are oriented and shown in the drawings, and in particular means that one element is to the side of another element rather than above or below the other element. For example, one element laterally adjacent another element will be beside the other element, one element laterally immediately adjacent another element will be directly beside the other element, and one element laterally surrounding another element will be adjacent and encircling the outer sidewall of the other element. All means-plus-function or step-plus-function elements in the claims that follow the

[0062] The description of various embodiments of the application has been made for the purpose of illustration rather than limitation. Many modifications and variations will become apparent to those of ordinary skill in the art, without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the disclosed embodiments, the practical application, or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the disclosed embodiments.

[0063] Thus, embodiments of a reconfigurable complementary metal-oxide-semiconductor (CMOS) device having multiple different modes of operation, including but not limited to frequency doubling mode, are disclosed above. The device can include N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs) that are threshold voltage programmable, connected in parallel, and have electrically connected gates. With this configuration, the threshold voltages of the NFETs and PFETs can be programmed simultaneously, and the mode of operation of the device can be set according to a particular combination of threshold voltages obtained in the NFETs and PFETs during programming. For example, if the NFETs have low positive threshold voltages and the PFETs have low negative threshold voltages, the device can operate in frequency doubling mode. Furthermore, the threshold voltages of the NFETs and PFETs can be reprogrammed simultaneously (e.g., in the field) as needed to switch the mode of operation of the device. Such a device can be small (i.e., can consume minimal chip area) and can achieve frequency doubling and other functions with minimal power consumption. Embodiments of methods for forming the device and embodiments of methods for reconfiguring the device (i.e., for simultaneously programming the NFETs and PFETs to set or switch the mode of operation) are also disclosed above.

Claims

1. A reconfigurable complementary metal-oxide-semiconductor device, comprising: an N-type field-effect transistor; and a P-type field-effect transistor, wherein the N-type field-effect transistor and the P-type field-effect transistor comprise threshold-voltage programmable field-effect transistors, wherein a first drain region and a first source region of the N-type field-effect transistor are electrically connected to a second source region and a second drain region of the P-type field-effect transistor, respectively, between an output node and a ground node, such that the N-type field-effect transistor and the P-type field-effect transistor are electrically connected in parallel between the output node and the ground node, and the N-type field-effect transistor and the P-type field-effect transistor have electrically connected gates, and wherein the output node is located at a junction between the first drain region and the second source region, the ground node is located at a junction between the first source region and the second drain region, and the electrically connected gates are electrically connected to an input node.

2. The reconfigurable complementary metal-oxide-semiconductor device of claim 1, wherein the N-type field-effect transistor comprising: a first body; a first channel region laterally located between the first source region and the first drain region within the first body; and a first gate located on the first channel region, wherein the P-type field-effect transistor comprises: a second body; a second channel region laterally located between the second source region and the second drain region within the second body; and a second gate located on the second channel region, and wherein the device further comprises: the input node located at a junction between the first gate and the second gate, a first programming node located at the first body, and a second programming node located at the second body.

3. The reconfigurable complementary metal-oxide-semiconductor device of claim 1, wherein the N-type field-effect transistor having a plurality of different programmable positive threshold voltages, wherein the P-type field-effect transistor has a plurality of different programmable negative threshold voltages, and wherein the device has a plurality of different operating modes varying with the plurality of different programmable positive threshold voltages of the N-type field-effect transistor and the plurality of different programmable negative threshold voltages of the P-type field-effect transistor.

4. The reconfigurable complementary metal oxide semiconductor device of claim 3, wherein, The device exhibits a particular one of a plurality of different drain current-gate voltage curves when the device is operated in a particular one of the plurality of different operating modes.

5. The reconfigurable complementary metal-oxide-semiconductor device of claim 1, wherein, the N-type field-effect transistor having a plurality of different programmable positive threshold voltages comprising at least a low positive threshold voltage and a high positive threshold voltage, wherein the P-type field-effect transistor has a plurality of different programmable negative threshold voltages comprising at least a low negative threshold voltage and a high negative threshold voltage, and wherein the device has at least four different device states, comprising: a first state in which the N-type field-effect transistor has the low positive threshold voltage and the P-type field-effect transistor has the low negative threshold voltage; a second state in which the N-type field effect transistor has the low positive threshold voltage and the P-type field effect transistor has the high negative threshold voltage; a third state in which the N-type field effect transistor has the high positive threshold voltage and the P-type field effect transistor has the high negative threshold voltage; and a fourth state in which the N-type field effect transistor has the high positive threshold voltage and the P-type field effect transistor has the low negative threshold voltage.

6. The reconfigurable complementary metal-oxide-semiconductor device of claim 5, wherein, the plurality of different programmable positive threshold voltages of the N-type field effect transistor further comprises an ultra-low positive threshold voltage, wherein the plurality of different programmable negative threshold voltages of the P-type field effect transistor further comprises an ultra-low negative threshold voltage, and wherein the device states further comprise a fifth state in which the N-type field effect transistor has the ultra-low positive threshold voltage and the P-type field effect transistor has the ultra-low negative threshold voltage.

7. The reconfigurable complementary metal oxide semiconductor device as defined by claim 1 wherein, The threshold voltage programmable field effect transistor comprises any one of a ferroelectric field effect transistor, a charge-trapping field effect transistor, and a floating gate field effect transistor.

8. The reconfigurable complementary metal oxide semiconductor device as defined by claim 1 wherein, The gate comprises different portions of a single gate structure.

9. A method of forming a reconfigurable complementary metal-oxide-semiconductor device, comprising: providing a substrate; and forming a device on the substrate, wherein the forming of the device comprises forming an N-type field effect transistor and a P-type field effect transistor, wherein the N-type field effect transistor and the P-type field effect transistor comprise threshold voltage programmable field effect transistors, wherein a first drain region and a first source region of the N-type field effect transistor are electrically connected to a second source region and a second drain region of the P-type field effect transistor, respectively, between an output node and a ground node, such that the N-type field effect transistor and the P-type field effect transistor are electrically connected in parallel between the output node and the ground node, and the N-type field effect transistor and the P-type field effect transistor have an electrically connected gate, and wherein the output node is at a junction between the first drain region and the second source region, the ground node is at a junction between the first source region and the second drain region, and the electrically connected gate is electrically connected to an input node.

10. The method of claim 9, wherein the N-type field effect transistor is formed to comprise a first body, a first channel region laterally between the first source region and the first drain region in the first body, and a first gate on the first channel region, wherein the P-type field effect transistor is formed to comprise a second body, a second channel region laterally between a second source region and a second drain region in the second body, and a second gate on the second channel region, and wherein the method further comprises forming a contact to the output node, a contact to the ground node, a contact to the input node at a junction between the first gate and the second gate, a contact to a first programming node at the first body, and a contact to a second programming node at the second body.

11. The method of claim 9, wherein, The threshold voltage programmable field effect transistor includes any one of a ferroelectric field effect transistor, a charge trapping field effect transistor, and a floating gate field effect transistor.

12. The method of claim 9, wherein, The forming of the N-type field effect transistor and the P-type field effect transistor includes forming a single gate structure over a first channel region of the N-type field effect transistor and over a second channel region of the P-type field effect transistor, such that the gate includes different portions of the single gate structure.

13. A method of reconfiguring a reconfigurable complementary metal-oxide-semiconductor device, comprising: providing a device including an N-type field effect transistor and a P-type field effect transistor, wherein the N-type field effect transistor and the P-type field effect transistor include threshold voltage programmable field effect transistors, wherein a first drain region and a first source region of the N-type field effect transistor are electrically connected to a second source region and a second drain region of the P-type field effect transistor, respectively, between an output node and a ground node, such that the N-type field effect transistor and the P-type field effect transistor are electrically connected in parallel between the output node and the ground node, and the N-type field effect transistor and the P-type field effect transistor have an electrically connected gate, and wherein the output node is at a junction between the first drain region and the second source region, the ground node is at a junction between the first source region and the second drain region, and the electrically connected gate is electrically connected to an input node; and simultaneously programming threshold voltages of the N-type field effect transistor and the P-type field effect transistor.

14. The method of claim 13, wherein the N-type field effect transistor includes a first body, a first channel region laterally between the first source region and the first drain region in the first body, and a first gate on the first channel region, wherein the P-type field effect transistor includes a second body, a second channel region laterally between a second source region and a second drain region in the second body, and a second gate on the second channel region, wherein the device further includes the input node at a junction between the first gate and the second gate, a first programming node at the first body, and a second programming node at the second body, and wherein the simultaneous programming of the threshold voltages of the N-type field effect transistor and the P-type field effect transistor includes simultaneously applying a set of voltage conditions to the device through the input node, the first programming node, and the second programming node.

15. The method of claim 14, wherein the N-type field effect transistor has a plurality of different programmable positive threshold voltages, wherein the P-type field effect transistor has a plurality of different programmable negative threshold voltages, and wherein the set of voltage conditions are applied to the device to achieve a particular combination of one of the plurality of different programmable positive threshold voltages of the N-type field effect transistor and one of the plurality of different programmable negative threshold voltages of the P-type field effect transistor to place the device in a particular one of a plurality of different operating modes.

16. The method of claim 15, wherein, When the device is operated in a particular one of the plurality of different operating modes, the device exhibits a particular one of a plurality of different drain current-gate voltage curves.

17. The method of claim 14, wherein, The N-type field effect transistor has a plurality of different programmable positive threshold voltages, including at least a low positive threshold voltage and a high positive threshold voltage, wherein the P-type field effect transistor has a plurality of different programmable negative threshold voltages, including at least a low negative threshold voltage and a high negative threshold voltage, and wherein the simultaneous programming of the threshold voltages of the N-type field effect transistor and the P-type field effect transistor is performed to achieve a particular one of at least four device states, including: a first state for a frequency doubling mode, wherein in the first state the N-type field effect transistor has the low positive threshold voltage and the P-type field effect transistor has the low negative threshold voltage; a second state for a positive signal transmission mode, wherein in the second state the N-type field effect transistor has the low positive threshold voltage and the P-type field effect transistor has the high negative threshold voltage; a third state for a signal blocking mode, wherein in the third state the N-type field effect transistor has the high positive threshold voltage and the P-type field effect transistor has the high negative threshold voltage; and a fourth state for a negative signal transmission mode, wherein in the fourth state the N-type field effect transistor has the high positive threshold voltage and the P-type field effect transistor has the low negative threshold voltage.

18. The method of claim 17, wherein, The N-type field effect transistor comprises an N-type ferroelectric field effect transistor and the P-type field effect transistor comprises a P-type ferroelectric field effect transistor, wherein the first state is achieved by applying a first set of voltage conditions, including: 0 volts on the input node, a negative programming voltage on the first programming node of the N-type ferroelectric field effect transistor, and a positive programming voltage on the second programming node of the P-type ferroelectric field effect transistor, wherein the second state is achieved by applying a second set of voltage conditions, including: 0 volts on the input node, the negative programming voltage on the first programming node of the N-type ferroelectric field effect transistor, and the positive programming voltage on the second programming node of the P-type ferroelectric field effect transistor, wherein the third state is achieved by applying a third set of voltage conditions, including: 0 volts on the input node, the positive programming voltage on the first programming node of the N-type ferroelectric field effect transistor, and the negative programming voltage on the second programming node of the P-type ferroelectric field effect transistor, and wherein the fourth state is achieved by applying a fourth set of voltage conditions, including: 0 volts on the input node, the positive programming voltage on the first programming node of the N-type ferroelectric field effect transistor, and the positive programming voltage on the second programming node of the P-type ferroelectric field effect transistor.

19. The method of claim 18, wherein the plurality of different programmable positive threshold voltages further comprises an ultra-low positive threshold voltage, wherein the plurality of different programmable negative threshold voltages further comprises an ultra-low negative threshold voltage, wherein the device states further comprises a fifth state, and in the fifth state, the N-type ferroelectric field effect transistor has the ultra-low positive threshold voltage and the P-type ferroelectric field effect transistor has the ultra-low negative threshold voltage, and wherein the fifth state is reached by applying a fifth set of voltage conditions, the fifth set of voltage conditions comprising: 0 volts on the input node, an extra negative programming voltage on the first programming node of the N-type ferroelectric field effect transistor, and an extra positive programming voltage on the second programming node of the P-type ferroelectric field effect transistor, and wherein the extra negative programming voltage has a higher absolute value compared to the negative programming voltage used for the first state, and the extra positive programming voltage has a high absolute value compared to the positive programming voltage used for the first state.

20. The method of claim 13, wherein, the threshold voltage programmable field effect transistor comprises any one of a ferroelectric field effect transistor, a charge-trapping field effect transistor, and a floating gate field effect transistor.

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