Array substrate and display panel

Abstract

The application provides an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a compensation transistor, a driving transistor, a reference signal line, a first power signal line and a first connecting part. The compensation transistor is connected between the gate and the second electrode of the driving transistor, and the active part of the compensation transistor comprises a conductor part. The first connecting part is electrically connected with the reference signal line. The orthographic projection of the first connecting part on the substrate and the orthographic projection of the conductor part on the substrate have an overlapping area, and the orthographic projection of the first connecting part on the substrate and the orthographic projection of the first power signal line on the substrate do not have an overlapping area. In this way, the leakage phenomenon of the compensation transistor is improved, the parasitic capacitance is reduced, and the transmittance of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display panel gradually becomes the development trend of the industry due to its self-luminous, high response speed, high contrast, flexible and other characteristics.

[0003] The array substrate in the display panel includes a pixel driving circuit, and the pixel driving circuit includes a driving transistor and a compensation transistor connected with the gate of the driving transistor. The leakage problem of the compensation transistor will cause the change of the gate voltage of the driving transistor, so that the output current provided by the driving transistor to the light-emitting device changes, thereby causing the display panel to have quality problems such as flicker or crosstalk.

[0004] Therefore, the display panel can be improved to have quality problems such as flicker or crosstalk by improving the leakage phenomenon of the compensation transistor. However, the current way to improve the leakage phenomenon of the compensation transistor will cause the problems of increased parasitic capacitance and reduced transmittance. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide an array substrate and a display panel to improve the leakage phenomenon of the compensation transistor while reducing the parasitic capacitance and improving the transmittance.

[0006] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the embodiments of the present application provides an array substrate, comprising: a substrate and a plurality of pixel driving circuits arranged on the substrate, each pixel driving circuit comprising a compensation transistor, a driving transistor, a reference signal line, a first power signal line and a first connecting part; the first pole of the compensation transistor is electrically connected with the second pole of the driving transistor, and the second pole of the compensation transistor is electrically connected with the gate of the driving transistor; the active part of the compensation transistor comprises a conductor part; the first connecting part is electrically connected with the reference signal line, and the orthographic projection of the first connecting part on the substrate and the orthographic projection of the conductor part on the substrate have an overlapping area, and the orthographic projection of the first connecting part on the substrate and the orthographic projection of the first power signal line on the substrate do not have an overlapping area.

[0008] In this way, by adding the first connecting part in each pixel driving circuit, electrically connecting the first connecting part with the reference signal line, and overlapping the conductor part in the active part of the compensation transistor with the first connecting part to form a coupling capacitor, the potential stability of the conductor part in the active part of the compensation transistor can be improved, thereby improving the leakage phenomenon of the compensation transistor; and since the added first connecting part does not overlap the first power signal line, that is, the first connecting part is spaced apart from the first power signal line, the area of the added first connecting part in the second conductive layer can be small, thereby reducing the parasitic capacitance and improving the transmittance of the display panel.

[0009] In an implementable embodiment, the active part of the compensation transistor further includes a first channel region and a second channel region, and the conductor part is located between the first channel region and the second channel region; the conductor part includes a first conductor part and a second conductor part connected to each other; the first conductor part extends along a first direction, and the second conductor part extends along a second direction, the first direction intersecting the second direction; the orthogonal projection of the first connecting part on the substrate overlaps the orthogonal projection of the first conductor part and / or the second conductor part on the substrate. In this way, when the first connecting part overlaps both the first conductor part and the second conductor part, the coupling capacitor formed between the first connecting part and the conductor part has a larger capacitance value, thereby making the potential of the conductor part more stable; and when the first connecting part overlaps the first conductor part or the second conductor part, the coupling capacitor formed between the first connecting part and the conductor part has a smaller capacitance value, thereby reducing the parasitic capacitance of the reference signal line.

[0010] In an implementable embodiment, each pixel driving circuit further includes a second connecting part, one end of the second connecting part being electrically connected with the reference signal line, and the other end of the second connecting part being electrically connected with the first connecting part. In this way, based on the original second connecting part in the array substrate, the first connecting part is electrically connected with the reference signal line, and the area of the added first connecting part can be small, thereby reducing the parasitic capacitance of the reference signal line.

[0011] In an implementable embodiment, the reference signal line is arranged in a layer different from the first power signal line, the first connecting part is arranged in the same layer as the reference signal line, and the second connecting part is arranged in the same layer as the first power signal line. In this way, by arranging the first connecting part in the same layer as the reference signal line, the total number of layers of the array substrate can be reduced, thereby reducing the total thickness of the array substrate; and the spacing distance between the first connecting part and the conductor part of the compensation transistor can be reduced, thereby improving the coupling capacitor formed between the first connecting part and the conductor part of the compensation transistor, so as to better improve the leakage phenomenon of the compensation transistor.

[0012] In an implementation, the first connection portion and the second connection portion are arranged in the same layer, and the first connection portion is also arranged in the same layer as the first power signal line. In this way, by arranging the added first connection portion and the second connection portion in the same layer, the total number of layers of the array substrate can be reduced, thereby reducing the total thickness of the array substrate. When the first connection portion and the second connection portion are arranged in the same layer, the first connection portion and the second connection portion do not need to be electrically connected through a via hole of the interlayer dielectric layer, thereby reducing the process complexity in manufacturing the via hole.

[0013] In an implementation, the pixel driving circuit further includes a first scan signal line and a first reset transistor. The gate of the first reset transistor is controlled by the first scan signal line, the first electrode of the first reset transistor is electrically connected to the reference signal line through the second connection portion, and the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor. The second connection portion is arranged to cross the first scan signal line on the substrate. In the second direction, the first connection portion and the reference signal line are respectively located on two sides of the first scan signal line. In this way, because the added first connection portion is located on the side of the first scan signal line away from the reference signal line, the extension length of the first connection portion is small, thereby reducing the area of the first connection portion, reducing the parasitic capacitance, and improving the transmittance of the display panel.

[0014] In an implementation, each pixel driving circuit further includes a second scan signal line, an emission control signal line, and a data line. The reference signal line, the first scan signal line, the second scan signal line, and the emission control signal line extend along the first direction, the first power signal line and the data line extend along the second direction, and the first direction intersects the second direction. The first scan signal line is located between the reference signal line and the second scan signal line, and the second scan signal line is located between the first scan signal line and the emission control signal line.

[0015] In an implementable embodiment, the gate of the compensation transistor is controlled by the second scan signal line, and the gate of the compensation transistor is a part of the second scan signal line which overlaps with the channel region of the compensation transistor; each pixel driving circuit further comprises a data writing transistor, a second reset transistor, a first light emitting control transistor, a second light emitting control transistor and a storage capacitor; the gate of the data writing transistor is controlled by the second scan signal line, the first electrode of the data writing transistor is electrically connected with the data line, and the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor; the gate of the second reset transistor is controlled by the first scan signal line, the first electrode of the second reset transistor is electrically connected with the reference signal line through the second connection part, and the second electrode of the second reset transistor is electrically connected with the first electrode of the light emitting device; the gate of the first light emitting control transistor is controlled by the light emitting control signal line, the first electrode of the first light emitting control transistor is electrically connected with the first power signal line, and the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor; the gate of the second light emitting control transistor is controlled by the light emitting control signal line, the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; the first plate of the storage capacitor is electrically connected with the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected with the first power signal line. In this way, the second scan signal line is directly used as the gate of the compensation transistor, so that the circuit arrangement of the pixel driving circuit is simpler; and based on the connection relationship of the data writing transistor, the second reset transistor, the first light emitting control transistor, the second light emitting control transistor and the storage capacitor in the pixel driving circuit, the pixel driving circuit can drive the light emitting device to emit light normally.

[0016] In an implementable embodiment, the active part of the compensation transistor is located in the active layer; the first scan signal line, the second scan signal line, the light emitting control signal line and the first plate of the storage capacitor are located in the first conductive layer; the reference signal line and the second plate of the storage capacitor are located in the second conductive layer; the first power signal line and the data line are located in the third conductive layer; the first gate insulating layer is arranged between the first conductive layer and the active layer, the second gate insulating layer is arranged between the second conductive layer and the first conductive layer, the interlayer dielectric layer is arranged between the third conductive layer and the second conductive layer, and the third conductive layer is located on the side of the interlayer dielectric layer away from the substrate.

[0017] The second aspect of the embodiments of the present application provides a display panel comprising the array substrate.

[0018] The possible implementation manners of the second aspect have effects similar to those of the first aspect and the possible designs of the first aspect, which will not be described herein again.

[0019] The construction of the present application and other objects and advantages thereof will become more apparent from the following description considered in connection with the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required by the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0021] Figure 1 A circuit diagram of a pixel driving circuit provided by the present application;

[0022] Figure 2 A timing diagram corresponding to the pixel driving circuit shown in Figure 1

[0023] A structural diagram of an array substrate in the related art; Figure 3

[0024] A structural diagram of an array substrate provided by the present application; Figure 4

[0025] A structural diagram of an active layer in the array substrate of the present application; Figure 5

[0026] A structural diagram of an active layer and a first conductive layer in the array substrate of the present application; Figure 6

[0027] A structural diagram of an active layer, a first conductive layer and a second conductive layer in the array substrate of the present application; Figure 7

[0028] A structural diagram of an active layer, a first conductive layer and a second conductive layer and various through holes in the array substrate of the present application; Figure 8

[0029] A structural diagram of another array substrate provided by the present application; Figure 9

[0030] A structural diagram of still another array substrate provided by the present application. Figure 10 DETAILED DESCRIPTION

[0031] ​An array substrate is arranged in an OLED display panel, the array substrate comprises a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel comprises a pixel driving circuit and a light emitting device electrically connected with the pixel driving circuit. Figure 1 As shown in the figure, the pixel driving circuit can comprise a driving transistor M1, a data writing transistor M2, a compensation transistor M3, a first reset transistor M4, a first light emitting control transistor M5, a second light emitting control transistor M6, a second reset transistor M7 and a storage capacitor C1; in addition, the pixel driving circuit further comprises a reference signal line REF, a first power signal line VDD, a first scan signal line Scan1, a second scan signal line Scan2, a light emitting control signal line EM and a data line Data.

[0032] The gate of the data writing transistor M2 is controlled by the second scan signal line Scan2, the first pole of the data writing transistor M2 is electrically connected with the data line Data, and the second pole of the data writing transistor M2 is electrically connected with the first pole of the driving transistor M1.

[0033] The gate of the compensation transistor M3 is controlled by the second scan signal line Scan2, the first pole of the compensation transistor M3 is electrically connected with the second pole of the driving transistor M1, and the second pole of the compensation transistor M3 is electrically connected with the gate of the driving transistor M1 and the first plate of the storage capacitor C1.

[0034] The gate of the first reset transistor M4 is controlled by the first scan signal line Scan1, the first pole of the first reset transistor M4 is electrically connected with the reference signal line REF, and the second pole of the first reset transistor M4 is electrically connected with the gate of the driving transistor M1.

[0035] The gate of the second reset transistor M7 is controlled by the first scan signal line Scan1, the first pole of the second reset transistor M7 is electrically connected with the reference signal line REF, and the second pole of the second reset transistor M7 is electrically connected with the first pole of the light emitting device EL.

[0036] The gate of the first light emitting control transistor M5 is controlled by the light emitting control signal line EM, the first pole of the first light emitting control transistor M5 is electrically connected with the first power signal line VDD, and the second pole of the first light emitting control transistor M5 is electrically connected with the first pole of the driving transistor M1.

[0037] The gate of the second light emitting control transistor M6 is controlled by the light emitting control signal line EM, the first pole of the second light emitting control transistor M6 is electrically connected with the second pole of the driving transistor M1, and the second pole of the second light emitting control transistor M6 is electrically connected with the first pole of the light emitting device EL.

[0038] The first plate of the storage capacitor C1 is electrically connected to the gate of the driving transistor M1, and the second plate of the storage capacitor C1 is electrically connected to the first power signal line VDD; the second plate of the light-emitting device EL is electrically connected to the second power signal line VSS. The voltage transmitted on the first power signal line VDD can be higher than the voltage transmitted on the second power signal line VSS.

[0039] In some embodiments, the driving transistor M1, the data writing transistor M2, the compensation transistor M3, the first reset transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6, and the second reset transistor M7 are all P-type transistors. In this case, Figure 1 The pixel driving circuit shown can be adopted Figure 2 The timing diagram shown is used for driving.

[0040] like Figure 2 As shown, during the reset phase t11, the first scan signal input to the first scan signal line Scan1 is at a low level, causing the first reset transistor M4 and the second reset transistor M7 to be turned on. Then, the reference signal input to the reference signal line REF is transmitted to the gate of the driving transistor M1 through the first reset transistor M4, resetting the gate of the driving transistor M1. In addition, the reference signal input to the reference signal line REF is also transmitted to the first electrode of the light-emitting device EL through the second reset transistor M7, resetting the first electrode of the light-emitting device EL.

[0041] In addition, during the reset phase t11, the second scan signal input to the second scan signal line Scan2 is at a high level, causing both the data writing transistor M2 and the compensation transistor M3 to be in the off state; the light emission control signal input to the light emission control signal line EM is also at a high level, causing both the first light emission control transistor M5 and the second light emission control transistor M6 to be in the off state.

[0042] During the data writing phase t12, the second scan signal input to the second scan signal line Scan2 is at a low level, causing both the data writing transistor M2 and the compensation transistor M3 to be turned on. The data signal input to the data line Data is then transmitted through the data writing transistor M2 to the first terminal of the driving transistor M1, and subsequently written to the gate of the driving transistor M1 through the driving transistor M1 and the compensation transistor M3. As the data signal is written, the gate voltage of the driving transistor M1 gradually increases until it reaches Vdata + Vth. Vdata refers to the data voltage of the data signal, and Vth refers to the threshold voltage of the driving transistor M1.

[0043] In addition, in the data writing stage t12, the first scan signal inputted by the first scan signal line Scanl is high, so that the first reset transistor M4 and the second reset transistor M7 are both in the off state; the light emitting control signal inputted by the light emitting control signal line EM is also high, so that the first light emitting control transistor M5 and the second light emitting control transistor M6 are both in the off state.

[0044] In the light emitting control stage t13, the light emitting control signal inputted by the light emitting control signal line EM is low, so that the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on, and then the driving current is provided to the first electrode of the light emitting device EL through the first light emitting control transistor M5, the driving transistor Ml and the second light emitting control transistor M6. The driving current I of the light emitting device EL = K(VgS-Vth) 2 = K(Vdata+Vth-Vdd-Vtt) 2 = K(Vdata-Vdd) 2 .

[0045] Wherein, K is a parameter related to the process and design, once the size of the driving transistor Ml and the process are determined, the parameter K can be determined, Vgs is the voltage difference between the gate and the source of the driving transistor Ml, and Vdd is the power voltage provided by the first power signal line VDD.

[0046] It can be seen that the size of the driving current inputted to the light emitting device EL is related to the power voltage Vdd provided by the first power signal line VDD and the data voltage Vdata of the data signal, and is irrelevant to the threshold voltage of the driving transistor Ml. Therefore, the threshold voltage of the driving transistor Ml can be compensated by setting the compensation transistor M3, so as to prevent the threshold voltage drift of the driving transistor Ml from causing the driving current inputted to the light emitting device EL to be unstable.

[0047] In addition, in the light emitting control stage t13, the first scan signal inputted by the first scan signal line Scanl is high, so that the first reset transistor M4 and the second reset transistor M7 are both in the off state; the second scan signal inputted by the second scan signal line Scan2 is high, so that the data writing transistor M2 and the compensation transistor M3 are both in the off state.

[0048] It should be noted that the above driving process is illustrated using an example where the driving transistor M1, data writing transistor M2, compensation transistor M3, first reset transistor M4, first light-emitting control transistor M5, second light-emitting control transistor M6, and second reset transistor M7 are all P-type transistors, which conduct when the gate is low and are cut off when the gate is high. Of course, in the embodiments of this application, the driving transistor M1, data writing transistor M2, compensation transistor M3, first reset transistor M4, first light-emitting control transistor M5, second light-emitting control transistor M6, and second reset transistor M7 can also be N-type transistors, which conduct when the gate is high and are cut off when the gate is low. Furthermore, to distinguish the two terminals of the transistor other than the gate, the source is referred to as the first terminal, and the drain as the second terminal.

[0049] During the use of the display panel, the compensation transistor M3 may experience leakage. When the compensation transistor M3 experiences leakage, the gate voltage of the driving transistor M1 will change, causing the output current supplied by the driving transistor M1 to the light-emitting device to change, which may lead to image quality problems such as flickering or crosstalk in the display panel.

[0050] To improve image quality issues such as flickering or crosstalk on the display panel caused by leakage current in the compensation transistor M3, in related technologies, such as Figure 3 As shown, a conductive structure 11 can be added to the second conductive layer in the display panel. The conductive structure 11 is electrically connected to the first power signal line VDD through a via penetrating the interlayer dielectric layer. The conductive structure 11 overlaps with the conductor portion in the active part of the compensation transistor M3 to form a coupling capacitor. The presence of this coupling capacitor can make the potential of the conductor portion in the active part of the compensation transistor M3 more stable, thereby improving the leakage phenomenon of the compensation transistor M3.

[0051] However, due to the large distance between the conductor portion of the compensation transistor M3 and the first power signal line VDD in the pixel driving circuit layout, the area of ​​the added conductive structure 11 in the second conductive layer is also large. When the area of ​​the conductive structure 11 is large, the parasitic capacitance of the first power signal line VDD increases, resulting in increased power consumption of the display panel; furthermore, a large area of ​​the conductive structure 11 also leads to a decrease in the transmittance of the display panel.

[0052] To solve the above technical problems, the embodiment of the present application provides an array substrate and a display panel. A first connecting part is added in each pixel driving circuit, the first connecting part is electrically connected with a reference signal line, and the first connecting part overlaps with a conductor part in an active part of a compensation transistor to form a coupling capacitor. The potential stability of the conductor part in the active part of the compensation transistor can be improved, so that the leakage phenomenon of the compensation transistor is improved. In addition, the first connecting part added in the second conductive layer has a small area because the first connecting part and the first power signal line do not overlap, that is, the first connecting part and the first power signal line have a certain interval distance, so that the parasitic capacitance is reduced and the transmittance of the display panel is improved.

[0053] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the drawings in the preferred embodiments of the present application. In the drawings, the same or similar notations represent the same or similar components or components with the same or similar functions throughout. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0054] Reference is made to Figure 4 Fig. 1, which shows a structural schematic diagram of an array substrate according to an embodiment of the present application. The array substrate includes a substrate 10 and a plurality of pixel driving circuits arranged on the substrate 10. Each pixel driving circuit includes a compensation transistor M3, a driving transistor M1 (not shown in Fig. 1), a reference signal line REF, a first power signal line VDD and a first connecting part 41. The first electrode of the compensation transistor M3 is electrically connected with the second electrode of the driving transistor M1, and the second electrode of the compensation transistor M3 is electrically connected with the gate electrode of the driving transistor M1. Figure 4

[0055] Figure 5 Fig. 2 shows a structural schematic diagram of an active layer in the array substrate according to an embodiment of the present application. As shown in Fig. 2, the active part 21 of the compensation transistor M3 includes a first channel region 211, a second channel region 212 and a conductor part 213 between the first channel region 211 and the second channel region 212. Figure 5

[0056] In the array substrate according to the embodiment of the present application, the first connecting part 41 is electrically connected with the reference signal line REF, the orthogonal projection of the first connecting part 41 on the substrate 10 overlaps with the orthogonal projection of the conductor part 213 on the substrate 10, and the orthogonal projection of the first connecting part 41 on the substrate 10 does not overlap with the orthogonal projection of the first power signal line VDD on the substrate 10.​​

[0057] In actual products, substrate 10 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a polyimide (PI) substrate. Multiple pixel driving circuits are distributed on substrate 10, and these pixel driving circuits are arranged in an array.

[0058] The driving transistor M1 is a transistor used to drive the light-emitting device to emit light, and the compensation transistor M3 is a transistor used to compensate the threshold voltage of the driving transistor M1. The compensation transistor M3 is connected between the gate and the second electrode of the driving transistor M1.

[0059] In some embodiments, the compensation transistor M3 is a dual-gate transistor, meaning it employs a dual-gate structure comprising two channel regions and a gate corresponding to each channel region, with the two gates interconnected. When the compensation transistor M3 is a dual-gate transistor, the leakage current of the compensation transistor M3 can be reduced, thereby improving the stability of the gate voltage of the driving transistor M1.

[0060] The reference signal line REF refers to the signal line used during the reset phase t11 to input a reference signal to the first reset transistor M4, so as to reset the gate of the driving transistor M1 through the first reset transistor M4, and to input a reference signal to the second reset transistor M7, so as to reset the first terminal of the light-emitting device EL through the second reset transistor M7. The first power supply signal line VDD refers to the signal line used to provide the power supply voltage Vdd, which is used during the light-emitting control phase t13 to input the power supply voltage Vdd to the first light-emitting control transistor M5.

[0061] Among them, such as Figure 5 As shown, the active portion 21 of the compensation transistor M3 includes a first channel region 211, a second channel region 212, and a conductor portion 213 located between the first channel region 211 and the second channel region 212, and the first channel region 211, the conductor portion 213, and the second channel region 212 are connected in sequence.

[0062] The first connecting portion 41 is electrically connected to the reference signal line REF. The orthographic projection of the first connecting portion 41 on the substrate 10 overlaps with the orthographic projection of the conductor portion 213 on the substrate 10, meaning the first connecting portion 41 and the conductor portion 213 overlap, thus forming a coupling capacitor. Since the first connecting portion 41 is electrically connected to the reference signal line REF, and the reference signal provided by REF is a constant signal, the potential of the conductor portion 213 can be made more stable due to the coupling capacitor. This improves the leakage current phenomenon of the compensation transistor M3, making the output current provided by the driving transistor M1 to the light-emitting device more stable, thereby improving image quality problems such as flickering or crosstalk in the display panel.

[0063] And, since the first connecting part 41 is not electrically connected with the first power signal line VDD, the parasitic capacitance of the first power signal line VDD will not increase due to the first connecting part 41. Although the first connecting part 41 is electrically connected with the reference signal line REF, it will increase the parasitic capacitance of the reference signal line REF to some extent, but since the orthogonal projection of the first connecting part 41 on the substrate 10 does not overlap with the orthogonal projection of the first power signal line VDD on the substrate 10, i.e. the first connecting part 41 is spaced apart from the first power signal line VDD by a certain distance, and Figure 3 the conductive structure 11 in the first connecting part 41 will extend to the position of the first power signal line VDD and overlap with the first power signal line VDD, therefore, it can be known that the extension length of the first connecting part 41 will be smaller than the extension length of the conductive structure 11. Generally, the width of the traces in the array substrate does not differ much, when the extension length of the first connecting part 41 is smaller than the extension length of the conductive structure 11, the area of the first connecting part 41 (i.e. the occupied area of the orthogonal projection of the first connecting part 41 on the substrate 10) can be smaller than the area of the conductive structure 11 (i.e. the occupied area of the orthogonal projection of the conductive structure 11 on the substrate 10).

[0064] When the area of the first connecting part 41 is small, the lateral parasitic capacitance between the first connecting part 41 and other metal lines is small, and therefore the parasitic capacitance of the reference signal line REF increases is small, thus the parasitic capacitance of the array substrate can be reduced, so that the power consumption of the display panel can be reduced. And when the area of the first connecting part 41 is small, the shielding area of the first connecting part 41 to light is also small, so that the transmittance of the display panel can be improved.

[0065] In some embodiments, the conductor part 213 includes a first conductor part and a second conductor part connected with each other; the first conductor part extends along a first direction X, and the second conductor part extends along a second direction Y, the first direction X intersects with the second direction Y.

[0066] Specifically, the first conductor part is connected with the first channel region 211, and the extension direction of the first channel region 211 is the same as the extension direction of the first conductor part; the second conductor part is connected with the second channel region 212, and the extension direction of the second channel region 212 is the same as the extension direction of the second conductor part.

[0067] In some optional embodiments, the reference signal line REF can extend along the first direction X. The first power signal line VDD can extend along the second direction Y. The first direction X can be perpendicular to the second direction Y. The first direction X can be the row direction of the array substrate, and the second direction Y can be the column direction of the array substrate. At this time, the active part 21 of the compensation transistor M3 is in an inverted “L” distribution.

[0068] It should be noted that the perpendicularity of the first direction X and the second direction Y can be understood as perpendicularity within the allowable range of process error. For example, when the angle between the first direction X and the second direction Y is within a preset angle range, it is considered to be perpendicular, such as 85° to 95°.

[0069] Of course, in other embodiments, the first direction X and the second direction Y may not be perpendicular. In this case, the angle between the first direction X and the second direction Y may be greater than a first preset angle or less than a second preset angle. For example, the first preset angle is 95°, and the second preset angle may be 85°.

[0070] exist Figure 4 In the array substrate shown, the orthographic projection of the first connection portion 41 on the substrate 10 overlaps with the orthographic projections of the first conductor portion and the second conductor portion on the substrate 10; that is, the first connection portion 41 overlaps with both the first conductor portion and the second conductor portion. In this case, the area of ​​the overlapping region between the first connection portion 41 and the conductor portion 213 is larger, resulting in a larger capacitance value of the coupling capacitor formed between the first connection portion 41 and the conductor portion 213, thereby making the potential of the conductor portion 213 more stable.

[0071] Of course, in some embodiments, the orthographic projection of the first connection portion 41 on the substrate 10 may overlap with the orthographic projection of the first conductor portion on the substrate 10, and the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the second conductor portion on the substrate 10 may not overlap. In this case, the area of ​​the overlapping region between the first connection portion 41 and the conductor portion 213 is smaller, which results in a smaller capacitance value of the coupling capacitor formed between the first connection portion 41 and the conductor portion 213, thereby reducing the parasitic capacitance of the reference signal line REF.

[0072] In other embodiments, the orthographic projection of the first connection portion 41 on the substrate 10 may overlap with the orthographic projection of the second conductor portion on the substrate 10, and there may be no overlap between the orthographic projection of the first connection portion 41 on the substrate 10 and the orthographic projection of the first conductor portion on the substrate 10. In this case, the area of ​​the overlap region between the first connection portion 41 and the conductor portion 213 is smaller, resulting in a smaller capacitance value of the coupling capacitor formed between the first connection portion 41 and the conductor portion 213, thereby reducing the parasitic capacitance of the reference signal line REF.

[0073] In the embodiments of this application, such as Figure 4 As shown, each pixel driving circuit also includes a second connection part 61, one end of which is electrically connected to the reference signal line REF, and the other end of which is electrically connected to the first connection part 41.

[0074] That is, the first connection part 41 can not be directly connected with the reference signal line REF, but be connected with the reference signal line REF through the second connection part 61. The first connection part 41 and the second connection part 61 are disposed in different layers. In some embodiments, the reference signal line REF can be disposed in a layer different from the first power signal line VDD.

[0075] In some embodiments, the first connection part 41 can be disposed in the same layer as the reference signal line REF.

[0076] In some embodiments, the second connection part 61 can be disposed in the same layer as the first power signal line VDD.

[0077] It should be noted that the "same layer" in the embodiments of the present application refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form by one patterning process. According to different specific patterns, the one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights and / or have different thicknesses.

[0078] In addition, in some embodiments, each pixel driving circuit can further include a first scan signal line Scan1. The first scan signal line Scan1 can extend along the first direction X.

[0079] In addition, in some embodiments, each pixel driving circuit can further include a second scan signal line Scan2. The second scan signal line Scan2 can extend along the first direction X.

[0080] In addition, in some embodiments, each pixel driving circuit can further include a light-emitting control signal line EM (not shown in the figure). The light-emitting control signal line EM can extend along the first direction X. Figure 4

[0081] In addition, in some embodiments, each pixel driving circuit can further include a data line Data. The data line Data can extend along the second direction Y.

[0082] The reference signal line REF, the first scan signal line Scan1, the second scan signal line Scan2 and the light-emitting control signal line EM can extend along the first direction, and the first power signal line VDD and the data line Data can extend along the second direction, and the first direction intersects with the second direction. Optionally, the first direction is perpendicular to the second direction.

[0083] In the figure, the first scan signal line Scan1 can be located between the reference signal line REF and the second scan signal line Scan2, and the second scan signal line Scan2 can be located between the first scan signal line Scan1 and the light-emitting control signal line EM. ​

[0084] In the embodiments of the present application, as shown in Figure 4 The gate of the compensation transistor M3 is controlled by the second scan signal line Scan2, and the gate of the compensation transistor M3 is the part of the second scan signal line Scan2 which overlaps with the first channel region 211 and the second channel region 212.

[0085] In the embodiments of the present application, the gate of the compensation transistor M3 can be directly used as the second scan signal line Scan2, so that the circuit arrangement of the pixel driving circuit is more simple; of course, the gate of the compensation transistor M3 can be additionally provided and electrically connected with the second scan signal line Scan2, so that the gate of the compensation transistor M3 is controlled by the second scan signal line Scan2.

[0086] In some embodiments, each pixel driving circuit can further include a data writing transistor M2.

[0087] The gate of the data writing transistor M2 is controlled by the second scan signal line Scan2, the first electrode of the data writing transistor M2 is electrically connected with the data line Data, and the second electrode of the data writing transistor M2 is electrically connected with the first electrode of the driving transistor M1.

[0088] Figure 5 The structure shown by reference numeral 22 represents the active part of the data writing transistor M2. The gate of the data writing transistor M2 is the part of the second scan signal line Scan2 which overlaps with the channel region in the active part 22 of the data writing transistor M2.

[0089] In some embodiments, each pixel driving circuit can further include a first reset transistor M4.

[0090] The gate of the first reset transistor M4 is controlled by the first scan signal line Scan1, the first electrode of the first reset transistor M4 is electrically connected with the reference signal line REF through the second connection part 61, and the second electrode of the first reset transistor M4 is electrically connected with the gate of the driving transistor M1.

[0091] The first reset transistor M4 is also a double-gate transistor, and the double-gate structure can reduce the leakage current of the first reset transistor M4, thereby improving the stability of the gate voltage of the first reset transistor M4. Figure 5 The structure shown by reference numeral 23 represents the active part of the first reset transistor M4, and it can be seen that the active part of the first reset transistor M4 is in inverted "U" shape. The gate of the first reset transistor M4 is the part of the first scan signal line Scan1 which overlaps with the two channel regions in the active part 23 of the first reset transistor M4.

[0092] In some embodiments, each pixel driving circuit can further include a second reset transistor M7.

[0093] The gate of the second reset transistor M7 is controlled by the first scan signal line Scanl, the first electrode of the second reset transistor M7 is electrically connected with the reference signal line REF through the second connection part 61, and the second electrode of the second reset transistor M7 is electrically connected with the first electrode of the light emitting device EL.

[0094] Figure 5 The structure shown by reference numeral 24 represents the active part of the second reset transistor M7. The gate of the second reset transistor M7 can be the part of the first scan signal line Scanl which overlaps with the channel region in the active part 24 of the second reset transistor M7.

[0095] In some embodiments, each pixel driving circuit can further include a first light emitting control transistor M5.

[0096] The gate of the first light emitting control transistor M5 is controlled by the light emitting control signal line EM, the first electrode of the first light emitting control transistor M5 is electrically connected with the first power signal line VDD, and the second electrode of the first light emitting control transistor M5 is electrically connected with the first electrode of the driving transistor Ml.

[0097] The specific structure of the first light emitting control transistor M5 is not shown in Figures 4 to 8 In each pixel driving circuit, the first light emitting control transistor M5 can be located on the side of the second scan signal line Scan2 which is away from the first scan signal line Scanl. Moreover, the gate of the first light emitting control transistor M5 can be the part of the light emitting control signal line EM which overlaps with the channel region in the active part of the first light emitting control transistor M5.

[0098] In some embodiments, each pixel driving circuit can further include a second light emitting control transistor M6.

[0099] The gate of the second light emitting control transistor M6 is controlled by the light emitting control signal line EM, the first electrode of the second light emitting control transistor M6 is electrically connected with the second electrode of the driving transistor Ml, and the second electrode of the second light emitting control transistor M6 is electrically connected with the first electrode of the light emitting device EL.

[0100] The specific structure of the second light emitting control transistor M6 is not shown in Figures 4 to 8 In each pixel driving circuit, the second light emitting control transistor M6 can be located on the side of the second scan signal line Scan2 which is away from the first scan signal line Scanl. Moreover, the gate of the second light emitting control transistor M6 can be the part of the light emitting control signal line EM which overlaps with the channel region in the active part of the second light emitting control transistor M6.

[0101] In some embodiments, each pixel driving circuit can further include a storage capacitor C1.

[0102] A first plate of the storage capacitor C1 is electrically connected with the gate of the driving transistor M1, and a second plate of the storage capacitor C1 is electrically connected with the first power signal line VDD. There is an overlapping area between the first plate and the second plate of the storage capacitor, and both the first plate and the second plate are located between the second scan signal line Scan2 and the light-emitting control signal line EM.

[0103] In the actual manufacturing process, a patterning process is used to form the active layer of the array substrate on the substrate 10. The active layer of each pixel driving circuit includes the active part 21 of the compensation transistor M3, the active part 22 of the data writing transistor M2, the active part 23 of the first reset transistor M4, and the active part 24 of the second reset transistor M7 as shown in FIG. 2B; in addition, the active layer of each pixel driving circuit also includes the active part of the driving transistor M1, the active part of the first light-emitting control transistor M5, and the active part of the second light-emitting control transistor M6 which are not shown in FIG. 2B. Figure 5 Figure 5 In the actual manufacturing process, a patterning process is used to form the active layer of the array substrate on the substrate 10. The active layer of each pixel driving circuit includes the active part 21 of the compensation transistor M3, the active part 22 of the data writing transistor M2, the active part 23 of the first reset transistor M4, and the active part 24 of the second reset transistor M7 as shown in FIG. 2B; in addition, the active layer of each pixel driving circuit also includes the active part of the driving transistor M1, the active part of the first light-emitting control transistor M5, and the active part of the second light-emitting control transistor M6 which are not shown in FIG. 2B.

[0104] After the active layer is formed on the substrate 10, a first gate insulating layer covering the active layer and the substrate 10 is formed, and then a patterning process is used to form the first conductive layer of the array substrate on the first gate insulating layer. The first conductive layer can include the first scan signal line Scan1 and the second scan signal line Scan2 as shown in FIG. 2C; in addition, the first conductive layer can also include the light-emitting control signal line EM and the first plate of the storage capacitor C1 which are not shown in FIG. 2C. Figure 6 Figure 6 In the actual manufacturing process, a patterning process is used to form the active layer of the array substrate on the substrate 10. The active layer of each pixel driving circuit includes the active part 21 of the compensation transistor M3, the active part 22 of the data writing transistor M2, the active part 23 of the first reset transistor M4, and the active part 24 of the second reset transistor M7 as shown in FIG. 2B; in addition, the active layer of each pixel driving circuit also includes the active part of the driving transistor M1, the active part of the first light-emitting control transistor M5, and the active part of the second light-emitting control transistor M6 which are not shown in FIG. 2B.

[0105] That is, the first scan signal line Scan1, the second scan signal line Scan2, the light-emitting control signal line EM, and the first plate of the storage capacitor C1 are all located in the first conductive layer, and the first conductive layer can also be referred to as the first gate layer.

[0106] After the first conductive layer is formed on the first gate insulating layer, a second gate insulating layer covering the first conductive layer and the first gate insulating layer is formed, and then a patterning process is used to form the second conductive layer of the array substrate on the second gate insulating layer. The second conductive layer can include the reference signal line REF and the first connection part 41 as shown in FIG. 2D; in addition, the second conductive layer can also include the second plate of the storage capacitor C1 which is not shown in FIG. 2D. Figure 7 Figure 7 In the actual manufacturing process, a patterning process is used to form the active layer of the array substrate on the substrate 10. The active layer of each pixel driving circuit includes the active part 21 of the compensation transistor M3, the active part 22 of the data writing transistor M2, the active part 23 of the first reset transistor M4, and the active part 24 of the second reset transistor M7 as shown in FIG. 2B; in addition, the active layer of each pixel driving circuit also includes the active part of the driving transistor M1, the active part of the first light-emitting control transistor M5, and the active part of the second light-emitting control transistor M6 which are not shown in FIG. 2B.

[0107] That is, the reference signal line REF, the first connection part 41, and the second plate of the storage capacitor C1 are all located in the second conductive layer, and the second conductive layer can also be referred to as the second gate layer.

[0108] ​​​After forming a second conductive layer on the second gate insulating layer, an interlayer dielectric layer covering the second conductive layer and the second gate insulating layer can be formed. Then, an etching process is used to form a through-hole. Figure 8 In the first via 51, the second via 52 penetrates the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer; the third via 53 penetrates the interlayer dielectric layer; the fourth via 54 penetrates the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer; and the fifth via 55 penetrates the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer. Along the second direction, the third via 53 is located on the side of the first scan signal line Scan1 away from the reference signal line REF.

[0109] Finally, a third conductive layer of the array substrate is formed on the interlayer dielectric layer using a patterning process. This third conductive layer includes, for example, the following: Figure 4 The first power signal line VDD, the data line Data, the second connection part 61, and the third connection part 62 are shown.

[0110] In other words, the first power signal line VDD, the data line Data, the second connection part 61 and the third connection part 62 are all located in the third conductive layer, which can also be called the source and drain electrode layer.

[0111] It is understandable that, during the formation of the third conductive layer, the conductive material of the third conductive layer can be formed within the aforementioned through-hole to form a structure as described above. Figure 4 The array substrate is shown. Therefore, the second connection portion 61 is electrically connected to the reference signal line REF through the through-hole first via 51, and the second connection portion 61 is electrically connected to the active layer through the through-hole second via 52 (specifically: the second connection portion 61 is electrically connected to the active portion of the first reset transistor M4 and the active portion of the second reset transistor M7 through the through-hole second via 52, so that the second connection portion 61 is electrically connected to the first electrode of the first reset transistor M4 through the through-hole second via 52, and the second connection portion 61 is electrically connected to the second reset transistor M7 through the through-hole second via 52). The first terminal is electrically connected), the second connection portion 61 is also electrically connected to the first connection portion 41 through the through third via 53; the third connection portion 62 is electrically connected to the active layer through the through fourth via 54 (specifically: the third connection portion 62 is electrically connected to the second terminal of the compensation transistor M3 through the through fourth via 54), and the data line Data is electrically connected to the active portion 22 of the data writing transistor M2 through the through fifth via 55 (specifically: the data line Data is electrically connected to the first terminal of the data writing transistor M2 through the through fifth via 55).

[0112] because Figure 4 Most of the conductor segments in the second connection portion 61 shown (i.e., the conductor segments between the first via 51 and the second via 52) are Figure 3 The map shown inherently contains,Figure 4 The second connection part 61 shown in FIG. 1 is different from the corresponding conductive segment in FIG. 1 in that the second connection part 61 further extends towards the side of the second scan signal line Scan2 and is electrically connected with the first connection part 41 through the third via hole 53. Figure 3 As can be seen, the extension length of the first connection part 41 is smaller than the extension length of the conductive structure 11 in FIG. 1.

[0113] The layout shown in FIG. 1, Figure 3 The newly added conductive segment in the layout shown in FIG. 1 includes the wire segment extending in the second connection part 61 and the first connection part 41, and removes the conductive structure 11 in FIG. 1. Figure 4 Since the extension length of the wire segment extending in the second connection part 61 is very short, and the first connection part 41 is spaced apart from the first power signal line VDD by a certain distance, while the conductive structure 11 in FIG. 1 extends to the position of the first power signal line VDD, it can be known that the sum of the extension length of the first connection part 41 and the extension length of the wire segment extending in the second connection part 61 is also smaller than the extension length of the conductive structure 11, so that the total area of the first connection part 41 and the wire segment extending in the second connection part 61 is smaller than the area of the conductive structure 11, thereby reducing the parasitic capacitance of the reference signal line REF and improving the transmittance of the display panel. Figure 3 Figure 3 In addition, the wire segment extending in the second connection part 61 has no overlapping area with the active pattern in the active layer (i.e., the active part 23 of the first reset transistor M4 and the active part 24 of the second reset transistor M7) on the substrate 10.

[0114] Optionally, the first end of the second connection part 61 has an overlapping area with the reference signal line REF on the substrate 10. The first end of the second connection part 61 is electrically connected with the reference signal line REF through the first via hole 51. Optionally, the second end of the second connection part 61 has an overlapping area with the first connection part 41 on the substrate 10. The second end of the second connection part 61 is electrically connected with the first connection part 41 through the third via hole 53. The projection of the second connection part 61 on the substrate 10 and the projection of the first scan signal line Scan1 on the substrate 10 can be cross-arranged. The projections of the first end and the second end of the second connection part 61 on the substrate 10 can be located on both sides of the projection of the first scan signal line Scan1 on the substrate, i.e., in the second direction Y, the first connection part 41 and the reference signal line REF are respectively located on both sides of the first scan signal line Scan1. The projections of the first via hole 51 and the second via hole 52 on the substrate can be located on both sides of the projection of the first scan signal line Scan1 on the substrate.

[0115] Optionally, the first end of the second connection part 61 has an overlapping area with the reference signal line REF on the substrate 10. The first end of the second connection part 61 is electrically connected with the reference signal line REF through the first via hole 51. Optionally, the second end of the second connection part 61 has an overlapping area with the first connection part 41 on the substrate 10. The second end of the second connection part 61 is electrically connected with the first connection part 41 through the third via hole 53. The projection of the second connection part 61 on the substrate 10 and the projection of the first scan signal line Scan1 on the substrate 10 can be cross-arranged. The projections of the first end and the second end of the second connection part 61 on the substrate 10 can be located on both sides of the projection of the first scan signal line Scan1 on the substrate, i.e., in the second direction Y, the first connection part 41 and the reference signal line REF are respectively located on both sides of the first scan signal line Scan1. The projections of the first via hole 51 and the second via hole 52 on the substrate can be located on both sides of the projection of the first scan signal line Scan1 on the substrate.

[0116] ​Optionally, the first connection portion 41 can be located on the side of the first scan signal line Scan1 away from the reference signal line REF. The orthogonal projection of the first connection portion 41 on the substrate 10 can not overlap with the orthogonal projection of the second scan signal line Scan2 on the substrate 10. The orthogonal projections of the first connection portion 41 and the second connection portion 61 on the substrate 10 can be located on the same side of the orthogonal projection of the first power supply signal line VDD on the substrate 10. There can be no wire segment between the conductor portion 213 and the first power supply signal line VDD to form a coupling capacitor.

[0117] According to the above description, it can be known that the first conductive layer is provided with the first gate insulating layer between the first conductive layer and the active layer, the second conductive layer is provided with the second gate insulating layer between the second conductive layer and the first conductive layer, and the third conductive layer is provided with the interlayer dielectric layer between the third conductive layer and the second conductive layer, and the third conductive layer is located on the side of the interlayer dielectric layer away from the substrate 10.

[0118] The materials of the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer can all be inorganic insulating materials, for example, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer can be silicon nitride layers or silicon oxide layers, or the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer can also include silicon nitride layers and silicon oxide layers arranged in a stack. The materials of the first conductive layer, the second conductive layer and the third conductive layer can be metal materials such as titanium, aluminum, molybdenum and copper.

[0119] It should be noted that, Figure 4 The array substrate shown only shows the circuit structure in one pixel driving circuit, and the circuit structure only includes Figure 1 Part of the transistors and part of the signal lines in the pixel driving circuit.

[0120] In addition, the array substrate further includes a passivation layer covering the third conductive layer and the interlayer dielectric layer, and a planarization layer provided on the side of the passivation layer away from the substrate 10. The passivation layer can be a silicon nitride layer or a silicon oxide layer, or the passivation layer can also include silicon nitride layers and silicon oxide layers arranged in a stack; the material of the planarization layer can be an organic material, such as a resin material.

[0121] In other embodiments, as Figure 9 shown, the compensation transistor M3 can also be a single-gate transistor, which includes one channel region and a gate corresponding to the channel region.

[0122] Specifically, the active part 21 of the compensation transistor M3 can include a channel region and a conductor portion, the channel region can be Figure 5 the second channel region 212 shown, at this time, the active part 21 of the compensation transistor M3 does not include Figure 5 the first channel region 211 shown, and Figure 5 the area corresponding to the first channel region 211 shown is also subjected to conductorization processing to form a conductor portion, that isFigure 9 The conductor section actually includes Figure 5 The conductor portion 213 shown, and Figure 5 The structure shown is the first channel region 211 after conductor treatment.

[0123] Therefore, as Figure 9 As shown, the gate of the compensation transistor M3 is controlled by the second scan signal line Scan2, and the gate of the compensation transistor M3 is the part of the second scan signal line Scan2 that overlaps with the channel region (i.e., the second channel region 212).

[0124] In other embodiments, such as Figure 10 As shown, each pixel driving circuit also includes a second connection portion 61. The first connection portion 41 and the second connection portion 61 are disposed on the same layer, and the first connection portion 41 is also disposed on the same layer as the first power signal line VDD. That is to say, the first connection portion 41, the second connection portion 61 and the first power signal line VDD are all disposed on the same layer.

[0125] The first connecting part 41 and the second connecting part 61 can be formed using the same patterning process, so that the first connecting part 41 and the second connecting part 61 are an integral structure.

[0126] It should be noted that, Figure 10 and Figure 4 The difference in the maps shown is that, in Figure 4 In the layout shown, the first connecting part 41 and the second connecting part 61 are disposed on different layers, and the two are electrically connected through a through third via 53; while Figure 10 In the layout shown, the first connecting part 41 and the second connecting part 61 are arranged on the same layer. They do not require an electrical connection via a through-hole 53; instead, they are formed as a single integrated structure using the same patterning process during manufacturing. Therefore, Figure 10 The layout shown eliminates the need for a third via during the manufacturing process, thus reducing the complexity of via fabrication.

[0127] Therefore, in this embodiment of the application, by adding a first connection portion to each pixel driving circuit, electrically connecting the first connection portion to the reference signal line, and having the first connection portion overlap with the conductor portion in the active portion of the compensation transistor to form a coupling capacitance, the potential stability of the conductor portion in the active portion of the compensation transistor can be improved, thereby improving the leakage phenomenon of the compensation transistor; and since the added first connection portion and the first power signal line do not overlap, that is, the first connection portion and the first power signal line have a certain distance between them, the area of ​​the added first connection portion in the second conductive layer can be smaller, thereby reducing parasitic capacitance and improving the transmittance of the display panel.

[0128] The display panel provided in the embodiments of the present application also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0129] In addition, the display panel can further include a light emitting device layer and an encapsulation layer disposed on the array substrate. The light emitting device layer includes an anode, a pixel defining layer, a light emitting layer, a cathode, and the like. Figure 1 The light emitting device EL in the array substrate includes an anode, a light emitting layer, and a cathode disposed in a stack, the first electrode of the light emitting device EL refers to the anode, and the second electrode of the light emitting device EL refers to the cathode.

[0130] Specifically, the anode can be located on the side of the planar layer of the array substrate away from the substrate 10, the pixel defining layer is also located on the side of the planar layer of the array substrate away from the substrate 10, and the pixel defining layer has a pixel opening exposing the anode, the light emitting layer is located in the pixel opening, and the cathode layer covers the pixel defining layer and the light emitting layer.

[0131] The encapsulation layer can be an organic encapsulation layer, an inorganic encapsulation layer, or a stack structure of an organic encapsulation layer and an inorganic encapsulation layer.

[0132] The display panel can include a first display area and a second display area. The light sensing element can be used to collect light transmitted through the second display area. The light sensing element can include one or more of a camera, a fingerprint identification module. The transmittance of the second display area can be greater than or equal to the transmittance of the first display area. The second display area is provided with the same or similar pixel driving circuit as the Figure 4 、 Figure 9 and Figure 10 The pixel driving circuit of the first display area and the second display area can be the same or different. The display panel can be a full-screen display without a non-display area, and the frame width is almost zero.

[0133] It should be noted that the display panel provided in the embodiments of the present application can be an organic light emitting display panel, and can also be a liquid crystal display panel. Exemplarily, the display panel can be a mobile phone, a tablet computer, a wearable device, a display, a notebook computer, a navigator, or any product or component having a display function.

[0134] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms “mounting”, “connection”, “connecting” should be understood in a broad sense, for example, it can be fixedly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0135] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and like terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0136] The terms "first", "second", "third", "fourth" and the like in the description of the present application and the above drawings (if any) are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products or devices.

[0137] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized by, The application relates to a display panel, comprising: a substrate and a plurality of pixel driving circuits arranged on the substrate, each of the pixel driving circuits comprising a compensation transistor, a driving transistor, a reference signal line, a first power signal line and a first connecting part; a first electrode of the compensation transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the compensation transistor is electrically connected with a gate electrode of the driving transistor; an active part of the compensation transistor comprises a conductor part; the first connecting part is electrically connected with the reference signal line, a normal projection of the first connecting part on the substrate and a normal projection of the conductor part on the substrate have an overlapping area, and a normal projection of the first connecting part on the substrate and a normal projection of the first power signal line on the substrate do not have an overlapping area; each of the pixel driving circuits further comprises a second connecting part, one end of the second connecting part is electrically connected with the reference signal line, and the other end of the second connecting part is electrically connected with the first connecting part; the pixel driving circuit further comprises a first scanning signal line and a first reset transistor; a gate electrode of the first reset transistor is controlled by the first scanning signal line, a first electrode of the first reset transistor is electrically connected with the reference signal line through the second connecting part, and a second electrode of the first reset transistor is electrically connected with the gate electrode of the driving transistor; a normal projection of the second connecting part on the substrate is arranged to cross a normal projection of the first scanning signal line on the substrate; and, along a second direction, the first connecting part and the reference signal line are respectively located on two sides of the first scanning signal line.

2. The array substrate of claim 1, wherein, the active part of the compensation transistor further comprises a first channel region and a second channel region, and the conductor part is located between the first channel region and the second channel region; the conductor part comprises a first conductor part and a second conductor part which are connected with each other; the first conductor part extends along a first direction, and the second conductor part extends along a second direction, and the first direction intersects with the second direction; a normal projection of the first connecting part on the substrate has an overlapping area with a normal projection of the first conductor part and / or the second conductor part on the substrate.

3. The array substrate of claim 1, wherein, the reference signal line is arranged in a layer different from that of the first power signal line, the first connecting part is arranged in a layer same as that of the reference signal line, and the second connecting part is arranged in a layer same as that of the first power signal line.

4. The array substrate of claim 1, wherein, the first connecting part and the second connecting part are arranged in a same layer, and the first connecting part is further arranged in a same layer as the first power signal line.

5. The array substrate of claim 1, wherein, each of the pixel driving circuits further comprises a second scanning signal line, a light-emitting control signal line and a data line; the reference signal line, the first scanning signal line, the second scanning signal line and the light-emitting control signal line extend along a first direction, and the first power signal line and the data line extend along a second direction, and the first direction intersects with the second direction.

6. The array substrate of claim 5, wherein, the first scanning signal line is located between the reference signal line and the second scanning signal line, and the second scanning signal line is located between the first scanning signal line and the light-emitting control signal line.

7. The array substrate of claim 6, wherein, The gate of the compensation transistor is controlled by the second scan signal line, and the gate of the compensation transistor is the part of the second scan signal line which overlaps with the channel region of the compensation transistor.

8. The array substrate of claim 7, wherein, Each of the pixel driving circuits further comprises a data writing transistor, a second reset transistor, a first light emitting control transistor, a second light emitting control transistor and a storage capacitor; The gate of the data writing transistor is controlled by the second scan signal line, the first electrode of the data writing transistor is electrically connected with the data line, and the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor; The gate of the second reset transistor is controlled by the first scan signal line, the first electrode of the second reset transistor is electrically connected with the reference signal line through the second connecting part, and the second electrode of the second reset transistor is electrically connected with the first electrode of the light emitting device; The gate of the first light emitting control transistor is controlled by the light emitting control signal line, the first electrode of the first light emitting control transistor is electrically connected with the first power signal line, and the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor; The gate of the second light emitting control transistor is controlled by the light emitting control signal line, the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; The first plate of the storage capacitor is electrically connected with the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected with the first power signal line.

9. The array substrate of claim 8, wherein, The active part of the compensation transistor is located in an active layer; the first scan signal line, the second scan signal line, the light emitting control signal line and the first plate of the storage capacitor are located in a first conductive layer; The reference signal line and the second plate of the storage capacitor are located in a second conductive layer; The first power signal line and the data line are located in a third conductive layer; A first gate insulating layer is arranged between the first conductive layer and the active layer, a second gate insulating layer is arranged between the second conductive layer and the first conductive layer, an interlayer dielectric layer is arranged between the third conductive layer and the second conductive layer, and the third conductive layer is located on the side of the interlayer dielectric layer away from the substrate.

10. The array substrate of claim 1, wherein, Further comprising: a second reset transistor, The gate of the second reset transistor is controlled by the first scan signal line, the first electrode of the second reset transistor is electrically connected with the reference signal line through the second connecting part, and the second electrode of the second reset transistor is electrically connected with the first electrode of the light emitting device; The active part of the second reset transistor and the active part of the first reset transistor are directly connected, and the second connecting part is electrically connected with the active part of the second reset transistor and the active part of the first reset transistor through the same second via.

11. The array substrate of claim 10, wherein, The second connecting part is electrically connected with the first connecting part through a third via.

12. The array substrate of claim 10, wherein, The second connecting part is arranged in the same layer as the first connecting part, and the second connecting part and the first connecting part are connected as an integrated structure.

13. The array substrate of claim 1, wherein, The compensation transistor is a single-gate transistor, and the first power signal line and the first connection portion are transparent.

14. A display panel, characterized by The array substrate comprises the array substrate as claimed in any one of claims 1 to 13.

15. The display panel of claim 14, wherein, The display panel comprises a first display area and a second display area, the transmittance of the second display area being greater than or equal to the transmittance of the first display area; the second display area is provided with the pixel driving circuit; A photosensitive element is used to collect light transmitted through the second display area; the photosensitive element comprises one or more of a camera and a fingerprint identification module.

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