Synchronous rectification control method and apparatus

Abstract

This invention discloses a synchronous rectification control method and apparatus. The method includes: identifying the power transistor drive signal of a bridge-type structure in a resonant converter and generating a trigger signal based on the power transistor drive signal, wherein the power transistor of the bridge-type structure is disposed in the primary circuit of the resonant converter; generating a rectifier transistor drive signal based on the trigger signal and controlling the rectifier transistor to conduct based on the rectifier transistor drive signal, wherein the rectifier transistor is disposed in the secondary circuit of the resonant converter; after detecting the disappearance of the trigger signal, continuously controlling the rectifier transistor to conduct through a holding circuit; and triggering a rectifier transistor turn-off signal when the voltage difference between the source and drain of the rectifier transistor exceeds a set voltage threshold, and controlling the rectifier transistor to turn off based on the rectifier transistor turn-off signal. This invention solves the technical problem in related technologies where there is a lack of an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier transistors in the secondary circuit of a resonant converter.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and more specifically, to a synchronous rectification control method and apparatus. Background Technology

[0002] Switching converters are constantly evolving towards higher power density. In this process, synchronous rectification technology has been widely applied. Its basic principle is to replace rectifier diodes with MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) that have lower on-resistance, thereby significantly reducing the conduction losses of the rectifier diodes. However, this correspondingly increases the complexity of the entire converter control. In hard-switching topologies such as flyback and forward converters, the switching timing of the synchronous rectifier diode is either in phase or out of phase with the main power transistor, and the drive signal is relatively easy to obtain. However, in resonant topologies such as LLC converters, the control of the synchronous rectifier diode is more complex, requiring it to be turned off earlier or later than the main power transistor in different operating modes. Therefore, accurately controlling the synchronous rectifier diode to exhibit the unidirectional conductivity of a diode while minimizing losses is key to the application of synchronous rectification technology in resonant topologies.

[0003] Figure 1 This is a circuit diagram of an existing LLC topology converter. (Refer to...) Figure 1 As shown, the LLC topology conversion circuit includes a first switch Q1, a second switch Q2, a series resonant capacitor Cr, a series resonant inductor Lr, and a magnetizing inductor Lm disposed on the primary side of the converter; a first synchronous rectifier SR1 and a second synchronous rectifier SR2 disposed on the secondary side of the converter; a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4; a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4.

[0004] Figure 2 This is a circuit timing and waveform diagram of an existing LLC topology converter. In the diagram, Io represents the converter's output current. Figure 3 This is the equivalent circuit diagram of an existing LLC topology converter operating within the time period t1-t2; Figure 4 This is the equivalent circuit diagram of an existing LLC topology converter operating during the time interval t2-t3. (Refer to...) Figure 3As shown, the converter operates during the time period t1-t2, corresponding to a series resonance state, i.e., Lr and Cr resonate in series. The voltage on the magnetizing inductor Lm is clamped and only acts as a load, not participating in the resonance. During the time period t1-t2, Ir splits into two branches: the current Ilm flowing through the magnetizing inductor Lm and the current Inp flowing through the primary winding np, i.e., Ir = Ilm + Inp. Due to the presence of Inp, energy is transferred to the secondary side of the converter, and the rectifier diode SR1, output capacitor C0, and load R0 on the secondary side of the converter form a loop. Figure 4 The equivalent circuit diagram for this topology operating during the time period t2-t3 is shown. During this period, Ir = Ilm, Inp = 0. That is, during the t2-t3 period, the secondary current of the converter is zero, and the output rectifier diode SR1 achieves ZCS (Zero Current Switch), with the output capacitor C0 providing energy to the load. During this stage, Q1 remains on, and (Lr + Lm) forms a series resonance with Cr. Since the time is short and (Lm + Lr) is also large, the current is assumed to remain constant, and Ir = Ilm. Figure 5 This is a schematic diagram of the signal flow and circuit when current reverse current occurs in an existing LLC topology converter. (Refer to...) Figure 5 As shown, when the primary power transistor Q1 and the secondary rectifier transistor SR1, or Q2 and the secondary rectifier transistor SR2, are simultaneously switched on and off in an LLC topology converter, if the resonant frequency in the LLC resonant circuit is higher than the switching frequency, the primary current conforms to the following: Ir = Ilm, Inp = 0. The current Inp of the primary coil np is also zero, meaning the current in the secondary coil is also zero. This means the secondary current will reach zero earlier than the primary drive signal. If the rectifier transistors in the secondary circuit are not turned off at this time, and the secondary drive remains consistent with the primary drive, a reverse current phenomenon will occur in the secondary circuit. However, related technologies cannot solve the problem of reverse current caused by the secondary rectifier transistors not being turned off in time or being mistakenly turned on when the resonant frequency in the circuit is higher than the switching frequency of the primary switch transistor in the LLC topology converter. In other words, related technologies lack an effective synchronous rectification control method for controlling the switching on and off of the rectifier transistors.

[0005] There is currently no effective solution to the above problems. Summary of the Invention

[0006] This invention provides a synchronous rectification control method and apparatus to at least solve the technical problem in the related art of lacking an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier tubes in the secondary circuit of a resonant converter.

[0007] According to one aspect of the present invention, a synchronous rectification method is provided, comprising: identifying a power transistor drive signal of a bridge structure in a resonant converter and generating a trigger signal based on the power transistor drive signal, wherein the power transistor of the bridge structure is disposed in the primary circuit of the resonant converter; generating a rectifier drive signal based on the trigger signal and controlling the rectifier to turn on based on the rectifier drive signal, wherein the rectifier is disposed in the secondary circuit of the resonant converter; after detecting that the trigger signal disappears, continuously controlling the rectifier to turn on through a holding circuit; and triggering a rectifier turn-off signal when detecting that the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, and controlling the rectifier to turn off based on the rectifier turn-off signal.

[0008] Optionally, identifying the power transistor drive signal in the bridge structure of the resonant converter and generating a trigger signal based on the power transistor drive signal includes: detecting the power transistor drive signal in the bridge structure of the resonant converter; receiving the power transistor drive signal in a trigger line and generating a trigger signal based on the power transistor drive signal, wherein the rising edge of the trigger signal corresponds to the rising edge of the power transistor drive signal.

[0009] Optionally, the step of continuously controlling the rectifier tube to conduct after detecting the disappearance of the trigger signal includes: inputting the trigger signal and the rectifier tube drive signal to a NOR gate circuit, so that the NOR gate circuit continuously outputs an enable signal, and the enable signal controls the synchronous rectification unit to output the rectifier tube drive signal to control the rectifier tube to conduct.

[0010] Optionally, the bridge structure in the resonant converter includes an upper half-bridge structure and a lower half-bridge structure; the power transistor drive signal includes a first power transistor drive signal corresponding to the upper half-bridge structure and a second power transistor drive signal corresponding to the lower half-bridge structure; the trigger signal includes a first trigger signal and a second trigger signal, wherein the rising edge of the first trigger signal corresponds to the rising edge of the first power transistor drive signal, and the rising edge of the second trigger signal corresponds to the rising edge of the second power transistor drive signal; the enable signal includes a first enable signal corresponding to the first trigger signal and a second enable signal corresponding to the second trigger signal; the rectifier drive signal includes a first rectifier drive signal generated based on the first enable signal and a second rectifier drive signal generated based on the second enable signal.

[0011] Optionally, controlling the rectifier tube to turn on based on the rectifier tube drive signal includes: controlling the rectifier tube to turn on based on the first rectifier tube drive signal, or controlling the rectifier tube to turn on based on the second rectifier tube drive signal; and after detecting that the trigger signal has disappeared, continuously controlling the rectifier tube to turn on through a holding circuit.

[0012] Optionally, the rectifier includes a first rectifier and a second rectifier. By interlocking the first enable signal and the second enable signal, the following two operations are controlled to not exist simultaneously: the first power transistor drive signal controls the first rectifier to turn on, and the second power transistor drive signal controls the second rectifier to turn on.

[0013] According to another aspect of the present invention, a synchronous rectification control device is also provided, comprising: a trigger signal generation unit, configured to identify a power transistor drive signal of a bridge structure in a resonant converter and generate a trigger signal based on the power transistor drive signal, wherein the power transistor of the bridge structure is disposed in the primary circuit of the resonant converter; a synchronous rectification control unit, configured to generate a rectifier drive signal based on the trigger signal and control the rectifier to turn on based on the rectifier drive signal, wherein the rectifier is disposed in the secondary circuit of the resonant converter; after detecting that the trigger signal disappears, continuously controlling the rectifier to turn on through a holding circuit; and triggering a rectifier turn-off signal when detecting that the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, and controlling the rectifier to turn off based on the rectifier turn-off signal.

[0014] Optionally, the holding circuit includes a NOR gate circuit, and the synchronous rectification control unit includes: a logic control unit and a rectifier drive signal output unit, wherein the NOR gate circuit is used to receive the trigger signal and the rectifier drive signal, and generate an enable signal based on the trigger signal and the rectifier drive signal; the logic control unit is used to receive the enable signal and the rectifier turn-off signal, and output the rectifier drive signal through the rectifier drive signal output unit when the enable signal is received, and output the rectifier turn-off signal through the rectifier drive signal output unit to control the rectifier to turn off when the rectifier turn-off signal is received.

[0015] Optionally, the trigger signal generation unit includes: a signal identification unit, configured to detect the power transistor drive signal in the bridge structure of the resonant converter, and generate a first-level control signal based on the power transistor drive signal; and a signal processing unit, configured to receive the first-level control signal, and generate a trigger signal based on the first-level control signal, wherein the rising edge of the trigger signal corresponds to the rising edge of the power transistor drive signal.

[0016] Optionally, it further includes: a signal interlock circuit for controlling the rectifier diode turn-on signal enabled by a first trigger signal and the rectifier diode turn-on signal enabled by a second trigger signal to not occur simultaneously, wherein the first trigger signal is a signal generated based on a first power transistor drive signal, the second trigger signal is a signal generated based on a second power transistor drive signal, and the bridge structure in the resonant converter includes: an upper half-bridge structure and a lower half-bridge structure, the first power transistor drive signal is a drive signal corresponding to the upper half-bridge structure, and the second power transistor drive signal is a drive signal corresponding to the lower half-bridge structure.

[0017] In this embodiment of the invention, a power transistor drive signal in the bridge structure of the resonant converter is identified, and a trigger signal is generated based on the power transistor drive signal. The power transistor in the bridge structure is disposed in the primary circuit of the resonant converter. A rectifier drive signal is generated based on the trigger signal, and the rectifier is controlled to turn on based on the rectifier drive signal. The rectifier is disposed in the secondary circuit of the resonant converter. After the trigger signal is detected to disappear, the rectifier is continuously controlled to turn on by a holding circuit. When the voltage difference between the source and drain of the rectifier is detected to exceed a set voltage threshold, a rectifier turn-off signal is triggered, and the rectifier is controlled to turn off based on the rectifier turn-off signal. The primary power transistor drive signal is converted into a trigger signal to control the generation of the rectifier drive signal, which controls the rectifier to turn on. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is generated, and the rectifier is controlled to turn off based on the rectifier turn-off signal. This ensures that the rectifier diodes and their corresponding power diodes are turned on synchronously and are turned off before reverse current is generated in the secondary circuit of the converter, thus preventing reverse current from being generated in the secondary circuit. This achieves effective control of the rectifier diodes and solves the problem of the lack of an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier diodes in related technologies. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0019] Figure 1 This is a circuit diagram of an LLC topology converter in the prior art;

[0020] Figure 2 This is a circuit timing diagram and waveform diagram of an existing LLC topology converter;

[0021] Figure 3 This is the equivalent circuit diagram of an existing LLC topology converter operating within the time period t1-t2;

[0022] Figure 4 This is the equivalent circuit diagram of an existing LLC topology converter operating during the time period t2-t3;

[0023] Figure 5 This is a schematic diagram of the energy flow and circuit when current backflow occurs in an existing LLC topology converter;

[0024] Figure 6 This is a flowchart of an optional synchronous rectification control method according to an embodiment of the present invention;

[0025] Figure 7 This is a structural block diagram of an optional synchronous rectification control device according to an embodiment of the present invention;

[0026] Figure 8 This is a structural block diagram of another optional synchronous rectification control device according to an embodiment of the present invention;

[0027] Figure 9 This is a circuit diagram of an optional trigger signal generation unit according to an embodiment of the present invention;

[0028] Figure 10 This is a circuit diagram of an optional signal amplification unit according to an embodiment of the present invention;

[0029] Figure 11 This is a circuit diagram of another optional signal amplification unit according to an embodiment of the present invention;

[0030] Figure 12 This is a circuit diagram of an optional signal demodulation unit according to an embodiment of the present invention;

[0031] Figure 13 This is a circuit diagram of an optional first synchronous rectification control unit according to an embodiment of the present invention;

[0032] Figure 14 This is a circuit diagram of an optional peripheral control unit according to an embodiment of the present invention;

[0033] Figure 15 This is a timing diagram of the operation of a synchronous rectification control device according to an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Example 1

[0037] According to an embodiment of the present invention, a method embodiment for synchronous rectification control is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0038] Figure 6 This is a flowchart of an optional synchronous rectification control method according to an embodiment of the present invention, such as... Figure 6 As shown, the method includes the following steps:

[0039] Step S602: Identify the power transistor drive signal of the bridge structure in the resonant converter and generate a trigger signal based on the power transistor drive signal, wherein the power transistor of the bridge structure is set in the primary circuit of the resonant converter.

[0040] Step S604: Generate a rectifier drive signal based on the trigger signal, and control the rectifier to turn on based on the rectifier drive signal. The rectifier is set in the secondary circuit of the resonant converter.

[0041] In one alternative embodiment, the rectifier drive signal is a PWM (Pulse Width Modulation) signal.

[0042] Step S606: After the trigger signal is detected to disappear, the rectifier tube is continuously controlled to be turned on by the holding circuit.

[0043] Step S608: When the voltage difference between the source and drain of the rectifier exceeds the set voltage threshold, a rectifier turn-off signal is triggered, and the rectifier is turned off based on the rectifier turn-off signal.

[0044] In the above optional embodiments, the power transistor drive signal of the bridge structure in the resonant converter is identified, and a trigger signal is generated based on the power transistor drive signal. The power transistor of the bridge structure is placed in the primary circuit of the resonant converter. A rectifier drive signal is generated based on the trigger signal, and the rectifier is controlled to turn on based on the rectifier drive signal. The rectifier is placed in the secondary circuit of the resonant converter. After the trigger signal is detected to disappear, the rectifier is continuously controlled to turn on by a holding circuit. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is triggered, and the rectifier is controlled to turn off based on the rectifier turn-off signal. The primary power transistor drive signal is converted into a trigger signal to control the generation of the rectifier drive signal. The rectifier drive signal controls the rectifier to turn on. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is generated, and the rectifier is controlled to turn off based on the rectifier turn-off signal. Therefore, it ensures that the rectifier diodes and their corresponding power diodes conduct synchronously, and that the rectifier diodes remain on after the trigger signal disappears, ensuring that synchronous rectification continues to operate. Furthermore, it ensures that the diodes are turned off before reverse current is generated in the secondary circuit of the converter, preventing reverse current from flowing into the secondary circuit. This achieves effective control of the rectifier diodes and solves the problem in related technologies of lacking an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier diodes. As an optional embodiment, the method for identifying the power transistor drive signal in the bridge structure of the resonant converter and generating a trigger signal based on the power transistor drive signal may include the following steps: detecting the power transistor drive signal in the bridge structure of the resonant converter; the trigger line receiving the power transistor drive signal and generating a trigger signal based on the power transistor drive signal, wherein the rising edge of the trigger signal corresponds to the rising edge of the power transistor drive signal.

[0045] In this optional embodiment, a trigger signal is generated based on the power transistor drive signal, and the rising edge of the trigger signal corresponds to the rising edge of the power transistor drive signal. Based on the trigger signal converted from the power transistor drive signal, a rectifier drive signal for controlling the rectifier diode to turn on is generated, thereby ensuring that the rectifier diode and the corresponding power transistor turn on synchronously, and achieving effective control of the rectifier diode.

[0046] As an optional embodiment, after the trigger signal is detected to disappear, the rectifier tube is continuously controlled to be turned on by the holding circuit, including: inputting the trigger signal and the rectifier tube drive signal to the NOR gate circuit, so that the NOR gate circuit continuously outputs an enable signal, and the enable signal controls the synchronous rectification unit to output the rectifier tube drive signal to control the rectifier tube to be turned on.

[0047] In this optional embodiment, a NOR gate is used to perform a NOR logic operation on the trigger signal and the rectifier drive signal. When the power transistor drive signal is converted into a trigger signal, the trigger signal is high. The NOR gate receives the high-level trigger signal and outputs a low-level enable signal. The low-level enable signal controls the synchronous rectification unit to output a high-level rectifier drive signal, controlling the rectifier to conduct. When the trigger signal disappears, the rectifier drive signal received by the NOR gate is still high, so the NOR gate continuously outputs a low-level enable signal. The low-level enable signal controls the synchronous rectification unit to output a high-level rectifier drive signal, continuing to control the rectifier to conduct. Thus, after detecting the disappearance of the trigger signal, the circuit continuously controls the rectifier to conduct, i.e., it realizes the latching function of the trigger signal. In addition, when the trigger signal is low, the enable signal output by the NOR gate is high. The high-level enable signal controls the synchronous rectification unit to stop outputting the rectifier drive signal, and the rectifier drive signal is low.

[0048] As an optional embodiment, the bridge structure in the resonant converter includes: an upper half-bridge structure and a lower half-bridge structure; the power transistor drive signals include a first power transistor drive signal corresponding to the upper half-bridge structure and a second power transistor drive signal corresponding to the lower half-bridge structure; the trigger signals include a first trigger signal and a second trigger signal, wherein the rising edge of the first trigger signal corresponds to the rising edge of the first power transistor drive signal, and the rising edge of the second trigger signal corresponds to the rising edge of the second power transistor drive signal; the enable signals include a first enable signal corresponding to the first trigger signal and a second enable signal corresponding to the second trigger signal; the rectifier drive signals include: a first rectifier drive signal generated based on the first enable signal and a second rectifier drive signal generated based on the second enable signal. In an optional embodiment, the first trigger signal and the second trigger signal are generated based on the first power transistor drive signal and the second power transistor drive signal, and the first rectifier drive signal and the second rectifier drive signal are generated based on the first trigger signal and the second trigger signal, respectively, and the first rectifier drive signal and the second rectifier drive signal are used to control the conduction of the first rectifier and the second rectifier. Therefore, by converting the drive signal of the power transistor in the primary circuit of the resonant converter, effective control of the rectifier transistor in the secondary circuit of the resonant converter can be achieved.

[0049] In some alternative embodiments, the bridge structure in the resonant converter includes a half-bridge structure or a full-bridge structure. In the half-bridge structure, the upper half-bridge structure corresponds to the upper half-bridge of the half-bridge structure, and the lower half-bridge structure corresponds to the lower half-bridge of the half-bridge structure; in the full-bridge structure, the upper half-bridge structure corresponds to the upper half-bridge of the full-bridge structure, and the lower half-bridge structure corresponds to the lower half-bridge of the full-bridge structure. In the full-bridge structure, the first power transistor includes a first sub-power transistor and a second sub-power transistor with gate interconnects, and the second power transistor includes a third sub-power transistor and a fourth sub-power transistor with gate interconnects.

[0050] As an optional embodiment, the method for controlling the conduction of a rectifier tube based on a rectifier tube drive signal may include the following steps: controlling the conduction of the rectifier tube based on a first rectifier tube drive signal, or controlling the conduction of the rectifier tube based on a second rectifier tube drive signal; and after the trigger signal is detected to disappear, continuously controlling the conduction of the rectifier tube through a holding circuit. Thus, the rectifier tube can continue to conduct after the first or second rectifier tube drive signal disappears, achieving effective control of the rectifier tube.

[0051] As an optional embodiment, the rectifier includes a first rectifier and a second rectifier. By interlocking the first and second enable signals, the following two operations are controlled to prevent simultaneous occurrence: a first power transistor drive signal controls the first rectifier to conduct, and a second power transistor drive signal controls the second rectifier to conduct. By interlocking the enable signals, the first and second rectifiers are prevented from conducting simultaneously, thus avoiding a short circuit in the first and second rectifier circuits caused by simultaneous activation, and improving circuit reliability.

[0052] Example 2

[0053] According to an embodiment of the present invention, a synchronous rectification device is also provided. Figure 7 This is a structural block diagram of an optional synchronous rectification control device according to an embodiment of the present invention. (Refer to...) Figure 7 As shown, the synchronous rectification control device includes a trigger signal generation unit 702 and a synchronous rectification control unit 704, which will be described in detail below.

[0054] A trigger signal generation unit 702 is used to identify the power transistor drive signal of the bridge structure in the resonant converter and generate a trigger signal based on the power transistor drive signal. The power transistor of the bridge structure is set in the primary circuit of the resonant converter. A synchronous rectification control unit 704 is connected to the trigger signal generation unit 702 and is used to generate a rectifier drive signal based on the trigger signal and control the rectifier to turn on based on the rectifier drive signal. The rectifier is set in the secondary circuit of the resonant converter. After the trigger signal is detected to disappear, the rectifier is continuously controlled to turn on by a holding circuit. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is triggered and the rectifier is controlled to turn off based on the rectifier turn-off signal.

[0055] It should be noted that the trigger signal generation unit 702 mentioned above corresponds to step S602 in Embodiment 1, and the synchronous rectification control unit 704 corresponds to steps S604 to S608 in Embodiment 1.

[0056] In the above optional embodiments, the trigger signal generation unit identifies the power transistor drive signal of the bridge structure in the resonant converter and generates a trigger signal based on the power transistor drive signal. The synchronous rectification control unit generates a rectifier drive signal based on the trigger signal, and after detecting the disappearance of the trigger signal, it continuously controls the rectifier to conduct through a holding circuit. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is triggered, and the rectifier is turned off based on the rectifier turn-off signal. The primary-side power transistor drive signal is converted into a trigger signal to control the generation of the rectifier drive signal. The rectifier drive signal controls the rectifier to conduct. When the voltage difference between the source and drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is generated, and the rectifier is turned off based on the rectifier turn-off signal. This ensures that the rectifier diodes and their corresponding power diodes are turned on synchronously and are turned off before reverse current is generated in the secondary circuit of the converter, thus preventing reverse current from being generated in the secondary circuit. This achieves effective control of the rectifier diodes and solves the problem of the lack of an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier diodes in related technologies.

[0057] As an optional embodiment, the holding circuit includes a NOR gate circuit, and the synchronous rectification control unit includes: a logic control unit and a rectifier drive signal output unit, wherein the NOR gate circuit is used to receive a trigger signal and a rectifier drive signal, and generate an enable signal based on the trigger signal and the rectifier drive signal; the logic control unit is used to receive an enable signal and a rectifier turn-off signal, and output a rectifier drive signal through the rectifier drive signal output unit when the enable signal is received, and output a rectifier turn-off signal through the rectifier drive signal output unit to control the rectifier to turn off when the rectifier turn-off signal is received.

[0058] In some optional embodiments, the synchronous rectification control unit further includes a drain-source voltage detection unit for detecting the voltage difference between the source and drain of the rectifier diode, and triggering a rectifier diode turn-off signal when the voltage difference between the source and drain of the rectifier diode exceeds a set voltage threshold.

[0059] The trigger signal generation unit includes: a signal recognition unit for detecting the power transistor drive signal in the bridge structure of the resonant converter and generating a first-level control signal based on the power transistor drive signal; and a signal processing unit for receiving the first-level control signal and generating a trigger signal based on the first-level control signal, wherein the rising edge of the trigger signal corresponds to the rising edge of the power transistor drive signal.

[0060] As an optional embodiment, it further includes: a signal interlock circuit for controlling the rectifier diode turn-on signal enabled by a first trigger signal and the rectifier diode turn-on signal enabled by a second trigger signal to not occur simultaneously, wherein the first trigger signal is a signal generated based on a first power transistor drive signal, the second trigger signal is a signal generated based on a second power transistor drive signal, and the bridge structure in the resonant converter includes: an upper half-bridge structure and a lower half-bridge structure, the first power transistor drive signal is a drive signal corresponding to the upper half-bridge structure, and the second power transistor drive signal is a drive signal corresponding to the lower half-bridge structure.

[0061] Based on the above embodiments and optional embodiments, an optional implementation method is provided. The following describes the synchronous rectification device provided by this optional implementation method in detail, taking the bridge structure of the resonant converter as a half-bridge structure, the power transistors in the half-bridge structure including a first power transistor and a second power transistor, the rectifier transistors in the secondary circuit including a first rectifier transistor and a second rectifier transistor, and the rectifier control unit including a first rectifier control unit and a second rectifier control unit as an example.

[0062] In related technologies, methods for synchronous rectification control include the following: First, by detecting the source and drain voltages of the synchronous rectifier diode, comparing the source and drain voltages, and generating a drive signal based on the comparison result, which is then provided to the gate of the synchronous rectifier diode. Second, by detecting the source and drain voltages of the synchronous rectifier diode, the direction of the current signal between its drain and source can be determined, and a corresponding self-driving signal can be generated accordingly. Third, by detecting the source and drain voltages of the synchronous rectifier diode, a detection signal indicating the current flow direction in the synchronous rectifier diode is obtained, and a push-pull circuit is used to push-pull the detection signal to an isolated drive converter, which then generates an isolated drive signal for controlling the synchronous rectifier diode. Both methods control the conduction or turn-off of the rectifier diode by detecting the voltage difference between its source and drain. However, these methods have limitations for circuits with LLC resonant topologies. They are only suitable for operating conditions where the switching frequency is higher than the resonant frequency. When the switching frequency is lower than the resonant frequency, inaccurate detection or parasitic parameter resonance (drain and source voltage oscillation) can lead to mis-conduction of the rectifier diode. This mis-conduction can cause problems such as... Figure 5 The phenomenon of current backflow is shown.

[0063] In related technologies, synchronous rectification control can also be achieved using the following method: A current transformer detection module detects the current in the synchronous rectifier diode. When current flows back into the synchronous rectifier diode, a rising edge signal is generated and output to a latch. The latch receives the rising edge signal and outputs a latched signal to an AND gate. The AND gate outputs the latched signal back to the latch. The AND gate then performs an AND operation with the control signal of the primary-side power transistor to generate a drive control output to the synchronous rectifier diode for control. This method has the following problems: During synchronous rectification control, the rectifier diode can only be turned off after the back-current signal of the synchronous rectifier diode is detected. This method has a certain lag; that is, the synchronous rectifier diode will only be turned off after a signal delay in the signal detection circuit and drive circuit after current back-current has occurred. If the signal delay time of the detection circuit and drive circuit is long, the risk is significant. In other words, this method cannot effectively control the rectifier diode to avoid current back-current in the secondary circuit of the converter.

[0064] Therefore, in this embodiment of the present disclosure, a synchronous rectification control device is provided. A trigger signal generation unit identifies the power transistor drive signal of the bridge structure in the resonant converter and generates a trigger signal based on the power transistor drive signal. The synchronous rectification control unit generates a rectifier transistor drive signal based on the trigger signal, and after detecting the disappearance of the trigger signal, continuously controls the rectifier transistor to conduct through a holding circuit. When the voltage difference between the source and drain of the rectifier transistor exceeds a set voltage threshold, a rectifier transistor turn-off signal is triggered, and the rectifier transistor is controlled to turn off based on the rectifier transistor turn-off signal. The primary-side power transistor drive signal is converted into a trigger signal, controlling the generation of the rectifier transistor drive signal. The rectifier transistor drive signal controls the rectifier transistor to conduct. When the voltage difference between the source and drain of the rectifier transistor exceeds a set voltage threshold, a rectifier transistor turn-off signal is generated, and the rectifier transistor is controlled to turn off based on the rectifier transistor turn-off signal. This ensures that the rectifier diodes and their corresponding power diodes are turned on synchronously and are turned off before reverse current is generated in the secondary circuit of the converter, thus preventing reverse current from being generated in the secondary circuit. This achieves effective control of the rectifier diodes and solves the problem of the lack of an effective synchronous rectification control method for controlling the turn-on and turn-off of rectifier diodes in related technologies.

[0065] Figure 8 This is a structural block diagram of another optional synchronous rectification control device (equivalent to the synchronous rectification control device in the foregoing embodiments) according to an embodiment of the present invention. (Refer to...) Figure 8As shown, the synchronous rectification control device includes a trigger signal generation unit 82, a synchronous rectification control unit 84, and a peripheral control unit 86. The signal input terminal of the trigger signal generation unit 82 is connected to the gates of the first power transistor Q1 and the second power transistor Q2 in the resonant converter. The output terminal of the trigger signal generation unit 82 is connected to the signal input terminals of the synchronous rectification control unit 84 and the peripheral control unit 86. The signal output terminal of the peripheral control unit 86 is connected to the second signal input terminal of the synchronous rectification control unit 84. The signal output terminal of the synchronous rectification control unit 84 is connected to the gate of the rectifier transistor. The trigger signal generation unit 82 includes a signal recognition unit 822, a delay unit 824, a signal amplification unit 826, and a signal demodulation unit 828. The circuitry and operating principles of each part are explained in detail below.

[0066] Figure 9 This is a circuit diagram of an optional trigger signal generation unit 82 according to an embodiment of the present invention. (Refer to...) Figure 9 As shown, there are various types of signal recognition units 822. For example, signal recognition unit 822 can be a trigger, specifically including Schmitt triggers, etc.; delay unit 824 includes a delay circuit and a first inverter B1 and a second inverter B2; signal amplification unit 826 includes a first drive amplifier circuit E1 and a second drive amplifier circuit E2; signal demodulation unit 828 includes an isolation converter T1 and a fifth diode D5, a sixth diode D6, a third resistor R3, and a fourth resistor R4.

[0067] Specifically, the gate of the first power transistor Q1 is connected to the first input terminal of the trigger, and based on this connection, a first power transistor drive signal G1 is sent to the signal identification unit. Similarly, the gate of the second power transistor Q2 is connected to the second input terminal of the signal identification unit, and based on this connection, a second power transistor drive signal G2 is sent to the signal identification unit. The first power transistor drive signal G1 and the second power transistor drive signal G2 are two complementary PWM signals with a certain dead time. After passing through the signal identification unit, the first power transistor drive signal G1 and the second power transistor drive signal G2 generate two identical first-level control signals. The rising edge of these two first-level signals corresponds to the rising edge of the first power transistor drive signal G1, and the falling edge corresponds to the falling edge of the first power transistor drive signal G1.

[0068] One primary control signal is delayed by a delay circuit and then connected to the input of the first inverter B1. The other primary control signal is connected to the input of the second inverter B2. The outputs of the first inverter B1 and the second inverter B2 output two secondary control signals. These two secondary control signals have the same frequency and duty cycle, differing only in phase. There are various types of delay circuits, including integrated circuits with delay functions, delay-type logic devices, and so on.

[0069] The output terminals of the first inverter B1 and the second inverter B2 are respectively connected to the first drive amplifier circuit E1 and the second drive amplifier circuit E2. The secondary control signal, after passing through the first drive amplifier circuit E1 and the second drive amplifier circuit E2, outputs the tertiary control signals OUT_A and OUT_B. The first drive amplifier circuit E1 and the second drive amplifier circuit E2 stabilize the aforementioned secondary control signal, ensuring high consistency between the output tertiary control signals OUT_A and OUT_B and the corresponding secondary control signals, preventing attenuation in subsequent circuits.

[0070] The output terminals of the first drive amplifier circuit E1 and the second drive amplifier circuit E2 are respectively connected to terminals 1 and 2 of the primary winding of the isolation converter. Terminal 5 of the secondary winding of the isolation converter T1 is connected to the anode of the fifth diode D5. Terminal 4 of the secondary winding of the isolation converter T1 is grounded and connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the cathode of the fifth diode D5. The converter T1 outputs the second trigger signal S2 through the fifth diode D5. Terminal 3 of the secondary winding of the isolation converter T1 is connected to the anode of the sixth diode D6. One end of the fourth resistor R4 is grounded and the other end of the fourth resistor R4 is connected to the cathode of the sixth diode D6. The converter T1 outputs the first trigger signal S1 through the sixth diode D6. The three-level control signals OUT_A and OUT_B are converted into two four-level control signals with a pulse width equal to the set delay time after passing through an isolation converter. One positive pulse rising edge of these four-level control signals corresponds to the rising edge of the power transistor drive signal in the bridge structure, and the other positive pulse rising edge corresponds to the rising edge of the power transistor drive signal in the lower bridge structure. In other words, the upper and lower power transistor drive signals of the bridge structure (half-bridge or full-bridge) are restored here after conversion. These two four-level control signals have the following characteristics: the falling edge of one narrow pulse signal corresponds to the rising edge of one of the three-level control signals, and the rising edge of the other narrow pulse corresponds to the falling edge of the other three-level control signal; the narrow pulse width is equal to the delay time set by the delay circuit. These two four-level control signals are then converted into the first trigger signal S1 and the second trigger signal S2 through a voltage divider.

[0071] The first and second driver amplifier circuits E1 and E2 can be of various types and are not limited to the structures described above; they may also include, for example... Figure 10 , Figure 11 The structure shown, the driver chip with current amplification function, etc.

[0072] Reference Figure 10As shown, the first drive amplifier circuit E1 includes a first MOSFET M1 and a second MOSFET M2. Taking the transmission of one of the three-stage control signals as an example: the output of the first inverter B1 is connected to the gate of the first MOSFET M1 and the gate of the second MOSFET M2. The source of the first MOSFET M1 and the drain of the second MOSFET M2 are connected to the first input terminal of the transformer T1. The drain of the first MOSFET M1 is connected to the power supply VCC, and the source of the second MOSFET M2 is grounded. The first MOSFET is an N-type MOSFET, and the second MOSFET is a P-type MOSFET. The second drive amplifier circuit E2 has the same structure as the first drive amplifier circuit E1 and is connected between the output of the second inverter B2 and the second input terminal of the transformer T1.

[0073] Reference Figure 11 As shown, the first drive amplifier circuit E1 includes a first transistor M3 and a second transistor M4. Taking the transmission of one of the three-stage control signals as an example: the output of the first inverter B1 is connected to the base of the first transistor M3 and the base of the second transistor M4. The collector of the first transistor M3 is connected to an external power supply, and the collector of the second transistor M4 is grounded. The emitters of the first transistor M3 and the second transistor M4 are connected to the second input terminal of the transformer T1. The first transistor M3 is an NPN transistor, and the second transistor M4 is a PNP transistor. The second drive amplifier circuit E2 has the same structure as the first drive amplifier circuit E1 and is connected between the output of the second inverter B2 and the second input terminal of the transformer T1.

[0074] The structure of the signal demodulation unit is not limited to the structure described above, and may also include, for example: Figure 12 The structure shown. (Refer to...) Figure 12 As shown, the signal demodulation unit includes a converter T2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The third terminal of converter T2 is connected to one end of the sixth resistor R6, and one end of the sixth resistor R6 is connected to one end of the eighth resistor R8; this connection point forms the output terminal for outputting the second trigger signal S2. The fifth terminal of converter T2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to one end of the seventh resistor R7; this connection point forms the output terminal for outputting the first trigger signal S1. The other end of the seventh resistor R7 is connected to the other end of the eighth resistor R8 and the fourth terminal of converter T2; this connection point is grounded.

[0075] The aforementioned first trigger signal S1 and second trigger signal S2, as well as the PWM drive signal output by the synchronous rectification control unit 84, are input to the corresponding NOR gate circuit for NOR operation, thereby generating an enable signal. After receiving the enable signal, the synchronous rectification control unit 84 sends out a rectifier drive signal and controls the corresponding synchronous rectifier to turn on based on the rectifier drive signal. The type of the rectifier drive signal is a PWM signal.

[0076] The first and second synchronous rectification control units have the same circuit structure. The following explanation uses the first synchronous rectification control unit as an example. Figure 13 This is a circuit diagram of an optional first synchronous rectification control unit according to an embodiment of the present invention. (Refer to...) Figure 13 As shown, the first trigger signal S1 is input to the first input terminal of the first NOR gate U1, and the first rectifier drive signal PWM1 output by the drive signal output unit is connected to the second input terminal of the NOR gate. After the two signals are NORed, the first enable signal DIS1 is output. The first enable signal DIS1 is input to the logic controller to control the output of the first rectifier drive signal PWM1. The output first rectifier drive signal PWM1 is connected to the gate of the first rectifier SR1 to control the turn-on of the first rectifier SR1.

[0077] The source of the first rectifier diode SR1 is grounded, and its drain is connected to the signal input terminal of the source-drain voltage detection unit. The source-drain voltage detection unit detects the source-drain voltage difference and generates a turn-off signal to control the first rectifier diode SR1 to turn off based on this difference. Specifically, the first synchronous rectification control unit detects the magnitude of the source-drain voltage difference of the corresponding rectifier diode and uses the detection result as the basis for determining whether the corresponding synchronous rectification control unit should stop outputting the rectifier diode drive signal. When the source-drain voltage difference of the rectifier diode rises to a set voltage threshold, the first synchronous rectification control unit stops outputting the rectifier diode drive signal, and the corresponding rectifier diode turns off.

[0078] Figure 14 This is a schematic diagram of circuit 86 of an optional peripheral control unit according to an embodiment of the present invention. (Refer to...) Figure 14As shown, the first trigger signal S1 is connected to the first input terminal of the first NOR gate U1, the first rectifier drive signal PWM1 output by the first synchronous rectification control unit is connected to the second input terminal of the first NOR gate U1, the first enable signal DIS1 output by the first NOR gate U1 is connected to the enable terminal of the first synchronous rectification control unit, the first rectifier drive signal PWM1 output by the first synchronous rectification control unit is connected to the gate of the first rectifier SR1 and the anode of the seventh diode D7; the cathode of the seventh diode D7 is connected to the enable terminal of the second synchronous rectification control unit. The second trigger signal S2 is connected to the first input terminal of the second NOR gate U2, the second rectifier drive signal PWM2 output by the second synchronous rectification control unit is connected to the second input terminal of the second NOR gate U2, the second enable signal DIS2 output by the second NOR gate U2 is connected to the enable terminal of the second synchronous rectification control unit, the second rectifier drive signal PWM2 output by the second synchronous rectification control unit is connected to the gate of the second rectifier SR2 and the anode of the eighth diode D8; the cathode of the eighth diode D8 is connected to the enable terminal of the first synchronous rectification control unit.

[0079] The first rectifier drive signal PWM1 output by the first synchronous rectification control unit is connected to the second input terminal of the first NOR gate U1, and the second rectifier drive signal PWM2 output by the second synchronous rectification control unit is connected to the second input terminal of the second NOR gate U2. They are respectively ORed with the corresponding first trigger signal S1 and second trigger signal S2, so that the synchronous rectification control unit continuously outputs a high-level signal to keep the corresponding rectifier tube on before receiving the turn-off signal, thereby realizing the trigger signal latching.

[0080] The aforementioned signal interlocking unit includes a seventh diode D7 and an eighth diode D8. The cathode of the seventh diode D7 is connected to the enable terminal of the second synchronous rectification control unit, and the cathode of the eighth diode D8 is connected to the enable terminal of the first synchronous rectification control unit, thereby achieving signal interlocking of the two enable signals. Specifically, when the first enable signal DIS1 input to the enable terminal of the first synchronous rectification control unit is low, the first synchronous rectification control unit outputs a high-level first rectifier drive signal PWM1. The first rectifier drive signal PWM1, after passing through the seventh diode D7, becomes the second enable signal DIS2 input to the enable terminal of the second synchronous rectification control unit. That is, the second enable signal DIS2 is high, and at this time, the second synchronous rectification control unit does not output the second rectifier drive signal PWM2. When the second enable signal DIS2 input to the enable terminal of the second synchronous rectification control unit is low, the second synchronous rectification control unit outputs a high-level second rectifier drive signal PWM2. This second rectifier drive signal PWM2, after passing through the eighth diode D8, becomes the first enable signal DIS1 input to the enable terminal of the first synchronous rectification control unit. That is, the first enable signal DIS1 is high, and at this time, the first synchronous rectification control unit does not output the first rectifier drive signal PWM1. This achieves interlocking of the first enable signal DIS1 and the second enable signal DIS2, ensuring that the two rectifiers will not be turned on simultaneously, avoiding short circuits caused by simultaneous turn-on of the two rectifiers, and improving circuit reliability.

[0081] Specifically, when the first enable signal DIS1 of the first synchronous rectification control unit is low, its output port outputs the first rectifier drive signal PWM1. The first rectifier drive signal PWM1 is used as the input signal of the second synchronous rectification control unit after passing through the seventh diode D7. When the second enable signal DIS2 of the second synchronous rectification control unit is low, its output port outputs the second rectifier drive signal PWM2. The second rectifier drive signal PWM2 is used as the input signal of the first synchronous rectification control unit after passing through the eighth diode D8. The enable signals of the first and second synchronous rectification control units cannot be low at the same time. Therefore, the enable signals of the first and second synchronous rectification control units are interlocked and will not work at the same time, thereby avoiding the simultaneous activation of the two rectifier tubes in the synchronous rectification circuit.

[0082] That is, the peripheral control unit connects the PWM drive signal from the synchronous rectification control unit to the input of the NOR gate. Thus, even after the trigger signal disappears, the high-level signal from the synchronous rectification control unit can still be maintained until the synchronous rectification control unit receives a shutdown signal and stops operating. During full-wave rectification, the first rectifier drive signal PWM1 output from the first synchronous rectification control unit is connected to the enable terminal of the second synchronous rectification control unit, and the second rectifier drive signal PWM2 output from the second synchronous rectification control unit is connected to the enable terminal of the first synchronous rectification control unit, forcing the drive signals of the two rectifiers to be complementary.

[0083] In the synchronous rectification control device provided in this optional embodiment, trigger signal latching is achieved by performing a OR-NOT logic operation on the rectifier drive signal and the trigger signal. Specifically, when the trigger signal disappears, the synchronous rectification control unit continuously outputs a high level through a holding circuit to ensure the rectifier is turned on. The specific latching method is as follows: when the rising edge of the demodulated signal arrives, the enable signal is low, and the synchronous rectification control unit outputs the rectifier drive signal. When the trigger signal disappears, because of the presence of the rectifier drive signal, the enable signal remains low, thus ensuring that the corresponding rectifier is always turned on until the source-drain voltage detection unit detects that the source-drain voltage difference is higher than a preset voltage threshold, at which point the synchronous rectification control unit stops outputting the rectifier drive signal. Furthermore, in this optional embodiment, the high-low level relationship between the enable signal and the rectifier drive signal is used to achieve interlocking between the first and second synchronous rectification control units, thereby preventing the first rectifier SR1 and the second rectifier SR2 from being shot-through.

[0084] Figure 15 This is a timing diagram of a synchronous rectification control device according to an embodiment of the present invention. The control principle of this optional embodiment will be further explained below using a first synchronous rectification control circuit as an example, with reference to... Figure 15 As shown, the rising edge of the first trigger signal S1 corresponds to the rising edge of the first rectifier drive signal PWM1. That is, after receiving the first trigger signal S1, the first synchronous rectification control unit generates the first rectifier drive signal PWM1, and controls the first rectifier SR1 to turn on based on the first rectifier drive signal PWM1. When the first trigger signal S1 is not received, the first synchronous rectification control unit will not output the first rectifier drive signal PWM1, and the first rectifier SR1 will not malfunction. This avoids the phenomenon of current backflow in the rectification circuit caused by the oscillation of the drain and source voltages of the first rectifier SR1 leading to malfunctioning turn-on of the rectifier.

[0085] In the synchronous rectification control device provided in the optional embodiment of the present invention, a trigger signal is generated by signal conversion and demodulation, and the synchronous rectifier tube is turned on based on the trigger signal. The synchronous rectification control device provided in the above optional embodiment is not only applicable to Figure 1 The LLC resonant converter shown is also applicable to circuits with other resonant topologies. The device avoids energy (current) backflow caused by rectifier tube malfunction and implements trigger signal latching, allowing the rectifier tube to remain on even after the trigger signal disappears, ensuring the circuit continues synchronous rectification. When the secondary side is full-wave rectifier (equivalent to the case where the rectifier tubes include the first and second rectifier tubes), rectifier tube interlocking is implemented to avoid short circuits caused by interconnection between secondary rectifier tubes. The sequence numbers of the above embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0086] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0087] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A synchronous rectification control method characterized by comprising: The method comprises: identifying a power tube driving signal of a bridge structure in a resonant converter, and generating a trigger signal based on the power tube driving signal, the power tube of the bridge structure being arranged in a primary side circuit of the resonant converter; generating a rectifier tube driving signal based on the trigger signal, and controlling the rectifier tube to be turned on based on the rectifier tube driving signal, the rectifier tube being arranged in a secondary side circuit of the resonant converter; after detecting that the trigger signal disappears, controlling the rectifier tube to be turned on continuously through a holding circuit; in a case where a voltage difference between a source and a drain of the rectifier tube exceeds a set voltage threshold, triggering a rectifier tube turn-off signal, and controlling the rectifier tube to be turned off based on the rectifier tube turn-off signal; wherein, after detecting that the trigger signal disappears, controlling the rectifier tube to be turned on continuously through the holding circuit comprises: inputting the trigger signal and the rectifier tube driving signal into a NOR gate circuit, so that the NOR gate circuit continuously outputs an enable signal, the enable signal controls a synchronous rectification unit to output the rectifier tube driving signal, and controls the rectifier tube to be turned on.

2. The method of claim 1, wherein, The method comprises: detecting a power tube driving signal in the bridge structure in the resonant converter; a trigger circuit receives the power tube driving signal, and generates a trigger signal based on the power tube driving signal, a rising edge of the trigger signal corresponding to a rising edge of the power tube driving signal.

3. The method of claim 1, wherein, The bridge structure in the resonant converter comprises: an upper half-bridge structure and a lower half-bridge structure; the power tube driving signal comprises a first power tube driving signal corresponding to the upper half-bridge structure and a second power tube driving signal corresponding to the lower half-bridge structure; the trigger signal comprises a first trigger signal and a second trigger signal, a rising edge of the first trigger signal corresponding to a rising edge of the first power tube driving signal, and a rising edge of the second trigger signal corresponding to a rising edge of the second power tube driving signal; the enable signal comprises a first enable signal corresponding to the first trigger signal and a second enable signal corresponding to the second trigger signal; the rectifier tube driving signal comprises a first rectifier tube driving signal generated based on the first enable signal and a second rectifier tube driving signal generated based on the second enable signal.

4. The method of claim 3, wherein: controlling the rectifier tube to be turned on based on the rectifier tube driving signal comprises: controlling the rectifier tube to be turned on based on the first rectifier tube driving signal, or controlling the rectifier tube to be turned on based on the second rectifier tube driving signal; after detecting that the trigger signal disappears, controlling the rectifier tube to be turned on continuously through the holding circuit.

5. The method of claim 4, wherein, The rectifier tube comprises a first rectifier tube and a second rectifier tube; by signal interlocking the first enable signal and the second enable signal, the following two operations are controlled to not exist at the same time: the first power tube driving signal controls the first rectifier tube to be turned on, and the second power tube driving signal controls the second rectifier tube to be turned on.

6. A synchronous rectification control device characterized by comprising: The method comprises: The trigger signal generation unit is configured to identify a power tube driving signal of a bridge structure in a resonant converter and generate a trigger signal based on the power tube driving signal, the power tube of the bridge structure being arranged in a primary side circuit of the resonant converter. The synchronous rectification control unit is configured to generate a rectifier driving signal based on the trigger signal and control the rectifier to be turned on based on the rectifier driving signal, the rectifier being arranged in a secondary side circuit of the resonant converter. After detecting that the trigger signal disappears, the rectifier is controlled to be turned on continuously by a holding circuit; in a case where a voltage difference between a source and a drain of the rectifier exceeds a set voltage threshold, a rectifier turn-off signal is triggered, and the rectifier is controlled to be turned off based on the rectifier turn-off signal. The holding circuit includes an NOR gate circuit configured to receive the trigger signal and the rectifier driving signal and generate an enable signal based on the trigger signal and the rectifier driving signal.

7. The apparatus of claim 6, wherein, The synchronous rectification control unit includes a logic control unit and a rectifier driving signal output unit, wherein The logic control unit is configured to receive the enable signal and the rectifier turn-off signal, output a rectifier driving signal through the rectifier driving signal output unit when the enable signal is received, and output a rectifier turn-off signal through the rectifier driving signal output unit when the rectifier turn-off signal is received to control the rectifier to be turned off.

8. The apparatus of claim 7, wherein, The trigger signal generation unit includes: A signal identification unit is configured to detect a power tube driving signal in the bridge structure in the resonant converter and generate a first control signal based on the power tube driving signal. A signal processing unit is configured to receive the first control signal and generate a trigger signal based on the first control signal, a rising edge of the trigger signal corresponding to a rising edge of the power tube driving signal.

9. The apparatus of claim 6, wherein, Further comprising: A signal interlocking circuit is configured to control the rectifier turn-on signal enabled based on a first trigger signal and the rectifier turn-on signal enabled based on a second trigger signal to not occur at the same time, wherein the first trigger signal is a signal generated based on a first power tube driving signal, the second trigger signal is a signal generated based on a second power tube driving signal, the bridge structure in the resonant converter includes an upper half-bridge structure and a lower half-bridge structure, the first power tube driving signal is a driving signal corresponding to the upper half-bridge structure, and the second power tube driving signal is a driving signal corresponding to the lower half-bridge structure.

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